From 376ad8da3d9337824e3093743b2a0aeca0562345 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 11 Aug 2021 10:43:46 +1000 Subject: [PATCH] boxarty rebased Build with fusesoc run --target=arty_a7-100 microwatt --memory_size=0 --no_bram --use_litesdcard --has_lpc --- fpga/arty_a7.xdc | 37 +- fpga/top-arty.vhdl | 62 +- hello_world/hello_world.bin | Bin 6280 -> 5432 bytes hello_world/hello_world.elf | Bin 87184 -> 85040 bytes lpc/lpc.v | 13153 ++++++++++++++++++++++++++++++++++ microwatt.core | 8 + soc.vhdl | 164 +- 7 files changed, 13401 insertions(+), 23 deletions(-) create mode 100644 lpc/lpc.v diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 4db6aab..6147d8f 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -80,14 +80,14 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdca # PMOD header JB (high-speed, no protection resisters) ################################################################################ -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_1 }]; -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_2 }]; -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_3 }]; -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_4 }]; -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_7 }]; -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_8 }]; -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_9 }]; -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_10 }]; +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[1] }]; +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[2] }]; +set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jb[3] }]; +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[6] }]; +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jb[7] }]; +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[7] }]; +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[9] }]; +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[10] }]; # connection to Digilent PmodSD on JB #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[3] }]; @@ -103,14 +103,14 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdca # PMOD header JC (high-speed, no protection resisters) ################################################################################ -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_1 }]; -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_2 }]; -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_3 }]; -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_4 }]; -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_7 }]; -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_8 }]; -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_9 }]; -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_10 }]; +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[1] }]; +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[2] }]; +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[3] }]; +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[4] }]; +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[7] }]; +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[8] }]; +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[9] }]; +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[10] }]; ################################################################################ # PMOD header JD (standard, 200 ohm protection resisters) @@ -135,8 +135,8 @@ set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_po set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[3] }]; set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[4] }]; set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[5] }]; -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[6] }]; -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[7] }]; +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[4] }]; +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[8] }]; set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[8] }]; set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[9] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[10] }]; @@ -552,3 +552,4 @@ set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] + diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 7171be9..75d555d 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -17,6 +17,7 @@ entity toplevel is HAS_FPU : boolean := true; HAS_BTC : boolean := true; HAS_SHORT_MULT : boolean := false; + HAS_LPC : boolean := true; USE_LITEDRAM : boolean := false; NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false; @@ -60,6 +61,10 @@ entity toplevel is -- GPIO shield_io : inout std_ulogic_vector(44 downto 0); + -- LPC + pmod_jb : inout std_ulogic_vector(10 downto 1); + pmod_jc : inout std_ulogic_vector(10 downto 1); + -- Ethernet eth_ref_clk : out std_ulogic; eth_clocks_tx : in std_ulogic; @@ -163,6 +168,18 @@ architecture behaviour of toplevel is signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0); signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0); + -- LPC + signal lpc_data_o : std_ulogic_vector(3 downto 0); + signal lpc_data_o_reg : std_ulogic_vector(3 downto 0); + signal lpc_data_oe : std_ulogic; + signal lpc_data_i : std_ulogic_vector(3 downto 0); + signal lpc_irq_o : std_ulogic; + signal lpc_irq_oe : std_ulogic; + signal lpc_irq_i : std_ulogic; + signal lpc_frame_n : std_ulogic; + signal lpc_reset_n : std_ulogic; + signal lpc_clock : std_ulogic; + -- Fixup various memory sizes based on generics function get_bram_size return natural is begin @@ -196,6 +213,7 @@ begin HAS_FPU => HAS_FPU, HAS_BTC => HAS_BTC, HAS_SHORT_MULT => HAS_SHORT_MULT, + HAS_LPC => HAS_LPC, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 256 * 1024 * 1024, DRAM_INIT_SIZE => PAYLOAD_SIZE, @@ -238,6 +256,17 @@ begin gpio_out => gpio_out, gpio_dir => gpio_dir, + -- LPC + lpc_data_o => lpc_data_o, + lpc_data_oe => lpc_data_oe, + lpc_data_i => lpc_data_i, + lpc_frame_n => lpc_frame_n, + lpc_reset_n => lpc_reset_n, + lpc_clock => lpc_clock, + lpc_irq_o => lpc_irq_o, + lpc_irq_oe => lpc_irq_oe, + lpc_irq_i => lpc_irq_i, + -- External interrupts ext_irq_eth => ext_irq_eth, ext_irq_sdcard => ext_irq_sdcard, @@ -263,6 +292,35 @@ begin --uart_pmod_rts_n <= '0'; + -- LPC inout/bidir pins (assignments requested by paulus) + lpc_clock <= pmod_jb(1); + pmod_jb(2) <= '0'; + + lpc_data_i(0) <= pmod_jc(1); + lpc_data_i(1) <= pmod_jc(3); + lpc_data_i(2) <= pmod_jc(7); + lpc_data_i(3) <= pmod_jc(9); + lpc_data_o_reg <= lpc_data_o; + + pmod_jc(1) <= lpc_data_o_reg(0) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(2) <= '0'; + pmod_jc(3) <= lpc_data_o_reg(1) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(4) <= '0'; + pmod_jc(7) <= lpc_data_o_reg(2) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(8) <= '0'; + pmod_jc(9) <= lpc_data_o_reg(3) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(10) <= '0'; + + lpc_reset_n <= pmod_jb(3); + pmod_jb(4) <= 'Z'; -- actually comes out on 40-pin connector + lpc_frame_n <= pmod_jb(7); + pmod_jb(7) <= 'Z'; + pmod_jb(8) <= 'Z'; -- actually comes out on 40-pin connector + pmod_jb(9) <= lpc_irq_o when lpc_irq_oe = '1' and ext_rst_n = '1' else 'Z'; + lpc_irq_i <= pmod_jb(9); + pmod_jb(10) <= lpc_data_oe; + + -- SPI Flash -- -- Note: Unlike many other boards, the SPI flash on the Arty has @@ -699,8 +757,8 @@ begin gpio_in(3) <= shield_io(3); gpio_in(4) <= shield_io(4); gpio_in(5) <= shield_io(5); - gpio_in(6) <= shield_io(6); - gpio_in(7) <= shield_io(7); + gpio_in(6) <= shield_io(6); -- actually comes out on JB4 + gpio_in(7) <= shield_io(7); -- actually comes out on JB8 gpio_in(8) <= shield_io(8); gpio_in(9) <= shield_io(9); gpio_in(10) <= shield_io(10); diff --git a/hello_world/hello_world.bin b/hello_world/hello_world.bin index e4b14ca6f70843d9d43a149c8d18fb1f22072fe5..d1bf303a9243d8cfe15c3cd8fc84024c24504a3f 100755 GIT binary patch delta 619 zcmY*VOK1~O6g_V!W~SAU$)q6E;_F99>MSCHOlafGNc~{(lZABYjP1f@7hNPY(~KpH z3ND1#h22~pgAQ@(At?t0{+C=Q?eHUlyx zu&`(Rch{iY{$BIxp=0o@ujrcg5^nBdA9f-0>vr(G2i0fOJYbOHD(vhB3UkNj#o3vh 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zq*?z*p`|`7`^<6lhvxW_=5M6PpuNKSFM%KCk?7CQ^0{B(PhpRv|G&r4KfKu2KVtPb z-scwV zoP8Yq>sR@bi$Zq8`c&qzUo85d)jw?g(>`bh5|2L~=J*6U7`w&#!|Qxc_ZKrkvwvpO VbQ5Z#sX7J!w+Xryg%m '0'); + -- LPC signals + lpc_data_o : out std_ulogic_vector(3 downto 0); + lpc_data_oe : out std_ulogic; + lpc_data_i : in std_ulogic_vector(3 downto 0) := (others => '1'); + lpc_frame_n : in std_ulogic := '1'; + lpc_reset_n : in std_ulogic := '1'; + lpc_clock : in std_ulogic := '1'; + lpc_irq_o : out std_ulogic; + lpc_irq_oe : out std_ulogic; + lpc_irq_i : in std_ulogic := '0'; + -- DRAM controller signals alt_reset : in std_ulogic := '0' ); @@ -146,7 +161,7 @@ architecture behaviour of soc is -- Arbiter array (ghdl doesnt' support assigning the array -- elements in the entity instantiation) - constant NUM_WB_MASTERS : positive := 4; + constant NUM_WB_MASTERS : positive := 5; signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1); signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1); @@ -187,6 +202,26 @@ architecture behaviour of soc is signal wb_spiflash_is_reg : std_ulogic; signal wb_spiflash_is_map : std_ulogic; + -- LPC Flash controller signals: + signal wb_lpc_in : wb_io_master_out; + signal wb_lpc_out : wb_io_slave_out; + signal lpc_vuart_irq : std_ulogic; + signal lpc_ipmi_irq : std_ulogic; + + -- LPC master wb + signal lpc_master_wb_cyc : std_ulogic; + signal lpc_master_wb_stb : std_ulogic; + signal lpc_master_wb_err : std_ulogic; + signal lpc_master_wb_addr : std_ulogic_vector(29 downto 0); + + signal wb_lpc_dma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_lpc_dma_in : wb_io_slave_out; + signal wb_lpc_dma_nr : wb_io_master_out; + signal wb_lpc_dma_ir : wb_io_slave_out; + + -- for conversion from non-pipelined wishbone to pipelined + signal wb_lpc_dma_stb_sent : std_ulogic; + -- XICS signals: signal wb_xics_icp_in : wb_io_master_out; signal wb_xics_icp_out : wb_io_slave_out; @@ -225,6 +260,7 @@ architecture behaviour of soc is signal rst_core : std_ulogic := '1'; signal rst_uart : std_ulogic := '1'; signal rst_xics : std_ulogic := '1'; + signal rst_lpc : std_ulogic := '1'; signal rst_spi : std_ulogic := '1'; signal rst_gpio : std_ulogic := '1'; signal rst_bram : std_ulogic := '1'; @@ -243,6 +279,7 @@ architecture behaviour of soc is SLAVE_IO_SPI_FLASH_MAP, SLAVE_IO_GPIO, SLAVE_IO_EXTERNAL, + SLAVE_IO_LPC, SLAVE_IO_NONE); signal slave_io_dbg : slave_io_type; @@ -312,6 +349,7 @@ begin rst_spi <= rst; rst_xics <= rst; rst_gpio <= rst; + rst_lpc <= rst; rst_bram <= rst; rst_dtm <= rst; rst_wbar <= rst; @@ -360,11 +398,13 @@ begin wb_masters_out <= (0 => wishbone_dcore_out, 1 => wishbone_icore_out, 2 => wishbone_widen_data(wishbone_dma_out), - 3 => wishbone_debug_out); + 3 => wishbone_widen_data(wb_lpc_dma_out), + 4 => wishbone_debug_out); wishbone_dcore_in <= wb_masters_in(0); wishbone_icore_in <= wb_masters_in(1); wishbone_dma_in <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr); - wishbone_debug_in <= wb_masters_in(3); + wb_lpc_dma_in <= wishbone_narrow_data(wb_masters_in(3), wb_lpc_dma_out.adr); + wishbone_debug_in <= wb_masters_in(4); wishbone_arbiter_0: entity work.wishbone_arbiter generic map( NUM_MASTERS => NUM_WB_MASTERS @@ -616,6 +656,8 @@ begin slave_io := SLAVE_IO_UART1; elsif std_match(match, x"C8---") then slave_io := SLAVE_IO_EXTERNAL; + elsif std_match(match, x"CB---") then + slave_io := SLAVE_IO_LPC; elsif std_match(match, x"C0004") then slave_io := SLAVE_IO_ICP; elsif std_match(match, x"C0005") then @@ -636,6 +678,8 @@ begin wb_spiflash_is_map <= '0'; wb_gpio_in <= wb_sio_out; wb_gpio_in.cyc <= '0'; + wb_lpc_in <= wb_sio_out; + wb_lpc_in.cyc <= '0'; -- Only give xics 8 bits of wb addr (for now...) wb_xics_icp_in <= wb_sio_out; @@ -693,6 +737,9 @@ begin wb_sio_in <= wb_ext_io_out; end if; + when SLAVE_IO_LPC => + wb_lpc_in.cyc <= wb_sio_out.cyc; + wb_sio_in <= wb_lpc_out; when SLAVE_IO_SYSCON => wb_syscon_in.cyc <= wb_sio_out.cyc; wb_sio_in <= wb_syscon_out; @@ -892,6 +939,115 @@ begin wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack; end generate; + lpc_gen: if HAS_LPC generate + component lpc_top port ( + clk : in std_ulogic; + rst : in std_ulogic; + + lclk : in std_ulogic; + lframe : in std_ulogic; + lreset : in std_ulogic; + lad_en : out std_ulogic; + lad_out : out std_ulogic_vector(3 downto 0); + lad_in : in std_ulogic_vector(3 downto 0); + + adr : in std_ulogic_vector(13 downto 0); + dat_w : in std_ulogic_vector(31 downto 0); + dat_r : out std_ulogic_vector(31 downto 0); + ack : out std_ulogic; + cyc : in std_ulogic; + sel : in std_ulogic; + stb : in std_ulogic; + we : in std_ulogic; + + dma_adr : out std_ulogic_vector(29 downto 0); + dma_dat_w : out std_ulogic_vector(31 downto 0); + dma_dat_r : in std_ulogic_vector(31 downto 0); + dma_ack : in std_ulogic; + dma_cyc : out std_ulogic; + dma_sel : out std_ulogic_vector(3 downto 0); + dma_stb : out std_ulogic; + dma_we : out std_ulogic; + + bmc_ipmi_irq : out std_ulogic; + bmc_vuart_irq : out std_ulogic; + target_ipmi_irq : out std_ulogic; + target_vuart_irq : out std_ulogic + ); + end component; + begin + lpc0: lpc_top + port map( + rst => rst_lpc, + clk => system_clk, + + adr => wb_lpc_in.adr(13 downto 0), + dat_w => wb_lpc_in.dat(31 downto 0), + dat_r => wb_lpc_out.dat(31 downto 0), + ack => wb_lpc_out.ack, + cyc => wb_lpc_in.cyc, + sel => wb_lpc_in.sel(0), + stb => wb_lpc_in.stb, + we => wb_lpc_in.we, + + dma_adr => wb_lpc_dma_nr.adr(29 downto 0), + dma_dat_w => wb_lpc_dma_nr.dat(31 downto 0), + dma_dat_r => wb_lpc_dma_ir.dat(31 downto 0), + dma_sel => wb_lpc_dma_nr.sel, + dma_cyc => wb_lpc_dma_nr.cyc, + dma_stb => wb_lpc_dma_nr.stb, + dma_ack => wb_lpc_dma_ir.ack, + dma_we => wb_lpc_dma_nr.we, + + lclk => lpc_clock, + lframe => lpc_frame_n, + lreset => lpc_reset_n, + lad_out => lpc_data_o, + lad_in => lpc_data_i, + lad_en => lpc_data_oe, + + bmc_ipmi_irq => lpc_ipmi_irq, + bmc_vuart_irq => lpc_vuart_irq + ); + lpc_master_wb_err <= '0'; + lpc_irq_o <= '0'; + lpc_irq_oe <= '0'; + -- FIXME hook up irqs + + wb_lpc_out.stall <= not wb_lpc_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_lpc_dma_out <= wb_lpc_dma_nr; + if wb_lpc_dma_stb_sent = '1' or + (wb_lpc_dma_out.stb = '1' and wb_lpc_dma_in.stall = '0') then + wb_lpc_dma_out.stb <= '0'; + end if; + if wb_lpc_dma_nr.cyc = '0' or wb_lpc_dma_ir.ack = '1' then + wb_lpc_dma_stb_sent <= '0'; + elsif wb_lpc_dma_in.stall = '0' then + wb_lpc_dma_stb_sent <= wb_lpc_dma_nr.stb; + end if; + wb_lpc_dma_ir <= wb_lpc_dma_in; + end if; + end process; + + end generate; + + no_lpc_gen: if not HAS_LPC generate + lpc_data_o <= (others => '0'); + lpc_data_oe <= '0'; + lpc_irq_o <= '0'; + lpc_irq_oe <= '0'; + + wb_lpc_out.dat <= (others => '1'); + wb_lpc_out.ack <= wb_lpc_in.cyc and wb_lpc_in.stb; + wb_lpc_out.stall <= wb_lpc_in.cyc and not wb_lpc_out.ack; + end generate; + xics_icp: entity work.xics_icp port map( clk => system_clk, @@ -942,6 +1098,8 @@ begin int_level_in(2) <= uart1_irq; int_level_in(3) <= ext_irq_sdcard; int_level_in(4) <= gpio_intr; + int_level_in(5) <= lpc_vuart_irq; + int_level_in(6) <= lpc_ipmi_irq; end process; -- BRAM Memory slave