From 4c21587c4d0dcd6fdacf742fdd5454823919831e Mon Sep 17 00:00:00 2001
From: Michael Neuling <mikey@neuling.org>
Date: Mon, 8 Feb 2021 20:17:48 +1100
Subject: [PATCH] Fix DAR/DSISR reading before they are written

If the DAR and DSISR are read before they are written, we assert with:

  register_file.vhdl:55:25:@60195ns:(report note): Writing GPR 09 00000000XXXXXXXX
  register_file.vhdl:61:17:@60195ns:(assertion failure): Assertion violation

This initialises DAR/DSISR to avoid this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 loadstore1.vhdl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/loadstore1.vhdl b/loadstore1.vhdl
index ee4507b..3328617 100644
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@@ -275,6 +275,8 @@ begin
                 r2.wait_dc <= '0';
                 r2.wait_mmu <= '0';
                 r2.one_cycle <= '0';
+                r3.dar <= (others => '0');
+                r3.dsisr <= (others => '0');
                 r3.state <= IDLE;
                 r3.write_enable <= '0';
                 r3.interrupt <= '0';