From 5249d633cf65e37134da4afb841a95f4ec577e96 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 24 Feb 2022 10:18:28 +1100 Subject: [PATCH] Move register stage from after RAM to before RAM Signed-off-by: Anton Blanchard --- asic/main_bram.vhdl | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/asic/main_bram.vhdl b/asic/main_bram.vhdl index add4b29..b4c0762 100644 --- a/asic/main_bram.vhdl +++ b/asic/main_bram.vhdl @@ -34,30 +34,39 @@ architecture behaviour of main_bram is signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0); - signal obuf : std_logic_vector(WIDTH-1 downto 0); + signal addr_buf : std_logic_vector(HEIGHT_BITS-1 downto 0); + signal din_buf : std_logic_vector(WIDTH-1 downto 0); + signal sel_buf : std_logic_vector((WIDTH/8)-1 downto 0); + signal re_buf : std_ulogic; + signal we_buf : std_ulogic; begin assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE; -- Do we have a log2 round up issue here? assert (HEIGHT_BITS = 9) report "HEIGHT_BITS must be 10" severity FAILURE; assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE; - sel_qual <= sel when we = '1' else (others => '0'); + sel_qual <= sel_buf when we_buf = '1' else (others => '0'); memory_0 : RAM512 port map ( CLK => clk, WE0 => sel_qual(7 downto 0), - EN0 => re or we, - Di0 => din(63 downto 0), - Do0 => obuf(63 downto 0), - A0 => addr(8 downto 0) + EN0 => re_buf or we_buf, + Di0 => din_buf(63 downto 0), + Do0 => dout(63 downto 0), + A0 => addr_buf(8 downto 0) ); - -- The wishbone BRAM wrapper assumes a 1 cycle delay + -- The wishbone BRAM wrapper assumes a 1 cycle delay. + -- Since the DFFRAM already registers outputs, place this on the input side. memory_read_buffer: process(clk) begin if rising_edge(clk) then - dout <= obuf; + addr_buf <= addr; + din_buf <= din; + sel_buf <= sel; + re_buf <= re; + we_buf <= we; end if; end process; end architecture behaviour;