From 5a3cdc8b226393e1c2b77d44f9b5251a77b77a07 Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Fri, 14 Jan 2022 07:23:35 +0800
Subject: [PATCH] litedram: disable block_until_ready, regenerate

Recent litedram gets stuck at memtest unless block_until_ready=False.
(discussion in https://github.com/enjoy-digital/litedram/pull/292)

This change regenerates with latest litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
---
 litedram/gen-src/acorn-cle-215.yml            |    1 +
 litedram/gen-src/arty.yml                     |    1 +
 litedram/gen-src/genesys2.yml                 |    1 +
 litedram/gen-src/nexys-video.yml              |    1 +
 litedram/gen-src/sim.yml                      |    1 +
 litedram/gen-src/wukong-v2.yml                |    1 +
 .../acorn-cle-215/litedram_core.init          | 2165 ++--
 .../generated/acorn-cle-215/litedram_core.v   | 7961 ++++----------
 litedram/generated/arty/litedram_core.init    | 2165 ++--
 litedram/generated/arty/litedram_core.v       | 7831 ++++----------
 .../generated/genesys2/litedram_core.init     | 2882 +++--
 litedram/generated/genesys2/litedram_core.v   | 9355 ++++-------------
 .../generated/nexys-video/litedram_core.init  | 2165 ++--
 .../generated/nexys-video/litedram_core.v     | 8237 ++++-----------
 litedram/generated/sim/litedram_core.init     | 1545 +--
 litedram/generated/sim/litedram_core.v        | 8065 +++++++-------
 .../generated/wukong-v2/litedram-initmem.vhdl |    2 +-
 .../generated/wukong-v2/litedram_core.init    | 2165 ++--
 litedram/generated/wukong-v2/litedram_core.v  | 7831 ++++----------
 19 files changed, 19624 insertions(+), 42751 deletions(-)

diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml
index 0e3e9eb..034995c 100644
--- a/litedram/gen-src/acorn-cle-215.yml
+++ b/litedram/gen-src/acorn-cle-215.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml
index 22a0190..217d3eb 100644
--- a/litedram/gen-src/arty.yml
+++ b/litedram/gen-src/arty.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml
index ac1deeb..5acfc58 100644
--- a/litedram/gen-src/genesys2.yml
+++ b/litedram/gen-src/genesys2.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml
index 3752104..0772c96 100644
--- a/litedram/gen-src/nexys-video.yml
+++ b/litedram/gen-src/nexys-video.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml
index 22a0190..217d3eb 100644
--- a/litedram/gen-src/sim.yml
+++ b/litedram/gen-src/sim.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/gen-src/wukong-v2.yml b/litedram/gen-src/wukong-v2.yml
index 814b906..be0f76f 100644
--- a/litedram/gen-src/wukong-v2.yml
+++ b/litedram/gen-src/wukong-v2.yml
@@ -31,6 +31,7 @@
     "user_ports": {
         "native_0": {
             "type": "native",
+            "block_until_ready": False,
         },
     },
 }
diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init
index 5b1a383..1b6e88e 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
@@ -518,7 +518,7 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842afc4
+7c0802a63842adc4
 fbe1fff8fbc1fff0
 f821ff51f8010010
 f88100d83bc10020
@@ -527,96 +527,97 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-600000004800245d
+6000000048002159
 7fc3f3787c7f1b78
-6000000048001e69
+6000000048001b7d
 7fe3fb78382100b0
-0000000048002a54
+00000000480027d4
 0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842af203c4c0001
+3842ad203c4c0001
 7d8000267c0802a6
-9181000848002991
-48001e65f821fed1
+9181000848002711
+48001b79f821fed1
 3c62ffff60000000
-4bffff3938637b10
+4bffff3938637a90
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637b30
+63ff000838637ab0
 3c62ffff4bffff15
-38637b507bff0020
+38637ad07bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b68
+4bfffee938637ae8
 4e00000073e90002
 3c62ffff41820010
-4bfffed138637b70
+4bfffed138637af0
 4d80000073e90004
 3c62ffff41820010
-4bfffeb938637b78
+4bfffeb938637af8
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b80
+4bfffea138637b00
 4182001073e90010
-38637b903c62ffff
-73e901004bfffe8d
+38637b103c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637ba0
-3b7b7ba83f62ffff
+4bfffe7938637b20
+3b7b7b283f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bb0
+4bfffe4138637b30
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637bc8
+4bfffe1938637b48
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637be07884b282
+38637b607884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637bf87c892392
+38637b787c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637c187f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637b98
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,182 +625,161 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637c38
-4082009073890002
-38637c583c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637bb857a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637bd8
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637c70
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637c807fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847cb038a57ca0
-4bfffb8938637cb8
-6000000048000f2d
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637bf03c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637c007b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637c3038a57c20
+4bfffb897ca42b78
+6000000048000c55
 3c62ffff418e0024
-4bfffb7138637ce8
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637c60
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637d00
-38a000403c9df000
+4bfffb4938637c78
+38a000403c9af000
 3861007078840020
-6000000048001cbd
+6000000048001889
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637d18
+794a83e438637c90
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637d383c62ffff
+38637cb03c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d9888810070
+38637d1088810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637dc8
+4bfffaa938637d40
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-6000000048001c15
-38637de83c62ffff
+60000000480017e1
+38637d603c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187d503b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637d783c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff000480024a8
-7884002038a00038
-48001b917f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-48001b497f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637c68
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
+3ba000003f02ffff
+3b187cc83b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637cf0
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+4800222c7d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048001761
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+6000000048001719
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637be83c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061291004
+7c604f2a7c0004ac
+392000013d40c800
+794a0020614a1008
 7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
+000000004e800020
 0000000000000000
-3d20c80000000000
-612900045463063e
+3842a6f83c4c0001
+4182006828030002
+4182003028030003
+4082007c28030001
+6129101c3d20c800
 7c0004ac79290020
-3d40c8007c604f2a
-614a000839200001
-7c0004ac794a0020
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a8ac
-2803000341820068
-2803000141820030
-3d20c8004082007c
-7929002061290038
+3d40c8007c804f2a
+614a102039200001
+3d20c80048000024
+792900206129104c
 7c804f2a7c0004ac
 392000013d40c800
-48000024614a003c
-612900a03d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a00a439200001
-7c0004ac794a0020
-4e8000207d20572a
-6129006c3d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a007039200001
-7c8307b44bffffd0
-000000004bffff24
-0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
-7c604f2a7c0004ac
-610810143d00c800
-7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+794a0020614a1050
+7d20572a7c0004ac
+3d20c8004e800020
+7929002061291034
+7c804f2a7c0004ac
+392000013d40c800
+4bffffd0614a1038
+4bffff287c8307b4
 0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
+3d20c80000000000
+6129081039400001
+792900207d431830
 7c604f2a7c0004ac
-610810183d00c800
+610808143d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
 394000013d20c800
-7d43183061291010
+7d43183061290810
 7c0004ac79290020
 3d00c8007c604f2a
-790800206108101c
+7908002061080818
 7d40472a7c0004ac
 7c0004ac39400000
 4e8000207d404f2a
 0000000000000000
 3d20c80000000000
-6129101039400001
+6129081039400001
 792900207d431830
 7c604f2a7c0004ac
-610810203d00c800
+6108081c3d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
@@ -809,592 +789,524 @@ a12100a660000000
 4182001c28030003
 4082004028030001
 392000003d40c800
-48000010614a0048
+48000010614a1028
 392000003d40c800
-794a0020614a00b0
+794a0020614a1058
 7d20572a7c0004ac
 3d40c8004e800020
-614a007c39200000
+614a104039200000
 3d40c8004bffffe4
-614a001439200000
+614a101039200000
 000000004bffffd4
 0000000000000000
-3842a6583c4c0001
-4182006828030002
-4182003028030003
-4082007c28030001
+4182004028030002
+4182001c28030003
+4082004028030001
 392000003d40c800
-794a0020614a0040
-7d20572a7c0004ac
-614a00443d40c800
-3d40c80048000024
-614a00a839200000
-7c0004ac794a0020
-3d40c8007d20572a
-794a0020614a00ac
+48000010614a1024
+392000003d40c800
+794a0020614a1054
 7d20572a7c0004ac
 3d40c8004e800020
-614a007439200000
-7c0004ac794a0020
-3d40c8007d20572a
-4bffffd0614a0078
-4bfffc9438600000
-0000000000000000
-2c03000000000000
-3929000178690020
-3920000140800008
-3929ffff2c290001
-600000004d820020
-000000004bfffff0
-0000000000000000
-3842a5783c4c0001
-48001ffd7c0802a6
-3ce08020f821ffa1
-60e700033bc10020
-7fcaf3787c7c1b78
-78e700203be00004
-3920000039000004
-7888f8427d0903a6
+614a103c39200000
+3d40c8004bffffe4
+614a100c39200000
+000000004bffffd4
+0000000000000000
+786900202c030000
+4080000839290001
+2c29000139200001
+4d8200203929ffff
+4bfffff060000000
+0000000000000000
+3c4c000100000000
+7c0802a63842a454
+f821ffa148001e59
+60a500033ca08020
+394000007c7e1b78
+78a5002038c1001f
+3b81002039000004
+7ce652147d0903a6
+7888f86239200004
 7c8400d0788407e0
-7c8642787c843838
-7cca49ae7cc43378
-4200ffe039290001
-394a0004393fffff
-4082ffc4793f0021
-4bfffbdd38600000
-392000003d40c800
-794a0020614a0014
+7c8428383929ffff
+7d0443787c884278
+4200ffe09d070001
+282a0010394a0004
+3d40c8004082ffc0
+794a0020614a100c
 7d20572a7c0004ac
-4bfffbf938600009
-4bffff313860000f
-3ce0c8003d40c800
-60e700f8614a0028
-794a00207fc9f378
-38c0000478e70020
-7cc903a6394afff0
-8cc800013909ffff
-7cc0572a7c0004ac
-4200fff0394a0004
-39290004394a0034
-4082ffd07c2a3800
-63bd10303fa0c800
+614a10103d40c800
+7c0004ac794a0020
+386000097d20572a
+3860000f4bfffc85
+3d20c8004bffff29
+612910143cc0c800
+7f8ae37860c61074
+78c6002079290020
+38eaffff38a00004
+3be000047ca903a6
+8ca7000139000000
+7905400c3bffffff
+4200fff07ca82b78
+7ca04f2a7c0004ac
+394a000439290018
+4082ffc47c293000
+63bd08303fa0c800
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffe21
+7c0004ac4bfffe41
 5463063e7c60ee2a
-7c0004ac4bfffd99
-388000177fa0ee2a
-3fa0c80057a3063e
-63bd102c4bfffba5
-4bfffe913860000f
+7c0004ac4bfffdc1
+388000177c60ee2a
+3fa0c8005463063e
+63bd082c4bfffc21
+4bfffe7d3860000f
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffdd9
+7c0004ac4bfffdf9
 5463063e7c60ee2a
-7c0004ac4bfffd51
-388000257fa0ee2a
-4bfffb6157a3063e
-4bfffe513860000f
-4bfffacd38600000
-392000003d40c800
-794a0020614a0014
-7d20572a7c0004ac
-3ba100303860000b
-3860000f4bfffae5
-3ce0c8004bfffe1d
-60e700283d60c800
-3c8033333c005555
-616b00f83d800f0f
-78e7002038c00000
-60005555207c0001
-618c0f0f60843333
-7c0004ac796b0020
-992100307d203e2a
-7c0004ac39270004
-992100317d204e2a
-7c0004ac39270008
-992100327d204e2a
-7c0004ac3927000c
-992100337d204e2a
-38a0000039200004
-7d2532147d2903a6
-7c091800552907fe
-7d45e8ae40820058
-7d0852787d1e28ae
-5509063e790afe62
-7d4a48507d4a0038
-554af0be7c895038
-7d4952147d4a2038
-7d2952145549e13e
-552ac23e7d894838
-552a843e7d295214
-552906be7d295214
-793f00207d29fa14
-4200ff9838a50001
-38c6000438e70034
-3bde00047c275800
-4082ff3878c60020
-7fe3fb7838210060
-0000000048001d98
-0000048001000000
-3842a2a83c4c0001
-7d9080267c0802a6
-48001d2191810008
-2e250000f821ff71
-4192001c7c7e1b78
-7c641b787c852378
-38637e003c62ffff
-600000004bfff2b5
-3f62ffff7fc3f378
-3b8000204bfffa61
-3b7b7e103ba00000
-7fc3f3783880002a
-388000544bfffcd9
-7fc3f3787c7f1b78
-7d3f1a144bfffcc9
-212900807d240034
-548360265484d97e
-7fa9ea147d234a14
-419200107bbd0020
-4bfff2517f63db78
-7fc3f37860000000
-4bfffa4d3b9cffff
-4082ffa47b9c0021
-3c62ffff41920014
-4bfff22938637e18
-3821009060000000
-818100087fa3eb78
-48001ca87d908120
-0300000000000000
-3c4c000100000580
-7c0802a63842a1bc
-f821ff7148001c39
+7c0004ac4bfffd79
+388000257c60ee2a
+4bfffbdd5463063e
+4bfffe3d3860000f
+6129100c3d20c800
+7c0004ac79290020
+3d20c8007fe04f2a
+7929002061291010
+7fe04f2a7c0004ac
+23de00013860000b
+3860000f4bfffb5d
+3d00c8004bfffe01
+610810183c80c800
+3ca033333d605555
+608410783c000f0f
+7908002038c00000
+616b555538610030
+60000f0f60a53333
+7c0004ac78840020
+394100307d20462a
+392000047d20552c
+7d2903a639400000
+552907fe7d265214
+408200547c09f000
+7d3c50ae7cea18ae
+5527063e7d293a78
+7d2958387929fe62
+7d2728387d293850
+7d2928385529f0be
+54e9e13e7ce74a14
+7d2900387d293a14
+7d293a145527c23e
+7d293a145527843e
+7fff4a14552906be
+4200ff9c394a0001
+3b9c000439080018
+38c600047c282000
+382100604082ff6c
+48001c0c7be30020
+0100000000000000
+3c4c000100000480
+7c0802a63842a19c
+f821ff7148001b99
 7c7f1b783ba00000
-3880002a4bfff9a1
-4bfffc257fe3fb78
-7c7e1b7838800054
-4bfffc157fe3fb78
-7d3c07b4393d0001
-2c0300007c7e1a14
-2c0900204182001c
-7fe3fb784182007c
-4bfff9ad7f9de378
-7fbeeb784bffffbc
-3b5d00017fe3fb78
-7f5a07b44bfff999
-3880002a3b60ffff
-4bfffbc57fe3fb78
-7c7c1b7838800054
-4bfffbb57fe3fb78
-2c0300007c7c1a14
-2c1bffff41820010
-7f5bd37840820008
-2c09001f393a0001
-4181001c7d3a07b4
-4bfff9457fe3fb78
-7f9de3784bffffb4
-4bffff943bc0ffff
-395d00022c1d001e
-4181000839200000
-2c1bffff213d001e
-7d2907b47d295214
-7d3b4b7840820008
-7fbeda142c1effff
+3880002a4bfffb35
+4bfffd297fe3fb78
+3b9d000138800054
+7fe3fb787c7e1b78
+7c63f2144bfffd15
+4182001c2c030000
+418200742c1c0020
+7f9de3787fe3fb78
+4bffffc04bfffb41
+7fe3fb787fbeeb78
+4bfffb2d3b7d0001
+3880002a3b80ffff
+4bfffcd17fe3fb78
+7c7a1b7838800054
+4bfffcc17fe3fb78
+2c0300007c63d214
+2c1cffff41820010
+7f7cdb7840820008
+2c1b001f3b7b0001
+7fe3fb784181001c
+4bffffb84bfffae1
+3bc0ffff3ba00020
+2c1d001e4bffff9c
+39200000395d0002
+213d001e41810008
+7d2952142c1cffff
+7d3c4b7840820008
+7fbee2142c1effff
 7fbd01947fbd0e70
-408200387bbd06e0
-38637e203c62ffff
-600000004bfff0dd
+4082003857bd06fe
+38637d783c62ffff
+600000004bfff2cd
 3bc000007fe3fb78
-386000644bfff889
-7c1df0004bfffad5
+386000644bfffa2d
+7c1df0004bfffbe9
 3821009040820034
-7cbed85048001b48
+7cbee05048001ab8
 7ca50e703c62ffff
-7fa4eb787ca50194
-7ca507b438637e30
-600000004bfff095
+7fa407b47ca50194
+7ca507b438637d88
+600000004bfff285
 7fe3fb784bffffb8
-4bfff88d3bde0001
-7fde07b438600064
-4bffffb04bfffa85
-0100000000000000
-3c4c000100000680
-3d40c8003842a01c
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c09000e
-f80100107c0802a6
-3920000ef821ffa1
-7d20572a7c0004ac
-38637e483c62ffff
-600000004bfff01d
-e801001038210060
-4e8000207c0803a6
+4bfffa2d3bde0001
+4bfffb9d38600064
+000000004bffffb4
+0000068001000000
+3842a0103c4c0001
+612910003d20c800
+7c0004ac79290020
+280a000e7d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac3940000e
+3c62ffff7d404f2a
+4bfff21138637da0
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429fa83c4c0001
+612910003d20c800
+7c0004ac79290020
+280a00017d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac39400001
+3c62ffff7d404f2a
+4bfff1a938637dc8
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429f403c4c0001
+4800190d7c0802a6
+3f80c800f821ff01
+3ea2ffff3f00c800
+3e62ffff3e82ffff
+639c08103f22ffff
+3e42ffff63180820
+3b4000013ba00000
+3ab57df03ae00000
+3a737e083a947e00
+7b9c00203b397b28
+3a527e107b180020
+7fb0eb787ba307e0
+7f56e8304bfff925
+3a2000003be00000
+7fbe07b439e00000
+7fc4f3787de507b4
+39c000207ea3ab78
+600000004bfff0f5
+3b6000007fc3f378
+3880002a4bfff855
+4bfffa497fc3f378
+39ceffff38800054
+7fc3f378f8610060
+e92100604bfffa35
+7c6400347c634a14
+5484d97e20630080
+7c8407b454896026
+7e83a3787d291a14
+4bfff0997f7b4a14
+7fc3f37860000000
+2c0e00004bfff849
+7e639b784082ffa4
+600000004bfff07d
+4bfffc997fc3f378
+4bfff0697f23cb78
+7c11d84060000000
+7dff7b784080000c
+2c0f00077f71db78
+7c0004ac4182002c
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+39ef00017ee0e72a
+3ba000014bffff28
+7fe507b44bffff00
+7e4393787fc4f378
+4bfff0117bff0020
+7a0307e060000000
+393f00014bfff80d
+420000287d2903a6
+4bfffc197fc3f378
+4bffefe97f23cb78
+2c1d000160000000
+382101004082ffb4
+7c0004ac480017b8
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+4bffffc07ee0e72a
 0100000000000000
-3c4c000100000080
-3d40c80038429fb4
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c090001
-f80100107c0802a6
-39200001f821ffa1
-7d20572a7c0004ac
-38637e703c62ffff
-600000004bffefb5
-e801001038210060
+3c4c000100001280
+7c0802a638429d64
+f821ffa1f8010010
+386000004bfffd49
+386000004bfff6fd
+386000014bfff78d
+386000014bfff6ed
+3c62ffff4bfff77d
+4bffef6938637e28
+4bfffde560000000
+382100604bfffd79
+e801001038600001
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429f4c
-f821ff61480019c1
-3f42ffff3be00000
-3b5a7ba83f02ffff
-57fd063e3b187e98
-7fa3eb783b600000
-4bfff7b53b200000
-38a000013bc00000
-7fe3fb787fc4f378
-7c7c1b784bfffc61
-4bfffd417fe3fb78
-4bffef317f43d378
-7c19e04060000000
-7fdbf3784080000c
-2c1e00077f99e378
-7fa3eb7841820020
-4bfff7b13bde0001
-4bffffb07fde07b4
-4bffff903be00001
-7fe4fb787f65db78
-3bc000007f03c378
-600000004bffeee5
-4bfff7357fa3eb78
-408200287c1ed800
-4bfffcd17fe3fb78
-4bffeec17f43d378
-2c1f000160000000
-382100a04082ffb8
-7fa3eb7848001938
-4bfff7493bde0001
-4bffffc47fde07b4
-0100000000000000
-3c4c000100000880
-7c0802a638429e44
-f821ff1148001895
-4bfffe193f60c800
-3f20c80038600000
-386000004bfff621
-4bfff6b53ee0c800
-637b101038600001
-386000014bfff609
-4bfff69d63391024
-62f710283c62ffff
-3ec2ffff38637eb0
-600000004bffee2d
-3be000003ea2ffff
-7b7b00203ba00001
-7af700207b390020
-3ad67ed83b000000
-7ffa07b43ab57ed0
-7fb1f8307fb2f830
-3a6000003b80ffff
-57f4063e3bc00000
-7e20df2a7c0004ac
-7fa0cf2a7c0004ac
-392900017bc90020
-420000f47d2903a6
-7f00df2a7c0004ac
-3a0000007e83a378
-39e000004bfff611
-7de47b7838a00000
-4bfffabd7f43d378
-7c691b787c038040
-7e09837840800008
-793000207e83a378
-392f00014bfff62d
-7d2f07b42c090008
-7c1098404082ffc8
-7fdcf3784081000c
-393e00027e138378
-7d3e07b42c090008
-600000004082ff70
-7be91764394280d0
-2c1e00007fca4aaa
-2c1cffff40800078
-7f44d3784082006c
-4bffed297ea3ab78
-7f9ee37860000000
-7e40df2a7c0004ac
-7fa0cf2a7c0004ac
-7bc900202c1e0000
-4080000839290001
-2c29000139200001
-408200443929ffff
-7f00df2a7c0004ac
-41820040283f0001
-4bfffed83be00001
-7fa0bf2a7c0004ac
-7f9ee3784bffff04
-7f44d3787fc5f378
-4bffecb97ec3b378
-4bffff9460000000
-7fa0bf2a7c0004ac
-3c62ffff4bffffac
-4bffec9938637ba8
-3c62ffff60000000
-4bffec8938637ee0
-4bfffcf960000000
-382100f04bfffc8d
-480016d838600001
-0100000000000000
-3c4c000100001180
-7c0802a638429c1c
-f821ff6148001691
-6129102c3d20c800
-792900203b200002
+7c0802a638429cf4
+f821ff51480016e5
+6129082c3d20c800
+792900203b000002
+7f004f2a7c0004ac
+3b2000033d20c800
+7929002061290830
 7f204f2a7c0004ac
-3b4000033d20c800
-7929002061291030
-7f404f2a7c0004ac
 3c62ffff3fc0c800
-38637ef03c804000
-4bffec0963de1000
-3ba0000160000000
-7bde00204bfffba5
-7fa0f72a7c0004ac
+38637e383c804000
+4bffeee163de0800
+3b80000160000000
+7bde00204bfffc89
+7f80f72a7c0004ac
 3be00000386003e8
-7c0004ac4bfff5f5
-3f80c8007fe0f72a
-639c0800386003e8
-7b9c00204bfff5dd
-7fe0e72a7c0004ac
-637b08043f60c800
+7c0004ac4bfff7f1
+386003e87fe0f72a
+4bfff7dd3f60c800
 7c0004ac7b7b0020
-3fc0c8007fe0df2a
-63de001438600000
-7bde00204bfff231
-7fe0f72a7c0004ac
-3920000c3f00c800
-7c0004ac7b180020
-386000007d20c72a
-4bfff5816063c350
-4bfff1fd38600000
+3f40c8007fe0df2a
+7b5a0020635a0004
+7fe0d72a7c0004ac
+63bd100c3fa0c800
+7c0004ac7bbd0020
+3fc0c8007fe0ef2a
+7bde002063de1010
 7fe0f72a7c0004ac
-7c0004ac3920000e
-386027107d20c72a
-386002004bfff55d
-7c0004ac4bfff1d9
+3920000c3ee0c800
+7af7002062f71000
+7d20bf2a7c0004ac
+6063c35038600000
+7c0004ac4bfff771
+7c0004ac7fe0ef2a
+3920000e7fe0f72a
+7d20bf2a7c0004ac
+4bfff74d38602710
+7c0004ac39200200
+7c0004ac7d20ef2a
+3860000f7f00f72a
+7c0004ac4bfff485
+7c0004ac7fe0ef2a
 3860000f7f20f72a
-386000004bfff205
-7c0004ac4bfff1c1
-3860000f7f40f72a
-386000064bfff1ed
-7c0004ac4bfff1a9
-3860000f7fa0f72a
-386009304bfff1d5
-7c0004ac4bfff191
+392000064bfff46d
+7d20ef2a7c0004ac
+7f80f72a7c0004ac
+4bfff4513860000f
+7c0004ac39200930
+7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff1bd
-386004004bfff4f5
-7c0004ac4bfff171
-386000037fe0f72a
-386000c84bfff19d
-4bfffc414bfff4d5
-3c8000204bfffacd
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100a07fa0e72a
-38c0000048001518
-3c80002038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000088001000000
-38429a103c4c0001
+386000c84bfff435
+392004004bfff6d9
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfff41138600003
+4bfff6b5386000c8
+4bfffb954bfffddd
+3c6040003c800020
+6000000048000779
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100b07f80df2a
+480015487d2307b4
+38a0000038c00000
+3c6040003c800020
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000980
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+38429a883c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637f103c62ffff
-600000004bffea2d
+38637e583c62ffff
+600000004bffeca5
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffe9f138637f18
+4bffec6938637e60
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637f28
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e70
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637f387ca54b92
+38637e807ca54b92
 000000004bffffa4
 0000008001000000
-384299403c4c0001
+384299b83c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bffe95138637f48
+4bffebc938637e90
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffe93938637f58
+4bffebb138637ea0
 3821007060000000
-00000000480013e8
+00000000480013e0
 0000018001000000
-384298d83c4c0001
-4800135d7c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bffe959
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bffe929
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d000048001330
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+384299503c4c0001
+480013557c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bffebc9
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bffeb79
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f8
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384297f03c4c0001
-480012797c0802a6
+384298403c4c0001
+480012497c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
-4bffe8657bff0020
-395f000160000000
-7d4903a62fbe0000
+420000387cbd2b78
+4bffeabd7bff0020
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126838210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e00284800123c
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a6384296ec
-480011557d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67f60
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384297583c4c0001
+7d8000267c0802a6
+918100084800113d
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67ea8
 3c62ffff4082009c
-38637f607b251028
-4bfffd357ba40020
-38637ba83c62ffff
-600000004bffe6a5
-4bffe70d3ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637f7078a51028
-4bfffccd7ba40020
-38637ba83c62ffff
-600000004bffe63d
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637f707ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fac7d838120
+38637ea87b851028
+4bfffd357b240020
+38637b283c62ffff
+600000004bffe91d
+600000004bffe989
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637eb87b051028
+4bfffcdd7be40020
+38637b283c62ffff
+600000004bffe8c5
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010ac
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637eb87ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a6384294d4
+3c4c000100000b80
+7c0802a638429594
 918100087d908026
-f821ff8148000f51
+f821ff7148000f89
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637f80
-600000004bffe4dd
-38637f983c62ffff
+7cbc2b7838637ec8
+600000004bffe79d
+38637ee03c62ffff
 3c62ffff4092000c
-4bffe4c138637fa8
+4bffe78138637ef0
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637fb83c62ffff
-600000004bffe4a5
+4bfffaad7bfde8c2
+38637f003c62ffff
+600000004bffe765
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1403,467 +1315,475 @@ f821ff8148000f51
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637fc0
-600000004bffe455
-4bfff9fd7f83e378
-38637fd03c62ffff
-600000004bffe43d
-38637ba83c62ffff
-600000004bffe42d
-600000004bffe499
-409200287cf602a6
+7f9c4b9238637f08
+600000004bffe715
+4bfffa457f83e378
+38637f183c62ffff
+600000004bffe6fd
+38637b283c62ffff
+600000004bffe6ed
+600000004bffe759
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637fd8
-600000004bffe3a5
-4bfff94d7fe3fb78
-38637fd03c62ffff
-600000004bffe38d
-38637ba83c62ffff
-600000004bffe37d
-8181000838210080
-48000e047d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a6384292cc
-f821ff7148000d49
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f8000
-3b60ffff4081000c
-3c62ffff577b0420
-38637fe87fc4f378
-600000004bffe2c5
-4bfff86d7fe3fb78
-38637fb83c62ffff
-600000004bffe2ad
-7fc3f3787f44d378
-38a000004bfff989
-7c7c1b787f64db78
-4bfffa5d7fc3f378
-38a0000138c00000
-7c7d1b787fe4fb78
-4bfffb497fc3f378
-7d291a147d3cea14
-2c0900007c7e1b78
-3c62ffff41820068
-7f84e3787b45f882
-4bffe24938637ff8
-6000000060000000
-7fa4eb787b65f082
-4bffe23138628010
-6000000060000000
-7fc4f3787be5f082
-4bffe21938628028
-6000000060000000
-4bffe20938628040
-3860000060000000
-48000c8c38210090
-3862805060000000
-600000004bffe1ed
-4bffffe438600001
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f20
+600000004bffe675
+4bfff9a57fe3fb78
+38637f183c62ffff
+600000004bffe65d
+38637b283c62ffff
+600000004bffe64d
+8181000838210090
+48000e4c7d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384293b83c4c0001
+48000db57c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f80007c9a2378
+4081000c7ffbfb78
+577b04203b60ffff
+7fc4f3783c62ffff
+4bffe5b138637f30
+7fe3fb7860000000
+3c62ffff4bfff8e1
+4bffe59938637f00
+7f44d37860000000
+4bfff9fd7fc3f378
+7f64db7838a00000
+7fc3f3787c7c1b78
+38c000004bfffaf9
+7fe4fb7838a00001
+7fc3f3787c7d1b78
+7d3de2144bfffbc9
+7c7e1b787d291a14
+4182006c2c090000
+7b45f8823c62ffff
+38637f407f84e378
+600000004bffe535
+7b65f0823c62ffff
+38637f587fa4eb78
+600000004bffe51d
+7be5f0823c62ffff
+38637f707fc4f378
+600000004bffe505
+38637f883c62ffff
+600000004bffe4f5
+3821009038600000
+48000cf47c6307b4
+38637f983c62ffff
+600000004bffe4d5
+4bffffe038600001
 0100000000000000
 3c4c000100000680
-600000003842918c
-6000000039228114
-89290000394280c8
-4182002c2c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-7c0004ace92a0000
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-e94a00005469063e
-7d2057ea7c0004ac
-000000004e800020
+6000000038429274
+6000000089228018
+2c09000039428010
+e92a00004182002c
+7c0004ac39290014
+712900207d204eaa
+e92a00004182ffec
+7c604faa7c0004ac
+e92a00004e800020
+7c0004ac39290010
+712900087d204eea
+5469063e4082ffec
+7c0004ace94a0000
+4e8000207d2057ea
 0000000000000000
-384291083c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-3be3fffff821ffd1
-2c3e00008fdf0001
-3821003040820010
-48000bd038600000
-4082000c281e000a
-4bffff413860000d
-4bffff397fc3f378
-000000004bffffd0
-0000028001000000
-384290a83c4c0001
-610800203d00c000
-7c0004ac79080020
-3d20c0007d0046ea
-6129000879080600
-7c0004ac79290020
-712900207d204eea
-3d20c00041820018
-7929002061290040
+3c4c000100000000
+7c0802a6384291f4
+fbe1fff8fbc1fff0
+f821ffd1f8010010
+8fdf00013be3ffff
+408200102c1e0000
+3860000038210030
+2c1e000a48000c3c
+3860000d4082000c
+7fc307b44bffff45
+4bffffd04bffff3d
+0100000000000000
+3c4c000100000280
+3d40c00038429194
+794a0020614a0020
+7d4056ea7c0004ac
+794a06003d20c000
+7929002061290008
 7d204eea7c0004ac
-600000003d40c000
-38e2811460000000
-794a0020614a2000
-3d40001cf94280c8
-7d085392614a2000
-794a0fc3792af804
-3920000141820080
-614a200c3d40c000
-794a002099270000
-7c0004ac3920ff80
-e92280c87d2057aa
-7d004faa7c0004ac
-7908c202e92280c8
+4182001871290020
+612900403d20c000
+7c0004ac79290020
+7929f8047d204eea
+79290fc33d00c000
+7908002061082000
+f902801060000000
+610820003d00001c
+418200847d4a4392
+3920000160000000
+3d00c00099228018
+3920ff806108200c
+7c0004ac79080020
+e92280107d2047aa
+7d404faa7c0004ac
+794ac202e9228010
 7c0004ac39290004
-e92280c87d004faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e92280c8
+39290010e9228010
 7d404faa7c0004ac
-39400007e92280c8
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
-994700003d20c000
-612920183908ffff
-7c0004ac79290020
-4e8000207d004fea
+394affff60000000
+3d20c00099228018
+7929002061292018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9072442000028
+7d434a147ca92850
+7c844a1439050001
+392000007d0903a6
+4e80002042000018
+7d23512a7d24502a
+4bffffcc394a0008
+7d0a49ae7d0448ae
+4bffffdc39290001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 2c24000000000000
 3881fff040820008
 f864000028050024
 4d81002038600000
-78e783e43ce00001
-e944000060e72600
-28090020892a0000
-2c25000040810028
-2c0500104182003c
-3860000041820038
-394a000148000080
-4bffffd0f9440000
-712900017ce94c36
-2c2500004082ffec
-38a0000a4082ffdc
-38a0000a4bffffd4
-4082ffc828090030
-2c090078892a0001
-394a00024082ffbc
-f944000038a00010
-38c9ffd04bffffac
-280a000954ca063e
-7cc9073441810034
-4c8000207c092800
-7c6519d238e70001
-7c691a14f8e40000
-89270000e8e40000
-4082ffc82c290000
-3949ff9f4e800020
-280a0019554a063e
-3929ffa941810010
-4bffffbc7d290734
-554a063e3949ffbf
+6108ffff3d00fffe
+6108d9ff790883e4
+89490000e9240000
+40810028280a0020
+4182003c2c250000
+418200382c050010
+4800008838600000
+f924000039290001
+7d0a56344bffffd0
+4182ffec714a0001
+4082ffdc2c250000
+4bffffd438a0000a
+2c0a003038a0000a
+894900014082ffc8
+4082ffbc2c0a0078
+38a0001039290002
+4bffffacf9240000
+54e7063e38eaffd0
+4181003c28070009
+7d2a07343929ffd0
+4c8000207c0a2800
+7c6519d239080001
+f90400007d290734
+e90400007c691a14
+714900ff89480000
+4e8000204082ffc0
+54e7063e38eaff9f
+4181000c28070019
+4bffffb83929ffa9
+554a063e394affbf
 4d810020280a0019
-4bffffe43929ffc9
+4bffffa03929ffc9
 0000000000000000
-7c6a1b7800000000
-7d2a18ae38600000
-4d8200202c090000
-4bfffff038630001
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000307d2903a6
-78aa072478a9e8c2
-7d0352141d29fff8
-7ca92a147c845214
-3945000139200000
-420000187d4903a6
-7d24502a4e800020
-394a00087d23512a
-7d4448ae4bffffc4
-392900017d4849ae
-000000004bffffdc
-0000000000000000
-280900193923ff9f
-3863ffe04d810020
-4e8000207c6307b4
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428da4
-918100087d908026
-f821ffa148000819
-7c7c1b783be00000
-600000007cbe2b78
-7cdd3378e9228060
-60000000f9210020
-f9210028e9228068
-2c2900007ca92b78
-2c3f000040820034
-3be0000140820008
-2e2700007c3f2040
-3b7fffff38600000
-3821006040810038
-7d90812081810008
-281d001048000800
-7929e10240820014
-7fff07b43bff0001
-7d29eb924bffffb4
-7f5ed3784bfffff0
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-600000004bffff21
-7c3df0405463063e
-7c69d9aee93c0000
-4081ffc83b7bffff
-38600001e93c0000
-fbfc00007fe9fa14
-000000004bffff84
-0000068003000000
-38428ca83c4c0001
-480007297c0802a6
+38428e903c4c0001
+480008897c0802a6
+7c7e1b78f821ffa1
+7ca32b787c9c2378
+38a0000a38800000
+eb3e00007cfd3b78
+7d3a4b787d1b4378
+4bfffe797cdf3378
+2b9d001060000000
+7c681b7839200000
+408200242c3f0000
+408200082c090000
+7d29d21439200001
+418100547c034800
+4800087038210060
+7bffe102409e0010
+4bffffcc39290001
+4bfffff47fffeb92
+2c2a00019b690000
+e93e0000394affff
+f93e000039290001
+e93e00004182ffc8
+7c28e0407d194850
+4bffffb44180ffd8
+2c0900007d294050
+794a00203949ffff
+40810010394a0001
+7c0940003d008000
+394000014082ffcc
+000000004bffffc4
+0000078001000000
+38428d983c4c0001
+480007997c0802a6
 3bc00000f821ffb1
 7c9c23787c7f1b78
 7cbd2b78eb630000
-4bfffe217fa3eb78
-7c23f04060000000
-e95f000040810014
-7c29e0407d3b5050
-3821005041800010
-4800073038600001
-3bde00017d3df0ae
-e93f0000992a0000
-f93f000039290001
-000000004bffffb8
-0000058001000000
-38428c283c4c0001
-480006a17c0802a6
-7c7d1b78f821ffa1
-7ca32b787c9b2378
-38a0000a38800000
-eb3d00007d3f4b78
-7cfc3b787cde3378
-4bfffc717d1a4378
-3920000060000000
-2c3e00007c6307b4
-2c2900004082002c
-3920000140820008
-7c0348007d3f4a14
-418100607d2a07b4
-3860000038210060
-281c001048000684
-7bdee10240820014
-7d2907b439290001
-7fdee3924bffffbc
-9b4800004bfffff0
-3929ffff2c290001
-394a0001e95d0000
-4182ffbcf95d0000
-7d594050e91d0000
-4180ffd87c2ad840
-7d4a18504bffffa8
-392affff2c0a0000
-3929000179290020
-3c60800040810010
-4082ffcc7c0a1800
-4bffffc439200001
+4bfffd697fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007a4
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428b24
-f821fed148000571
-f86100607c741b79
-4182006438600000
-4182005c2c240000
-6000000039210040
-3ae4ffff60000000
-3b210020f9210078
-3a4280803ac00000
-3a2280783ba10060
+3c4c000100000580
+7c0802a638428d1c
+918100087d908026
+f821ffa148000711
+2b8600103be00000
+3d22ffff7c7c1b78
+7cbe2b78e9297fa8
+7caa2b787cdd3378
+3d22fffff9210020
+f9210028e9297fb0
+408200342c2a0000
+408200082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8181000838210060
+480006f47d908120
+794ae102409e0010
+4bffffbc3bff0001
+4bfffff47d4aeb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdad
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428c283c4c0001
+480005f57c0802a6
+3be00000f821fee1
+f86100607c691b79
+41820060f9210068
+418200582c240000
+3e62ffff39210040
+3ae4ffff3e22ffff
+3b010020f9210070
+3a4000203ac00000
+3ba100603a737fc8
+e94100683a317fc0
 ebc1006089250000
-418200102c290000
-7c3fb8407ff4f050
-3920000041800020
-e8610060993e0000
-7e8307b47e941850
-4800054438210130
-3945000128090025
-38e00000408204c4
-e901007889250000
-7cea07b4f8a10068
-390700017d2741ae
-7d0807b48d250001
-4182005828090064
-4182005028090069
-4182004828090075
-4182004028090078
-4182003828090058
-4182003028090070
-4182002828090063
-4182002028090073
-4182001828090025
-418200102809004f
-38e700012809006f
-394a00024082ff88
-7d4a07b428090025
-7d5952147d194214
-9aca002099280020
-393e000140820020
-39200025f9210060
-e9210068993e0000
-4bffff0438a90002
-eb66000039260008
-3a6000207fffb850
-f92100703b010041
-3929ffd289210041
+712a00ff7feaf050
+7c3fb8404182000c
+3920000041800018
+38210120993e0000
+480005c47fe307b4
+390500012c0a0025
+38e0000040820548
+e901007089250000
+7cea3b787cb02b78
+7d2741ae8c650001
+5469063e39070001
+418200b02c090064
+4181002c28090078
+4181002c28090068
+418200982c090058
+4181008828090058
+418200882c090025
+418200802c09004f
+4bffffa438e70001
+548b063e3883ff97
+4181ffec280b000f
+396b75043d62ffff
+7c8b22aa788415a8
+7c8903a67c845a14
+000000484e800420
+ffffffccffffffcc
+ffffffccffffffcc
+00000048ffffffcc
+ffffffcc00000048
+00000048ffffffcc
+00000048ffffffcc
+ffffffccffffffcc
+2c09006300000048
+394a00024bffff84
+7d0807b42c090025
+7d1842147d4a07b4
+986800207d585214
+408200189aca0020
+993e0000395e0001
+38b00002f9410060
+892100414bfffeb4
+7fffb850eb860000
+3aa0002039e60008
+3929ffd23b210041
 4082000c712900fd
-3b0100423a600030
-3b4000043aa00000
-3a0000013b800000
-7ddb00d039e0002d
-2809004f48000164
-3898000188f80001
-38c9ffa8418201d0
-2805002254c5063e
-3ca2ffff41810370
-78c615a838a576b8
-7cc62a147cc532aa
-4e8004207cc903a6
-0000035000000148
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000024400000350
-000003500000008c
-0000035000000350
-0000008c00000338
-0000035000000350
-0000035000000328
-000001a000000350
-00000350000001ec
-0000028400000350
-0000008c00000350
-0000035000000350
-000003500000014c
-2809007500000330
-9aca00207d41e214
-418200347f6adb78
-3929ffff57491838
-7f6948397e094836
-99e8000041820020
-39290001e9210060
-7b491f24f9210060
-7dca50387d52482a
+3b2100423aa00030
+3b4000043a800000
+56b5063e3b600000
+480001687ddc00d0
+38b900012c06004f
+38e8ffa8418201dc
+2804002254e4063e
+3c82ffff418103ac
+78e715a838847600
+7ce722147ce43aaa
+4e8004207ce903a6
+0000038c00000150
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+000002580000038c
+0000038c0000008c
+0000038c0000038c
+0000008c00000370
+0000038c0000038c
+0000038c0000035c
+000001ac0000038c
+0000038c000001fc
+000002980000038c
+0000008c0000038c
+0000038c0000038c
+0000038c00000154
+2c06007500000368
+7d4152147b6a0020
+7f8ae3789aca0020
+5747183841820038
+38e7ffff39000001
+7f8840397d083836
+3940002d41820020
+9949ffff39290001
+7b491e68f9210060
+7dca50387d53482a
 7d465378e8810060
-f941008038e0000a
-392000007f25cb78
-7fa3eb787e689b78
+f941007838e0000a
+392000007f05c378
+7fa3eb787ea8ab78
 7c84f8507c9e2050
-e88100604bfffc31
-7ea7ab78e9410080
+e88100604bfffa79
+7a8707e0e9410078
 7c9e205038c0000a
 7c84f8507d455378
-4bfffa917fa3eb78
-893800003b180001
-2c290000e9010060
-7d5e405041820010
-4181fe887c3f5040
-4bfffe28e8c10070
-7d21e2143aa00001
-7c8af85038e00010
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffba9
-38c000107ea7ab78
-e96100807c9e2050
-4bffff787d655b78
-38e000087d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffb55f9610080
-7ea7ab78e8810060
+4bfffbc97fa3eb78
+891900003b390001
+710600ffe9210060
+7d5e485041820010
+4181fe847c3f5040
+4bfffe307de67b78
+7b6900203a800001
+7d214a1438e00010
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff9edf9610078
+7a8707e0e8810060
+7c9e205038c00010
+7d655b78e9610078
+7b6900204bffff74
+7d214a1438e00008
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff995f9610078
+7a8707e0e8810060
 7c9e205038c00008
-7d21e2144bffffac
-7f66db7838e00010
-9ac900207c8af850
-3920000239000020
-7fa3eb787f25cb78
-e88100604bfffb19
-7fa3eb787e258b78
+7b6900204bffffa8
+7d214a1438e00010
+7c8af8507f86e378
+9ac9002039000020
+392000027f05c378
+4bfff9557fa3eb78
+7e258b78e8810060
+7c9e20507fa3eb78
+4bfffa357c84f850
+7a8707e0e8810060
+7f85e37838c00010
+4bfffec87c9e2050
+390000207b690020
+38e0000a7d214a14
+7f05c37838c00001
+7c8af8509ac90020
+7fa3eb7839200000
+e92100604bfff8f9
+392900019b890000
+4bfffe94f9210060
+38a0000a7b680020
+f9410080f9210088
+388000007d014214
+9ac800207f03c378
+600000004bfff76d
+7f83e378f8610078
+600000004bfff735
+e9410080e9010078
+7c281840e9210088
+e88100604181003c
+7fa3eb787f85e378
 7c84f8507c9e2050
-e88100604bfffa81
-38c000107ea7ab78
-7c9e20507f65db78
-7d21e2144bfffed4
-38e0000a39000020
-9ac9002038c00001
-392000007f25cb78
-7fa3eb787c8af850
-e92100604bfffac1
-e92100609b690000
-f921006039290001
-7d21e2144bfffea0
-f901009038a0000a
-38800000f9410088
-9ac900207f23cb78
-600000004bfff72d
-7f63db78f8610080
-600000004bfff83d
-7c291840e9210080
-7d2348514081004c
-e9010090e9410088
-408200087d4af850
-e8c1006039200001
-7c2a38407ce83050
-38e0002040810024
-3929ffff2c290001
-e8e1006098e60000
-f8e1006038e70001
-e88100604082ffd4
-7fa3eb787f65db78
-7c84f8507c9e2050
-4bfffdfc4bfff989
-418200482807006c
-4bfffdec3b400008
-3b40000228070068
-7c9823784082fde0
-4bfffdd43b400001
-554a063e3949ffd0
-4181fdc4280a0009
-7f81e214395c0001
-795c0020993c0020
-7c9823784bfffdb0
-993e00004bffffb8
-e92100607d455378
-f921006039290001
-000000004bfffae8
+4bfffe2c4bfff979
+392900019a490000
+7c29184039000001
+f921006040820034
+7ce9f0504bffffcc
+7ce7fa147c634050
+2c2700007d4af850
+390000007c691a14
+40820008394a0001
+2c2a000139400001
+4082ffb4394affff
+4082ffc071080001
+893900014bffff8c
+4182004c2c09006c
+4bfffdbc3b400008
+3b40000289390001
+4082fdac2c090068
+3b4000017cb92b78
+3928ffd04bfffda0
+280900095529063e
+7b6900204181fd90
+7d214a143b7b0001
+4bfffd7c99090020
+4bffffb47cb92b78
+3bde0001993e0000
+fbc100607d054378
+000000004bfffa6c
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -1938,9 +1858,8 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -1982,10 +1901,6 @@ ebe1fff8e8010010
 20676e69746f6f42
 415244206d6f7266
 0000000a2e2e2e4d
-62202c64256d2020
-007c203a64323025
-0000000000006425
-000000000000207c
 203a7379616c6564
 000000000000002d
 203a7379616c6564
@@ -2001,15 +1916,13 @@ ebe1fff8e8010010
 7764726168206f74
 746e6f6320657261
 0000000a2e6c6f72
+62202c64256d2020
+007c203a64323025
+0000000000006425
+000000000000207c
 203a747365622020
 302562202c64256d
 6000000000206432
-616c206574697257
-61632079636e6574
-6f6974617262696c
-00000000000a3a6e
-0000202d3a64256d
-002064253a64256d
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v
index 41a3761..da66195 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@@ -1,9 +1,25 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:37
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire clk,
-	input wire rst,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:13
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire clk,
+	input  wire rst,
 	output wire pll_locked,
 	output wire [15:0] ddram_a,
 	output wire [2:0] ddram_ba,
@@ -12,9 +28,9 @@ module litedram_core(
 	output wire ddram_we_n,
 	output wire ddram_cs_n,
 	output wire [1:0] ddram_dm,
-	inout wire [15:0] ddram_dq,
-	inout wire [1:0] ddram_dqs_p,
-	inout wire [1:0] ddram_dqs_n,
+	inout  wire [15:0] ddram_dq,
+	inout  wire [1:0] ddram_dqs_p,
+	inout  wire [1:0] ddram_dqs_n,
 	output wire ddram_clk_p,
 	output wire ddram_clk_n,
 	output wire ddram_cke,
@@ -22,32 +38,38 @@ module litedram_core(
 	output wire ddram_reset_n,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [25:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [25:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [15:0] user_port_native_0_wdata_we,
-	input wire [127:0] user_port_native_0_wdata_data,
+	input  wire [15:0] user_port_native_0_wdata_we,
+	input  wire [127:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [127:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg  main_rst = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
@@ -55,7 +77,7 @@ wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
 wire main_reset;
-reg main_power_down = 1'd0;
+reg  main_power_down = 1'd0;
 wire main_locked;
 wire main_clkin;
 wire main_clkout0;
@@ -66,48 +88,48 @@ wire main_clkout2;
 wire main_clkout_buf2;
 wire main_clkout3;
 wire main_clkout_buf3;
-reg [3:0] main_reset_counter = 4'd15;
-reg main_ic_reset = 1'd1;
-reg main_a7ddrphy_rst_storage = 1'd0;
-reg main_a7ddrphy_rst_re = 1'd0;
-reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg main_a7ddrphy_wlevel_en_re = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg  [3:0] main_reset_counter = 4'd15;
+reg  main_ic_reset = 1'd1;
+reg  main_a7ddrphy_rst_storage = 1'd0;
+reg  main_a7ddrphy_rst_re = 1'd0;
+reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
+reg  main_a7ddrphy_wlevel_en_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
 wire main_a7ddrphy_wlevel_strobe_r;
-reg main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg main_a7ddrphy_dly_sel_re = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+reg  main_a7ddrphy_dly_sel_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_rst_r;
-reg main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_inc_r;
-reg main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg main_a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg main_a7ddrphy_wrphase_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg  main_a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+reg  main_a7ddrphy_wrphase_re = 1'd0;
 wire [15:0] main_a7ddrphy_dfi_p0_address;
 wire [2:0] main_a7ddrphy_dfi_p0_bank;
 wire main_a7ddrphy_dfi_p0_cas_n;
@@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
 wire main_a7ddrphy_dfi_p0_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
 wire main_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p0_rddata_valid;
 wire [15:0] main_a7ddrphy_dfi_p1_address;
 wire [2:0] main_a7ddrphy_dfi_p1_bank;
@@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
 wire main_a7ddrphy_dfi_p1_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
 wire main_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p1_rddata_valid;
 wire [15:0] main_a7ddrphy_dfi_p2_address;
 wire [2:0] main_a7ddrphy_dfi_p2_bank;
@@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
 wire main_a7ddrphy_dfi_p2_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
 wire main_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p2_rddata_valid;
 wire [15:0] main_a7ddrphy_dfi_p3_address;
 wire [2:0] main_a7ddrphy_dfi_p3_bank;
@@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
 wire main_a7ddrphy_dfi_p3_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
 wire main_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p3_rddata_valid;
 wire main_a7ddrphy_sd_clk_se_nodelay;
-reg main_a7ddrphy_dqs_oe = 1'd0;
+reg  main_a7ddrphy_dqs_oe = 1'd0;
 wire main_a7ddrphy_dqs_preamble;
 wire main_a7ddrphy_dqs_postamble;
 wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_dqspattern0 = 1'd0;
-reg main_a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dqspattern0 = 1'd0;
+reg  main_a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
 wire main_a7ddrphy_dqs_o_no_delay0;
 wire main_a7ddrphy_dqs_t0;
-reg [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
 wire main_a7ddrphy0;
 wire main_a7ddrphy_dqs_o_no_delay1;
 wire main_a7ddrphy_dqs_t1;
-reg [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
 wire main_a7ddrphy1;
-reg [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
 wire main_a7ddrphy_dq_oe;
 wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
 wire main_a7ddrphy_dq_o_nodelay0;
 wire main_a7ddrphy_dq_i_nodelay0;
 wire main_a7ddrphy_dq_i_delayed0;
 wire main_a7ddrphy_dq_t0;
-reg [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip03;
-reg [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay1;
 wire main_a7ddrphy_dq_i_nodelay1;
 wire main_a7ddrphy_dq_i_delayed1;
 wire main_a7ddrphy_dq_t1;
-reg [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip13;
-reg [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay2;
 wire main_a7ddrphy_dq_i_nodelay2;
 wire main_a7ddrphy_dq_i_delayed2;
 wire main_a7ddrphy_dq_t2;
-reg [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip21;
-reg [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay3;
 wire main_a7ddrphy_dq_i_nodelay3;
 wire main_a7ddrphy_dq_i_delayed3;
 wire main_a7ddrphy_dq_t3;
-reg [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip31;
-reg [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay4;
 wire main_a7ddrphy_dq_i_nodelay4;
 wire main_a7ddrphy_dq_i_delayed4;
 wire main_a7ddrphy_dq_t4;
-reg [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip41;
-reg [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay5;
 wire main_a7ddrphy_dq_i_nodelay5;
 wire main_a7ddrphy_dq_i_delayed5;
 wire main_a7ddrphy_dq_t5;
-reg [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip51;
-reg [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay6;
 wire main_a7ddrphy_dq_i_nodelay6;
 wire main_a7ddrphy_dq_i_delayed6;
 wire main_a7ddrphy_dq_t6;
-reg [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip61;
-reg [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay7;
 wire main_a7ddrphy_dq_i_nodelay7;
 wire main_a7ddrphy_dq_i_delayed7;
 wire main_a7ddrphy_dq_t7;
-reg [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip71;
-reg [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay8;
 wire main_a7ddrphy_dq_i_nodelay8;
 wire main_a7ddrphy_dq_i_delayed8;
 wire main_a7ddrphy_dq_t8;
-reg [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip81;
-reg [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay9;
 wire main_a7ddrphy_dq_i_nodelay9;
 wire main_a7ddrphy_dq_i_delayed9;
 wire main_a7ddrphy_dq_t9;
-reg [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip91;
-reg [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay10;
 wire main_a7ddrphy_dq_i_nodelay10;
 wire main_a7ddrphy_dq_i_delayed10;
 wire main_a7ddrphy_dq_t10;
-reg [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip101;
-reg [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay11;
 wire main_a7ddrphy_dq_i_nodelay11;
 wire main_a7ddrphy_dq_i_delayed11;
 wire main_a7ddrphy_dq_t11;
-reg [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip111;
-reg [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay12;
 wire main_a7ddrphy_dq_i_nodelay12;
 wire main_a7ddrphy_dq_i_delayed12;
 wire main_a7ddrphy_dq_t12;
-reg [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip121;
-reg [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay13;
 wire main_a7ddrphy_dq_i_nodelay13;
 wire main_a7ddrphy_dq_i_delayed13;
 wire main_a7ddrphy_dq_t13;
-reg [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip131;
-reg [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay14;
 wire main_a7ddrphy_dq_i_nodelay14;
 wire main_a7ddrphy_dq_i_delayed14;
 wire main_a7ddrphy_dq_t14;
-reg [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip141;
-reg [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay15;
 wire main_a7ddrphy_dq_i_nodelay15;
 wire main_a7ddrphy_dq_i_delayed15;
 wire main_a7ddrphy_dq_t15;
-reg [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip151;
-reg [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 wire [15:0] main_litedramcore_inti_p0_address;
 wire [2:0] main_litedramcore_inti_p0_bank;
-reg main_litedramcore_inti_p0_cas_n = 1'd1;
-reg main_litedramcore_inti_p0_cs_n = 1'd1;
-reg main_litedramcore_inti_p0_ras_n = 1'd1;
-reg main_litedramcore_inti_p0_we_n = 1'd1;
+reg  main_litedramcore_inti_p0_cas_n = 1'd1;
+reg  main_litedramcore_inti_p0_cs_n = 1'd1;
+reg  main_litedramcore_inti_p0_ras_n = 1'd1;
+reg  main_litedramcore_inti_p0_we_n = 1'd1;
 wire main_litedramcore_inti_p0_cke;
 wire main_litedramcore_inti_p0_odt;
 wire main_litedramcore_inti_p0_reset_n;
-reg main_litedramcore_inti_p0_act_n = 1'd1;
+reg  main_litedramcore_inti_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p0_wrdata;
 wire main_litedramcore_inti_p0_wrdata_en;
 wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
 wire main_litedramcore_inti_p0_rddata_en;
-reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
+reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_inti_p1_address;
 wire [2:0] main_litedramcore_inti_p1_bank;
-reg main_litedramcore_inti_p1_cas_n = 1'd1;
-reg main_litedramcore_inti_p1_cs_n = 1'd1;
-reg main_litedramcore_inti_p1_ras_n = 1'd1;
-reg main_litedramcore_inti_p1_we_n = 1'd1;
+reg  main_litedramcore_inti_p1_cas_n = 1'd1;
+reg  main_litedramcore_inti_p1_cs_n = 1'd1;
+reg  main_litedramcore_inti_p1_ras_n = 1'd1;
+reg  main_litedramcore_inti_p1_we_n = 1'd1;
 wire main_litedramcore_inti_p1_cke;
 wire main_litedramcore_inti_p1_odt;
 wire main_litedramcore_inti_p1_reset_n;
-reg main_litedramcore_inti_p1_act_n = 1'd1;
+reg  main_litedramcore_inti_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p1_wrdata;
 wire main_litedramcore_inti_p1_wrdata_en;
 wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
 wire main_litedramcore_inti_p1_rddata_en;
-reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
+reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_inti_p2_address;
 wire [2:0] main_litedramcore_inti_p2_bank;
-reg main_litedramcore_inti_p2_cas_n = 1'd1;
-reg main_litedramcore_inti_p2_cs_n = 1'd1;
-reg main_litedramcore_inti_p2_ras_n = 1'd1;
-reg main_litedramcore_inti_p2_we_n = 1'd1;
+reg  main_litedramcore_inti_p2_cas_n = 1'd1;
+reg  main_litedramcore_inti_p2_cs_n = 1'd1;
+reg  main_litedramcore_inti_p2_ras_n = 1'd1;
+reg  main_litedramcore_inti_p2_we_n = 1'd1;
 wire main_litedramcore_inti_p2_cke;
 wire main_litedramcore_inti_p2_odt;
 wire main_litedramcore_inti_p2_reset_n;
-reg main_litedramcore_inti_p2_act_n = 1'd1;
+reg  main_litedramcore_inti_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p2_wrdata;
 wire main_litedramcore_inti_p2_wrdata_en;
 wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
 wire main_litedramcore_inti_p2_rddata_en;
-reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
+reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_inti_p3_address;
 wire [2:0] main_litedramcore_inti_p3_bank;
-reg main_litedramcore_inti_p3_cas_n = 1'd1;
-reg main_litedramcore_inti_p3_cs_n = 1'd1;
-reg main_litedramcore_inti_p3_ras_n = 1'd1;
-reg main_litedramcore_inti_p3_we_n = 1'd1;
+reg  main_litedramcore_inti_p3_cas_n = 1'd1;
+reg  main_litedramcore_inti_p3_cs_n = 1'd1;
+reg  main_litedramcore_inti_p3_ras_n = 1'd1;
+reg  main_litedramcore_inti_p3_we_n = 1'd1;
 wire main_litedramcore_inti_p3_cke;
 wire main_litedramcore_inti_p3_odt;
 wire main_litedramcore_inti_p3_reset_n;
-reg main_litedramcore_inti_p3_act_n = 1'd1;
+reg  main_litedramcore_inti_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p3_wrdata;
 wire main_litedramcore_inti_p3_wrdata_en;
 wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
 wire main_litedramcore_inti_p3_rddata_en;
-reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
+reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_slave_p0_address;
 wire [2:0] main_litedramcore_slave_p0_bank;
 wire main_litedramcore_slave_p0_cas_n;
@@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata;
 wire main_litedramcore_slave_p0_wrdata_en;
 wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
 wire main_litedramcore_slave_p0_rddata_en;
-reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_slave_p1_address;
 wire [2:0] main_litedramcore_slave_p1_bank;
 wire main_litedramcore_slave_p1_cas_n;
@@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata;
 wire main_litedramcore_slave_p1_wrdata_en;
 wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
 wire main_litedramcore_slave_p1_rddata_en;
-reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_slave_p2_address;
 wire [2:0] main_litedramcore_slave_p2_bank;
 wire main_litedramcore_slave_p2_cas_n;
@@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata;
 wire main_litedramcore_slave_p2_wrdata_en;
 wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
 wire main_litedramcore_slave_p2_rddata_en;
-reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [15:0] main_litedramcore_slave_p3_address;
 wire [2:0] main_litedramcore_slave_p3_bank;
 wire main_litedramcore_slave_p3_cas_n;
@@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata;
 wire main_litedramcore_slave_p3_wrdata_en;
 wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
 wire main_litedramcore_slave_p3_rddata_en;
-reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [15:0] main_litedramcore_master_p0_address = 16'd0;
-reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg main_litedramcore_master_p0_cas_n = 1'd1;
-reg main_litedramcore_master_p0_cs_n = 1'd1;
-reg main_litedramcore_master_p0_ras_n = 1'd1;
-reg main_litedramcore_master_p0_we_n = 1'd1;
-reg main_litedramcore_master_p0_cke = 1'd0;
-reg main_litedramcore_master_p0_odt = 1'd0;
-reg main_litedramcore_master_p0_reset_n = 1'd0;
-reg main_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [15:0] main_litedramcore_master_p0_address = 16'd0;
+reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg  main_litedramcore_master_p0_cas_n = 1'd1;
+reg  main_litedramcore_master_p0_cs_n = 1'd1;
+reg  main_litedramcore_master_p0_ras_n = 1'd1;
+reg  main_litedramcore_master_p0_we_n = 1'd1;
+reg  main_litedramcore_master_p0_cke = 1'd0;
+reg  main_litedramcore_master_p0_odt = 1'd0;
+reg  main_litedramcore_master_p0_reset_n = 1'd0;
+reg  main_litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p0_rddata;
 wire main_litedramcore_master_p0_rddata_valid;
-reg [15:0] main_litedramcore_master_p1_address = 16'd0;
-reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg main_litedramcore_master_p1_cas_n = 1'd1;
-reg main_litedramcore_master_p1_cs_n = 1'd1;
-reg main_litedramcore_master_p1_ras_n = 1'd1;
-reg main_litedramcore_master_p1_we_n = 1'd1;
-reg main_litedramcore_master_p1_cke = 1'd0;
-reg main_litedramcore_master_p1_odt = 1'd0;
-reg main_litedramcore_master_p1_reset_n = 1'd0;
-reg main_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [15:0] main_litedramcore_master_p1_address = 16'd0;
+reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg  main_litedramcore_master_p1_cas_n = 1'd1;
+reg  main_litedramcore_master_p1_cs_n = 1'd1;
+reg  main_litedramcore_master_p1_ras_n = 1'd1;
+reg  main_litedramcore_master_p1_we_n = 1'd1;
+reg  main_litedramcore_master_p1_cke = 1'd0;
+reg  main_litedramcore_master_p1_odt = 1'd0;
+reg  main_litedramcore_master_p1_reset_n = 1'd0;
+reg  main_litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p1_rddata;
 wire main_litedramcore_master_p1_rddata_valid;
-reg [15:0] main_litedramcore_master_p2_address = 16'd0;
-reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg main_litedramcore_master_p2_cas_n = 1'd1;
-reg main_litedramcore_master_p2_cs_n = 1'd1;
-reg main_litedramcore_master_p2_ras_n = 1'd1;
-reg main_litedramcore_master_p2_we_n = 1'd1;
-reg main_litedramcore_master_p2_cke = 1'd0;
-reg main_litedramcore_master_p2_odt = 1'd0;
-reg main_litedramcore_master_p2_reset_n = 1'd0;
-reg main_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [15:0] main_litedramcore_master_p2_address = 16'd0;
+reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg  main_litedramcore_master_p2_cas_n = 1'd1;
+reg  main_litedramcore_master_p2_cs_n = 1'd1;
+reg  main_litedramcore_master_p2_ras_n = 1'd1;
+reg  main_litedramcore_master_p2_we_n = 1'd1;
+reg  main_litedramcore_master_p2_cke = 1'd0;
+reg  main_litedramcore_master_p2_odt = 1'd0;
+reg  main_litedramcore_master_p2_reset_n = 1'd0;
+reg  main_litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p2_rddata;
 wire main_litedramcore_master_p2_rddata_valid;
-reg [15:0] main_litedramcore_master_p3_address = 16'd0;
-reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg main_litedramcore_master_p3_cas_n = 1'd1;
-reg main_litedramcore_master_p3_cs_n = 1'd1;
-reg main_litedramcore_master_p3_ras_n = 1'd1;
-reg main_litedramcore_master_p3_we_n = 1'd1;
-reg main_litedramcore_master_p3_cke = 1'd0;
-reg main_litedramcore_master_p3_odt = 1'd0;
-reg main_litedramcore_master_p3_reset_n = 1'd0;
-reg main_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [15:0] main_litedramcore_master_p3_address = 16'd0;
+reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg  main_litedramcore_master_p3_cas_n = 1'd1;
+reg  main_litedramcore_master_p3_cs_n = 1'd1;
+reg  main_litedramcore_master_p3_ras_n = 1'd1;
+reg  main_litedramcore_master_p3_we_n = 1'd1;
+reg  main_litedramcore_master_p3_cke = 1'd0;
+reg  main_litedramcore_master_p3_odt = 1'd0;
+reg  main_litedramcore_master_p3_reset_n = 1'd0;
+reg  main_litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p3_rddata;
 wire main_litedramcore_master_p3_rddata_valid;
 wire main_litedramcore_sel;
 wire main_litedramcore_cke;
 wire main_litedramcore_odt;
 wire main_litedramcore_reset_n;
-reg [3:0] main_litedramcore_storage = 4'd1;
-reg main_litedramcore_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] main_litedramcore_storage = 4'd1;
+reg  main_litedramcore_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector0_command_issue_r;
-reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0;
-reg main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0;
+reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector0_rddata_we;
-reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector1_command_issue_r;
-reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0;
-reg main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0;
+reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector1_rddata_we;
-reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector2_command_issue_r;
-reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0;
-reg main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0;
+reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector2_rddata_we;
-reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector3_command_issue_r;
-reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0;
-reg main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0;
+reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector3_rddata_we;
-reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire main_litedramcore_interface_bank0_valid;
 wire main_litedramcore_interface_bank0_ready;
 wire main_litedramcore_interface_bank0_we;
@@ -706,131 +728,131 @@ wire [22:0] main_litedramcore_interface_bank7_addr;
 wire main_litedramcore_interface_bank7_lock;
 wire main_litedramcore_interface_bank7_wdata_ready;
 wire main_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
 wire [127:0] main_litedramcore_interface_rdata;
-reg [15:0] main_litedramcore_dfi_p0_address = 16'd0;
-reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg main_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [15:0] main_litedramcore_dfi_p0_address = 16'd0;
+reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p0_we_n = 1'd1;
 wire main_litedramcore_dfi_p0_cke;
 wire main_litedramcore_dfi_p0_odt;
 wire main_litedramcore_dfi_p0_reset_n;
-reg main_litedramcore_dfi_p0_act_n = 1'd1;
+reg  main_litedramcore_dfi_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p0_rddata;
 wire main_litedramcore_dfi_p0_rddata_valid;
-reg [15:0] main_litedramcore_dfi_p1_address = 16'd0;
-reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg main_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [15:0] main_litedramcore_dfi_p1_address = 16'd0;
+reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p1_we_n = 1'd1;
 wire main_litedramcore_dfi_p1_cke;
 wire main_litedramcore_dfi_p1_odt;
 wire main_litedramcore_dfi_p1_reset_n;
-reg main_litedramcore_dfi_p1_act_n = 1'd1;
+reg  main_litedramcore_dfi_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p1_rddata;
 wire main_litedramcore_dfi_p1_rddata_valid;
-reg [15:0] main_litedramcore_dfi_p2_address = 16'd0;
-reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg main_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [15:0] main_litedramcore_dfi_p2_address = 16'd0;
+reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p2_we_n = 1'd1;
 wire main_litedramcore_dfi_p2_cke;
 wire main_litedramcore_dfi_p2_odt;
 wire main_litedramcore_dfi_p2_reset_n;
-reg main_litedramcore_dfi_p2_act_n = 1'd1;
+reg  main_litedramcore_dfi_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p2_rddata;
 wire main_litedramcore_dfi_p2_rddata_valid;
-reg [15:0] main_litedramcore_dfi_p3_address = 16'd0;
-reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg main_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [15:0] main_litedramcore_dfi_p3_address = 16'd0;
+reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p3_we_n = 1'd1;
 wire main_litedramcore_dfi_p3_cke;
 wire main_litedramcore_dfi_p3_odt;
 wire main_litedramcore_dfi_p3_reset_n;
-reg main_litedramcore_dfi_p3_act_n = 1'd1;
+reg  main_litedramcore_dfi_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p3_rddata;
 wire main_litedramcore_dfi_p3_rddata_valid;
-reg main_litedramcore_cmd_valid = 1'd0;
-reg main_litedramcore_cmd_ready = 1'd0;
-reg main_litedramcore_cmd_last = 1'd0;
-reg [15:0] main_litedramcore_cmd_payload_a = 16'd0;
-reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg main_litedramcore_cmd_payload_cas = 1'd0;
-reg main_litedramcore_cmd_payload_ras = 1'd0;
-reg main_litedramcore_cmd_payload_we = 1'd0;
-reg main_litedramcore_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_cmd_valid = 1'd0;
+reg  main_litedramcore_cmd_ready = 1'd0;
+reg  main_litedramcore_cmd_last = 1'd0;
+reg  [15:0] main_litedramcore_cmd_payload_a = 16'd0;
+reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg  main_litedramcore_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_cmd_payload_we = 1'd0;
+reg  main_litedramcore_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_cmd_payload_is_write = 1'd0;
 wire main_litedramcore_wants_refresh;
 wire main_litedramcore_wants_zqcs;
 wire main_litedramcore_timer_wait;
 wire main_litedramcore_timer_done0;
 wire [9:0] main_litedramcore_timer_count0;
 wire main_litedramcore_timer_done1;
-reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
 wire main_litedramcore_postponer_req_i;
-reg main_litedramcore_postponer_req_o = 1'd0;
-reg main_litedramcore_postponer_count = 1'd0;
-reg main_litedramcore_sequencer_start0 = 1'd0;
+reg  main_litedramcore_postponer_req_o = 1'd0;
+reg  main_litedramcore_postponer_count = 1'd0;
+reg  main_litedramcore_sequencer_start0 = 1'd0;
 wire main_litedramcore_sequencer_done0;
 wire main_litedramcore_sequencer_start1;
-reg main_litedramcore_sequencer_done1 = 1'd0;
-reg [6:0] main_litedramcore_sequencer_counter = 7'd0;
-reg main_litedramcore_sequencer_count = 1'd0;
+reg  main_litedramcore_sequencer_done1 = 1'd0;
+reg  [6:0] main_litedramcore_sequencer_counter = 7'd0;
+reg  main_litedramcore_sequencer_count = 1'd0;
 wire main_litedramcore_zqcs_timer_wait;
 wire main_litedramcore_zqcs_timer_done0;
 wire [26:0] main_litedramcore_zqcs_timer_count0;
 wire main_litedramcore_zqcs_timer_done1;
-reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg main_litedramcore_zqcs_executer_start = 1'd0;
-reg main_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  main_litedramcore_zqcs_executer_start = 1'd0;
+reg  main_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
 wire main_litedramcore_bankmachine0_req_valid;
 wire main_litedramcore_bankmachine0_req_ready;
 wire main_litedramcore_bankmachine0_req_we;
 wire [22:0] main_litedramcore_bankmachine0_req_addr;
 wire main_litedramcore_bankmachine0_req_lock;
-reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine0_refresh_req;
-reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine0_row = 16'd0;
-reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine0_row = 16'd0;
+reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
 wire main_litedramcore_bankmachine0_row_hit;
-reg main_litedramcore_bankmachine0_row_open = 1'd0;
-reg main_litedramcore_bankmachine0_row_close = 1'd0;
-reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine0_row_open = 1'd0;
+reg  main_litedramcore_bankmachine0_row_close = 1'd0;
+reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine1_req_valid;
 wire main_litedramcore_bankmachine1_req_ready;
 wire main_litedramcore_bankmachine1_req_we;
 wire [22:0] main_litedramcore_bankmachine1_req_addr;
 wire main_litedramcore_bankmachine1_req_lock;
-reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine1_refresh_req;
-reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine1_row = 16'd0;
-reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine1_row = 16'd0;
+reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
 wire main_litedramcore_bankmachine1_row_hit;
-reg main_litedramcore_bankmachine1_row_open = 1'd0;
-reg main_litedramcore_bankmachine1_row_close = 1'd0;
-reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine1_row_open = 1'd0;
+reg  main_litedramcore_bankmachine1_row_close = 1'd0;
+reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine2_req_valid;
 wire main_litedramcore_bankmachine2_req_ready;
 wire main_litedramcore_bankmachine2_req_we;
 wire [22:0] main_litedramcore_bankmachine2_req_addr;
 wire main_litedramcore_bankmachine2_req_lock;
-reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine2_refresh_req;
-reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine2_row = 16'd0;
-reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine2_row = 16'd0;
+reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
 wire main_litedramcore_bankmachine2_row_hit;
-reg main_litedramcore_bankmachine2_row_open = 1'd0;
-reg main_litedramcore_bankmachine2_row_close = 1'd0;
-reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine2_row_open = 1'd0;
+reg  main_litedramcore_bankmachine2_row_close = 1'd0;
+reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine3_req_valid;
 wire main_litedramcore_bankmachine3_req_ready;
 wire main_litedramcore_bankmachine3_req_we;
 wire [22:0] main_litedramcore_bankmachine3_req_addr;
 wire main_litedramcore_bankmachine3_req_lock;
-reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine3_refresh_req;
-reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine3_row = 16'd0;
-reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine3_row = 16'd0;
+reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
 wire main_litedramcore_bankmachine3_row_hit;
-reg main_litedramcore_bankmachine3_row_open = 1'd0;
-reg main_litedramcore_bankmachine3_row_close = 1'd0;
-reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine3_row_open = 1'd0;
+reg  main_litedramcore_bankmachine3_row_close = 1'd0;
+reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine4_req_valid;
 wire main_litedramcore_bankmachine4_req_ready;
 wire main_litedramcore_bankmachine4_req_we;
 wire [22:0] main_litedramcore_bankmachine4_req_addr;
 wire main_litedramcore_bankmachine4_req_lock;
-reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine4_refresh_req;
-reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine4_row = 16'd0;
-reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine4_row = 16'd0;
+reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
 wire main_litedramcore_bankmachine4_row_hit;
-reg main_litedramcore_bankmachine4_row_open = 1'd0;
-reg main_litedramcore_bankmachine4_row_close = 1'd0;
-reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine4_row_open = 1'd0;
+reg  main_litedramcore_bankmachine4_row_close = 1'd0;
+reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine5_req_valid;
 wire main_litedramcore_bankmachine5_req_ready;
 wire main_litedramcore_bankmachine5_req_we;
 wire [22:0] main_litedramcore_bankmachine5_req_addr;
 wire main_litedramcore_bankmachine5_req_lock;
-reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine5_refresh_req;
-reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine5_row = 16'd0;
-reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine5_row = 16'd0;
+reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
 wire main_litedramcore_bankmachine5_row_hit;
-reg main_litedramcore_bankmachine5_row_open = 1'd0;
-reg main_litedramcore_bankmachine5_row_close = 1'd0;
-reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine5_row_open = 1'd0;
+reg  main_litedramcore_bankmachine5_row_close = 1'd0;
+reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine6_req_valid;
 wire main_litedramcore_bankmachine6_req_ready;
 wire main_litedramcore_bankmachine6_req_we;
 wire [22:0] main_litedramcore_bankmachine6_req_addr;
 wire main_litedramcore_bankmachine6_req_lock;
-reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine6_refresh_req;
-reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine6_row = 16'd0;
-reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine6_row = 16'd0;
+reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
 wire main_litedramcore_bankmachine6_row_hit;
-reg main_litedramcore_bankmachine6_row_open = 1'd0;
-reg main_litedramcore_bankmachine6_row_close = 1'd0;
-reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine6_row_open = 1'd0;
+reg  main_litedramcore_bankmachine6_row_close = 1'd0;
+reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine7_req_valid;
 wire main_litedramcore_bankmachine7_req_ready;
 wire main_litedramcore_bankmachine7_req_we;
 wire [22:0] main_litedramcore_bankmachine7_req_addr;
 wire main_litedramcore_bankmachine7_req_lock;
-reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine7_refresh_req;
-reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0;
+reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0;
 wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] main_litedramcore_bankmachine7_row = 16'd0;
-reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] main_litedramcore_bankmachine7_row = 16'd0;
+reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
 wire main_litedramcore_bankmachine7_row_hit;
-reg main_litedramcore_bankmachine7_row_open = 1'd0;
-reg main_litedramcore_bankmachine7_row_close = 1'd0;
-reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine7_row_open = 1'd0;
+reg  main_litedramcore_bankmachine7_row_close = 1'd0;
+reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire main_litedramcore_ras_allowed;
 wire main_litedramcore_cas_allowed;
 wire [1:0] main_litedramcore_rdcmdphase;
 wire [1:0] main_litedramcore_wrcmdphase;
-reg main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_valid;
-reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [15:0] main_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire main_litedramcore_choose_cmd_cmd_payload_is_read;
 wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_cmd_request;
-reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
 wire main_litedramcore_choose_cmd_ce;
-reg main_litedramcore_choose_req_want_reads = 1'd0;
-reg main_litedramcore_choose_req_want_writes = 1'd0;
-reg main_litedramcore_choose_req_want_cmds = 1'd0;
-reg main_litedramcore_choose_req_want_activates = 1'd0;
+reg  main_litedramcore_choose_req_want_reads = 1'd0;
+reg  main_litedramcore_choose_req_want_writes = 1'd0;
+reg  main_litedramcore_choose_req_want_cmds = 1'd0;
+reg  main_litedramcore_choose_req_want_activates = 1'd0;
 wire main_litedramcore_choose_req_cmd_valid;
-reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [15:0] main_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_req_cmd_payload_is_cmd;
 wire main_litedramcore_choose_req_cmd_payload_is_read;
 wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_req_request;
-reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
 wire main_litedramcore_choose_req_ce;
-reg [15:0] main_litedramcore_nop_a = 16'd0;
-reg [2:0] main_litedramcore_nop_ba = 3'd0;
-reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg main_litedramcore_steerer0 = 1'd1;
-reg main_litedramcore_steerer1 = 1'd1;
-reg main_litedramcore_steerer2 = 1'd1;
-reg main_litedramcore_steerer3 = 1'd1;
-reg main_litedramcore_steerer4 = 1'd1;
-reg main_litedramcore_steerer5 = 1'd1;
-reg main_litedramcore_steerer6 = 1'd1;
-reg main_litedramcore_steerer7 = 1'd1;
+reg  [15:0] main_litedramcore_nop_a = 16'd0;
+reg  [2:0] main_litedramcore_nop_ba = 3'd0;
+reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg  main_litedramcore_steerer0 = 1'd1;
+reg  main_litedramcore_steerer1 = 1'd1;
+reg  main_litedramcore_steerer2 = 1'd1;
+reg  main_litedramcore_steerer3 = 1'd1;
+reg  main_litedramcore_steerer4 = 1'd1;
+reg  main_litedramcore_steerer5 = 1'd1;
+reg  main_litedramcore_steerer6 = 1'd1;
+reg  main_litedramcore_steerer7 = 1'd1;
 wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
-reg main_litedramcore_trrdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
+reg  main_litedramcore_trrdcon_count = 1'd0;
 wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] main_litedramcore_tfawcon_count;
-reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
 wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
-reg main_litedramcore_tccdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
+reg  main_litedramcore_tccdcon_count = 1'd0;
 wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
 wire main_litedramcore_read_available;
 wire main_litedramcore_write_available;
-reg main_litedramcore_en0 = 1'd0;
+reg  main_litedramcore_en0 = 1'd0;
 wire main_litedramcore_max_time0;
-reg [4:0] main_litedramcore_time0 = 5'd0;
-reg main_litedramcore_en1 = 1'd0;
+reg  [4:0] main_litedramcore_time0 = 5'd0;
+reg  main_litedramcore_en1 = 1'd0;
 wire main_litedramcore_max_time1;
-reg [3:0] main_litedramcore_time1 = 4'd0;
+reg  [3:0] main_litedramcore_time1 = 4'd0;
 wire main_litedramcore_go_to_refresh;
-reg main_init_done_storage = 1'd0;
-reg main_init_done_re = 1'd0;
-reg main_init_error_storage = 1'd0;
-reg main_init_error_re = 1'd0;
+reg  main_init_done_storage = 1'd0;
+reg  main_init_done_re = 1'd0;
+reg  main_init_error_storage = 1'd0;
+reg  main_init_error_re = 1'd0;
 wire [29:0] main_wb_bus_adr;
 wire [31:0] main_wb_bus_dat_w;
 wire [31:0] main_wb_bus_dat_r;
@@ -1570,6 +1592,7 @@ wire main_wb_bus_we;
 wire [2:0] main_wb_bus_cti;
 wire [1:0] main_wb_bus_bte;
 wire main_wb_bus_err;
+wire main_user_enable;
 wire main_user_port_cmd_valid;
 wire main_user_port_cmd_ready;
 wire main_user_port_cmd_payload_we;
@@ -1590,26 +1613,26 @@ wire builder_reset5;
 wire builder_reset6;
 wire builder_reset7;
 wire builder_pll_fb;
-reg [1:0] builder_refresher_state = 2'd0;
-reg [1:0] builder_refresher_next_state = 2'd0;
-reg [3:0] builder_bankmachine0_state = 4'd0;
-reg [3:0] builder_bankmachine0_next_state = 4'd0;
-reg [3:0] builder_bankmachine1_state = 4'd0;
-reg [3:0] builder_bankmachine1_next_state = 4'd0;
-reg [3:0] builder_bankmachine2_state = 4'd0;
-reg [3:0] builder_bankmachine2_next_state = 4'd0;
-reg [3:0] builder_bankmachine3_state = 4'd0;
-reg [3:0] builder_bankmachine3_next_state = 4'd0;
-reg [3:0] builder_bankmachine4_state = 4'd0;
-reg [3:0] builder_bankmachine4_next_state = 4'd0;
-reg [3:0] builder_bankmachine5_state = 4'd0;
-reg [3:0] builder_bankmachine5_next_state = 4'd0;
-reg [3:0] builder_bankmachine6_state = 4'd0;
-reg [3:0] builder_bankmachine6_next_state = 4'd0;
-reg [3:0] builder_bankmachine7_state = 4'd0;
-reg [3:0] builder_bankmachine7_next_state = 4'd0;
-reg [3:0] builder_multiplexer_state = 4'd0;
-reg [3:0] builder_multiplexer_next_state = 4'd0;
+reg  [1:0] builder_refresher_state = 2'd0;
+reg  [1:0] builder_refresher_next_state = 2'd0;
+reg  [3:0] builder_bankmachine0_state = 4'd0;
+reg  [3:0] builder_bankmachine0_next_state = 4'd0;
+reg  [3:0] builder_bankmachine1_state = 4'd0;
+reg  [3:0] builder_bankmachine1_next_state = 4'd0;
+reg  [3:0] builder_bankmachine2_state = 4'd0;
+reg  [3:0] builder_bankmachine2_next_state = 4'd0;
+reg  [3:0] builder_bankmachine3_state = 4'd0;
+reg  [3:0] builder_bankmachine3_next_state = 4'd0;
+reg  [3:0] builder_bankmachine4_state = 4'd0;
+reg  [3:0] builder_bankmachine4_next_state = 4'd0;
+reg  [3:0] builder_bankmachine5_state = 4'd0;
+reg  [3:0] builder_bankmachine5_next_state = 4'd0;
+reg  [3:0] builder_bankmachine6_state = 4'd0;
+reg  [3:0] builder_bankmachine6_next_state = 4'd0;
+reg  [3:0] builder_bankmachine7_state = 4'd0;
+reg  [3:0] builder_bankmachine7_next_state = 4'd0;
+reg  [3:0] builder_multiplexer_state = 4'd0;
+reg  [3:0] builder_multiplexer_next_state = 4'd0;
 wire builder_roundrobin0_request;
 wire builder_roundrobin0_grant;
 wire builder_roundrobin0_ce;
@@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce;
 wire builder_roundrobin7_request;
 wire builder_roundrobin7_grant;
 wire builder_roundrobin7_ce;
-reg builder_locked0 = 1'd0;
-reg builder_locked1 = 1'd0;
-reg builder_locked2 = 1'd0;
-reg builder_locked3 = 1'd0;
-reg builder_locked4 = 1'd0;
-reg builder_locked5 = 1'd0;
-reg builder_locked6 = 1'd0;
-reg builder_locked7 = 1'd0;
-reg builder_new_master_wdata_ready0 = 1'd0;
-reg builder_new_master_wdata_ready1 = 1'd0;
-reg builder_new_master_rdata_valid0 = 1'd0;
-reg builder_new_master_rdata_valid1 = 1'd0;
-reg builder_new_master_rdata_valid2 = 1'd0;
-reg builder_new_master_rdata_valid3 = 1'd0;
-reg builder_new_master_rdata_valid4 = 1'd0;
-reg builder_new_master_rdata_valid5 = 1'd0;
-reg builder_new_master_rdata_valid6 = 1'd0;
-reg builder_new_master_rdata_valid7 = 1'd0;
-reg builder_new_master_rdata_valid8 = 1'd0;
-reg [13:0] builder_litedramcore_adr = 14'd0;
-reg builder_litedramcore_we = 1'd0;
-reg [7:0] builder_litedramcore_dat_w = 8'd0;
-wire [7:0] builder_litedramcore_dat_r;
+reg  builder_locked0 = 1'd0;
+reg  builder_locked1 = 1'd0;
+reg  builder_locked2 = 1'd0;
+reg  builder_locked3 = 1'd0;
+reg  builder_locked4 = 1'd0;
+reg  builder_locked5 = 1'd0;
+reg  builder_locked6 = 1'd0;
+reg  builder_locked7 = 1'd0;
+reg  builder_new_master_wdata_ready0 = 1'd0;
+reg  builder_new_master_wdata_ready1 = 1'd0;
+reg  builder_new_master_rdata_valid0 = 1'd0;
+reg  builder_new_master_rdata_valid1 = 1'd0;
+reg  builder_new_master_rdata_valid2 = 1'd0;
+reg  builder_new_master_rdata_valid3 = 1'd0;
+reg  builder_new_master_rdata_valid4 = 1'd0;
+reg  builder_new_master_rdata_valid5 = 1'd0;
+reg  builder_new_master_rdata_valid6 = 1'd0;
+reg  builder_new_master_rdata_valid7 = 1'd0;
+reg  builder_new_master_rdata_valid8 = 1'd0;
+reg  [13:0] builder_litedramcore_adr = 14'd0;
+reg  builder_litedramcore_we = 1'd0;
+reg  [31:0] builder_litedramcore_dat_w = 32'd0;
+wire [31:0] builder_litedramcore_dat_r;
 wire [29:0] builder_litedramcore_wishbone_adr;
 wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] builder_litedramcore_wishbone_sel;
 wire builder_litedramcore_wishbone_cyc;
 wire builder_litedramcore_wishbone_stb;
-reg builder_litedramcore_wishbone_ack = 1'd0;
+reg  builder_litedramcore_wishbone_ack = 1'd0;
 wire builder_litedramcore_wishbone_we;
 wire [2:0] builder_litedramcore_wishbone_cti;
 wire [1:0] builder_litedramcore_wishbone_bte;
-reg builder_litedramcore_wishbone_err = 1'd0;
+reg  builder_litedramcore_wishbone_err = 1'd0;
 wire [13:0] builder_interface0_bank_bus_adr;
 wire builder_interface0_bank_bus_we;
-wire [7:0] builder_interface0_bank_bus_dat_w;
-reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
-reg builder_csrbank0_init_done0_re = 1'd0;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank0_init_done0_re = 1'd0;
 wire builder_csrbank0_init_done0_r;
-reg builder_csrbank0_init_done0_we = 1'd0;
+reg  builder_csrbank0_init_done0_we = 1'd0;
 wire builder_csrbank0_init_done0_w;
-reg builder_csrbank0_init_error0_re = 1'd0;
+reg  builder_csrbank0_init_error0_re = 1'd0;
 wire builder_csrbank0_init_error0_r;
-reg builder_csrbank0_init_error0_we = 1'd0;
+reg  builder_csrbank0_init_error0_we = 1'd0;
 wire builder_csrbank0_init_error0_w;
 wire builder_csrbank0_sel;
 wire [13:0] builder_interface1_bank_bus_adr;
 wire builder_interface1_bank_bus_we;
-wire [7:0] builder_interface1_bank_bus_dat_w;
-reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
-reg builder_csrbank1_rst0_re = 1'd0;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank1_rst0_re = 1'd0;
 wire builder_csrbank1_rst0_r;
-reg builder_csrbank1_rst0_we = 1'd0;
+reg  builder_csrbank1_rst0_we = 1'd0;
 wire builder_csrbank1_rst0_w;
-reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg builder_csrbank1_wlevel_en0_re = 1'd0;
+reg  builder_csrbank1_wlevel_en0_re = 1'd0;
 wire builder_csrbank1_wlevel_en0_r;
-reg builder_csrbank1_wlevel_en0_we = 1'd0;
+reg  builder_csrbank1_wlevel_en0_we = 1'd0;
 wire builder_csrbank1_wlevel_en0_w;
-reg builder_csrbank1_dly_sel0_re = 1'd0;
+reg  builder_csrbank1_dly_sel0_re = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_r;
-reg builder_csrbank1_dly_sel0_we = 1'd0;
+reg  builder_csrbank1_dly_sel0_we = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_w;
-reg builder_csrbank1_rdphase0_re = 1'd0;
+reg  builder_csrbank1_rdphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_r;
-reg builder_csrbank1_rdphase0_we = 1'd0;
+reg  builder_csrbank1_rdphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_w;
-reg builder_csrbank1_wrphase0_re = 1'd0;
+reg  builder_csrbank1_wrphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_r;
-reg builder_csrbank1_wrphase0_we = 1'd0;
+reg  builder_csrbank1_wrphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_w;
 wire builder_csrbank1_sel;
 wire [13:0] builder_interface2_bank_bus_adr;
 wire builder_interface2_bank_bus_we;
-wire [7:0] builder_interface2_bank_bus_dat_w;
-reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
-reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank2_dfii_control0_re = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_r;
-reg builder_csrbank2_dfii_control0_we = 1'd0;
+reg  builder_csrbank2_dfii_control0_we = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_w;
-reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address1_r;
-reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address1_w;
-reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
-reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
-reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi0_address0_r;
+reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi0_address0_w;
+reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
-reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
-reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
-reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
-reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
-reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
-reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
-reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
-reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address1_r;
-reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address1_w;
-reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
-reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
-reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi1_address0_r;
+reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi1_address0_w;
+reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
-reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
-reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
-reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
-reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
-reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
-reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
-reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
-reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address1_r;
-reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address1_w;
-reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
-reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
-reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi2_address0_r;
+reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi2_address0_w;
+reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
-reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
-reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
-reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
-reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
-reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
-reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
-reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
-reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address1_r;
-reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address1_w;
-reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
-reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
-reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi3_address0_r;
+reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [15:0] builder_csrbank2_dfii_pi3_address0_w;
+reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
-reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
-reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
-reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
-reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
-reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
-reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
-reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
-reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
 wire builder_csrbank2_sel;
 wire [13:0] builder_csr_interconnect_adr;
 wire builder_csr_interconnect_we;
-wire [7:0] builder_csr_interconnect_dat_w;
-wire [7:0] builder_csr_interconnect_dat_r;
-reg [1:0] builder_state = 2'd0;
-reg [1:0] builder_next_state = 2'd0;
-reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
-reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg builder_litedramcore_we_next_value2 = 1'd0;
-reg builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg builder_rhs_array_muxed0 = 1'd0;
-reg [15:0] builder_rhs_array_muxed1 = 16'd0;
-reg [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg builder_rhs_array_muxed3 = 1'd0;
-reg builder_rhs_array_muxed4 = 1'd0;
-reg builder_rhs_array_muxed5 = 1'd0;
-reg builder_t_array_muxed0 = 1'd0;
-reg builder_t_array_muxed1 = 1'd0;
-reg builder_t_array_muxed2 = 1'd0;
-reg builder_rhs_array_muxed6 = 1'd0;
-reg [15:0] builder_rhs_array_muxed7 = 16'd0;
-reg [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg builder_rhs_array_muxed9 = 1'd0;
-reg builder_rhs_array_muxed10 = 1'd0;
-reg builder_rhs_array_muxed11 = 1'd0;
-reg builder_t_array_muxed3 = 1'd0;
-reg builder_t_array_muxed4 = 1'd0;
-reg builder_t_array_muxed5 = 1'd0;
-reg [22:0] builder_rhs_array_muxed12 = 23'd0;
-reg builder_rhs_array_muxed13 = 1'd0;
-reg builder_rhs_array_muxed14 = 1'd0;
-reg [22:0] builder_rhs_array_muxed15 = 23'd0;
-reg builder_rhs_array_muxed16 = 1'd0;
-reg builder_rhs_array_muxed17 = 1'd0;
-reg [22:0] builder_rhs_array_muxed18 = 23'd0;
-reg builder_rhs_array_muxed19 = 1'd0;
-reg builder_rhs_array_muxed20 = 1'd0;
-reg [22:0] builder_rhs_array_muxed21 = 23'd0;
-reg builder_rhs_array_muxed22 = 1'd0;
-reg builder_rhs_array_muxed23 = 1'd0;
-reg [22:0] builder_rhs_array_muxed24 = 23'd0;
-reg builder_rhs_array_muxed25 = 1'd0;
-reg builder_rhs_array_muxed26 = 1'd0;
-reg [22:0] builder_rhs_array_muxed27 = 23'd0;
-reg builder_rhs_array_muxed28 = 1'd0;
-reg builder_rhs_array_muxed29 = 1'd0;
-reg [22:0] builder_rhs_array_muxed30 = 23'd0;
-reg builder_rhs_array_muxed31 = 1'd0;
-reg builder_rhs_array_muxed32 = 1'd0;
-reg [22:0] builder_rhs_array_muxed33 = 23'd0;
-reg builder_rhs_array_muxed34 = 1'd0;
-reg builder_rhs_array_muxed35 = 1'd0;
-reg [2:0] builder_array_muxed0 = 3'd0;
-reg [15:0] builder_array_muxed1 = 16'd0;
-reg builder_array_muxed2 = 1'd0;
-reg builder_array_muxed3 = 1'd0;
-reg builder_array_muxed4 = 1'd0;
-reg builder_array_muxed5 = 1'd0;
-reg builder_array_muxed6 = 1'd0;
-reg [2:0] builder_array_muxed7 = 3'd0;
-reg [15:0] builder_array_muxed8 = 16'd0;
-reg builder_array_muxed9 = 1'd0;
-reg builder_array_muxed10 = 1'd0;
-reg builder_array_muxed11 = 1'd0;
-reg builder_array_muxed12 = 1'd0;
-reg builder_array_muxed13 = 1'd0;
-reg [2:0] builder_array_muxed14 = 3'd0;
-reg [15:0] builder_array_muxed15 = 16'd0;
-reg builder_array_muxed16 = 1'd0;
-reg builder_array_muxed17 = 1'd0;
-reg builder_array_muxed18 = 1'd0;
-reg builder_array_muxed19 = 1'd0;
-reg builder_array_muxed20 = 1'd0;
-reg [2:0] builder_array_muxed21 = 3'd0;
-reg [15:0] builder_array_muxed22 = 16'd0;
-reg builder_array_muxed23 = 1'd0;
-reg builder_array_muxed24 = 1'd0;
-reg builder_array_muxed25 = 1'd0;
-reg builder_array_muxed26 = 1'd0;
-reg builder_array_muxed27 = 1'd0;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg  [1:0] builder_state = 2'd0;
+reg  [1:0] builder_next_state = 2'd0;
+reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
+reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg  builder_litedramcore_we_next_value2 = 1'd0;
+reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg  builder_rhs_array_muxed0 = 1'd0;
+reg  [15:0] builder_rhs_array_muxed1 = 16'd0;
+reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg  builder_rhs_array_muxed3 = 1'd0;
+reg  builder_rhs_array_muxed4 = 1'd0;
+reg  builder_rhs_array_muxed5 = 1'd0;
+reg  builder_t_array_muxed0 = 1'd0;
+reg  builder_t_array_muxed1 = 1'd0;
+reg  builder_t_array_muxed2 = 1'd0;
+reg  builder_rhs_array_muxed6 = 1'd0;
+reg  [15:0] builder_rhs_array_muxed7 = 16'd0;
+reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg  builder_rhs_array_muxed9 = 1'd0;
+reg  builder_rhs_array_muxed10 = 1'd0;
+reg  builder_rhs_array_muxed11 = 1'd0;
+reg  builder_t_array_muxed3 = 1'd0;
+reg  builder_t_array_muxed4 = 1'd0;
+reg  builder_t_array_muxed5 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed12 = 23'd0;
+reg  builder_rhs_array_muxed13 = 1'd0;
+reg  builder_rhs_array_muxed14 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed15 = 23'd0;
+reg  builder_rhs_array_muxed16 = 1'd0;
+reg  builder_rhs_array_muxed17 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed18 = 23'd0;
+reg  builder_rhs_array_muxed19 = 1'd0;
+reg  builder_rhs_array_muxed20 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed21 = 23'd0;
+reg  builder_rhs_array_muxed22 = 1'd0;
+reg  builder_rhs_array_muxed23 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed24 = 23'd0;
+reg  builder_rhs_array_muxed25 = 1'd0;
+reg  builder_rhs_array_muxed26 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed27 = 23'd0;
+reg  builder_rhs_array_muxed28 = 1'd0;
+reg  builder_rhs_array_muxed29 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed30 = 23'd0;
+reg  builder_rhs_array_muxed31 = 1'd0;
+reg  builder_rhs_array_muxed32 = 1'd0;
+reg  [22:0] builder_rhs_array_muxed33 = 23'd0;
+reg  builder_rhs_array_muxed34 = 1'd0;
+reg  builder_rhs_array_muxed35 = 1'd0;
+reg  [2:0] builder_array_muxed0 = 3'd0;
+reg  [15:0] builder_array_muxed1 = 16'd0;
+reg  builder_array_muxed2 = 1'd0;
+reg  builder_array_muxed3 = 1'd0;
+reg  builder_array_muxed4 = 1'd0;
+reg  builder_array_muxed5 = 1'd0;
+reg  builder_array_muxed6 = 1'd0;
+reg  [2:0] builder_array_muxed7 = 3'd0;
+reg  [15:0] builder_array_muxed8 = 16'd0;
+reg  builder_array_muxed9 = 1'd0;
+reg  builder_array_muxed10 = 1'd0;
+reg  builder_array_muxed11 = 1'd0;
+reg  builder_array_muxed12 = 1'd0;
+reg  builder_array_muxed13 = 1'd0;
+reg  [2:0] builder_array_muxed14 = 3'd0;
+reg  [15:0] builder_array_muxed15 = 16'd0;
+reg  builder_array_muxed16 = 1'd0;
+reg  builder_array_muxed17 = 1'd0;
+reg  builder_array_muxed18 = 1'd0;
+reg  builder_array_muxed19 = 1'd0;
+reg  builder_array_muxed20 = 1'd0;
+reg  [2:0] builder_array_muxed21 = 3'd0;
+reg  [15:0] builder_array_muxed22 = 16'd0;
+reg  builder_array_muxed23 = 1'd0;
+reg  builder_array_muxed24 = 1'd0;
+reg  builder_array_muxed25 = 1'd0;
+reg  builder_array_muxed26 = 1'd0;
+reg  builder_array_muxed27 = 1'd0;
 wire builder_xilinxasyncresetsynchronizerimpl0;
 wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl1;
@@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3;
 wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl3_expr;
 
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
 assign init_done = main_init_done_storage;
 assign init_error = main_init_error_storage;
 assign main_wb_bus_adr = wb_ctrl_adr;
@@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
 assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
 assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
-assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
 assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = rst;
+assign main_reset = (rst | main_rst);
 assign pll_locked = main_locked;
 assign main_clkin = clk;
 assign iodelay_clk = main_clkout_buf0;
@@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2;
 assign sys4x_dqs_clk = main_clkout_buf3;
 assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
 assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-
-// synthesis translate_off
-reg dummy_d;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
@@ -2081,14 +1989,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
 	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
 	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-// synthesis translate_off
-	dummy_d = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_1;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
@@ -2123,14 +2024,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
 	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
 	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-// synthesis translate_off
-	dummy_d_1 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_2;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
@@ -2165,14 +2059,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
 	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
 	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-// synthesis translate_off
-	dummy_d_2 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_3;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
@@ -2207,19 +2094,12 @@ always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
 	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
 	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-// synthesis translate_off
-	dummy_d_3 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-
-// synthesis translate_off
-reg dummy_d_4;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqs_oe <= 1'd0;
 	if (main_a7ddrphy_wlevel_en_storage) begin
@@ -2227,16 +2107,9 @@ always @(*) begin
 	end else begin
 		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
 	end
-// synthesis translate_off
-	dummy_d_4 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
 assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqspattern_o0 <= 8'd0;
 	main_a7ddrphy_dqspattern_o0 <= 7'd85;
@@ -2252,14 +2125,7 @@ always @(*) begin
 			main_a7ddrphy_dqspattern_o0 <= 1'd1;
 		end
 	end
-// synthesis translate_off
-	dummy_d_5 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip00 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value0)
@@ -2288,14 +2154,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_6 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip10 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value0)
@@ -2324,14 +2183,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_7 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip01 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value1)
@@ -2360,14 +2212,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_8 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip11 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value1)
@@ -2396,14 +2241,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_9 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip02 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value2)
@@ -2432,14 +2270,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_10 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip04 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value3)
@@ -2468,14 +2299,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_11 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip12 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value2)
@@ -2504,14 +2328,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_12 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip14 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value3)
@@ -2540,14 +2357,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_13 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip20 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value0)
@@ -2576,14 +2386,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_14 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip22 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value1)
@@ -2612,14 +2415,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_15 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip30 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value0)
@@ -2648,14 +2444,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_16 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip32 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value1)
@@ -2684,14 +2473,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_17 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_18;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip40 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value0)
@@ -2720,14 +2502,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_18 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_19;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip42 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value1)
@@ -2756,14 +2531,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_19 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_20;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip50 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value0)
@@ -2792,14 +2560,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_20 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_21;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip52 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value1)
@@ -2828,14 +2589,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_21 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip60 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value0)
@@ -2864,14 +2618,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_22 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip62 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value1)
@@ -2900,14 +2647,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_23 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip70 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value0)
@@ -2936,14 +2676,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_24 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip72 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value1)
@@ -2972,14 +2705,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_25 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_26;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip80 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value0)
@@ -3008,14 +2734,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_26 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip82 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value1)
@@ -3044,14 +2763,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_27 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip90 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value0)
@@ -3080,14 +2792,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_28 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip92 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value1)
@@ -3116,14 +2821,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_29 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip100 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value0)
@@ -3152,14 +2850,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_30 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_31;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip102 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value1)
@@ -3188,14 +2879,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_31 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_32;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip110 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value0)
@@ -3224,14 +2908,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_32 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_33;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip112 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value1)
@@ -3260,14 +2937,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_33 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_34;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip120 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value0)
@@ -3296,14 +2966,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_34 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_35;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip122 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value1)
@@ -3332,14 +2995,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_35 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_36;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip130 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value0)
@@ -3368,14 +3024,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_36 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_37;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip132 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value1)
@@ -3404,14 +3053,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_37 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_38;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip140 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value0)
@@ -3440,14 +3082,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_38 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip142 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value1)
@@ -3476,14 +3111,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_39 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_40;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip150 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value0)
@@ -3512,14 +3140,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_40 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_41;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip152 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value1)
@@ -3548,9 +3169,6 @@ always @(*) begin
 			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_41 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
 assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
@@ -3680,10 +3298,21 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-
-// synthesis translate_off
-reg dummy_d_42;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_wrdata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	end else begin
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+	end
+end
+always @(*) begin
+	main_litedramcore_inti_p3_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3691,28 +3320,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_42 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_43;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_43 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_44;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3720,14 +3335,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_44 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_45;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3735,14 +3343,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_45 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_46;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 16'd0;
 	if (main_litedramcore_sel) begin
@@ -3750,14 +3351,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
-// synthesis translate_off
-	dummy_d_46 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_47;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3765,14 +3359,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
-// synthesis translate_off
-	dummy_d_47 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_48;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3780,14 +3367,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_48 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_49;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3795,14 +3375,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_49 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_50;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3810,28 +3383,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_50 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_51;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_51 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_52;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3839,28 +3398,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
-// synthesis translate_off
-	dummy_d_52 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_53;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_53 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_54;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3868,14 +3413,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_54 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_55;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3883,14 +3421,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
-// synthesis translate_off
-	dummy_d_55 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_56;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3898,14 +3429,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_56 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_57;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3913,14 +3437,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
-// synthesis translate_off
-	dummy_d_57 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_58;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -3928,28 +3445,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_58 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_59;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
-// synthesis translate_off
-	dummy_d_59 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_60;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3957,28 +3460,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_60 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_61;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_61 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_62;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3986,14 +3475,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_62 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_63;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4001,14 +3483,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_63 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_64;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_address <= 16'd0;
 	if (main_litedramcore_sel) begin
@@ -4016,14 +3491,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
-// synthesis translate_off
-	dummy_d_64 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_65;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4031,14 +3499,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
-// synthesis translate_off
-	dummy_d_65 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_66;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4046,14 +3507,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_66 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_67;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4061,14 +3515,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_67 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_68;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4076,57 +3523,29 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_68 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_69;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_69 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_70;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
+	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_70 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_71;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+	main_litedramcore_master_p0_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
 	end else begin
+		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_71 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_72;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4134,14 +3553,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
-// synthesis translate_off
-	dummy_d_72 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_73;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4149,14 +3561,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
-// synthesis translate_off
-	dummy_d_73 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_74;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4164,14 +3569,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_74 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4179,14 +3577,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
-// synthesis translate_off
-	dummy_d_75 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_76;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4194,28 +3585,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_76 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_77;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
-// synthesis translate_off
-	dummy_d_77 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_78;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4223,28 +3600,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_78 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_79;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_79 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_80;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4252,14 +3615,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_80 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_81;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4267,14 +3623,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_81 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_82;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 16'd0;
 	if (main_litedramcore_sel) begin
@@ -4282,14 +3631,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
-// synthesis translate_off
-	dummy_d_82 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_83;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4297,14 +3639,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
-// synthesis translate_off
-	dummy_d_83 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_84;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4312,14 +3647,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_84 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_85;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4327,14 +3655,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_85 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_86;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	end else begin
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4342,28 +3670,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_86 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_87;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_87 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_88;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4371,28 +3685,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
-// synthesis translate_off
-	dummy_d_88 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_89;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4400,14 +3700,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_91;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4415,14 +3708,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
-// synthesis translate_off
-	dummy_d_91 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_92;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4430,14 +3716,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_92 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_93;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4445,14 +3724,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
-// synthesis translate_off
-	dummy_d_93 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_94;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4460,28 +3732,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_94 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_95;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
-// synthesis translate_off
-	dummy_d_95 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_96;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4489,28 +3747,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_96 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_97 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_98;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4518,14 +3762,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_98 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_99;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4533,14 +3770,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_99 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_100;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 16'd0;
 	if (main_litedramcore_sel) begin
@@ -4548,14 +3778,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4563,14 +3786,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_101 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_102;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4578,14 +3794,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_102 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_103;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4593,14 +3802,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_103 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_104;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4608,28 +3810,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_104 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_105;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_105 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_106;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4637,28 +3825,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
-// synthesis translate_off
-	dummy_d_106 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_107;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
-	end else begin
-	end
-// synthesis translate_off
-	dummy_d_107 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_108;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4666,28 +3833,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
-// synthesis translate_off
-	dummy_d_108 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
-	end
-// synthesis translate_off
-	dummy_d_109 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_110;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4695,14 +3841,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
-// synthesis translate_off
-	dummy_d_110 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_111;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4710,14 +3849,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_111 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_112;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4725,24 +3857,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
-// synthesis translate_off
-	dummy_d_112 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_113;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
-	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
-	end
-// synthesis translate_off
-	dummy_d_113 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
 assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
@@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4767,14 +3885,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_114 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_115;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4782,14 +3893,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_115 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_116;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4797,24 +3901,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_116 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_117;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
-	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_117 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
@@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c
 assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
 assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_118;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4833,14 +3923,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_118 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_119;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4848,14 +3931,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_119 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4863,24 +3939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_120 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
-	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_121 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
@@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c
 assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
 assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p2_cas_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4899,14 +3961,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4914,14 +3969,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_123 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4929,24 +3977,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_124 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
-	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_125 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
@@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c
 assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
 assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_126;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4965,14 +3999,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_126 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4980,14 +4007,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_127 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4995,24 +4015,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_128 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
-	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_129 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
@@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 &
 assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
 assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
 assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
 always @(*) begin
 	builder_refresher_next_state <= 2'd0;
 	builder_refresher_next_state <= builder_refresher_state;
@@ -5124,119 +4122,88 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_130 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_131;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
+	main_litedramcore_cmd_valid <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
+					main_litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_131 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_132;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
+	main_litedramcore_zqcs_executer_start <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
+					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_132 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_133;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
+	main_litedramcore_cmd_last <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+				end else begin
+					main_litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_133 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_134;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
+	main_litedramcore_sequencer_start0 <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_cmd_ready) begin
+				main_litedramcore_sequencer_start0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
-			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_134 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
@@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_135;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
@@ -5263,17 +4226,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_135 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
 assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
 assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_136;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
@@ -5281,9 +4237,6 @@ always @(*) begin
 			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_136 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
@@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_137;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
@@ -5313,9 +4262,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_137 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
@@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_138;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine0_next_state <= 4'd0;
 	builder_bankmachine0_next_state <= builder_bankmachine0_state;
@@ -5389,14 +4331,45 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_138 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_139;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5422,14 +4395,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_139 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5470,14 +4436,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_140 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_141;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5503,14 +4462,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_141 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_142;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5536,14 +4488,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_142 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_143;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5578,22 +4523,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_143 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_144;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5606,44 +4550,19 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_144 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5659,14 +4578,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_145 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5707,47 +4619,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_146 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_147 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5777,14 +4649,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5822,14 +4687,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_149 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_150;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5867,14 +4725,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_150 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_151;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5912,9 +4763,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_151 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
@@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_152;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
@@ -5941,17 +4785,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_152 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
 assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
 assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_153;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
@@ -5959,9 +4796,6 @@ always @(*) begin
 			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_153 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
@@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_154;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
@@ -5991,9 +4821,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_154 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
@@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_155;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine1_next_state <= 4'd0;
 	builder_bankmachine1_next_state <= builder_bankmachine1_state;
@@ -6067,14 +4890,45 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_155 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_156;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6100,14 +4954,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_156 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_157;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6148,14 +4995,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_157 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6181,14 +5021,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_158 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_159;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6214,14 +5047,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_159 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_160;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6256,14 +5082,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_160 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6292,14 +5111,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_161 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6340,47 +5152,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_162 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_163 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6410,14 +5182,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_164 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_165;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6455,14 +5220,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_165 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_166;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6500,22 +5258,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_166 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_167;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6528,31 +5282,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_167 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_168;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6590,9 +5322,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_168 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
@@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_169;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
@@ -6619,17 +5344,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_169 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
 assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_170;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
@@ -6637,9 +5355,6 @@ always @(*) begin
 			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_170 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
@@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_171;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
@@ -6669,9 +5380,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_171 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
@@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_172;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine2_next_state <= 4'd0;
 	builder_bankmachine2_next_state <= builder_bankmachine2_state;
@@ -6745,14 +5449,45 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_172 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_173;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6778,14 +5513,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_173 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6826,22 +5554,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_174 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_175;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6854,31 +5578,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_175 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6904,14 +5606,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_176 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6937,14 +5632,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_177 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_178;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6979,14 +5667,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_178 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7015,14 +5696,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_179 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7063,47 +5737,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_180 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7133,14 +5767,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_182 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_183;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7178,14 +5805,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_183 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_184;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7223,14 +5843,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_184 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_185;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7268,9 +5881,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_185 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
@@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_186;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
@@ -7297,17 +5903,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
 assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
 assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
@@ -7315,9 +5914,6 @@ always @(*) begin
 			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
@@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_188;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
@@ -7347,9 +5939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_188 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
@@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_189;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine3_next_state <= 4'd0;
 	builder_bankmachine3_next_state <= builder_bankmachine3_state;
@@ -7423,14 +6008,45 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_189 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_190;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7456,14 +6072,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_190 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_191;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7504,14 +6113,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_191 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7537,24 +6139,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_192 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_193;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7565,44 +6163,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_193 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_194;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
+	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7615,14 +6191,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_194 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_195;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7657,14 +6226,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_195 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7693,14 +6255,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_196 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7741,47 +6296,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_197 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_198 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_199;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7811,14 +6326,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_199 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_200;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7856,14 +6364,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_200 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_201;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7901,14 +6402,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_201 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_202;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7946,9 +6440,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_202 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
@@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_203;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
@@ -7975,17 +6462,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_203 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
 assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
 assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_204;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
@@ -7993,9 +6473,6 @@ always @(*) begin
 			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_204 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
@@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_205;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
@@ -8025,9 +6498,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_205 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
@@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_206;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine4_next_state <= 4'd0;
 	builder_bankmachine4_next_state <= builder_bankmachine4_state;
@@ -8101,16 +6567,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_206 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_207;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -8119,9 +6578,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8132,29 +6588,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_207 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8168,41 +6629,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_208 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_209;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
+	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8215,27 +6657,23 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_209 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_210;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8246,24 +6684,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_210 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_211;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8276,44 +6722,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_211 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_212;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8326,21 +6750,11 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_212 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8362,10 +6776,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8374,24 +6785,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_213 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8407,18 +6814,14 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_214 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -8441,8 +6844,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -8452,14 +6855,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_215 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_216;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8489,14 +6885,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_216 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_217;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8534,14 +6923,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_217 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8579,14 +6961,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_218 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_219;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8624,9 +6999,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_219 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
@@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_220;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
@@ -8653,17 +7021,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
 assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
 assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
@@ -8671,9 +7032,6 @@ always @(*) begin
 			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_221 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
@@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_222;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
@@ -8703,9 +7057,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_222 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
@@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_223;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine5_next_state <= 4'd0;
 	builder_bankmachine5_next_state <= builder_bankmachine5_state;
@@ -8779,14 +7126,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_223 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8812,14 +7216,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_224 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_225;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8860,14 +7257,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_225 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8893,14 +7283,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_226 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8926,14 +7309,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_227 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_228;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8968,14 +7344,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_228 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_229;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9004,14 +7373,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_229 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_230;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9052,47 +7414,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_231 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9122,14 +7444,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_232 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9167,14 +7482,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_233 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_234;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9212,14 +7520,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_234 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_235;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9257,54 +7558,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_235 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_236 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
@@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
@@ -9331,17 +7580,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_237 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
 assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
 assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_238;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
@@ -9349,9 +7591,6 @@ always @(*) begin
 			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_238 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
@@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_239;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
@@ -9381,9 +7616,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_239 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
@@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_240;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine6_next_state <= 4'd0;
 	builder_bankmachine6_next_state <= builder_bankmachine6_state;
@@ -9457,16 +7685,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_240 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_241;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -9475,9 +7696,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9488,16 +7706,50 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_241 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9538,22 +7790,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_242 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_243;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9566,31 +7814,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_243 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_244;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9616,14 +7842,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_244 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_245;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9649,14 +7868,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_245 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9691,14 +7903,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_246 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9727,14 +7932,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_247 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9775,47 +7973,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_248 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_249 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_250;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9845,14 +8003,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_250 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_251;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9890,14 +8041,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_251 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_252;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9935,14 +8079,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_252 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9980,9 +8117,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_253 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
@@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]);
 assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_254;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
 	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
@@ -10009,17 +8139,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_254 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
 assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_255;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
@@ -10027,9 +8150,6 @@ always @(*) begin
 			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_255 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
@@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_256;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
@@ -10059,9 +8175,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_256 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
@@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_257;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine7_next_state <= 4'd0;
 	builder_bankmachine7_next_state <= builder_bankmachine7_state;
@@ -10135,14 +8244,45 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_257 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_258;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10168,14 +8308,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_258 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_259;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10216,14 +8349,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_259 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_260;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10249,14 +8375,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_260 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_261;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10282,14 +8401,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_261 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_262;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10324,22 +8436,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_262 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_263;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10352,31 +8460,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_263 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_264;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10405,14 +8491,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_264 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10453,47 +8532,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_266 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10523,14 +8562,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_267 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10568,14 +8600,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_268 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10613,14 +8638,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_269 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10658,9 +8676,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_270 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
@@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_valids <= 8'd0;
 	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
@@ -10706,9 +8717,6 @@ always @(*) begin
 	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-// synthesis translate_off
-	dummy_d_271 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
 assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
@@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
 assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
 assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
 assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
 	end
-// synthesis translate_off
-	dummy_d_272 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
 	end
-// synthesis translate_off
-	dummy_d_273 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
 	end
-// synthesis translate_off
-	dummy_d_274 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
@@ -10768,14 +8751,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
 		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_275 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
@@ -10784,14 +8760,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
 		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_276 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
@@ -10800,14 +8769,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
 		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_277 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
@@ -10816,14 +8778,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
 		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_278 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
@@ -10832,14 +8787,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
 		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_279 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
@@ -10848,14 +8796,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
 		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_280 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
@@ -10864,14 +8805,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
 		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_281 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
@@ -10880,15 +8814,8 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
 		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_282 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_valids <= 8'd0;
 	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
@@ -10899,9 +8826,6 @@ always @(*) begin
 	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-// synthesis translate_off
-	dummy_d_283 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
 assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
@@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
 assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
 assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
 assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
 	end
-// synthesis translate_off
-	dummy_d_284 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
 	end
-// synthesis translate_off
-	dummy_d_285 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
 	end
-// synthesis translate_off
-	dummy_d_286 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
 assign main_litedramcore_dfi_p0_reset_n = 1'd1;
@@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1;
 assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
 assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
 assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
 always @(*) begin
 	builder_multiplexer_next_state <= 4'd0;
 	builder_multiplexer_next_state <= builder_multiplexer_state;
@@ -11023,27 +8922,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_287 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
+	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
+			main_litedramcore_steerer_sel0 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
+			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -11062,36 +8955,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
+			main_litedramcore_steerer_sel0 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_288 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
+	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -11110,30 +8990,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_289 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
+	main_litedramcore_steerer_sel1 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -11155,30 +9024,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_290 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
+	main_litedramcore_steerer_sel2 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -11200,27 +9065,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_291 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
+	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -11241,24 +9103,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_292 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -11280,22 +9141,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_293 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
+	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
 		end
@@ -11318,22 +9175,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_294 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -11354,25 +9207,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_295 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -11393,26 +9238,15 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11435,28 +9269,18 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -11475,30 +9299,21 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
+	main_litedramcore_en1 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			main_litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -11519,9 +9334,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_299 = dummy_s;
-// synthesis translate_on
 end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
@@ -11566,41 +9378,27 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
 assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
+	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_300 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
+	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_301 = dummy_s;
-// synthesis translate_on
 end
 assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
 assign builder_roundrobin0_grant = 1'd0;
@@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0;
 assign builder_roundrobin5_grant = 1'd0;
 assign builder_roundrobin6_grant = 1'd0;
 assign builder_roundrobin7_grant = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
 always @(*) begin
 	builder_next_state <= 2'd0;
 	builder_next_state <= builder_state;
@@ -11631,173 +9425,114 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_302 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	builder_litedramcore_wishbone_dat_r <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_303 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	builder_litedramcore_dat_w_next_value0 <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_304 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
+	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
-			end
+			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
+	builder_litedramcore_wishbone_ack <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_306 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
+	builder_litedramcore_adr_next_value1 <= 14'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
+			builder_litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
+				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_307 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
+	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
+				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_308 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
+	builder_litedramcore_we_next_value2 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
+			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_309 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
+	builder_litedramcore_we_next_value_ce2 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
+			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_310 = dummy_s;
-// synthesis translate_on
 end
 assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
 assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
@@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
+	builder_csrbank0_init_done0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_311 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
+	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_312 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
+	builder_csrbank0_init_error0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_313 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
+	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_314 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_315 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_316 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_317 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_318 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_319 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_320 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_321 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_322 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_323 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_324 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_325 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_326 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_327 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_328 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_329 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_330 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_331 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_332 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_333 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_335 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_336 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_337 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_338;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_338 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_339;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_339 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_340;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_340 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
 assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
@@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_341;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_341 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_342;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_control0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
 		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_342 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_343;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_control0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_343 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_344;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_344 = dummy_s;
-// synthesis translate_on
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_345;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_345 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_346;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
 	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
 		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_346 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_347;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_347 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_348;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_348 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_349;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
 		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_349 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_350;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
 		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_350 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_351;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
 		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_351 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_352;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
 		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_352 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_353;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_353 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_354;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_354 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_355;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_355 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_356;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_357 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_358;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_358 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_359;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_359 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_360;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_360 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_361;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_361 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_362;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_362 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_363;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_363 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_364;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_364 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_365;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_365 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_366;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_366 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_367;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_367 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_368;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_368 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_369;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_369 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_370;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_370 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_371;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
 		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_371 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_372;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
 		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_372 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_373;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_373 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_374;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_374 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_375;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_375 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_376;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_376 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_377;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_377 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_378;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_378 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_379;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_379 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_380;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_380 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_381;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_381 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_382;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_382 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_383;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_383 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_384;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_384 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_385;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_385 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_386;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_386 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_387;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_387 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_388;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_388 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_389;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_389 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_390;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_390 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_391;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_391 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_392;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_392 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_393;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_393 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_394;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_394 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_395;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_395 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_396;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_396 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_397;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_397 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_398;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
 		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_398 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_399;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_399 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_400;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_400 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_401;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_401 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_402;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_402 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_403;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_403 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_404;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_404 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_405;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_405 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_406;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_406 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_407;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_407 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_408;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_408 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_409;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_409 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_410;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_410 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_411;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_411 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_412;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_412 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_413;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_413 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_414;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_414 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_415;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_416;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_416 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_417;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_417 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_418;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_418 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_419;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_419 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_420;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_420 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_421;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_421 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_422;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_422 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_423;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_423 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_424;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_424 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_425;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_425 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_426;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_426 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_427;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_427 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_428;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_428 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_429;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_429 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_430;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_430 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_431;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_431 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_432;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_432 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_433;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_433 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_434;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_434 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_435;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_435 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_436;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_436 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_437;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_437 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_438;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_438 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_439;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_439 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_440;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_440 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_441;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_441 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_442;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_442 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_443;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_443 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_444;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_444 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_445;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_445 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_446;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_446 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
@@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
 assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
 assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[15:8];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0];
 assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[15:8];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0];
 assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[15:8];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0];
 assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[15:8];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0];
 assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_csr_interconnect_adr = builder_litedramcore_adr;
 assign builder_csr_interconnect_we = builder_litedramcore_we;
 assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
@@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-
-// synthesis translate_off
-reg dummy_d_447;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13760,14 +10147,7 @@ always @(*) begin
 			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_447 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_448;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed1 <= 16'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13796,14 +10176,7 @@ always @(*) begin
 			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_448 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_449;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed2 <= 3'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13832,14 +10205,7 @@ always @(*) begin
 			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_449 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_450;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13868,14 +10234,7 @@ always @(*) begin
 			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_450 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_451;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13904,14 +10263,7 @@ always @(*) begin
 			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_451 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_452;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13940,14 +10292,7 @@ always @(*) begin
 			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_452 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_453;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13976,14 +10321,7 @@ always @(*) begin
 			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_453 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_454;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed1 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14012,14 +10350,7 @@ always @(*) begin
 			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_454 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_455;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed2 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14048,14 +10379,7 @@ always @(*) begin
 			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_455 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_456;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed6 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14084,14 +10408,7 @@ always @(*) begin
 			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_456 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_457;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed7 <= 16'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14120,14 +10437,7 @@ always @(*) begin
 			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_457 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_458;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed8 <= 3'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14156,14 +10466,7 @@ always @(*) begin
 			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_458 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_459;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed9 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14192,14 +10495,7 @@ always @(*) begin
 			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_459 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_460;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed10 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14228,14 +10524,7 @@ always @(*) begin
 			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_460 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_461;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed11 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14264,14 +10553,7 @@ always @(*) begin
 			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_461 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_462;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14300,14 +10582,7 @@ always @(*) begin
 			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_462 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_463;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14336,14 +10611,7 @@ always @(*) begin
 			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_463 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_464;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14372,14 +10640,7 @@ always @(*) begin
 			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_464 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_465;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed12 <= 23'd0;
 	case (builder_roundrobin0_grant)
@@ -14387,14 +10648,7 @@ always @(*) begin
 			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_465 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_466;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed13 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14402,14 +10656,7 @@ always @(*) begin
 			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_466 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_467;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed14 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14417,14 +10664,7 @@ always @(*) begin
 			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_467 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_468;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed15 <= 23'd0;
 	case (builder_roundrobin1_grant)
@@ -14432,14 +10672,7 @@ always @(*) begin
 			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_468 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_469;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed16 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14447,14 +10680,7 @@ always @(*) begin
 			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_469 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_470;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed17 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14462,14 +10688,7 @@ always @(*) begin
 			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_470 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_471;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed18 <= 23'd0;
 	case (builder_roundrobin2_grant)
@@ -14477,14 +10696,7 @@ always @(*) begin
 			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_471 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_472;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed19 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14492,14 +10704,7 @@ always @(*) begin
 			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_472 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_473;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed20 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14507,14 +10712,7 @@ always @(*) begin
 			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_473 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_474;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed21 <= 23'd0;
 	case (builder_roundrobin3_grant)
@@ -14522,14 +10720,7 @@ always @(*) begin
 			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_474 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_475;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed22 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14537,14 +10728,7 @@ always @(*) begin
 			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_475 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_476;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed23 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14552,14 +10736,7 @@ always @(*) begin
 			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_476 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_477;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed24 <= 23'd0;
 	case (builder_roundrobin4_grant)
@@ -14567,14 +10744,7 @@ always @(*) begin
 			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_477 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_478;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed25 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14582,14 +10752,7 @@ always @(*) begin
 			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_478 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_479;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed26 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14597,14 +10760,7 @@ always @(*) begin
 			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_479 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_480;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed27 <= 23'd0;
 	case (builder_roundrobin5_grant)
@@ -14612,14 +10768,7 @@ always @(*) begin
 			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_480 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_481;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed28 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14627,14 +10776,7 @@ always @(*) begin
 			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_481 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_482;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed29 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14642,14 +10784,7 @@ always @(*) begin
 			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_482 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_483;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed30 <= 23'd0;
 	case (builder_roundrobin6_grant)
@@ -14657,14 +10792,7 @@ always @(*) begin
 			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_483 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_484;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed31 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14672,14 +10800,7 @@ always @(*) begin
 			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_484 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_485;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed32 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14687,14 +10808,7 @@ always @(*) begin
 			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_485 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_486;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed33 <= 23'd0;
 	case (builder_roundrobin7_grant)
@@ -14702,14 +10816,7 @@ always @(*) begin
 			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_486 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_487;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed34 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14717,14 +10824,7 @@ always @(*) begin
 			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_487 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_488;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed35 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14732,14 +10832,7 @@ always @(*) begin
 			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_488 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_489;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed0 <= 3'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14756,14 +10849,7 @@ always @(*) begin
 			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_489 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_490;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed1 <= 16'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14780,14 +10866,7 @@ always @(*) begin
 			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_490 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_491;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed2 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14804,14 +10883,7 @@ always @(*) begin
 			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_491 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_492;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed3 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14828,14 +10900,7 @@ always @(*) begin
 			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_492 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_493;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed4 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14852,14 +10917,7 @@ always @(*) begin
 			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_493 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_494;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed5 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14876,14 +10934,7 @@ always @(*) begin
 			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_494 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_495;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed6 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14900,14 +10951,7 @@ always @(*) begin
 			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_495 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_496;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed7 <= 3'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14924,14 +10968,7 @@ always @(*) begin
 			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_496 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_497;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed8 <= 16'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14948,14 +10985,7 @@ always @(*) begin
 			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_497 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_498;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed9 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14972,14 +11002,7 @@ always @(*) begin
 			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_498 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_499;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed10 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14996,14 +11019,7 @@ always @(*) begin
 			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_499 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_500;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed11 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15020,14 +11036,7 @@ always @(*) begin
 			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_500 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_501;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed12 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15044,14 +11053,7 @@ always @(*) begin
 			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_501 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_502;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed13 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15068,14 +11070,7 @@ always @(*) begin
 			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_502 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_503;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed14 <= 3'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15092,14 +11087,7 @@ always @(*) begin
 			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_503 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_504;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed15 <= 16'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15116,14 +11104,7 @@ always @(*) begin
 			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_504 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_505;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed16 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15140,14 +11121,7 @@ always @(*) begin
 			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_505 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_506;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed17 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15164,14 +11138,7 @@ always @(*) begin
 			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_506 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_507;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed18 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15188,14 +11155,7 @@ always @(*) begin
 			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_507 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_508;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed19 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15212,14 +11172,7 @@ always @(*) begin
 			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_508 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_509;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed20 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15236,14 +11189,7 @@ always @(*) begin
 			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_509 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_510;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed21 <= 3'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15260,14 +11206,7 @@ always @(*) begin
 			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_510 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_511;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed22 <= 16'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15284,14 +11223,7 @@ always @(*) begin
 			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_511 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_512;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed23 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15308,14 +11240,7 @@ always @(*) begin
 			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_512 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_513;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed24 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15332,14 +11257,7 @@ always @(*) begin
 			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_513 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_514;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed25 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15356,14 +11274,7 @@ always @(*) begin
 			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_514 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_515;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed26 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15380,14 +11291,7 @@ always @(*) begin
 			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_515 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_516;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed27 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15404,15 +11308,17 @@ always @(*) begin
 			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_516 = dummy_s;
-// synthesis translate_on
 end
 assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge iodelay_clk) begin
 	if ((main_reset_counter != 1'd0)) begin
 		main_reset_counter <= (main_reset_counter - 1'd1);
@@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+			5'd24: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
 	end
 	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address1_re) begin
-		main_litedramcore_phaseinjector0_address_storage[15:8] <= builder_csrbank2_dfii_pi0_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+		main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r;
 	end
 	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
 	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
 		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
 	end
 	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
 	if (builder_csrbank2_dfii_pi1_command0_re) begin
 		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
 	end
 	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address1_re) begin
-		main_litedramcore_phaseinjector1_address_storage[15:8] <= builder_csrbank2_dfii_pi1_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+		main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r;
 	end
 	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
 	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
 		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
 	end
 	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
 	if (builder_csrbank2_dfii_pi2_command0_re) begin
 		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
 	end
 	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address1_re) begin
-		main_litedramcore_phaseinjector2_address_storage[15:8] <= builder_csrbank2_dfii_pi2_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+		main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r;
 	end
 	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
 	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
 		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
 	end
 	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
 	if (builder_csrbank2_dfii_pi3_command0_re) begin
 		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
 	end
 	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address1_re) begin
-		main_litedramcore_phaseinjector3_address_storage[15:8] <= builder_csrbank2_dfii_pi3_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+		main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r;
 	end
 	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
 	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
 		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
 	end
 	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
 		main_a7ddrphy_rst_storage <= 1'd0;
 		main_a7ddrphy_rst_re <= 1'd0;
@@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
 BUFG BUFG(
 	.I(main_clkout0),
 	.O(main_clkout_buf0)
@@ -19625,118 +15404,150 @@ IOBUF IOBUF_15(
 	.O(main_a7ddrphy_dq_i_nodelay15)
 );
 
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage[0:15];
-reg [25:0] memdat;
+reg [25:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_1[0:15];
-reg [25:0] memdat_1;
+reg [25:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_2[0:15];
-reg [25:0] memdat_2;
+reg [25:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_3[0:15];
-reg [25:0] memdat_3;
+reg [25:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_4[0:15];
-reg [25:0] memdat_4;
+reg [25:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_5[0:15];
-reg [25:0] memdat_5;
+reg [25:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_6[0:15];
-reg [25:0] memdat_6;
+reg [25:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 26-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 26 
+// Port 1 | Read: Async | Write: ---- | 
 reg [25:0] storage_7[0:15];
-reg [25:0] memdat_7;
+reg [25:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 FD FD(
 	.C(main_clkin),
 	.D(main_reset),
@@ -19893,3 +15704,7 @@ PLLE2_ADV #(
 );
 
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:13.
+//------------------------------------------------------------------------------
diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 5b1a383..1b6e88e 100644
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -518,7 +518,7 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842afc4
+7c0802a63842adc4
 fbe1fff8fbc1fff0
 f821ff51f8010010
 f88100d83bc10020
@@ -527,96 +527,97 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-600000004800245d
+6000000048002159
 7fc3f3787c7f1b78
-6000000048001e69
+6000000048001b7d
 7fe3fb78382100b0
-0000000048002a54
+00000000480027d4
 0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842af203c4c0001
+3842ad203c4c0001
 7d8000267c0802a6
-9181000848002991
-48001e65f821fed1
+9181000848002711
+48001b79f821fed1
 3c62ffff60000000
-4bffff3938637b10
+4bffff3938637a90
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637b30
+63ff000838637ab0
 3c62ffff4bffff15
-38637b507bff0020
+38637ad07bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b68
+4bfffee938637ae8
 4e00000073e90002
 3c62ffff41820010
-4bfffed138637b70
+4bfffed138637af0
 4d80000073e90004
 3c62ffff41820010
-4bfffeb938637b78
+4bfffeb938637af8
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b80
+4bfffea138637b00
 4182001073e90010
-38637b903c62ffff
-73e901004bfffe8d
+38637b103c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637ba0
-3b7b7ba83f62ffff
+4bfffe7938637b20
+3b7b7b283f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bb0
+4bfffe4138637b30
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637bc8
+4bfffe1938637b48
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637be07884b282
+38637b607884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637bf87c892392
+38637b787c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637c187f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637b98
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,182 +625,161 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637c38
-4082009073890002
-38637c583c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637bb857a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637bd8
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637c70
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637c807fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847cb038a57ca0
-4bfffb8938637cb8
-6000000048000f2d
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637bf03c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637c007b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637c3038a57c20
+4bfffb897ca42b78
+6000000048000c55
 3c62ffff418e0024
-4bfffb7138637ce8
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637c60
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637d00
-38a000403c9df000
+4bfffb4938637c78
+38a000403c9af000
 3861007078840020
-6000000048001cbd
+6000000048001889
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637d18
+794a83e438637c90
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637d383c62ffff
+38637cb03c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d9888810070
+38637d1088810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637dc8
+4bfffaa938637d40
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-6000000048001c15
-38637de83c62ffff
+60000000480017e1
+38637d603c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187d503b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637d783c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff000480024a8
-7884002038a00038
-48001b917f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-48001b497f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637c68
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
+3ba000003f02ffff
+3b187cc83b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637cf0
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+4800222c7d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048001761
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+6000000048001719
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637be83c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061291004
+7c604f2a7c0004ac
+392000013d40c800
+794a0020614a1008
 7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
+000000004e800020
 0000000000000000
-3d20c80000000000
-612900045463063e
+3842a6f83c4c0001
+4182006828030002
+4182003028030003
+4082007c28030001
+6129101c3d20c800
 7c0004ac79290020
-3d40c8007c604f2a
-614a000839200001
-7c0004ac794a0020
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a8ac
-2803000341820068
-2803000141820030
-3d20c8004082007c
-7929002061290038
+3d40c8007c804f2a
+614a102039200001
+3d20c80048000024
+792900206129104c
 7c804f2a7c0004ac
 392000013d40c800
-48000024614a003c
-612900a03d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a00a439200001
-7c0004ac794a0020
-4e8000207d20572a
-6129006c3d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a007039200001
-7c8307b44bffffd0
-000000004bffff24
-0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
-7c604f2a7c0004ac
-610810143d00c800
-7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+794a0020614a1050
+7d20572a7c0004ac
+3d20c8004e800020
+7929002061291034
+7c804f2a7c0004ac
+392000013d40c800
+4bffffd0614a1038
+4bffff287c8307b4
 0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
+3d20c80000000000
+6129081039400001
+792900207d431830
 7c604f2a7c0004ac
-610810183d00c800
+610808143d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
 394000013d20c800
-7d43183061291010
+7d43183061290810
 7c0004ac79290020
 3d00c8007c604f2a
-790800206108101c
+7908002061080818
 7d40472a7c0004ac
 7c0004ac39400000
 4e8000207d404f2a
 0000000000000000
 3d20c80000000000
-6129101039400001
+6129081039400001
 792900207d431830
 7c604f2a7c0004ac
-610810203d00c800
+6108081c3d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
@@ -809,592 +789,524 @@ a12100a660000000
 4182001c28030003
 4082004028030001
 392000003d40c800
-48000010614a0048
+48000010614a1028
 392000003d40c800
-794a0020614a00b0
+794a0020614a1058
 7d20572a7c0004ac
 3d40c8004e800020
-614a007c39200000
+614a104039200000
 3d40c8004bffffe4
-614a001439200000
+614a101039200000
 000000004bffffd4
 0000000000000000
-3842a6583c4c0001
-4182006828030002
-4182003028030003
-4082007c28030001
+4182004028030002
+4182001c28030003
+4082004028030001
 392000003d40c800
-794a0020614a0040
-7d20572a7c0004ac
-614a00443d40c800
-3d40c80048000024
-614a00a839200000
-7c0004ac794a0020
-3d40c8007d20572a
-794a0020614a00ac
+48000010614a1024
+392000003d40c800
+794a0020614a1054
 7d20572a7c0004ac
 3d40c8004e800020
-614a007439200000
-7c0004ac794a0020
-3d40c8007d20572a
-4bffffd0614a0078
-4bfffc9438600000
-0000000000000000
-2c03000000000000
-3929000178690020
-3920000140800008
-3929ffff2c290001
-600000004d820020
-000000004bfffff0
-0000000000000000
-3842a5783c4c0001
-48001ffd7c0802a6
-3ce08020f821ffa1
-60e700033bc10020
-7fcaf3787c7c1b78
-78e700203be00004
-3920000039000004
-7888f8427d0903a6
+614a103c39200000
+3d40c8004bffffe4
+614a100c39200000
+000000004bffffd4
+0000000000000000
+786900202c030000
+4080000839290001
+2c29000139200001
+4d8200203929ffff
+4bfffff060000000
+0000000000000000
+3c4c000100000000
+7c0802a63842a454
+f821ffa148001e59
+60a500033ca08020
+394000007c7e1b78
+78a5002038c1001f
+3b81002039000004
+7ce652147d0903a6
+7888f86239200004
 7c8400d0788407e0
-7c8642787c843838
-7cca49ae7cc43378
-4200ffe039290001
-394a0004393fffff
-4082ffc4793f0021
-4bfffbdd38600000
-392000003d40c800
-794a0020614a0014
+7c8428383929ffff
+7d0443787c884278
+4200ffe09d070001
+282a0010394a0004
+3d40c8004082ffc0
+794a0020614a100c
 7d20572a7c0004ac
-4bfffbf938600009
-4bffff313860000f
-3ce0c8003d40c800
-60e700f8614a0028
-794a00207fc9f378
-38c0000478e70020
-7cc903a6394afff0
-8cc800013909ffff
-7cc0572a7c0004ac
-4200fff0394a0004
-39290004394a0034
-4082ffd07c2a3800
-63bd10303fa0c800
+614a10103d40c800
+7c0004ac794a0020
+386000097d20572a
+3860000f4bfffc85
+3d20c8004bffff29
+612910143cc0c800
+7f8ae37860c61074
+78c6002079290020
+38eaffff38a00004
+3be000047ca903a6
+8ca7000139000000
+7905400c3bffffff
+4200fff07ca82b78
+7ca04f2a7c0004ac
+394a000439290018
+4082ffc47c293000
+63bd08303fa0c800
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffe21
+7c0004ac4bfffe41
 5463063e7c60ee2a
-7c0004ac4bfffd99
-388000177fa0ee2a
-3fa0c80057a3063e
-63bd102c4bfffba5
-4bfffe913860000f
+7c0004ac4bfffdc1
+388000177c60ee2a
+3fa0c8005463063e
+63bd082c4bfffc21
+4bfffe7d3860000f
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffdd9
+7c0004ac4bfffdf9
 5463063e7c60ee2a
-7c0004ac4bfffd51
-388000257fa0ee2a
-4bfffb6157a3063e
-4bfffe513860000f
-4bfffacd38600000
-392000003d40c800
-794a0020614a0014
-7d20572a7c0004ac
-3ba100303860000b
-3860000f4bfffae5
-3ce0c8004bfffe1d
-60e700283d60c800
-3c8033333c005555
-616b00f83d800f0f
-78e7002038c00000
-60005555207c0001
-618c0f0f60843333
-7c0004ac796b0020
-992100307d203e2a
-7c0004ac39270004
-992100317d204e2a
-7c0004ac39270008
-992100327d204e2a
-7c0004ac3927000c
-992100337d204e2a
-38a0000039200004
-7d2532147d2903a6
-7c091800552907fe
-7d45e8ae40820058
-7d0852787d1e28ae
-5509063e790afe62
-7d4a48507d4a0038
-554af0be7c895038
-7d4952147d4a2038
-7d2952145549e13e
-552ac23e7d894838
-552a843e7d295214
-552906be7d295214
-793f00207d29fa14
-4200ff9838a50001
-38c6000438e70034
-3bde00047c275800
-4082ff3878c60020
-7fe3fb7838210060
-0000000048001d98
-0000048001000000
-3842a2a83c4c0001
-7d9080267c0802a6
-48001d2191810008
-2e250000f821ff71
-4192001c7c7e1b78
-7c641b787c852378
-38637e003c62ffff
-600000004bfff2b5
-3f62ffff7fc3f378
-3b8000204bfffa61
-3b7b7e103ba00000
-7fc3f3783880002a
-388000544bfffcd9
-7fc3f3787c7f1b78
-7d3f1a144bfffcc9
-212900807d240034
-548360265484d97e
-7fa9ea147d234a14
-419200107bbd0020
-4bfff2517f63db78
-7fc3f37860000000
-4bfffa4d3b9cffff
-4082ffa47b9c0021
-3c62ffff41920014
-4bfff22938637e18
-3821009060000000
-818100087fa3eb78
-48001ca87d908120
-0300000000000000
-3c4c000100000580
-7c0802a63842a1bc
-f821ff7148001c39
+7c0004ac4bfffd79
+388000257c60ee2a
+4bfffbdd5463063e
+4bfffe3d3860000f
+6129100c3d20c800
+7c0004ac79290020
+3d20c8007fe04f2a
+7929002061291010
+7fe04f2a7c0004ac
+23de00013860000b
+3860000f4bfffb5d
+3d00c8004bfffe01
+610810183c80c800
+3ca033333d605555
+608410783c000f0f
+7908002038c00000
+616b555538610030
+60000f0f60a53333
+7c0004ac78840020
+394100307d20462a
+392000047d20552c
+7d2903a639400000
+552907fe7d265214
+408200547c09f000
+7d3c50ae7cea18ae
+5527063e7d293a78
+7d2958387929fe62
+7d2728387d293850
+7d2928385529f0be
+54e9e13e7ce74a14
+7d2900387d293a14
+7d293a145527c23e
+7d293a145527843e
+7fff4a14552906be
+4200ff9c394a0001
+3b9c000439080018
+38c600047c282000
+382100604082ff6c
+48001c0c7be30020
+0100000000000000
+3c4c000100000480
+7c0802a63842a19c
+f821ff7148001b99
 7c7f1b783ba00000
-3880002a4bfff9a1
-4bfffc257fe3fb78
-7c7e1b7838800054
-4bfffc157fe3fb78
-7d3c07b4393d0001
-2c0300007c7e1a14
-2c0900204182001c
-7fe3fb784182007c
-4bfff9ad7f9de378
-7fbeeb784bffffbc
-3b5d00017fe3fb78
-7f5a07b44bfff999
-3880002a3b60ffff
-4bfffbc57fe3fb78
-7c7c1b7838800054
-4bfffbb57fe3fb78
-2c0300007c7c1a14
-2c1bffff41820010
-7f5bd37840820008
-2c09001f393a0001
-4181001c7d3a07b4
-4bfff9457fe3fb78
-7f9de3784bffffb4
-4bffff943bc0ffff
-395d00022c1d001e
-4181000839200000
-2c1bffff213d001e
-7d2907b47d295214
-7d3b4b7840820008
-7fbeda142c1effff
+3880002a4bfffb35
+4bfffd297fe3fb78
+3b9d000138800054
+7fe3fb787c7e1b78
+7c63f2144bfffd15
+4182001c2c030000
+418200742c1c0020
+7f9de3787fe3fb78
+4bffffc04bfffb41
+7fe3fb787fbeeb78
+4bfffb2d3b7d0001
+3880002a3b80ffff
+4bfffcd17fe3fb78
+7c7a1b7838800054
+4bfffcc17fe3fb78
+2c0300007c63d214
+2c1cffff41820010
+7f7cdb7840820008
+2c1b001f3b7b0001
+7fe3fb784181001c
+4bffffb84bfffae1
+3bc0ffff3ba00020
+2c1d001e4bffff9c
+39200000395d0002
+213d001e41810008
+7d2952142c1cffff
+7d3c4b7840820008
+7fbee2142c1effff
 7fbd01947fbd0e70
-408200387bbd06e0
-38637e203c62ffff
-600000004bfff0dd
+4082003857bd06fe
+38637d783c62ffff
+600000004bfff2cd
 3bc000007fe3fb78
-386000644bfff889
-7c1df0004bfffad5
+386000644bfffa2d
+7c1df0004bfffbe9
 3821009040820034
-7cbed85048001b48
+7cbee05048001ab8
 7ca50e703c62ffff
-7fa4eb787ca50194
-7ca507b438637e30
-600000004bfff095
+7fa407b47ca50194
+7ca507b438637d88
+600000004bfff285
 7fe3fb784bffffb8
-4bfff88d3bde0001
-7fde07b438600064
-4bffffb04bfffa85
-0100000000000000
-3c4c000100000680
-3d40c8003842a01c
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c09000e
-f80100107c0802a6
-3920000ef821ffa1
-7d20572a7c0004ac
-38637e483c62ffff
-600000004bfff01d
-e801001038210060
-4e8000207c0803a6
+4bfffa2d3bde0001
+4bfffb9d38600064
+000000004bffffb4
+0000068001000000
+3842a0103c4c0001
+612910003d20c800
+7c0004ac79290020
+280a000e7d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac3940000e
+3c62ffff7d404f2a
+4bfff21138637da0
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429fa83c4c0001
+612910003d20c800
+7c0004ac79290020
+280a00017d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac39400001
+3c62ffff7d404f2a
+4bfff1a938637dc8
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429f403c4c0001
+4800190d7c0802a6
+3f80c800f821ff01
+3ea2ffff3f00c800
+3e62ffff3e82ffff
+639c08103f22ffff
+3e42ffff63180820
+3b4000013ba00000
+3ab57df03ae00000
+3a737e083a947e00
+7b9c00203b397b28
+3a527e107b180020
+7fb0eb787ba307e0
+7f56e8304bfff925
+3a2000003be00000
+7fbe07b439e00000
+7fc4f3787de507b4
+39c000207ea3ab78
+600000004bfff0f5
+3b6000007fc3f378
+3880002a4bfff855
+4bfffa497fc3f378
+39ceffff38800054
+7fc3f378f8610060
+e92100604bfffa35
+7c6400347c634a14
+5484d97e20630080
+7c8407b454896026
+7e83a3787d291a14
+4bfff0997f7b4a14
+7fc3f37860000000
+2c0e00004bfff849
+7e639b784082ffa4
+600000004bfff07d
+4bfffc997fc3f378
+4bfff0697f23cb78
+7c11d84060000000
+7dff7b784080000c
+2c0f00077f71db78
+7c0004ac4182002c
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+39ef00017ee0e72a
+3ba000014bffff28
+7fe507b44bffff00
+7e4393787fc4f378
+4bfff0117bff0020
+7a0307e060000000
+393f00014bfff80d
+420000287d2903a6
+4bfffc197fc3f378
+4bffefe97f23cb78
+2c1d000160000000
+382101004082ffb4
+7c0004ac480017b8
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+4bffffc07ee0e72a
 0100000000000000
-3c4c000100000080
-3d40c80038429fb4
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c090001
-f80100107c0802a6
-39200001f821ffa1
-7d20572a7c0004ac
-38637e703c62ffff
-600000004bffefb5
-e801001038210060
+3c4c000100001280
+7c0802a638429d64
+f821ffa1f8010010
+386000004bfffd49
+386000004bfff6fd
+386000014bfff78d
+386000014bfff6ed
+3c62ffff4bfff77d
+4bffef6938637e28
+4bfffde560000000
+382100604bfffd79
+e801001038600001
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429f4c
-f821ff61480019c1
-3f42ffff3be00000
-3b5a7ba83f02ffff
-57fd063e3b187e98
-7fa3eb783b600000
-4bfff7b53b200000
-38a000013bc00000
-7fe3fb787fc4f378
-7c7c1b784bfffc61
-4bfffd417fe3fb78
-4bffef317f43d378
-7c19e04060000000
-7fdbf3784080000c
-2c1e00077f99e378
-7fa3eb7841820020
-4bfff7b13bde0001
-4bffffb07fde07b4
-4bffff903be00001
-7fe4fb787f65db78
-3bc000007f03c378
-600000004bffeee5
-4bfff7357fa3eb78
-408200287c1ed800
-4bfffcd17fe3fb78
-4bffeec17f43d378
-2c1f000160000000
-382100a04082ffb8
-7fa3eb7848001938
-4bfff7493bde0001
-4bffffc47fde07b4
-0100000000000000
-3c4c000100000880
-7c0802a638429e44
-f821ff1148001895
-4bfffe193f60c800
-3f20c80038600000
-386000004bfff621
-4bfff6b53ee0c800
-637b101038600001
-386000014bfff609
-4bfff69d63391024
-62f710283c62ffff
-3ec2ffff38637eb0
-600000004bffee2d
-3be000003ea2ffff
-7b7b00203ba00001
-7af700207b390020
-3ad67ed83b000000
-7ffa07b43ab57ed0
-7fb1f8307fb2f830
-3a6000003b80ffff
-57f4063e3bc00000
-7e20df2a7c0004ac
-7fa0cf2a7c0004ac
-392900017bc90020
-420000f47d2903a6
-7f00df2a7c0004ac
-3a0000007e83a378
-39e000004bfff611
-7de47b7838a00000
-4bfffabd7f43d378
-7c691b787c038040
-7e09837840800008
-793000207e83a378
-392f00014bfff62d
-7d2f07b42c090008
-7c1098404082ffc8
-7fdcf3784081000c
-393e00027e138378
-7d3e07b42c090008
-600000004082ff70
-7be91764394280d0
-2c1e00007fca4aaa
-2c1cffff40800078
-7f44d3784082006c
-4bffed297ea3ab78
-7f9ee37860000000
-7e40df2a7c0004ac
-7fa0cf2a7c0004ac
-7bc900202c1e0000
-4080000839290001
-2c29000139200001
-408200443929ffff
-7f00df2a7c0004ac
-41820040283f0001
-4bfffed83be00001
-7fa0bf2a7c0004ac
-7f9ee3784bffff04
-7f44d3787fc5f378
-4bffecb97ec3b378
-4bffff9460000000
-7fa0bf2a7c0004ac
-3c62ffff4bffffac
-4bffec9938637ba8
-3c62ffff60000000
-4bffec8938637ee0
-4bfffcf960000000
-382100f04bfffc8d
-480016d838600001
-0100000000000000
-3c4c000100001180
-7c0802a638429c1c
-f821ff6148001691
-6129102c3d20c800
-792900203b200002
+7c0802a638429cf4
+f821ff51480016e5
+6129082c3d20c800
+792900203b000002
+7f004f2a7c0004ac
+3b2000033d20c800
+7929002061290830
 7f204f2a7c0004ac
-3b4000033d20c800
-7929002061291030
-7f404f2a7c0004ac
 3c62ffff3fc0c800
-38637ef03c804000
-4bffec0963de1000
-3ba0000160000000
-7bde00204bfffba5
-7fa0f72a7c0004ac
+38637e383c804000
+4bffeee163de0800
+3b80000160000000
+7bde00204bfffc89
+7f80f72a7c0004ac
 3be00000386003e8
-7c0004ac4bfff5f5
-3f80c8007fe0f72a
-639c0800386003e8
-7b9c00204bfff5dd
-7fe0e72a7c0004ac
-637b08043f60c800
+7c0004ac4bfff7f1
+386003e87fe0f72a
+4bfff7dd3f60c800
 7c0004ac7b7b0020
-3fc0c8007fe0df2a
-63de001438600000
-7bde00204bfff231
-7fe0f72a7c0004ac
-3920000c3f00c800
-7c0004ac7b180020
-386000007d20c72a
-4bfff5816063c350
-4bfff1fd38600000
+3f40c8007fe0df2a
+7b5a0020635a0004
+7fe0d72a7c0004ac
+63bd100c3fa0c800
+7c0004ac7bbd0020
+3fc0c8007fe0ef2a
+7bde002063de1010
 7fe0f72a7c0004ac
-7c0004ac3920000e
-386027107d20c72a
-386002004bfff55d
-7c0004ac4bfff1d9
+3920000c3ee0c800
+7af7002062f71000
+7d20bf2a7c0004ac
+6063c35038600000
+7c0004ac4bfff771
+7c0004ac7fe0ef2a
+3920000e7fe0f72a
+7d20bf2a7c0004ac
+4bfff74d38602710
+7c0004ac39200200
+7c0004ac7d20ef2a
+3860000f7f00f72a
+7c0004ac4bfff485
+7c0004ac7fe0ef2a
 3860000f7f20f72a
-386000004bfff205
-7c0004ac4bfff1c1
-3860000f7f40f72a
-386000064bfff1ed
-7c0004ac4bfff1a9
-3860000f7fa0f72a
-386009304bfff1d5
-7c0004ac4bfff191
+392000064bfff46d
+7d20ef2a7c0004ac
+7f80f72a7c0004ac
+4bfff4513860000f
+7c0004ac39200930
+7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff1bd
-386004004bfff4f5
-7c0004ac4bfff171
-386000037fe0f72a
-386000c84bfff19d
-4bfffc414bfff4d5
-3c8000204bfffacd
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100a07fa0e72a
-38c0000048001518
-3c80002038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000088001000000
-38429a103c4c0001
+386000c84bfff435
+392004004bfff6d9
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfff41138600003
+4bfff6b5386000c8
+4bfffb954bfffddd
+3c6040003c800020
+6000000048000779
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100b07f80df2a
+480015487d2307b4
+38a0000038c00000
+3c6040003c800020
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000980
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+38429a883c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637f103c62ffff
-600000004bffea2d
+38637e583c62ffff
+600000004bffeca5
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffe9f138637f18
+4bffec6938637e60
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637f28
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e70
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637f387ca54b92
+38637e807ca54b92
 000000004bffffa4
 0000008001000000
-384299403c4c0001
+384299b83c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bffe95138637f48
+4bffebc938637e90
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffe93938637f58
+4bffebb138637ea0
 3821007060000000
-00000000480013e8
+00000000480013e0
 0000018001000000
-384298d83c4c0001
-4800135d7c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bffe959
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bffe929
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d000048001330
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+384299503c4c0001
+480013557c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bffebc9
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bffeb79
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f8
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384297f03c4c0001
-480012797c0802a6
+384298403c4c0001
+480012497c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
-4bffe8657bff0020
-395f000160000000
-7d4903a62fbe0000
+420000387cbd2b78
+4bffeabd7bff0020
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126838210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e00284800123c
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a6384296ec
-480011557d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67f60
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384297583c4c0001
+7d8000267c0802a6
+918100084800113d
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67ea8
 3c62ffff4082009c
-38637f607b251028
-4bfffd357ba40020
-38637ba83c62ffff
-600000004bffe6a5
-4bffe70d3ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637f7078a51028
-4bfffccd7ba40020
-38637ba83c62ffff
-600000004bffe63d
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637f707ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fac7d838120
+38637ea87b851028
+4bfffd357b240020
+38637b283c62ffff
+600000004bffe91d
+600000004bffe989
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637eb87b051028
+4bfffcdd7be40020
+38637b283c62ffff
+600000004bffe8c5
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010ac
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637eb87ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a6384294d4
+3c4c000100000b80
+7c0802a638429594
 918100087d908026
-f821ff8148000f51
+f821ff7148000f89
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637f80
-600000004bffe4dd
-38637f983c62ffff
+7cbc2b7838637ec8
+600000004bffe79d
+38637ee03c62ffff
 3c62ffff4092000c
-4bffe4c138637fa8
+4bffe78138637ef0
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637fb83c62ffff
-600000004bffe4a5
+4bfffaad7bfde8c2
+38637f003c62ffff
+600000004bffe765
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1403,467 +1315,475 @@ f821ff8148000f51
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637fc0
-600000004bffe455
-4bfff9fd7f83e378
-38637fd03c62ffff
-600000004bffe43d
-38637ba83c62ffff
-600000004bffe42d
-600000004bffe499
-409200287cf602a6
+7f9c4b9238637f08
+600000004bffe715
+4bfffa457f83e378
+38637f183c62ffff
+600000004bffe6fd
+38637b283c62ffff
+600000004bffe6ed
+600000004bffe759
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637fd8
-600000004bffe3a5
-4bfff94d7fe3fb78
-38637fd03c62ffff
-600000004bffe38d
-38637ba83c62ffff
-600000004bffe37d
-8181000838210080
-48000e047d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a6384292cc
-f821ff7148000d49
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f8000
-3b60ffff4081000c
-3c62ffff577b0420
-38637fe87fc4f378
-600000004bffe2c5
-4bfff86d7fe3fb78
-38637fb83c62ffff
-600000004bffe2ad
-7fc3f3787f44d378
-38a000004bfff989
-7c7c1b787f64db78
-4bfffa5d7fc3f378
-38a0000138c00000
-7c7d1b787fe4fb78
-4bfffb497fc3f378
-7d291a147d3cea14
-2c0900007c7e1b78
-3c62ffff41820068
-7f84e3787b45f882
-4bffe24938637ff8
-6000000060000000
-7fa4eb787b65f082
-4bffe23138628010
-6000000060000000
-7fc4f3787be5f082
-4bffe21938628028
-6000000060000000
-4bffe20938628040
-3860000060000000
-48000c8c38210090
-3862805060000000
-600000004bffe1ed
-4bffffe438600001
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f20
+600000004bffe675
+4bfff9a57fe3fb78
+38637f183c62ffff
+600000004bffe65d
+38637b283c62ffff
+600000004bffe64d
+8181000838210090
+48000e4c7d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384293b83c4c0001
+48000db57c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f80007c9a2378
+4081000c7ffbfb78
+577b04203b60ffff
+7fc4f3783c62ffff
+4bffe5b138637f30
+7fe3fb7860000000
+3c62ffff4bfff8e1
+4bffe59938637f00
+7f44d37860000000
+4bfff9fd7fc3f378
+7f64db7838a00000
+7fc3f3787c7c1b78
+38c000004bfffaf9
+7fe4fb7838a00001
+7fc3f3787c7d1b78
+7d3de2144bfffbc9
+7c7e1b787d291a14
+4182006c2c090000
+7b45f8823c62ffff
+38637f407f84e378
+600000004bffe535
+7b65f0823c62ffff
+38637f587fa4eb78
+600000004bffe51d
+7be5f0823c62ffff
+38637f707fc4f378
+600000004bffe505
+38637f883c62ffff
+600000004bffe4f5
+3821009038600000
+48000cf47c6307b4
+38637f983c62ffff
+600000004bffe4d5
+4bffffe038600001
 0100000000000000
 3c4c000100000680
-600000003842918c
-6000000039228114
-89290000394280c8
-4182002c2c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-7c0004ace92a0000
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-e94a00005469063e
-7d2057ea7c0004ac
-000000004e800020
+6000000038429274
+6000000089228018
+2c09000039428010
+e92a00004182002c
+7c0004ac39290014
+712900207d204eaa
+e92a00004182ffec
+7c604faa7c0004ac
+e92a00004e800020
+7c0004ac39290010
+712900087d204eea
+5469063e4082ffec
+7c0004ace94a0000
+4e8000207d2057ea
 0000000000000000
-384291083c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-3be3fffff821ffd1
-2c3e00008fdf0001
-3821003040820010
-48000bd038600000
-4082000c281e000a
-4bffff413860000d
-4bffff397fc3f378
-000000004bffffd0
-0000028001000000
-384290a83c4c0001
-610800203d00c000
-7c0004ac79080020
-3d20c0007d0046ea
-6129000879080600
-7c0004ac79290020
-712900207d204eea
-3d20c00041820018
-7929002061290040
+3c4c000100000000
+7c0802a6384291f4
+fbe1fff8fbc1fff0
+f821ffd1f8010010
+8fdf00013be3ffff
+408200102c1e0000
+3860000038210030
+2c1e000a48000c3c
+3860000d4082000c
+7fc307b44bffff45
+4bffffd04bffff3d
+0100000000000000
+3c4c000100000280
+3d40c00038429194
+794a0020614a0020
+7d4056ea7c0004ac
+794a06003d20c000
+7929002061290008
 7d204eea7c0004ac
-600000003d40c000
-38e2811460000000
-794a0020614a2000
-3d40001cf94280c8
-7d085392614a2000
-794a0fc3792af804
-3920000141820080
-614a200c3d40c000
-794a002099270000
-7c0004ac3920ff80
-e92280c87d2057aa
-7d004faa7c0004ac
-7908c202e92280c8
+4182001871290020
+612900403d20c000
+7c0004ac79290020
+7929f8047d204eea
+79290fc33d00c000
+7908002061082000
+f902801060000000
+610820003d00001c
+418200847d4a4392
+3920000160000000
+3d00c00099228018
+3920ff806108200c
+7c0004ac79080020
+e92280107d2047aa
+7d404faa7c0004ac
+794ac202e9228010
 7c0004ac39290004
-e92280c87d004faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e92280c8
+39290010e9228010
 7d404faa7c0004ac
-39400007e92280c8
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
-994700003d20c000
-612920183908ffff
-7c0004ac79290020
-4e8000207d004fea
+394affff60000000
+3d20c00099228018
+7929002061292018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9072442000028
+7d434a147ca92850
+7c844a1439050001
+392000007d0903a6
+4e80002042000018
+7d23512a7d24502a
+4bffffcc394a0008
+7d0a49ae7d0448ae
+4bffffdc39290001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 2c24000000000000
 3881fff040820008
 f864000028050024
 4d81002038600000
-78e783e43ce00001
-e944000060e72600
-28090020892a0000
-2c25000040810028
-2c0500104182003c
-3860000041820038
-394a000148000080
-4bffffd0f9440000
-712900017ce94c36
-2c2500004082ffec
-38a0000a4082ffdc
-38a0000a4bffffd4
-4082ffc828090030
-2c090078892a0001
-394a00024082ffbc
-f944000038a00010
-38c9ffd04bffffac
-280a000954ca063e
-7cc9073441810034
-4c8000207c092800
-7c6519d238e70001
-7c691a14f8e40000
-89270000e8e40000
-4082ffc82c290000
-3949ff9f4e800020
-280a0019554a063e
-3929ffa941810010
-4bffffbc7d290734
-554a063e3949ffbf
+6108ffff3d00fffe
+6108d9ff790883e4
+89490000e9240000
+40810028280a0020
+4182003c2c250000
+418200382c050010
+4800008838600000
+f924000039290001
+7d0a56344bffffd0
+4182ffec714a0001
+4082ffdc2c250000
+4bffffd438a0000a
+2c0a003038a0000a
+894900014082ffc8
+4082ffbc2c0a0078
+38a0001039290002
+4bffffacf9240000
+54e7063e38eaffd0
+4181003c28070009
+7d2a07343929ffd0
+4c8000207c0a2800
+7c6519d239080001
+f90400007d290734
+e90400007c691a14
+714900ff89480000
+4e8000204082ffc0
+54e7063e38eaff9f
+4181000c28070019
+4bffffb83929ffa9
+554a063e394affbf
 4d810020280a0019
-4bffffe43929ffc9
+4bffffa03929ffc9
 0000000000000000
-7c6a1b7800000000
-7d2a18ae38600000
-4d8200202c090000
-4bfffff038630001
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000307d2903a6
-78aa072478a9e8c2
-7d0352141d29fff8
-7ca92a147c845214
-3945000139200000
-420000187d4903a6
-7d24502a4e800020
-394a00087d23512a
-7d4448ae4bffffc4
-392900017d4849ae
-000000004bffffdc
-0000000000000000
-280900193923ff9f
-3863ffe04d810020
-4e8000207c6307b4
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428da4
-918100087d908026
-f821ffa148000819
-7c7c1b783be00000
-600000007cbe2b78
-7cdd3378e9228060
-60000000f9210020
-f9210028e9228068
-2c2900007ca92b78
-2c3f000040820034
-3be0000140820008
-2e2700007c3f2040
-3b7fffff38600000
-3821006040810038
-7d90812081810008
-281d001048000800
-7929e10240820014
-7fff07b43bff0001
-7d29eb924bffffb4
-7f5ed3784bfffff0
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-600000004bffff21
-7c3df0405463063e
-7c69d9aee93c0000
-4081ffc83b7bffff
-38600001e93c0000
-fbfc00007fe9fa14
-000000004bffff84
-0000068003000000
-38428ca83c4c0001
-480007297c0802a6
+38428e903c4c0001
+480008897c0802a6
+7c7e1b78f821ffa1
+7ca32b787c9c2378
+38a0000a38800000
+eb3e00007cfd3b78
+7d3a4b787d1b4378
+4bfffe797cdf3378
+2b9d001060000000
+7c681b7839200000
+408200242c3f0000
+408200082c090000
+7d29d21439200001
+418100547c034800
+4800087038210060
+7bffe102409e0010
+4bffffcc39290001
+4bfffff47fffeb92
+2c2a00019b690000
+e93e0000394affff
+f93e000039290001
+e93e00004182ffc8
+7c28e0407d194850
+4bffffb44180ffd8
+2c0900007d294050
+794a00203949ffff
+40810010394a0001
+7c0940003d008000
+394000014082ffcc
+000000004bffffc4
+0000078001000000
+38428d983c4c0001
+480007997c0802a6
 3bc00000f821ffb1
 7c9c23787c7f1b78
 7cbd2b78eb630000
-4bfffe217fa3eb78
-7c23f04060000000
-e95f000040810014
-7c29e0407d3b5050
-3821005041800010
-4800073038600001
-3bde00017d3df0ae
-e93f0000992a0000
-f93f000039290001
-000000004bffffb8
-0000058001000000
-38428c283c4c0001
-480006a17c0802a6
-7c7d1b78f821ffa1
-7ca32b787c9b2378
-38a0000a38800000
-eb3d00007d3f4b78
-7cfc3b787cde3378
-4bfffc717d1a4378
-3920000060000000
-2c3e00007c6307b4
-2c2900004082002c
-3920000140820008
-7c0348007d3f4a14
-418100607d2a07b4
-3860000038210060
-281c001048000684
-7bdee10240820014
-7d2907b439290001
-7fdee3924bffffbc
-9b4800004bfffff0
-3929ffff2c290001
-394a0001e95d0000
-4182ffbcf95d0000
-7d594050e91d0000
-4180ffd87c2ad840
-7d4a18504bffffa8
-392affff2c0a0000
-3929000179290020
-3c60800040810010
-4082ffcc7c0a1800
-4bffffc439200001
+4bfffd697fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007a4
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428b24
-f821fed148000571
-f86100607c741b79
-4182006438600000
-4182005c2c240000
-6000000039210040
-3ae4ffff60000000
-3b210020f9210078
-3a4280803ac00000
-3a2280783ba10060
+3c4c000100000580
+7c0802a638428d1c
+918100087d908026
+f821ffa148000711
+2b8600103be00000
+3d22ffff7c7c1b78
+7cbe2b78e9297fa8
+7caa2b787cdd3378
+3d22fffff9210020
+f9210028e9297fb0
+408200342c2a0000
+408200082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8181000838210060
+480006f47d908120
+794ae102409e0010
+4bffffbc3bff0001
+4bfffff47d4aeb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdad
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428c283c4c0001
+480005f57c0802a6
+3be00000f821fee1
+f86100607c691b79
+41820060f9210068
+418200582c240000
+3e62ffff39210040
+3ae4ffff3e22ffff
+3b010020f9210070
+3a4000203ac00000
+3ba100603a737fc8
+e94100683a317fc0
 ebc1006089250000
-418200102c290000
-7c3fb8407ff4f050
-3920000041800020
-e8610060993e0000
-7e8307b47e941850
-4800054438210130
-3945000128090025
-38e00000408204c4
-e901007889250000
-7cea07b4f8a10068
-390700017d2741ae
-7d0807b48d250001
-4182005828090064
-4182005028090069
-4182004828090075
-4182004028090078
-4182003828090058
-4182003028090070
-4182002828090063
-4182002028090073
-4182001828090025
-418200102809004f
-38e700012809006f
-394a00024082ff88
-7d4a07b428090025
-7d5952147d194214
-9aca002099280020
-393e000140820020
-39200025f9210060
-e9210068993e0000
-4bffff0438a90002
-eb66000039260008
-3a6000207fffb850
-f92100703b010041
-3929ffd289210041
+712a00ff7feaf050
+7c3fb8404182000c
+3920000041800018
+38210120993e0000
+480005c47fe307b4
+390500012c0a0025
+38e0000040820548
+e901007089250000
+7cea3b787cb02b78
+7d2741ae8c650001
+5469063e39070001
+418200b02c090064
+4181002c28090078
+4181002c28090068
+418200982c090058
+4181008828090058
+418200882c090025
+418200802c09004f
+4bffffa438e70001
+548b063e3883ff97
+4181ffec280b000f
+396b75043d62ffff
+7c8b22aa788415a8
+7c8903a67c845a14
+000000484e800420
+ffffffccffffffcc
+ffffffccffffffcc
+00000048ffffffcc
+ffffffcc00000048
+00000048ffffffcc
+00000048ffffffcc
+ffffffccffffffcc
+2c09006300000048
+394a00024bffff84
+7d0807b42c090025
+7d1842147d4a07b4
+986800207d585214
+408200189aca0020
+993e0000395e0001
+38b00002f9410060
+892100414bfffeb4
+7fffb850eb860000
+3aa0002039e60008
+3929ffd23b210041
 4082000c712900fd
-3b0100423a600030
-3b4000043aa00000
-3a0000013b800000
-7ddb00d039e0002d
-2809004f48000164
-3898000188f80001
-38c9ffa8418201d0
-2805002254c5063e
-3ca2ffff41810370
-78c615a838a576b8
-7cc62a147cc532aa
-4e8004207cc903a6
-0000035000000148
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000024400000350
-000003500000008c
-0000035000000350
-0000008c00000338
-0000035000000350
-0000035000000328
-000001a000000350
-00000350000001ec
-0000028400000350
-0000008c00000350
-0000035000000350
-000003500000014c
-2809007500000330
-9aca00207d41e214
-418200347f6adb78
-3929ffff57491838
-7f6948397e094836
-99e8000041820020
-39290001e9210060
-7b491f24f9210060
-7dca50387d52482a
+3b2100423aa00030
+3b4000043a800000
+56b5063e3b600000
+480001687ddc00d0
+38b900012c06004f
+38e8ffa8418201dc
+2804002254e4063e
+3c82ffff418103ac
+78e715a838847600
+7ce722147ce43aaa
+4e8004207ce903a6
+0000038c00000150
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+000002580000038c
+0000038c0000008c
+0000038c0000038c
+0000008c00000370
+0000038c0000038c
+0000038c0000035c
+000001ac0000038c
+0000038c000001fc
+000002980000038c
+0000008c0000038c
+0000038c0000038c
+0000038c00000154
+2c06007500000368
+7d4152147b6a0020
+7f8ae3789aca0020
+5747183841820038
+38e7ffff39000001
+7f8840397d083836
+3940002d41820020
+9949ffff39290001
+7b491e68f9210060
+7dca50387d53482a
 7d465378e8810060
-f941008038e0000a
-392000007f25cb78
-7fa3eb787e689b78
+f941007838e0000a
+392000007f05c378
+7fa3eb787ea8ab78
 7c84f8507c9e2050
-e88100604bfffc31
-7ea7ab78e9410080
+e88100604bfffa79
+7a8707e0e9410078
 7c9e205038c0000a
 7c84f8507d455378
-4bfffa917fa3eb78
-893800003b180001
-2c290000e9010060
-7d5e405041820010
-4181fe887c3f5040
-4bfffe28e8c10070
-7d21e2143aa00001
-7c8af85038e00010
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffba9
-38c000107ea7ab78
-e96100807c9e2050
-4bffff787d655b78
-38e000087d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffb55f9610080
-7ea7ab78e8810060
+4bfffbc97fa3eb78
+891900003b390001
+710600ffe9210060
+7d5e485041820010
+4181fe847c3f5040
+4bfffe307de67b78
+7b6900203a800001
+7d214a1438e00010
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff9edf9610078
+7a8707e0e8810060
+7c9e205038c00010
+7d655b78e9610078
+7b6900204bffff74
+7d214a1438e00008
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff995f9610078
+7a8707e0e8810060
 7c9e205038c00008
-7d21e2144bffffac
-7f66db7838e00010
-9ac900207c8af850
-3920000239000020
-7fa3eb787f25cb78
-e88100604bfffb19
-7fa3eb787e258b78
+7b6900204bffffa8
+7d214a1438e00010
+7c8af8507f86e378
+9ac9002039000020
+392000027f05c378
+4bfff9557fa3eb78
+7e258b78e8810060
+7c9e20507fa3eb78
+4bfffa357c84f850
+7a8707e0e8810060
+7f85e37838c00010
+4bfffec87c9e2050
+390000207b690020
+38e0000a7d214a14
+7f05c37838c00001
+7c8af8509ac90020
+7fa3eb7839200000
+e92100604bfff8f9
+392900019b890000
+4bfffe94f9210060
+38a0000a7b680020
+f9410080f9210088
+388000007d014214
+9ac800207f03c378
+600000004bfff76d
+7f83e378f8610078
+600000004bfff735
+e9410080e9010078
+7c281840e9210088
+e88100604181003c
+7fa3eb787f85e378
 7c84f8507c9e2050
-e88100604bfffa81
-38c000107ea7ab78
-7c9e20507f65db78
-7d21e2144bfffed4
-38e0000a39000020
-9ac9002038c00001
-392000007f25cb78
-7fa3eb787c8af850
-e92100604bfffac1
-e92100609b690000
-f921006039290001
-7d21e2144bfffea0
-f901009038a0000a
-38800000f9410088
-9ac900207f23cb78
-600000004bfff72d
-7f63db78f8610080
-600000004bfff83d
-7c291840e9210080
-7d2348514081004c
-e9010090e9410088
-408200087d4af850
-e8c1006039200001
-7c2a38407ce83050
-38e0002040810024
-3929ffff2c290001
-e8e1006098e60000
-f8e1006038e70001
-e88100604082ffd4
-7fa3eb787f65db78
-7c84f8507c9e2050
-4bfffdfc4bfff989
-418200482807006c
-4bfffdec3b400008
-3b40000228070068
-7c9823784082fde0
-4bfffdd43b400001
-554a063e3949ffd0
-4181fdc4280a0009
-7f81e214395c0001
-795c0020993c0020
-7c9823784bfffdb0
-993e00004bffffb8
-e92100607d455378
-f921006039290001
-000000004bfffae8
+4bfffe2c4bfff979
+392900019a490000
+7c29184039000001
+f921006040820034
+7ce9f0504bffffcc
+7ce7fa147c634050
+2c2700007d4af850
+390000007c691a14
+40820008394a0001
+2c2a000139400001
+4082ffb4394affff
+4082ffc071080001
+893900014bffff8c
+4182004c2c09006c
+4bfffdbc3b400008
+3b40000289390001
+4082fdac2c090068
+3b4000017cb92b78
+3928ffd04bfffda0
+280900095529063e
+7b6900204181fd90
+7d214a143b7b0001
+4bfffd7c99090020
+4bffffb47cb92b78
+3bde0001993e0000
+fbc100607d054378
+000000004bfffa6c
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -1938,9 +1858,8 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -1982,10 +1901,6 @@ ebe1fff8e8010010
 20676e69746f6f42
 415244206d6f7266
 0000000a2e2e2e4d
-62202c64256d2020
-007c203a64323025
-0000000000006425
-000000000000207c
 203a7379616c6564
 000000000000002d
 203a7379616c6564
@@ -2001,15 +1916,13 @@ ebe1fff8e8010010
 7764726168206f74
 746e6f6320657261
 0000000a2e6c6f72
+62202c64256d2020
+007c203a64323025
+0000000000006425
+000000000000207c
 203a747365622020
 302562202c64256d
 6000000000206432
-616c206574697257
-61632079636e6574
-6f6974617262696c
-00000000000a3a6e
-0000202d3a64256d
-002064253a64256d
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index 525dde1..cad0120 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -1,9 +1,25 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:31
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire clk,
-	input wire rst,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:09
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire clk,
+	input  wire rst,
 	output wire pll_locked,
 	output wire [13:0] ddram_a,
 	output wire [2:0] ddram_ba,
@@ -12,9 +28,9 @@ module litedram_core(
 	output wire ddram_we_n,
 	output wire ddram_cs_n,
 	output wire [1:0] ddram_dm,
-	inout wire [15:0] ddram_dq,
-	inout wire [1:0] ddram_dqs_p,
-	inout wire [1:0] ddram_dqs_n,
+	inout  wire [15:0] ddram_dq,
+	inout  wire [1:0] ddram_dqs_p,
+	inout  wire [1:0] ddram_dqs_n,
 	output wire ddram_clk_p,
 	output wire ddram_clk_n,
 	output wire ddram_cke,
@@ -22,32 +38,38 @@ module litedram_core(
 	output wire ddram_reset_n,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [23:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [23:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [15:0] user_port_native_0_wdata_we,
-	input wire [127:0] user_port_native_0_wdata_data,
+	input  wire [15:0] user_port_native_0_wdata_we,
+	input  wire [127:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [127:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg  main_rst = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
@@ -55,7 +77,7 @@ wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
 wire main_reset;
-reg main_power_down = 1'd0;
+reg  main_power_down = 1'd0;
 wire main_locked;
 wire main_clkin;
 wire main_clkout0;
@@ -66,48 +88,48 @@ wire main_clkout2;
 wire main_clkout_buf2;
 wire main_clkout3;
 wire main_clkout_buf3;
-reg [3:0] main_reset_counter = 4'd15;
-reg main_ic_reset = 1'd1;
-reg main_a7ddrphy_rst_storage = 1'd0;
-reg main_a7ddrphy_rst_re = 1'd0;
-reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg main_a7ddrphy_wlevel_en_re = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg  [3:0] main_reset_counter = 4'd15;
+reg  main_ic_reset = 1'd1;
+reg  main_a7ddrphy_rst_storage = 1'd0;
+reg  main_a7ddrphy_rst_re = 1'd0;
+reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
+reg  main_a7ddrphy_wlevel_en_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
 wire main_a7ddrphy_wlevel_strobe_r;
-reg main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg main_a7ddrphy_dly_sel_re = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+reg  main_a7ddrphy_dly_sel_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_rst_r;
-reg main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_inc_r;
-reg main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg main_a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg main_a7ddrphy_wrphase_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg  main_a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+reg  main_a7ddrphy_wrphase_re = 1'd0;
 wire [13:0] main_a7ddrphy_dfi_p0_address;
 wire [2:0] main_a7ddrphy_dfi_p0_bank;
 wire main_a7ddrphy_dfi_p0_cas_n;
@@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
 wire main_a7ddrphy_dfi_p0_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
 wire main_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p0_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p1_address;
 wire [2:0] main_a7ddrphy_dfi_p1_bank;
@@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
 wire main_a7ddrphy_dfi_p1_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
 wire main_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p1_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p2_address;
 wire [2:0] main_a7ddrphy_dfi_p2_bank;
@@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
 wire main_a7ddrphy_dfi_p2_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
 wire main_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p2_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p3_address;
 wire [2:0] main_a7ddrphy_dfi_p3_bank;
@@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
 wire main_a7ddrphy_dfi_p3_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
 wire main_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p3_rddata_valid;
 wire main_a7ddrphy_sd_clk_se_nodelay;
-reg main_a7ddrphy_dqs_oe = 1'd0;
+reg  main_a7ddrphy_dqs_oe = 1'd0;
 wire main_a7ddrphy_dqs_preamble;
 wire main_a7ddrphy_dqs_postamble;
 wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_dqspattern0 = 1'd0;
-reg main_a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dqspattern0 = 1'd0;
+reg  main_a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
 wire main_a7ddrphy_dqs_o_no_delay0;
 wire main_a7ddrphy_dqs_t0;
-reg [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
 wire main_a7ddrphy0;
 wire main_a7ddrphy_dqs_o_no_delay1;
 wire main_a7ddrphy_dqs_t1;
-reg [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
 wire main_a7ddrphy1;
-reg [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
 wire main_a7ddrphy_dq_oe;
 wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
 wire main_a7ddrphy_dq_o_nodelay0;
 wire main_a7ddrphy_dq_i_nodelay0;
 wire main_a7ddrphy_dq_i_delayed0;
 wire main_a7ddrphy_dq_t0;
-reg [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip03;
-reg [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay1;
 wire main_a7ddrphy_dq_i_nodelay1;
 wire main_a7ddrphy_dq_i_delayed1;
 wire main_a7ddrphy_dq_t1;
-reg [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip13;
-reg [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay2;
 wire main_a7ddrphy_dq_i_nodelay2;
 wire main_a7ddrphy_dq_i_delayed2;
 wire main_a7ddrphy_dq_t2;
-reg [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip21;
-reg [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay3;
 wire main_a7ddrphy_dq_i_nodelay3;
 wire main_a7ddrphy_dq_i_delayed3;
 wire main_a7ddrphy_dq_t3;
-reg [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip31;
-reg [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay4;
 wire main_a7ddrphy_dq_i_nodelay4;
 wire main_a7ddrphy_dq_i_delayed4;
 wire main_a7ddrphy_dq_t4;
-reg [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip41;
-reg [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay5;
 wire main_a7ddrphy_dq_i_nodelay5;
 wire main_a7ddrphy_dq_i_delayed5;
 wire main_a7ddrphy_dq_t5;
-reg [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip51;
-reg [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay6;
 wire main_a7ddrphy_dq_i_nodelay6;
 wire main_a7ddrphy_dq_i_delayed6;
 wire main_a7ddrphy_dq_t6;
-reg [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip61;
-reg [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay7;
 wire main_a7ddrphy_dq_i_nodelay7;
 wire main_a7ddrphy_dq_i_delayed7;
 wire main_a7ddrphy_dq_t7;
-reg [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip71;
-reg [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay8;
 wire main_a7ddrphy_dq_i_nodelay8;
 wire main_a7ddrphy_dq_i_delayed8;
 wire main_a7ddrphy_dq_t8;
-reg [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip81;
-reg [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay9;
 wire main_a7ddrphy_dq_i_nodelay9;
 wire main_a7ddrphy_dq_i_delayed9;
 wire main_a7ddrphy_dq_t9;
-reg [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip91;
-reg [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay10;
 wire main_a7ddrphy_dq_i_nodelay10;
 wire main_a7ddrphy_dq_i_delayed10;
 wire main_a7ddrphy_dq_t10;
-reg [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip101;
-reg [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay11;
 wire main_a7ddrphy_dq_i_nodelay11;
 wire main_a7ddrphy_dq_i_delayed11;
 wire main_a7ddrphy_dq_t11;
-reg [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip111;
-reg [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay12;
 wire main_a7ddrphy_dq_i_nodelay12;
 wire main_a7ddrphy_dq_i_delayed12;
 wire main_a7ddrphy_dq_t12;
-reg [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip121;
-reg [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay13;
 wire main_a7ddrphy_dq_i_nodelay13;
 wire main_a7ddrphy_dq_i_delayed13;
 wire main_a7ddrphy_dq_t13;
-reg [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip131;
-reg [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay14;
 wire main_a7ddrphy_dq_i_nodelay14;
 wire main_a7ddrphy_dq_i_delayed14;
 wire main_a7ddrphy_dq_t14;
-reg [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip141;
-reg [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay15;
 wire main_a7ddrphy_dq_i_nodelay15;
 wire main_a7ddrphy_dq_i_delayed15;
 wire main_a7ddrphy_dq_t15;
-reg [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip151;
-reg [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 wire [13:0] main_litedramcore_inti_p0_address;
 wire [2:0] main_litedramcore_inti_p0_bank;
-reg main_litedramcore_inti_p0_cas_n = 1'd1;
-reg main_litedramcore_inti_p0_cs_n = 1'd1;
-reg main_litedramcore_inti_p0_ras_n = 1'd1;
-reg main_litedramcore_inti_p0_we_n = 1'd1;
+reg  main_litedramcore_inti_p0_cas_n = 1'd1;
+reg  main_litedramcore_inti_p0_cs_n = 1'd1;
+reg  main_litedramcore_inti_p0_ras_n = 1'd1;
+reg  main_litedramcore_inti_p0_we_n = 1'd1;
 wire main_litedramcore_inti_p0_cke;
 wire main_litedramcore_inti_p0_odt;
 wire main_litedramcore_inti_p0_reset_n;
-reg main_litedramcore_inti_p0_act_n = 1'd1;
+reg  main_litedramcore_inti_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p0_wrdata;
 wire main_litedramcore_inti_p0_wrdata_en;
 wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
 wire main_litedramcore_inti_p0_rddata_en;
-reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
+reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p1_address;
 wire [2:0] main_litedramcore_inti_p1_bank;
-reg main_litedramcore_inti_p1_cas_n = 1'd1;
-reg main_litedramcore_inti_p1_cs_n = 1'd1;
-reg main_litedramcore_inti_p1_ras_n = 1'd1;
-reg main_litedramcore_inti_p1_we_n = 1'd1;
+reg  main_litedramcore_inti_p1_cas_n = 1'd1;
+reg  main_litedramcore_inti_p1_cs_n = 1'd1;
+reg  main_litedramcore_inti_p1_ras_n = 1'd1;
+reg  main_litedramcore_inti_p1_we_n = 1'd1;
 wire main_litedramcore_inti_p1_cke;
 wire main_litedramcore_inti_p1_odt;
 wire main_litedramcore_inti_p1_reset_n;
-reg main_litedramcore_inti_p1_act_n = 1'd1;
+reg  main_litedramcore_inti_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p1_wrdata;
 wire main_litedramcore_inti_p1_wrdata_en;
 wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
 wire main_litedramcore_inti_p1_rddata_en;
-reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
+reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p2_address;
 wire [2:0] main_litedramcore_inti_p2_bank;
-reg main_litedramcore_inti_p2_cas_n = 1'd1;
-reg main_litedramcore_inti_p2_cs_n = 1'd1;
-reg main_litedramcore_inti_p2_ras_n = 1'd1;
-reg main_litedramcore_inti_p2_we_n = 1'd1;
+reg  main_litedramcore_inti_p2_cas_n = 1'd1;
+reg  main_litedramcore_inti_p2_cs_n = 1'd1;
+reg  main_litedramcore_inti_p2_ras_n = 1'd1;
+reg  main_litedramcore_inti_p2_we_n = 1'd1;
 wire main_litedramcore_inti_p2_cke;
 wire main_litedramcore_inti_p2_odt;
 wire main_litedramcore_inti_p2_reset_n;
-reg main_litedramcore_inti_p2_act_n = 1'd1;
+reg  main_litedramcore_inti_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p2_wrdata;
 wire main_litedramcore_inti_p2_wrdata_en;
 wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
 wire main_litedramcore_inti_p2_rddata_en;
-reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
+reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p3_address;
 wire [2:0] main_litedramcore_inti_p3_bank;
-reg main_litedramcore_inti_p3_cas_n = 1'd1;
-reg main_litedramcore_inti_p3_cs_n = 1'd1;
-reg main_litedramcore_inti_p3_ras_n = 1'd1;
-reg main_litedramcore_inti_p3_we_n = 1'd1;
+reg  main_litedramcore_inti_p3_cas_n = 1'd1;
+reg  main_litedramcore_inti_p3_cs_n = 1'd1;
+reg  main_litedramcore_inti_p3_ras_n = 1'd1;
+reg  main_litedramcore_inti_p3_we_n = 1'd1;
 wire main_litedramcore_inti_p3_cke;
 wire main_litedramcore_inti_p3_odt;
 wire main_litedramcore_inti_p3_reset_n;
-reg main_litedramcore_inti_p3_act_n = 1'd1;
+reg  main_litedramcore_inti_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p3_wrdata;
 wire main_litedramcore_inti_p3_wrdata_en;
 wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
 wire main_litedramcore_inti_p3_rddata_en;
-reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
+reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p0_address;
 wire [2:0] main_litedramcore_slave_p0_bank;
 wire main_litedramcore_slave_p0_cas_n;
@@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata;
 wire main_litedramcore_slave_p0_wrdata_en;
 wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
 wire main_litedramcore_slave_p0_rddata_en;
-reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p1_address;
 wire [2:0] main_litedramcore_slave_p1_bank;
 wire main_litedramcore_slave_p1_cas_n;
@@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata;
 wire main_litedramcore_slave_p1_wrdata_en;
 wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
 wire main_litedramcore_slave_p1_rddata_en;
-reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p2_address;
 wire [2:0] main_litedramcore_slave_p2_bank;
 wire main_litedramcore_slave_p2_cas_n;
@@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata;
 wire main_litedramcore_slave_p2_wrdata_en;
 wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
 wire main_litedramcore_slave_p2_rddata_en;
-reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p3_address;
 wire [2:0] main_litedramcore_slave_p3_bank;
 wire main_litedramcore_slave_p3_cas_n;
@@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata;
 wire main_litedramcore_slave_p3_wrdata_en;
 wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
 wire main_litedramcore_slave_p3_rddata_en;
-reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] main_litedramcore_master_p0_address = 14'd0;
-reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg main_litedramcore_master_p0_cas_n = 1'd1;
-reg main_litedramcore_master_p0_cs_n = 1'd1;
-reg main_litedramcore_master_p0_ras_n = 1'd1;
-reg main_litedramcore_master_p0_we_n = 1'd1;
-reg main_litedramcore_master_p0_cke = 1'd0;
-reg main_litedramcore_master_p0_odt = 1'd0;
-reg main_litedramcore_master_p0_reset_n = 1'd0;
-reg main_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [13:0] main_litedramcore_master_p0_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg  main_litedramcore_master_p0_cas_n = 1'd1;
+reg  main_litedramcore_master_p0_cs_n = 1'd1;
+reg  main_litedramcore_master_p0_ras_n = 1'd1;
+reg  main_litedramcore_master_p0_we_n = 1'd1;
+reg  main_litedramcore_master_p0_cke = 1'd0;
+reg  main_litedramcore_master_p0_odt = 1'd0;
+reg  main_litedramcore_master_p0_reset_n = 1'd0;
+reg  main_litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p0_rddata;
 wire main_litedramcore_master_p0_rddata_valid;
-reg [13:0] main_litedramcore_master_p1_address = 14'd0;
-reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg main_litedramcore_master_p1_cas_n = 1'd1;
-reg main_litedramcore_master_p1_cs_n = 1'd1;
-reg main_litedramcore_master_p1_ras_n = 1'd1;
-reg main_litedramcore_master_p1_we_n = 1'd1;
-reg main_litedramcore_master_p1_cke = 1'd0;
-reg main_litedramcore_master_p1_odt = 1'd0;
-reg main_litedramcore_master_p1_reset_n = 1'd0;
-reg main_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p1_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg  main_litedramcore_master_p1_cas_n = 1'd1;
+reg  main_litedramcore_master_p1_cs_n = 1'd1;
+reg  main_litedramcore_master_p1_ras_n = 1'd1;
+reg  main_litedramcore_master_p1_we_n = 1'd1;
+reg  main_litedramcore_master_p1_cke = 1'd0;
+reg  main_litedramcore_master_p1_odt = 1'd0;
+reg  main_litedramcore_master_p1_reset_n = 1'd0;
+reg  main_litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p1_rddata;
 wire main_litedramcore_master_p1_rddata_valid;
-reg [13:0] main_litedramcore_master_p2_address = 14'd0;
-reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg main_litedramcore_master_p2_cas_n = 1'd1;
-reg main_litedramcore_master_p2_cs_n = 1'd1;
-reg main_litedramcore_master_p2_ras_n = 1'd1;
-reg main_litedramcore_master_p2_we_n = 1'd1;
-reg main_litedramcore_master_p2_cke = 1'd0;
-reg main_litedramcore_master_p2_odt = 1'd0;
-reg main_litedramcore_master_p2_reset_n = 1'd0;
-reg main_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p2_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg  main_litedramcore_master_p2_cas_n = 1'd1;
+reg  main_litedramcore_master_p2_cs_n = 1'd1;
+reg  main_litedramcore_master_p2_ras_n = 1'd1;
+reg  main_litedramcore_master_p2_we_n = 1'd1;
+reg  main_litedramcore_master_p2_cke = 1'd0;
+reg  main_litedramcore_master_p2_odt = 1'd0;
+reg  main_litedramcore_master_p2_reset_n = 1'd0;
+reg  main_litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p2_rddata;
 wire main_litedramcore_master_p2_rddata_valid;
-reg [13:0] main_litedramcore_master_p3_address = 14'd0;
-reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg main_litedramcore_master_p3_cas_n = 1'd1;
-reg main_litedramcore_master_p3_cs_n = 1'd1;
-reg main_litedramcore_master_p3_ras_n = 1'd1;
-reg main_litedramcore_master_p3_we_n = 1'd1;
-reg main_litedramcore_master_p3_cke = 1'd0;
-reg main_litedramcore_master_p3_odt = 1'd0;
-reg main_litedramcore_master_p3_reset_n = 1'd0;
-reg main_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p3_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg  main_litedramcore_master_p3_cas_n = 1'd1;
+reg  main_litedramcore_master_p3_cs_n = 1'd1;
+reg  main_litedramcore_master_p3_ras_n = 1'd1;
+reg  main_litedramcore_master_p3_we_n = 1'd1;
+reg  main_litedramcore_master_p3_cke = 1'd0;
+reg  main_litedramcore_master_p3_odt = 1'd0;
+reg  main_litedramcore_master_p3_reset_n = 1'd0;
+reg  main_litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p3_rddata;
 wire main_litedramcore_master_p3_rddata_valid;
 wire main_litedramcore_sel;
 wire main_litedramcore_cke;
 wire main_litedramcore_odt;
 wire main_litedramcore_reset_n;
-reg [3:0] main_litedramcore_storage = 4'd1;
-reg main_litedramcore_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] main_litedramcore_storage = 4'd1;
+reg  main_litedramcore_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector0_command_issue_r;
-reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector0_rddata_we;
-reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector1_command_issue_r;
-reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector1_rddata_we;
-reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector2_command_issue_r;
-reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector2_rddata_we;
-reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector3_command_issue_r;
-reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector3_rddata_we;
-reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire main_litedramcore_interface_bank0_valid;
 wire main_litedramcore_interface_bank0_ready;
 wire main_litedramcore_interface_bank0_we;
@@ -706,131 +728,131 @@ wire [20:0] main_litedramcore_interface_bank7_addr;
 wire main_litedramcore_interface_bank7_lock;
 wire main_litedramcore_interface_bank7_wdata_ready;
 wire main_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
 wire [127:0] main_litedramcore_interface_rdata;
-reg [13:0] main_litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg main_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p0_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p0_we_n = 1'd1;
 wire main_litedramcore_dfi_p0_cke;
 wire main_litedramcore_dfi_p0_odt;
 wire main_litedramcore_dfi_p0_reset_n;
-reg main_litedramcore_dfi_p0_act_n = 1'd1;
+reg  main_litedramcore_dfi_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p0_rddata;
 wire main_litedramcore_dfi_p0_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg main_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p1_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p1_we_n = 1'd1;
 wire main_litedramcore_dfi_p1_cke;
 wire main_litedramcore_dfi_p1_odt;
 wire main_litedramcore_dfi_p1_reset_n;
-reg main_litedramcore_dfi_p1_act_n = 1'd1;
+reg  main_litedramcore_dfi_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p1_rddata;
 wire main_litedramcore_dfi_p1_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg main_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p2_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p2_we_n = 1'd1;
 wire main_litedramcore_dfi_p2_cke;
 wire main_litedramcore_dfi_p2_odt;
 wire main_litedramcore_dfi_p2_reset_n;
-reg main_litedramcore_dfi_p2_act_n = 1'd1;
+reg  main_litedramcore_dfi_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p2_rddata;
 wire main_litedramcore_dfi_p2_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg main_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p3_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p3_we_n = 1'd1;
 wire main_litedramcore_dfi_p3_cke;
 wire main_litedramcore_dfi_p3_odt;
 wire main_litedramcore_dfi_p3_reset_n;
-reg main_litedramcore_dfi_p3_act_n = 1'd1;
+reg  main_litedramcore_dfi_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p3_rddata;
 wire main_litedramcore_dfi_p3_rddata_valid;
-reg main_litedramcore_cmd_valid = 1'd0;
-reg main_litedramcore_cmd_ready = 1'd0;
-reg main_litedramcore_cmd_last = 1'd0;
-reg [13:0] main_litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg main_litedramcore_cmd_payload_cas = 1'd0;
-reg main_litedramcore_cmd_payload_ras = 1'd0;
-reg main_litedramcore_cmd_payload_we = 1'd0;
-reg main_litedramcore_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_cmd_valid = 1'd0;
+reg  main_litedramcore_cmd_ready = 1'd0;
+reg  main_litedramcore_cmd_last = 1'd0;
+reg  [13:0] main_litedramcore_cmd_payload_a = 14'd0;
+reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg  main_litedramcore_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_cmd_payload_we = 1'd0;
+reg  main_litedramcore_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_cmd_payload_is_write = 1'd0;
 wire main_litedramcore_wants_refresh;
 wire main_litedramcore_wants_zqcs;
 wire main_litedramcore_timer_wait;
 wire main_litedramcore_timer_done0;
 wire [9:0] main_litedramcore_timer_count0;
 wire main_litedramcore_timer_done1;
-reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
 wire main_litedramcore_postponer_req_i;
-reg main_litedramcore_postponer_req_o = 1'd0;
-reg main_litedramcore_postponer_count = 1'd0;
-reg main_litedramcore_sequencer_start0 = 1'd0;
+reg  main_litedramcore_postponer_req_o = 1'd0;
+reg  main_litedramcore_postponer_count = 1'd0;
+reg  main_litedramcore_sequencer_start0 = 1'd0;
 wire main_litedramcore_sequencer_done0;
 wire main_litedramcore_sequencer_start1;
-reg main_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg main_litedramcore_sequencer_count = 1'd0;
+reg  main_litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
+reg  main_litedramcore_sequencer_count = 1'd0;
 wire main_litedramcore_zqcs_timer_wait;
 wire main_litedramcore_zqcs_timer_done0;
 wire [26:0] main_litedramcore_zqcs_timer_count0;
 wire main_litedramcore_zqcs_timer_done1;
-reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg main_litedramcore_zqcs_executer_start = 1'd0;
-reg main_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  main_litedramcore_zqcs_executer_start = 1'd0;
+reg  main_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
 wire main_litedramcore_bankmachine0_req_valid;
 wire main_litedramcore_bankmachine0_req_ready;
 wire main_litedramcore_bankmachine0_req_we;
 wire [20:0] main_litedramcore_bankmachine0_req_addr;
 wire main_litedramcore_bankmachine0_req_lock;
-reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine0_refresh_req;
-reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine0_row = 14'd0;
-reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine0_row = 14'd0;
+reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
 wire main_litedramcore_bankmachine0_row_hit;
-reg main_litedramcore_bankmachine0_row_open = 1'd0;
-reg main_litedramcore_bankmachine0_row_close = 1'd0;
-reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine0_row_open = 1'd0;
+reg  main_litedramcore_bankmachine0_row_close = 1'd0;
+reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine1_req_valid;
 wire main_litedramcore_bankmachine1_req_ready;
 wire main_litedramcore_bankmachine1_req_we;
 wire [20:0] main_litedramcore_bankmachine1_req_addr;
 wire main_litedramcore_bankmachine1_req_lock;
-reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine1_refresh_req;
-reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine1_row = 14'd0;
-reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine1_row = 14'd0;
+reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
 wire main_litedramcore_bankmachine1_row_hit;
-reg main_litedramcore_bankmachine1_row_open = 1'd0;
-reg main_litedramcore_bankmachine1_row_close = 1'd0;
-reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine1_row_open = 1'd0;
+reg  main_litedramcore_bankmachine1_row_close = 1'd0;
+reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine2_req_valid;
 wire main_litedramcore_bankmachine2_req_ready;
 wire main_litedramcore_bankmachine2_req_we;
 wire [20:0] main_litedramcore_bankmachine2_req_addr;
 wire main_litedramcore_bankmachine2_req_lock;
-reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine2_refresh_req;
-reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine2_row = 14'd0;
-reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine2_row = 14'd0;
+reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
 wire main_litedramcore_bankmachine2_row_hit;
-reg main_litedramcore_bankmachine2_row_open = 1'd0;
-reg main_litedramcore_bankmachine2_row_close = 1'd0;
-reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine2_row_open = 1'd0;
+reg  main_litedramcore_bankmachine2_row_close = 1'd0;
+reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine3_req_valid;
 wire main_litedramcore_bankmachine3_req_ready;
 wire main_litedramcore_bankmachine3_req_we;
 wire [20:0] main_litedramcore_bankmachine3_req_addr;
 wire main_litedramcore_bankmachine3_req_lock;
-reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine3_refresh_req;
-reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine3_row = 14'd0;
-reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine3_row = 14'd0;
+reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
 wire main_litedramcore_bankmachine3_row_hit;
-reg main_litedramcore_bankmachine3_row_open = 1'd0;
-reg main_litedramcore_bankmachine3_row_close = 1'd0;
-reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine3_row_open = 1'd0;
+reg  main_litedramcore_bankmachine3_row_close = 1'd0;
+reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine4_req_valid;
 wire main_litedramcore_bankmachine4_req_ready;
 wire main_litedramcore_bankmachine4_req_we;
 wire [20:0] main_litedramcore_bankmachine4_req_addr;
 wire main_litedramcore_bankmachine4_req_lock;
-reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine4_refresh_req;
-reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine4_row = 14'd0;
-reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine4_row = 14'd0;
+reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
 wire main_litedramcore_bankmachine4_row_hit;
-reg main_litedramcore_bankmachine4_row_open = 1'd0;
-reg main_litedramcore_bankmachine4_row_close = 1'd0;
-reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine4_row_open = 1'd0;
+reg  main_litedramcore_bankmachine4_row_close = 1'd0;
+reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine5_req_valid;
 wire main_litedramcore_bankmachine5_req_ready;
 wire main_litedramcore_bankmachine5_req_we;
 wire [20:0] main_litedramcore_bankmachine5_req_addr;
 wire main_litedramcore_bankmachine5_req_lock;
-reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine5_refresh_req;
-reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine5_row = 14'd0;
-reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine5_row = 14'd0;
+reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
 wire main_litedramcore_bankmachine5_row_hit;
-reg main_litedramcore_bankmachine5_row_open = 1'd0;
-reg main_litedramcore_bankmachine5_row_close = 1'd0;
-reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine5_row_open = 1'd0;
+reg  main_litedramcore_bankmachine5_row_close = 1'd0;
+reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine6_req_valid;
 wire main_litedramcore_bankmachine6_req_ready;
 wire main_litedramcore_bankmachine6_req_we;
 wire [20:0] main_litedramcore_bankmachine6_req_addr;
 wire main_litedramcore_bankmachine6_req_lock;
-reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine6_refresh_req;
-reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine6_row = 14'd0;
-reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine6_row = 14'd0;
+reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
 wire main_litedramcore_bankmachine6_row_hit;
-reg main_litedramcore_bankmachine6_row_open = 1'd0;
-reg main_litedramcore_bankmachine6_row_close = 1'd0;
-reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine6_row_open = 1'd0;
+reg  main_litedramcore_bankmachine6_row_close = 1'd0;
+reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine7_req_valid;
 wire main_litedramcore_bankmachine7_req_ready;
 wire main_litedramcore_bankmachine7_req_we;
 wire [20:0] main_litedramcore_bankmachine7_req_addr;
 wire main_litedramcore_bankmachine7_req_lock;
-reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine7_refresh_req;
-reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine7_row = 14'd0;
-reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine7_row = 14'd0;
+reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
 wire main_litedramcore_bankmachine7_row_hit;
-reg main_litedramcore_bankmachine7_row_open = 1'd0;
-reg main_litedramcore_bankmachine7_row_close = 1'd0;
-reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine7_row_open = 1'd0;
+reg  main_litedramcore_bankmachine7_row_close = 1'd0;
+reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire main_litedramcore_ras_allowed;
 wire main_litedramcore_cas_allowed;
 wire [1:0] main_litedramcore_rdcmdphase;
 wire [1:0] main_litedramcore_wrcmdphase;
-reg main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_valid;
-reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire main_litedramcore_choose_cmd_cmd_payload_is_read;
 wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_cmd_request;
-reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
 wire main_litedramcore_choose_cmd_ce;
-reg main_litedramcore_choose_req_want_reads = 1'd0;
-reg main_litedramcore_choose_req_want_writes = 1'd0;
-reg main_litedramcore_choose_req_want_cmds = 1'd0;
-reg main_litedramcore_choose_req_want_activates = 1'd0;
+reg  main_litedramcore_choose_req_want_reads = 1'd0;
+reg  main_litedramcore_choose_req_want_writes = 1'd0;
+reg  main_litedramcore_choose_req_want_cmds = 1'd0;
+reg  main_litedramcore_choose_req_want_activates = 1'd0;
 wire main_litedramcore_choose_req_cmd_valid;
-reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [13:0] main_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_req_cmd_payload_is_cmd;
 wire main_litedramcore_choose_req_cmd_payload_is_read;
 wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_req_request;
-reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
 wire main_litedramcore_choose_req_ce;
-reg [13:0] main_litedramcore_nop_a = 14'd0;
-reg [2:0] main_litedramcore_nop_ba = 3'd0;
-reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg main_litedramcore_steerer0 = 1'd1;
-reg main_litedramcore_steerer1 = 1'd1;
-reg main_litedramcore_steerer2 = 1'd1;
-reg main_litedramcore_steerer3 = 1'd1;
-reg main_litedramcore_steerer4 = 1'd1;
-reg main_litedramcore_steerer5 = 1'd1;
-reg main_litedramcore_steerer6 = 1'd1;
-reg main_litedramcore_steerer7 = 1'd1;
+reg  [13:0] main_litedramcore_nop_a = 14'd0;
+reg  [2:0] main_litedramcore_nop_ba = 3'd0;
+reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg  main_litedramcore_steerer0 = 1'd1;
+reg  main_litedramcore_steerer1 = 1'd1;
+reg  main_litedramcore_steerer2 = 1'd1;
+reg  main_litedramcore_steerer3 = 1'd1;
+reg  main_litedramcore_steerer4 = 1'd1;
+reg  main_litedramcore_steerer5 = 1'd1;
+reg  main_litedramcore_steerer6 = 1'd1;
+reg  main_litedramcore_steerer7 = 1'd1;
 wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
-reg main_litedramcore_trrdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
+reg  main_litedramcore_trrdcon_count = 1'd0;
 wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] main_litedramcore_tfawcon_count;
-reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
 wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
-reg main_litedramcore_tccdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
+reg  main_litedramcore_tccdcon_count = 1'd0;
 wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
 wire main_litedramcore_read_available;
 wire main_litedramcore_write_available;
-reg main_litedramcore_en0 = 1'd0;
+reg  main_litedramcore_en0 = 1'd0;
 wire main_litedramcore_max_time0;
-reg [4:0] main_litedramcore_time0 = 5'd0;
-reg main_litedramcore_en1 = 1'd0;
+reg  [4:0] main_litedramcore_time0 = 5'd0;
+reg  main_litedramcore_en1 = 1'd0;
 wire main_litedramcore_max_time1;
-reg [3:0] main_litedramcore_time1 = 4'd0;
+reg  [3:0] main_litedramcore_time1 = 4'd0;
 wire main_litedramcore_go_to_refresh;
-reg main_init_done_storage = 1'd0;
-reg main_init_done_re = 1'd0;
-reg main_init_error_storage = 1'd0;
-reg main_init_error_re = 1'd0;
+reg  main_init_done_storage = 1'd0;
+reg  main_init_done_re = 1'd0;
+reg  main_init_error_storage = 1'd0;
+reg  main_init_error_re = 1'd0;
 wire [29:0] main_wb_bus_adr;
 wire [31:0] main_wb_bus_dat_w;
 wire [31:0] main_wb_bus_dat_r;
@@ -1570,6 +1592,7 @@ wire main_wb_bus_we;
 wire [2:0] main_wb_bus_cti;
 wire [1:0] main_wb_bus_bte;
 wire main_wb_bus_err;
+wire main_user_enable;
 wire main_user_port_cmd_valid;
 wire main_user_port_cmd_ready;
 wire main_user_port_cmd_payload_we;
@@ -1590,26 +1613,26 @@ wire builder_reset5;
 wire builder_reset6;
 wire builder_reset7;
 wire builder_pll_fb;
-reg [1:0] builder_refresher_state = 2'd0;
-reg [1:0] builder_refresher_next_state = 2'd0;
-reg [3:0] builder_bankmachine0_state = 4'd0;
-reg [3:0] builder_bankmachine0_next_state = 4'd0;
-reg [3:0] builder_bankmachine1_state = 4'd0;
-reg [3:0] builder_bankmachine1_next_state = 4'd0;
-reg [3:0] builder_bankmachine2_state = 4'd0;
-reg [3:0] builder_bankmachine2_next_state = 4'd0;
-reg [3:0] builder_bankmachine3_state = 4'd0;
-reg [3:0] builder_bankmachine3_next_state = 4'd0;
-reg [3:0] builder_bankmachine4_state = 4'd0;
-reg [3:0] builder_bankmachine4_next_state = 4'd0;
-reg [3:0] builder_bankmachine5_state = 4'd0;
-reg [3:0] builder_bankmachine5_next_state = 4'd0;
-reg [3:0] builder_bankmachine6_state = 4'd0;
-reg [3:0] builder_bankmachine6_next_state = 4'd0;
-reg [3:0] builder_bankmachine7_state = 4'd0;
-reg [3:0] builder_bankmachine7_next_state = 4'd0;
-reg [3:0] builder_multiplexer_state = 4'd0;
-reg [3:0] builder_multiplexer_next_state = 4'd0;
+reg  [1:0] builder_refresher_state = 2'd0;
+reg  [1:0] builder_refresher_next_state = 2'd0;
+reg  [3:0] builder_bankmachine0_state = 4'd0;
+reg  [3:0] builder_bankmachine0_next_state = 4'd0;
+reg  [3:0] builder_bankmachine1_state = 4'd0;
+reg  [3:0] builder_bankmachine1_next_state = 4'd0;
+reg  [3:0] builder_bankmachine2_state = 4'd0;
+reg  [3:0] builder_bankmachine2_next_state = 4'd0;
+reg  [3:0] builder_bankmachine3_state = 4'd0;
+reg  [3:0] builder_bankmachine3_next_state = 4'd0;
+reg  [3:0] builder_bankmachine4_state = 4'd0;
+reg  [3:0] builder_bankmachine4_next_state = 4'd0;
+reg  [3:0] builder_bankmachine5_state = 4'd0;
+reg  [3:0] builder_bankmachine5_next_state = 4'd0;
+reg  [3:0] builder_bankmachine6_state = 4'd0;
+reg  [3:0] builder_bankmachine6_next_state = 4'd0;
+reg  [3:0] builder_bankmachine7_state = 4'd0;
+reg  [3:0] builder_bankmachine7_next_state = 4'd0;
+reg  [3:0] builder_multiplexer_state = 4'd0;
+reg  [3:0] builder_multiplexer_next_state = 4'd0;
 wire builder_roundrobin0_request;
 wire builder_roundrobin0_grant;
 wire builder_roundrobin0_ce;
@@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce;
 wire builder_roundrobin7_request;
 wire builder_roundrobin7_grant;
 wire builder_roundrobin7_ce;
-reg builder_locked0 = 1'd0;
-reg builder_locked1 = 1'd0;
-reg builder_locked2 = 1'd0;
-reg builder_locked3 = 1'd0;
-reg builder_locked4 = 1'd0;
-reg builder_locked5 = 1'd0;
-reg builder_locked6 = 1'd0;
-reg builder_locked7 = 1'd0;
-reg builder_new_master_wdata_ready0 = 1'd0;
-reg builder_new_master_wdata_ready1 = 1'd0;
-reg builder_new_master_rdata_valid0 = 1'd0;
-reg builder_new_master_rdata_valid1 = 1'd0;
-reg builder_new_master_rdata_valid2 = 1'd0;
-reg builder_new_master_rdata_valid3 = 1'd0;
-reg builder_new_master_rdata_valid4 = 1'd0;
-reg builder_new_master_rdata_valid5 = 1'd0;
-reg builder_new_master_rdata_valid6 = 1'd0;
-reg builder_new_master_rdata_valid7 = 1'd0;
-reg builder_new_master_rdata_valid8 = 1'd0;
-reg [13:0] builder_litedramcore_adr = 14'd0;
-reg builder_litedramcore_we = 1'd0;
-reg [7:0] builder_litedramcore_dat_w = 8'd0;
-wire [7:0] builder_litedramcore_dat_r;
+reg  builder_locked0 = 1'd0;
+reg  builder_locked1 = 1'd0;
+reg  builder_locked2 = 1'd0;
+reg  builder_locked3 = 1'd0;
+reg  builder_locked4 = 1'd0;
+reg  builder_locked5 = 1'd0;
+reg  builder_locked6 = 1'd0;
+reg  builder_locked7 = 1'd0;
+reg  builder_new_master_wdata_ready0 = 1'd0;
+reg  builder_new_master_wdata_ready1 = 1'd0;
+reg  builder_new_master_rdata_valid0 = 1'd0;
+reg  builder_new_master_rdata_valid1 = 1'd0;
+reg  builder_new_master_rdata_valid2 = 1'd0;
+reg  builder_new_master_rdata_valid3 = 1'd0;
+reg  builder_new_master_rdata_valid4 = 1'd0;
+reg  builder_new_master_rdata_valid5 = 1'd0;
+reg  builder_new_master_rdata_valid6 = 1'd0;
+reg  builder_new_master_rdata_valid7 = 1'd0;
+reg  builder_new_master_rdata_valid8 = 1'd0;
+reg  [13:0] builder_litedramcore_adr = 14'd0;
+reg  builder_litedramcore_we = 1'd0;
+reg  [31:0] builder_litedramcore_dat_w = 32'd0;
+wire [31:0] builder_litedramcore_dat_r;
 wire [29:0] builder_litedramcore_wishbone_adr;
 wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] builder_litedramcore_wishbone_sel;
 wire builder_litedramcore_wishbone_cyc;
 wire builder_litedramcore_wishbone_stb;
-reg builder_litedramcore_wishbone_ack = 1'd0;
+reg  builder_litedramcore_wishbone_ack = 1'd0;
 wire builder_litedramcore_wishbone_we;
 wire [2:0] builder_litedramcore_wishbone_cti;
 wire [1:0] builder_litedramcore_wishbone_bte;
-reg builder_litedramcore_wishbone_err = 1'd0;
+reg  builder_litedramcore_wishbone_err = 1'd0;
 wire [13:0] builder_interface0_bank_bus_adr;
 wire builder_interface0_bank_bus_we;
-wire [7:0] builder_interface0_bank_bus_dat_w;
-reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
-reg builder_csrbank0_init_done0_re = 1'd0;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank0_init_done0_re = 1'd0;
 wire builder_csrbank0_init_done0_r;
-reg builder_csrbank0_init_done0_we = 1'd0;
+reg  builder_csrbank0_init_done0_we = 1'd0;
 wire builder_csrbank0_init_done0_w;
-reg builder_csrbank0_init_error0_re = 1'd0;
+reg  builder_csrbank0_init_error0_re = 1'd0;
 wire builder_csrbank0_init_error0_r;
-reg builder_csrbank0_init_error0_we = 1'd0;
+reg  builder_csrbank0_init_error0_we = 1'd0;
 wire builder_csrbank0_init_error0_w;
 wire builder_csrbank0_sel;
 wire [13:0] builder_interface1_bank_bus_adr;
 wire builder_interface1_bank_bus_we;
-wire [7:0] builder_interface1_bank_bus_dat_w;
-reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
-reg builder_csrbank1_rst0_re = 1'd0;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank1_rst0_re = 1'd0;
 wire builder_csrbank1_rst0_r;
-reg builder_csrbank1_rst0_we = 1'd0;
+reg  builder_csrbank1_rst0_we = 1'd0;
 wire builder_csrbank1_rst0_w;
-reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg builder_csrbank1_wlevel_en0_re = 1'd0;
+reg  builder_csrbank1_wlevel_en0_re = 1'd0;
 wire builder_csrbank1_wlevel_en0_r;
-reg builder_csrbank1_wlevel_en0_we = 1'd0;
+reg  builder_csrbank1_wlevel_en0_we = 1'd0;
 wire builder_csrbank1_wlevel_en0_w;
-reg builder_csrbank1_dly_sel0_re = 1'd0;
+reg  builder_csrbank1_dly_sel0_re = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_r;
-reg builder_csrbank1_dly_sel0_we = 1'd0;
+reg  builder_csrbank1_dly_sel0_we = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_w;
-reg builder_csrbank1_rdphase0_re = 1'd0;
+reg  builder_csrbank1_rdphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_r;
-reg builder_csrbank1_rdphase0_we = 1'd0;
+reg  builder_csrbank1_rdphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_w;
-reg builder_csrbank1_wrphase0_re = 1'd0;
+reg  builder_csrbank1_wrphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_r;
-reg builder_csrbank1_wrphase0_we = 1'd0;
+reg  builder_csrbank1_wrphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_w;
 wire builder_csrbank1_sel;
 wire [13:0] builder_interface2_bank_bus_adr;
 wire builder_interface2_bank_bus_we;
-wire [7:0] builder_interface2_bank_bus_dat_w;
-reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
-reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank2_dfii_control0_re = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_r;
-reg builder_csrbank2_dfii_control0_we = 1'd0;
+reg  builder_csrbank2_dfii_control0_we = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_w;
-reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_address1_r;
-reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_address1_w;
-reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
-reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
-reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi0_address0_r;
+reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi0_address0_w;
+reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
-reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
-reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
-reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
-reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
-reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
-reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
-reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
-reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_address1_r;
-reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_address1_w;
-reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
-reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
-reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi1_address0_r;
+reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi1_address0_w;
+reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
-reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
-reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
-reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
-reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
-reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
-reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
-reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
-reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_address1_r;
-reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_address1_w;
-reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
-reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
-reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi2_address0_r;
+reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi2_address0_w;
+reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
-reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
-reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
-reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
-reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
-reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
-reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
-reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
-reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_address1_r;
-reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_address1_w;
-reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
-reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
-reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi3_address0_r;
+reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi3_address0_w;
+reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
-reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
-reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
-reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
-reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
-reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
-reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
-reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
-reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
 wire builder_csrbank2_sel;
 wire [13:0] builder_csr_interconnect_adr;
 wire builder_csr_interconnect_we;
-wire [7:0] builder_csr_interconnect_dat_w;
-wire [7:0] builder_csr_interconnect_dat_r;
-reg [1:0] builder_state = 2'd0;
-reg [1:0] builder_next_state = 2'd0;
-reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
-reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg builder_litedramcore_we_next_value2 = 1'd0;
-reg builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg builder_rhs_array_muxed0 = 1'd0;
-reg [13:0] builder_rhs_array_muxed1 = 14'd0;
-reg [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg builder_rhs_array_muxed3 = 1'd0;
-reg builder_rhs_array_muxed4 = 1'd0;
-reg builder_rhs_array_muxed5 = 1'd0;
-reg builder_t_array_muxed0 = 1'd0;
-reg builder_t_array_muxed1 = 1'd0;
-reg builder_t_array_muxed2 = 1'd0;
-reg builder_rhs_array_muxed6 = 1'd0;
-reg [13:0] builder_rhs_array_muxed7 = 14'd0;
-reg [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg builder_rhs_array_muxed9 = 1'd0;
-reg builder_rhs_array_muxed10 = 1'd0;
-reg builder_rhs_array_muxed11 = 1'd0;
-reg builder_t_array_muxed3 = 1'd0;
-reg builder_t_array_muxed4 = 1'd0;
-reg builder_t_array_muxed5 = 1'd0;
-reg [20:0] builder_rhs_array_muxed12 = 21'd0;
-reg builder_rhs_array_muxed13 = 1'd0;
-reg builder_rhs_array_muxed14 = 1'd0;
-reg [20:0] builder_rhs_array_muxed15 = 21'd0;
-reg builder_rhs_array_muxed16 = 1'd0;
-reg builder_rhs_array_muxed17 = 1'd0;
-reg [20:0] builder_rhs_array_muxed18 = 21'd0;
-reg builder_rhs_array_muxed19 = 1'd0;
-reg builder_rhs_array_muxed20 = 1'd0;
-reg [20:0] builder_rhs_array_muxed21 = 21'd0;
-reg builder_rhs_array_muxed22 = 1'd0;
-reg builder_rhs_array_muxed23 = 1'd0;
-reg [20:0] builder_rhs_array_muxed24 = 21'd0;
-reg builder_rhs_array_muxed25 = 1'd0;
-reg builder_rhs_array_muxed26 = 1'd0;
-reg [20:0] builder_rhs_array_muxed27 = 21'd0;
-reg builder_rhs_array_muxed28 = 1'd0;
-reg builder_rhs_array_muxed29 = 1'd0;
-reg [20:0] builder_rhs_array_muxed30 = 21'd0;
-reg builder_rhs_array_muxed31 = 1'd0;
-reg builder_rhs_array_muxed32 = 1'd0;
-reg [20:0] builder_rhs_array_muxed33 = 21'd0;
-reg builder_rhs_array_muxed34 = 1'd0;
-reg builder_rhs_array_muxed35 = 1'd0;
-reg [2:0] builder_array_muxed0 = 3'd0;
-reg [13:0] builder_array_muxed1 = 14'd0;
-reg builder_array_muxed2 = 1'd0;
-reg builder_array_muxed3 = 1'd0;
-reg builder_array_muxed4 = 1'd0;
-reg builder_array_muxed5 = 1'd0;
-reg builder_array_muxed6 = 1'd0;
-reg [2:0] builder_array_muxed7 = 3'd0;
-reg [13:0] builder_array_muxed8 = 14'd0;
-reg builder_array_muxed9 = 1'd0;
-reg builder_array_muxed10 = 1'd0;
-reg builder_array_muxed11 = 1'd0;
-reg builder_array_muxed12 = 1'd0;
-reg builder_array_muxed13 = 1'd0;
-reg [2:0] builder_array_muxed14 = 3'd0;
-reg [13:0] builder_array_muxed15 = 14'd0;
-reg builder_array_muxed16 = 1'd0;
-reg builder_array_muxed17 = 1'd0;
-reg builder_array_muxed18 = 1'd0;
-reg builder_array_muxed19 = 1'd0;
-reg builder_array_muxed20 = 1'd0;
-reg [2:0] builder_array_muxed21 = 3'd0;
-reg [13:0] builder_array_muxed22 = 14'd0;
-reg builder_array_muxed23 = 1'd0;
-reg builder_array_muxed24 = 1'd0;
-reg builder_array_muxed25 = 1'd0;
-reg builder_array_muxed26 = 1'd0;
-reg builder_array_muxed27 = 1'd0;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg  [1:0] builder_state = 2'd0;
+reg  [1:0] builder_next_state = 2'd0;
+reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
+reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg  builder_litedramcore_we_next_value2 = 1'd0;
+reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg  builder_rhs_array_muxed0 = 1'd0;
+reg  [13:0] builder_rhs_array_muxed1 = 14'd0;
+reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg  builder_rhs_array_muxed3 = 1'd0;
+reg  builder_rhs_array_muxed4 = 1'd0;
+reg  builder_rhs_array_muxed5 = 1'd0;
+reg  builder_t_array_muxed0 = 1'd0;
+reg  builder_t_array_muxed1 = 1'd0;
+reg  builder_t_array_muxed2 = 1'd0;
+reg  builder_rhs_array_muxed6 = 1'd0;
+reg  [13:0] builder_rhs_array_muxed7 = 14'd0;
+reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg  builder_rhs_array_muxed9 = 1'd0;
+reg  builder_rhs_array_muxed10 = 1'd0;
+reg  builder_rhs_array_muxed11 = 1'd0;
+reg  builder_t_array_muxed3 = 1'd0;
+reg  builder_t_array_muxed4 = 1'd0;
+reg  builder_t_array_muxed5 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed12 = 21'd0;
+reg  builder_rhs_array_muxed13 = 1'd0;
+reg  builder_rhs_array_muxed14 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed15 = 21'd0;
+reg  builder_rhs_array_muxed16 = 1'd0;
+reg  builder_rhs_array_muxed17 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed18 = 21'd0;
+reg  builder_rhs_array_muxed19 = 1'd0;
+reg  builder_rhs_array_muxed20 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed21 = 21'd0;
+reg  builder_rhs_array_muxed22 = 1'd0;
+reg  builder_rhs_array_muxed23 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed24 = 21'd0;
+reg  builder_rhs_array_muxed25 = 1'd0;
+reg  builder_rhs_array_muxed26 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed27 = 21'd0;
+reg  builder_rhs_array_muxed28 = 1'd0;
+reg  builder_rhs_array_muxed29 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed30 = 21'd0;
+reg  builder_rhs_array_muxed31 = 1'd0;
+reg  builder_rhs_array_muxed32 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed33 = 21'd0;
+reg  builder_rhs_array_muxed34 = 1'd0;
+reg  builder_rhs_array_muxed35 = 1'd0;
+reg  [2:0] builder_array_muxed0 = 3'd0;
+reg  [13:0] builder_array_muxed1 = 14'd0;
+reg  builder_array_muxed2 = 1'd0;
+reg  builder_array_muxed3 = 1'd0;
+reg  builder_array_muxed4 = 1'd0;
+reg  builder_array_muxed5 = 1'd0;
+reg  builder_array_muxed6 = 1'd0;
+reg  [2:0] builder_array_muxed7 = 3'd0;
+reg  [13:0] builder_array_muxed8 = 14'd0;
+reg  builder_array_muxed9 = 1'd0;
+reg  builder_array_muxed10 = 1'd0;
+reg  builder_array_muxed11 = 1'd0;
+reg  builder_array_muxed12 = 1'd0;
+reg  builder_array_muxed13 = 1'd0;
+reg  [2:0] builder_array_muxed14 = 3'd0;
+reg  [13:0] builder_array_muxed15 = 14'd0;
+reg  builder_array_muxed16 = 1'd0;
+reg  builder_array_muxed17 = 1'd0;
+reg  builder_array_muxed18 = 1'd0;
+reg  builder_array_muxed19 = 1'd0;
+reg  builder_array_muxed20 = 1'd0;
+reg  [2:0] builder_array_muxed21 = 3'd0;
+reg  [13:0] builder_array_muxed22 = 14'd0;
+reg  builder_array_muxed23 = 1'd0;
+reg  builder_array_muxed24 = 1'd0;
+reg  builder_array_muxed25 = 1'd0;
+reg  builder_array_muxed26 = 1'd0;
+reg  builder_array_muxed27 = 1'd0;
 wire builder_xilinxasyncresetsynchronizerimpl0;
 wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl1;
@@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3;
 wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl3_expr;
 
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
 assign init_done = main_init_done_storage;
 assign init_error = main_init_error_storage;
 assign main_wb_bus_adr = wb_ctrl_adr;
@@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
 assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
 assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
-assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
 assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = rst;
+assign main_reset = (rst | main_rst);
 assign pll_locked = main_locked;
 assign main_clkin = clk;
 assign iodelay_clk = main_clkout_buf0;
@@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2;
 assign sys4x_dqs_clk = main_clkout_buf3;
 assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
 assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-
-// synthesis translate_off
-reg dummy_d;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
@@ -2081,14 +1989,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
 	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
 	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-// synthesis translate_off
-	dummy_d = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_1;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
@@ -2123,14 +2024,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
 	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
 	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-// synthesis translate_off
-	dummy_d_1 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_2;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
@@ -2165,14 +2059,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
 	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
 	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-// synthesis translate_off
-	dummy_d_2 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_3;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
@@ -2207,19 +2094,12 @@ always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
 	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
 	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-// synthesis translate_off
-	dummy_d_3 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-
-// synthesis translate_off
-reg dummy_d_4;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqs_oe <= 1'd0;
 	if (main_a7ddrphy_wlevel_en_storage) begin
@@ -2227,16 +2107,9 @@ always @(*) begin
 	end else begin
 		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
 	end
-// synthesis translate_off
-	dummy_d_4 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
 assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqspattern_o0 <= 8'd0;
 	main_a7ddrphy_dqspattern_o0 <= 7'd85;
@@ -2252,14 +2125,7 @@ always @(*) begin
 			main_a7ddrphy_dqspattern_o0 <= 1'd1;
 		end
 	end
-// synthesis translate_off
-	dummy_d_5 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip00 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value0)
@@ -2288,14 +2154,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_6 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip10 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value0)
@@ -2324,14 +2183,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_7 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip01 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value1)
@@ -2360,14 +2212,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_8 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip11 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value1)
@@ -2396,14 +2241,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_9 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip02 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value2)
@@ -2432,14 +2270,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_10 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip04 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value3)
@@ -2468,14 +2299,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_11 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip12 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value2)
@@ -2504,14 +2328,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_12 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip14 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value3)
@@ -2540,14 +2357,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_13 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip20 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value0)
@@ -2576,14 +2386,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_14 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip22 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value1)
@@ -2612,14 +2415,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_15 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip30 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value0)
@@ -2648,14 +2444,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_16 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip32 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value1)
@@ -2684,14 +2473,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_17 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_18;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip40 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value0)
@@ -2720,14 +2502,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_18 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_19;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip42 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value1)
@@ -2756,14 +2531,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_19 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_20;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip50 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value0)
@@ -2792,14 +2560,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_20 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_21;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip52 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value1)
@@ -2828,14 +2589,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_21 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip60 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value0)
@@ -2864,14 +2618,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_22 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip62 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value1)
@@ -2900,14 +2647,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_23 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip70 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value0)
@@ -2936,14 +2676,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_24 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip72 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value1)
@@ -2972,14 +2705,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_25 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_26;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip80 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value0)
@@ -3008,14 +2734,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_26 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip82 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value1)
@@ -3044,14 +2763,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_27 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip90 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value0)
@@ -3080,14 +2792,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_28 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip92 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value1)
@@ -3116,14 +2821,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_29 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip100 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value0)
@@ -3152,14 +2850,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_30 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_31;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip102 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value1)
@@ -3188,14 +2879,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_31 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_32;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip110 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value0)
@@ -3224,14 +2908,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_32 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_33;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip112 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value1)
@@ -3260,14 +2937,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_33 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_34;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip120 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value0)
@@ -3296,14 +2966,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_34 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_35;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip122 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value1)
@@ -3332,14 +2995,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_35 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_36;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip130 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value0)
@@ -3368,14 +3024,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_36 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_37;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip132 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value1)
@@ -3404,14 +3053,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_37 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_38;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip140 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value0)
@@ -3440,14 +3082,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_38 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip142 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value1)
@@ -3476,14 +3111,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_39 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_40;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip150 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value0)
@@ -3512,14 +3140,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_40 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_41;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip152 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value1)
@@ -3548,9 +3169,6 @@ always @(*) begin
 			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_41 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
 assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
@@ -3680,10 +3298,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-
-// synthesis translate_off
-reg dummy_d_42;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	end else begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p0_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -3691,14 +3313,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
-// synthesis translate_off
-	dummy_d_42 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_43;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3706,14 +3321,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
-// synthesis translate_off
-	dummy_d_43 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_44;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3721,14 +3329,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_44 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_45;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3736,14 +3337,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_45 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_46;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3751,28 +3345,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_46 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_47;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_47 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_48;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3780,28 +3360,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_48 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_49;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_49 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_50;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3809,14 +3375,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
-// synthesis translate_off
-	dummy_d_50 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_51;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3824,14 +3383,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
-// synthesis translate_off
-	dummy_d_51 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_52;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3839,14 +3391,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_52 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_53;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3854,14 +3399,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
-// synthesis translate_off
-	dummy_d_53 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_54;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -3869,28 +3407,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_54 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_55;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
-// synthesis translate_off
-	dummy_d_55 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_56;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3898,28 +3422,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_56 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_57;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_57 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_58;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3927,14 +3437,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_58 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_59;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3942,14 +3445,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_59 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_60;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -3957,14 +3453,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
-// synthesis translate_off
-	dummy_d_60 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_61;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3972,14 +3461,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
-// synthesis translate_off
-	dummy_d_61 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_62;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3987,14 +3469,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_62 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_63;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4002,14 +3477,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_63 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_64;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4017,28 +3485,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_64 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_65;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_65 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_66;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4046,28 +3500,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
-// synthesis translate_off
-	dummy_d_66 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_67;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_67 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_68;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4075,14 +3515,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
-// synthesis translate_off
-	dummy_d_68 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_69;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4090,14 +3523,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
-// synthesis translate_off
-	dummy_d_69 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_70;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4105,14 +3531,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_70 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_71;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4120,14 +3539,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
-// synthesis translate_off
-	dummy_d_71 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_72;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4135,28 +3547,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_72 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_73;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
-// synthesis translate_off
-	dummy_d_73 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_74;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4164,28 +3562,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_74 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_75 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_76;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4193,14 +3577,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_76 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_77;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4208,14 +3585,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_77 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_78;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -4223,14 +3593,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
-// synthesis translate_off
-	dummy_d_78 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_79;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4238,14 +3601,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_79 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_80;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4253,14 +3609,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_80 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_81;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4268,14 +3617,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_81 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_82;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4283,28 +3625,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_82 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_83;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_83 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_84;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4312,28 +3640,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
-// synthesis translate_off
-	dummy_d_84 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_85;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_85 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_86;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4341,28 +3655,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
-// synthesis translate_off
-	dummy_d_86 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_87;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
-	end
-// synthesis translate_off
-	dummy_d_87 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_88;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4370,14 +3663,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
-// synthesis translate_off
-	dummy_d_88 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_89;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4385,14 +3671,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4400,14 +3679,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_91;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4415,28 +3687,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_91 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_92;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
-// synthesis translate_off
-	dummy_d_92 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_93;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4444,28 +3702,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_93 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_94;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_94 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_95;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4473,28 +3717,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_95 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_96;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
-// synthesis translate_off
-	dummy_d_96 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4502,14 +3732,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_97 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_98;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -4517,14 +3740,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
-// synthesis translate_off
-	dummy_d_98 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_99;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4532,14 +3748,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
-// synthesis translate_off
-	dummy_d_99 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_100;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4547,14 +3763,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4562,14 +3771,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_101 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_102;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4577,28 +3779,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_102 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_103;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_103 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_104;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4606,28 +3794,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
-// synthesis translate_off
-	dummy_d_104 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_105;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_105 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_106;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4635,14 +3809,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_106 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_107;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4650,14 +3817,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
-// synthesis translate_off
-	dummy_d_107 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_108;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4665,14 +3825,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_108 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4680,14 +3833,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
-// synthesis translate_off
-	dummy_d_109 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_110;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4695,14 +3841,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_110 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_111;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4710,14 +3849,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_111 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_112;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4725,24 +3857,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_112 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_113;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
-	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
-	end
-// synthesis translate_off
-	dummy_d_113 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
 assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
@@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p0_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4767,14 +3885,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_114 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_115;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4782,14 +3893,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_115 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_116;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4797,24 +3901,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_116 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_117;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_117 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
@@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c
 assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
 assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_118;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p1_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4833,14 +3923,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_118 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_119;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4848,14 +3931,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_119 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4863,24 +3939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_120 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_121 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
@@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c
 assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
 assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p2_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4899,14 +3961,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4914,14 +3969,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_123 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4929,24 +3977,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_124 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_125 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
@@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c
 assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
 assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_126;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p3_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4965,14 +3999,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_126 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4980,14 +4007,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_127 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4995,24 +4015,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_128 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_129 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
@@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 &
 assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
 assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
 assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
 always @(*) begin
 	builder_refresher_next_state <= 2'd0;
 	builder_refresher_next_state <= builder_refresher_state;
@@ -5124,119 +4122,88 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_130 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_131;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
+	main_litedramcore_cmd_last <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+				end else begin
+					main_litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_131 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_132;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
+	main_litedramcore_sequencer_start0 <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
+			if (main_litedramcore_cmd_ready) begin
+				main_litedramcore_sequencer_start0 <= 1'd1;
 			end
 		end
+		2'd2: begin
+		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_132 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_133;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
+	main_litedramcore_cmd_valid <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
+					main_litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_133 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_134;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
+	main_litedramcore_zqcs_executer_start <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
+					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_134 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
@@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_135;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
@@ -5263,17 +4226,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_135 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
 assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
 assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_136;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
@@ -5281,9 +4237,6 @@ always @(*) begin
 			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_136 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
@@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_137;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
@@ -5313,9 +4262,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_137 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
@@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_138;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine0_next_state <= 4'd0;
 	builder_bankmachine0_next_state <= builder_bankmachine0_state;
@@ -5389,14 +4331,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_138 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_139;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5422,14 +4398,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_139 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5455,14 +4424,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_140 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_141;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5497,14 +4459,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_141 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_142;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5533,14 +4488,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_142 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_143;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5581,14 +4529,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_143 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_144;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5614,14 +4555,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_144 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5651,14 +4585,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_145 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5696,16 +4623,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_146 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5730,8 +4650,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -5741,16 +4661,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_147 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5775,7 +4688,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5786,16 +4699,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5820,8 +4726,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -5831,14 +4737,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_149 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_150;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5864,57 +4763,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_150 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_151;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_151 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
@@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_152;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
@@ -5941,17 +4785,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_152 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
 assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
 assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_153;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
@@ -5959,9 +4796,6 @@ always @(*) begin
 			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_153 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
@@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_154;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
@@ -5991,9 +4821,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_154 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
@@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_155;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine1_next_state <= 4'd0;
 	builder_bankmachine1_next_state <= builder_bankmachine1_state;
@@ -6067,14 +4890,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_155 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_156;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6100,14 +4957,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_156 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_157;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6133,14 +4983,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_157 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6175,14 +5018,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_158 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_159;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6211,14 +5047,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_159 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_160;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6259,14 +5088,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_160 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6292,14 +5114,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_161 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6329,47 +5144,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_162 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_163 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6407,14 +5182,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_164 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_165;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6452,14 +5220,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_165 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_166;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6497,14 +5258,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_166 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_167;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6542,30 +5296,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_167 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_168;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6576,23 +5320,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_168 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
@@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_169;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
@@ -6619,17 +5344,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_169 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
 assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_170;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
@@ -6637,9 +5355,6 @@ always @(*) begin
 			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_170 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
@@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_171;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
@@ -6669,9 +5380,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_171 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
@@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_172;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine2_next_state <= 4'd0;
 	builder_bankmachine2_next_state <= builder_bankmachine2_state;
@@ -6745,22 +5449,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_172 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_173;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6778,10 +5481,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
+							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6790,14 +5490,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_173 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6823,14 +5516,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_174 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_175;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6856,14 +5542,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_175 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6898,14 +5577,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_176 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6934,14 +5606,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_177 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_178;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6982,14 +5647,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_178 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7015,14 +5673,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_179 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7052,14 +5703,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_180 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7097,14 +5741,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7142,14 +5779,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_182 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_183;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7187,16 +5817,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_183 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_184;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -7205,9 +5828,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7218,32 +5838,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_184 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_185;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7254,23 +5879,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_185 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
@@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_186;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
@@ -7297,17 +5903,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
 assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
 assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
@@ -7315,9 +5914,6 @@ always @(*) begin
 			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
@@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_188;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
@@ -7347,9 +5939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_188 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
@@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_189;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine3_next_state <= 4'd0;
 	builder_bankmachine3_next_state <= builder_bankmachine3_state;
@@ -7423,14 +6008,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_189 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_190;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7456,14 +6075,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_190 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_191;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7489,14 +6101,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_191 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7531,14 +6136,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_192 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_193;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7567,14 +6165,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_193 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_194;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7615,22 +6206,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_194 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_195;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7643,31 +6230,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_195 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7697,47 +6262,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_196 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_197 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7775,14 +6300,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_198 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_199;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7820,14 +6338,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_199 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_200;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7865,16 +6376,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_200 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_201;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -7883,9 +6387,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7896,32 +6397,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_201 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_202;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7932,23 +6438,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_202 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
@@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_203;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
@@ -7975,17 +6462,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_203 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
 assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
 assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_204;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
@@ -7993,9 +6473,6 @@ always @(*) begin
 			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_204 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
@@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_205;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
@@ -8025,9 +6498,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_205 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
@@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_206;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine4_next_state <= 4'd0;
 	builder_bankmachine4_next_state <= builder_bankmachine4_state;
@@ -8101,24 +6567,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_206 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_207;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8132,29 +6594,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_207 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
+	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8167,24 +6634,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_208 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_209;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8195,7 +6658,30 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
 			end else begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
@@ -8209,14 +6695,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_209 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_210;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8245,14 +6724,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_210 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_211;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8293,14 +6765,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_211 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_212;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8326,14 +6791,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_212 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8363,14 +6821,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_213 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8408,14 +6859,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_214 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8453,14 +6897,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_215 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_216;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8498,14 +6935,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_216 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_217;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8543,14 +6973,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_217 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8576,57 +6999,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_218 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_219;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_219 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
@@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_220;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
@@ -8653,17 +7021,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
 assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
 assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
@@ -8671,9 +7032,6 @@ always @(*) begin
 			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_221 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
@@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_222;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
@@ -8703,9 +7057,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_222 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
@@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_223;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine5_next_state <= 4'd0;
 	builder_bankmachine5_next_state <= builder_bankmachine5_state;
@@ -8779,22 +7126,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_223 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8812,10 +7158,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
+							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8824,14 +7167,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_224 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_225;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8857,14 +7193,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_225 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8890,14 +7219,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_226 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8932,14 +7254,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_227 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_228;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8968,14 +7283,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_228 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_229;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9016,14 +7324,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_229 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_230;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9049,14 +7350,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9086,14 +7380,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_231 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9131,14 +7418,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_232 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9176,14 +7456,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_233 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_234;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9221,16 +7494,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_234 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_235;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -9239,9 +7505,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9252,32 +7515,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_235 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9288,23 +7556,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_236 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
@@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
@@ -9331,17 +7580,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_237 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
 assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
 assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_238;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
@@ -9349,9 +7591,6 @@ always @(*) begin
 			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_238 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
@@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_239;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
@@ -9381,9 +7616,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_239 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
@@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_240;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine6_next_state <= 4'd0;
 	builder_bankmachine6_next_state <= builder_bankmachine6_state;
@@ -9457,24 +7685,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_240 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_241;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9488,29 +7712,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_241 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
+	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9523,24 +7752,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_242 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_243;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9551,31 +7776,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_243 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_244;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9610,14 +7813,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_244 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_245;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9646,14 +7842,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_245 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9694,14 +7883,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_246 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9727,14 +7909,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_247 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9764,14 +7939,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_248 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9809,14 +7977,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_249 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_250;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9854,14 +8015,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_250 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_251;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9899,16 +8053,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_251 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_252;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -9917,9 +8064,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9930,32 +8074,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_252 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9966,23 +8115,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_253 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
@@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_254;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
@@ -10009,17 +8139,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_254 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
 assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_255;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
@@ -10027,9 +8150,6 @@ always @(*) begin
 			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_255 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
@@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_256;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
@@ -10059,9 +8175,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_256 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
@@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_257;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine7_next_state <= 4'd0;
 	builder_bankmachine7_next_state <= builder_bankmachine7_state;
@@ -10135,14 +8244,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_257 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_258;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10168,14 +8311,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_258 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_259;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10201,14 +8337,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_259 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_260;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10243,14 +8372,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_260 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_261;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10279,14 +8401,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_261 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_262;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10327,14 +8442,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_262 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_263;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10360,14 +8468,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_263 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_264;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10397,16 +8498,9 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_264 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10432,7 +8526,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10442,16 +8536,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10476,8 +8563,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10487,16 +8574,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_266 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10521,7 +8601,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -10532,16 +8612,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_267 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10566,8 +8639,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -10577,14 +8650,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_268 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10610,57 +8676,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_269 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_270 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
@@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_valids <= 8'd0;
 	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
@@ -10706,9 +8717,6 @@ always @(*) begin
 	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-// synthesis translate_off
-	dummy_d_271 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
 assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
@@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
 assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
 assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
 assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
 	end
-// synthesis translate_off
-	dummy_d_272 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
 	end
-// synthesis translate_off
-	dummy_d_273 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
 	end
-// synthesis translate_off
-	dummy_d_274 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
@@ -10768,14 +8751,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
 		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_275 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
@@ -10784,14 +8760,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
 		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_276 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
@@ -10800,14 +8769,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
 		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_277 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
@@ -10816,14 +8778,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
 		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_278 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
@@ -10832,14 +8787,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
 		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_279 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
@@ -10848,14 +8796,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
 		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_280 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
@@ -10864,14 +8805,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
 		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_281 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
@@ -10880,15 +8814,8 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
 		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_282 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_valids <= 8'd0;
 	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
@@ -10899,9 +8826,6 @@ always @(*) begin
 	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-// synthesis translate_off
-	dummy_d_283 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
 assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
@@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
 assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
 assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
 assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
 	end
-// synthesis translate_off
-	dummy_d_284 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
 	end
-// synthesis translate_off
-	dummy_d_285 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
 	end
-// synthesis translate_off
-	dummy_d_286 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
 assign main_litedramcore_dfi_p0_reset_n = 1'd1;
@@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1;
 assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
 assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
 assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
 always @(*) begin
 	builder_multiplexer_next_state <= 4'd0;
 	builder_multiplexer_next_state <= builder_multiplexer_state;
@@ -11023,18 +8922,15 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_287 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
+	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -11055,24 +8951,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_288 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -11094,22 +8989,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_289 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
+	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
 		end
@@ -11132,22 +9023,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_290 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -11168,25 +9055,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_291 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -11207,32 +9086,15 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_292 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
+			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11253,23 +9115,46 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_293 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11297,14 +9182,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_294 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11346,14 +9224,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_295 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11381,14 +9252,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11429,14 +9293,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11477,51 +9334,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_299 = dummy_s;
-// synthesis translate_on
 end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
@@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
 assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11580,14 +9388,7 @@ always @(*) begin
 			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_300 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11598,9 +9399,6 @@ always @(*) begin
 			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_301 = dummy_s;
-// synthesis translate_on
 end
 assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
 assign builder_roundrobin0_grant = 1'd0;
@@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0;
 assign builder_roundrobin5_grant = 1'd0;
 assign builder_roundrobin6_grant = 1'd0;
 assign builder_roundrobin7_grant = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
 always @(*) begin
 	builder_next_state <= 2'd0;
 	builder_next_state <= builder_state;
@@ -11631,16 +9425,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_302 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	builder_litedramcore_dat_w_next_value0 <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
@@ -11650,14 +9437,7 @@ always @(*) begin
 			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_303 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (builder_state)
@@ -11669,14 +9449,19 @@ always @(*) begin
 			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_304 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_wishbone_ack <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	builder_litedramcore_adr_next_value1 <= 14'd0;
 	case (builder_state)
@@ -11691,14 +9476,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (builder_state)
@@ -11713,14 +9491,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_306 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value2 <= 1'd0;
 	case (builder_state)
@@ -11735,14 +9506,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_307 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value_ce2 <= 1'd0;
 	case (builder_state)
@@ -11757,14 +9521,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_308 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_wishbone_dat_r <= 32'd0;
 	case (builder_state)
@@ -11776,28 +9533,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_309 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
-always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_310 = dummy_s;
-// synthesis translate_on
 end
 assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
 assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
@@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
+	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_311 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
+	builder_csrbank0_init_done0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_312 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
+	builder_csrbank0_init_error0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_313 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
+	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_314 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_315 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_316 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_317 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_318 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_319 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_320 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_321 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_322 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_323 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_324 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_325 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_326 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_327 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_328 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_329 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_330 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_331 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_332 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_333 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_335 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_336 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_337 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_338;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_338 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_339;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_339 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_340;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_340 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
 assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
@@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_341;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
+	builder_csrbank2_dfii_control0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_341 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_342;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
+	builder_csrbank2_dfii_control0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_342 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_343;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_343 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_344;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_344 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_345;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_345 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_346;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_346 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_347;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_347 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_348;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_348 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_349;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_349 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_350;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_350 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_351;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_351 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_352;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_352 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_353;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_353 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_354;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_354 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_355;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_355 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_356;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_357 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_358;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_358 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_359;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_359 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_360;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_360 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_361;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_361 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_362;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_362 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_363;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_363 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_364;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_364 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_365;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_365 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_366;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_366 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_367;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_367 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_368;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_368 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_369;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_369 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_370;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_370 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_371;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_371 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_372;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
 		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_372 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_373;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_373 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_374;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_374 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_375;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_375 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_376;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_376 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_377;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_377 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_378;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_378 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_379;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_379 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_380;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_380 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_381;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_381 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_382;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_382 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_383;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_383 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_384;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_384 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_385;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_385 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_386;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_386 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_387;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_387 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_388;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_388 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_389;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_389 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_390;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_390 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_391;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_391 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_392;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_392 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_393;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_393 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_394;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_394 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_395;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_395 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_396;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_396 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_397;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_397 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_398;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
 		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_398 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_399;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_399 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_400;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_400 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_401;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_401 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_402;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_402 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_403;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_403 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_404;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_404 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_405;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_405 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_406;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_406 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_407;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_407 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_408;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_408 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_409;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_409 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_410;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_410 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_411;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_411 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_412;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_412 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_413;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_413 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_414;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_414 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_415;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_416;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_416 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_417;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_417 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_418;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_418 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_419;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_419 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_420;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_420 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_421;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_421 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_422;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_422 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_423;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_423 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_424;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_424 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_425;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_425 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_426;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_426 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_427;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_427 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_428;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_428 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_429;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_429 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_430;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_430 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_431;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_431 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_432;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_432 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_433;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_433 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_434;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_434 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_435;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_435 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_436;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_436 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_437;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_437 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_438;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_438 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_439;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_439 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_440;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_440 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_441;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_441 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_442;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_442 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_443;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_443 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_444;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_444 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_445;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_445 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_446;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_446 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
@@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
 assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
 assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
 assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
 assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
 assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
 assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_csr_interconnect_adr = builder_litedramcore_adr;
 assign builder_csr_interconnect_we = builder_litedramcore_we;
 assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
@@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-
-// synthesis translate_off
-reg dummy_d_447;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13760,14 +10147,7 @@ always @(*) begin
 			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_447 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_448;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed1 <= 14'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13796,14 +10176,7 @@ always @(*) begin
 			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_448 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_449;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed2 <= 3'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13832,14 +10205,7 @@ always @(*) begin
 			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_449 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_450;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13868,14 +10234,7 @@ always @(*) begin
 			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_450 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_451;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13904,14 +10263,7 @@ always @(*) begin
 			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_451 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_452;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13940,14 +10292,7 @@ always @(*) begin
 			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_452 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_453;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13976,14 +10321,7 @@ always @(*) begin
 			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_453 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_454;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed1 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14012,14 +10350,7 @@ always @(*) begin
 			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_454 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_455;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed2 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14048,14 +10379,7 @@ always @(*) begin
 			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_455 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_456;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed6 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14084,14 +10408,7 @@ always @(*) begin
 			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_456 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_457;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed7 <= 14'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14120,14 +10437,7 @@ always @(*) begin
 			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_457 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_458;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed8 <= 3'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14156,14 +10466,7 @@ always @(*) begin
 			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_458 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_459;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed9 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14192,14 +10495,7 @@ always @(*) begin
 			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_459 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_460;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed10 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14228,14 +10524,7 @@ always @(*) begin
 			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_460 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_461;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed11 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14264,14 +10553,7 @@ always @(*) begin
 			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_461 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_462;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14300,14 +10582,7 @@ always @(*) begin
 			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_462 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_463;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14336,14 +10611,7 @@ always @(*) begin
 			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_463 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_464;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14372,14 +10640,7 @@ always @(*) begin
 			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_464 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_465;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed12 <= 21'd0;
 	case (builder_roundrobin0_grant)
@@ -14387,14 +10648,7 @@ always @(*) begin
 			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_465 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_466;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed13 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14402,14 +10656,7 @@ always @(*) begin
 			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_466 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_467;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed14 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14417,14 +10664,7 @@ always @(*) begin
 			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_467 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_468;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed15 <= 21'd0;
 	case (builder_roundrobin1_grant)
@@ -14432,14 +10672,7 @@ always @(*) begin
 			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_468 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_469;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed16 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14447,14 +10680,7 @@ always @(*) begin
 			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_469 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_470;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed17 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14462,14 +10688,7 @@ always @(*) begin
 			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_470 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_471;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed18 <= 21'd0;
 	case (builder_roundrobin2_grant)
@@ -14477,14 +10696,7 @@ always @(*) begin
 			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_471 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_472;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed19 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14492,14 +10704,7 @@ always @(*) begin
 			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_472 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_473;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed20 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14507,14 +10712,7 @@ always @(*) begin
 			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_473 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_474;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed21 <= 21'd0;
 	case (builder_roundrobin3_grant)
@@ -14522,14 +10720,7 @@ always @(*) begin
 			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_474 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_475;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed22 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14537,14 +10728,7 @@ always @(*) begin
 			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_475 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_476;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed23 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14552,14 +10736,7 @@ always @(*) begin
 			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_476 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_477;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed24 <= 21'd0;
 	case (builder_roundrobin4_grant)
@@ -14567,14 +10744,7 @@ always @(*) begin
 			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_477 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_478;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed25 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14582,14 +10752,7 @@ always @(*) begin
 			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_478 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_479;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed26 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14597,14 +10760,7 @@ always @(*) begin
 			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_479 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_480;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed27 <= 21'd0;
 	case (builder_roundrobin5_grant)
@@ -14612,14 +10768,7 @@ always @(*) begin
 			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_480 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_481;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed28 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14627,14 +10776,7 @@ always @(*) begin
 			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_481 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_482;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed29 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14642,14 +10784,7 @@ always @(*) begin
 			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_482 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_483;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed30 <= 21'd0;
 	case (builder_roundrobin6_grant)
@@ -14657,14 +10792,7 @@ always @(*) begin
 			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_483 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_484;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed31 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14672,14 +10800,7 @@ always @(*) begin
 			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_484 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_485;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed32 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14687,14 +10808,7 @@ always @(*) begin
 			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_485 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_486;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed33 <= 21'd0;
 	case (builder_roundrobin7_grant)
@@ -14702,14 +10816,7 @@ always @(*) begin
 			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_486 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_487;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed34 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14717,14 +10824,7 @@ always @(*) begin
 			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_487 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_488;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed35 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14732,14 +10832,7 @@ always @(*) begin
 			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_488 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_489;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed0 <= 3'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14756,14 +10849,7 @@ always @(*) begin
 			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_489 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_490;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed1 <= 14'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14780,14 +10866,7 @@ always @(*) begin
 			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_490 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_491;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed2 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14804,14 +10883,7 @@ always @(*) begin
 			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_491 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_492;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed3 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14828,14 +10900,7 @@ always @(*) begin
 			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_492 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_493;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed4 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14852,14 +10917,7 @@ always @(*) begin
 			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_493 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_494;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed5 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14876,14 +10934,7 @@ always @(*) begin
 			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_494 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_495;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed6 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14900,14 +10951,7 @@ always @(*) begin
 			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_495 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_496;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed7 <= 3'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14924,14 +10968,7 @@ always @(*) begin
 			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_496 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_497;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed8 <= 14'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14948,14 +10985,7 @@ always @(*) begin
 			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_497 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_498;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed9 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14972,14 +11002,7 @@ always @(*) begin
 			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_498 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_499;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed10 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14996,14 +11019,7 @@ always @(*) begin
 			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_499 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_500;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed11 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15020,14 +11036,7 @@ always @(*) begin
 			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_500 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_501;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed12 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15044,14 +11053,7 @@ always @(*) begin
 			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_501 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_502;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed13 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15068,14 +11070,7 @@ always @(*) begin
 			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_502 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_503;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed14 <= 3'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15092,14 +11087,7 @@ always @(*) begin
 			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_503 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_504;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed15 <= 14'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15116,14 +11104,7 @@ always @(*) begin
 			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_504 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_505;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed16 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15140,14 +11121,7 @@ always @(*) begin
 			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_505 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_506;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed17 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15164,14 +11138,7 @@ always @(*) begin
 			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_506 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_507;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed18 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15188,14 +11155,7 @@ always @(*) begin
 			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_507 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_508;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed19 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15212,14 +11172,7 @@ always @(*) begin
 			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_508 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_509;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed20 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15236,14 +11189,7 @@ always @(*) begin
 			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_509 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_510;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed21 <= 3'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15260,14 +11206,7 @@ always @(*) begin
 			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_510 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_511;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed22 <= 14'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15284,14 +11223,7 @@ always @(*) begin
 			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_511 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_512;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed23 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15308,14 +11240,7 @@ always @(*) begin
 			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_512 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_513;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed24 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15332,14 +11257,7 @@ always @(*) begin
 			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_513 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_514;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed25 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15356,14 +11274,7 @@ always @(*) begin
 			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_514 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_515;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed26 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15380,14 +11291,7 @@ always @(*) begin
 			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_515 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_516;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed27 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15404,15 +11308,17 @@ always @(*) begin
 			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_516 = dummy_s;
-// synthesis translate_on
 end
 assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge iodelay_clk) begin
 	if ((main_reset_counter != 1'd0)) begin
 		main_reset_counter <= (main_reset_counter - 1'd1);
@@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+			5'd24: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
 	end
 	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address1_re) begin
-		main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+		main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
 	end
 	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
 	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
 		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
 	end
 	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
 	if (builder_csrbank2_dfii_pi1_command0_re) begin
 		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
 	end
 	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address1_re) begin
-		main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+		main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
 	end
 	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
 	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
 		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
 	end
 	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
 	if (builder_csrbank2_dfii_pi2_command0_re) begin
 		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
 	end
 	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address1_re) begin
-		main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+		main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
 	end
 	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
 	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
 		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
 	end
 	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
 	if (builder_csrbank2_dfii_pi3_command0_re) begin
 		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
 	end
 	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address1_re) begin
-		main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+		main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
 	end
 	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
 	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
 		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
 	end
 	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
 		main_a7ddrphy_rst_storage <= 1'd0;
 		main_a7ddrphy_rst_re <= 1'd0;
@@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
 BUFG BUFG(
 	.I(main_clkout0),
 	.O(main_clkout_buf0)
@@ -19581,118 +15360,150 @@ IOBUF IOBUF_15(
 	.O(main_a7ddrphy_dq_i_nodelay15)
 );
 
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage[0:15];
-reg [23:0] memdat;
+reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_1[0:15];
-reg [23:0] memdat_1;
+reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_2[0:15];
-reg [23:0] memdat_2;
+reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_3[0:15];
-reg [23:0] memdat_3;
+reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_4[0:15];
-reg [23:0] memdat_4;
+reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_5[0:15];
-reg [23:0] memdat_5;
+reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_6[0:15];
-reg [23:0] memdat_6;
+reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_7[0:15];
-reg [23:0] memdat_7;
+reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 FD FD(
 	.C(main_clkin),
 	.D(main_reset),
@@ -19849,3 +15660,7 @@ PLLE2_ADV #(
 );
 
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:09.
+//------------------------------------------------------------------------------
diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init
index 6b2631b..49b28a5 100644
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
@@ -527,11 +527,11 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-6000000048002fc5
+6000000048002f19
 7fc3f3787c7f1b78
-60000000480029d1
+600000004800293d
 7fe3fb78382100b0
-00000000480035bc
+0000000048003594
 0000028001000000
 000000004e800020
 0000000000000000
@@ -540,83 +540,84 @@ f9410108f9210100
 0000000000000000
 3842bc203c4c0001
 7d8000267c0802a6
-91810008480034f9
-480029cdf821fed1
+91810008480034d1
+48002939f821fed1
 3c62ffff60000000
-4bffff3938637978
+4bffff3938637950
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637998
+63ff000838637970
 3c62ffff4bffff15
-386379b87bff0020
+386379907bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee9386379d0
+4bfffee9386379a8
 4e00000073e90002
 3c62ffff41820010
-4bfffed1386379d8
+4bfffed1386379b0
 4d80000073e90004
 3c62ffff41820010
-4bfffeb9386379e0
+4bfffeb9386379b8
 4d00000073e90008
 3c62ffff41820010
-4bfffea1386379e8
+4bfffea1386379c0
 4182001073e90010
-386379f83c62ffff
-73e901004bfffe8d
+386379d03c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637a08
-3b7b7a103f62ffff
+4bfffe79386379e0
+3b7b79e83f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637a18
+4bfffe41386379f0
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637a30
+4bfffe1938637a08
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637a487884b282
+38637a207884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637a607c892392
+38637a387c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637a807f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637a58
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,1142 +625,1128 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637aa0
-4082009073890002
-38637ac03c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637a7857a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637a98
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637ad8
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637ae87fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847b1838a57b08
-4bfffb8938637b20
-6000000048001a39
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637ab03c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637ac07b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637af038a57ae0
+4bfffb897ca42b78
+60000000480019cd
 3c62ffff418e0024
-4bfffb7138637b50
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637b20
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637b68
-38a000403c9df000
+4bfffb4938637b38
+38a000403c9af000
 3861007078840020
-6000000048002825
+6000000048002649
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637b80
+794a83e438637b50
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637ba03c62ffff
+38637b703c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637c0088810070
+38637bd088810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637c30
+4bfffaa938637c00
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-600000004800277d
-38637c503c62ffff
+60000000480025a1
+38637c203c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187bb83b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637be03c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff00048003010
-7884002038a00038
-480026f97f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-480026b17f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637ad0
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
+3ba000003f02ffff
+3b187b883b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637bb0
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+48002fec7d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048002521
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+60000000480024d9
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637aa83c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061291004
+7c604f2a7c0004ac
+392000013d40c800
+794a0020614a1008
 7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
-0000000000000000
-3d20c80000000000
-612900045463063e
-7c0004ac79290020
-3d40c8007c604f2a
-614a000839200001
-7c0004ac794a0020
-4e8000207d20572a
+000000004e800020
 0000000000000000
-3c4c000100000000
-280300023842b5ac
-2803000341820068
-2803000141820030
-3d20c8004082007c
-7929002061290058
-7c804f2a7c0004ac
-392000013d40c800
-48000024614a005c
-612901003d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a010439200001
-7c0004ac794a0020
-4e8000207d20572a
-612900ac3d20c800
+3842b5f83c4c0001
+4182006828030002
+4182003028030003
+4082007c28030001
+612910243d20c800
 7c0004ac79290020
 3d40c8007c804f2a
-614a00b039200001
-7c8307b44bffffd0
-000000004bffff24
-0000000000000000
+614a102839200001
+3d20c80048000024
+7929002061291064
+7c804f2a7c0004ac
 392000013d40c800
-7d231830614a1018
-7c0004ac794a0020
-3d00c8007c60572a
-7908002061081030
-7d20472a7c0004ac
-610810383d00c800
-7c0004ac79080020
-392000007d20472a
+794a0020614a1068
 7d20572a7c0004ac
-000000004e800020
-0000000000000000
-3d20c80039400001
-612910187d431830
-792900205463063e
-7c604f2a7c0004ac
-6108101c3d00c800
+3d20c8004e800020
+7929002061291044
+7c804f2a7c0004ac
+392000013d40c800
+4bffffd0614a1048
+4bffff287c8307b4
+0000000000000000
+3d40c80000000000
+614a081839200001
+794a00207d231830
+7c60572a7c0004ac
+610808303d00c800
 7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+3d00c8007d20472a
+7908002061080838
+7d20472a7c0004ac
+7c0004ac39200000
+4e8000207d20572a
 0000000000000000
-3d20c80039400001
-612910187d431830
-792900205463063e
+3d20c80000000000
+6129081839400001
+792900207d431830
 7c604f2a7c0004ac
-610810203d00c800
+6108081c3d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
-3d20c80039400001
-612910187d431830
-792900205463063e
-7c604f2a7c0004ac
-610810243d00c800
-7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+394000013d20c800
+7d43183061290818
+7c0004ac79290020
+3d00c8007c604f2a
+7908002061080820
+7d40472a7c0004ac
+7c0004ac39400000
+4e8000207d404f2a
 0000000000000000
-3d20c80039400001
-612910187d431830
-792900205463063e
+3d20c80000000000
+6129081839400001
+792900207d431830
 7c604f2a7c0004ac
-610810283d00c800
+610808243d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
-4182004028030002
-4182001c28030003
-4082004028030001
+394000013d20c800
+7d43183061290818
+7c0004ac79290020
+3d00c8007c604f2a
+7908002061080828
+7d40472a7c0004ac
+7c0004ac39400000
+4e8000207d404f2a
+0000000000000000
+2803000200000000
+2803000341820040
+280300014182001c
+3d40c80040820040
+614a103039200000
+3d40c80048000010
+614a107039200000
+7c0004ac794a0020
+4e8000207d20572a
 392000003d40c800
-48000010614a0068
+4bffffe4614a1050
 392000003d40c800
-794a0020614a0110
-7d20572a7c0004ac
-3d40c8004e800020
-614a00bc39200000
-3d40c8004bffffe4
-614a001439200000
-000000004bffffd4
-0000000000000000
-3842b2f03c4c0001
-4182006828030002
-4182003028030003
-4082007c28030001
-392000003d40c800
-794a0020614a0060
-7d20572a7c0004ac
-614a00643d40c800
-3d40c80048000024
-614a010839200000
+4bffffd4614a1010
+0000000000000000
+2803000200000000
+2803000341820040
+280300014182001c
+3d40c80040820040
+614a102c39200000
+3d40c80048000010
+614a106c39200000
 7c0004ac794a0020
-3d40c8007d20572a
-794a0020614a010c
-7d20572a7c0004ac
-3d40c8004e800020
-614a00b439200000
-7c0004ac794a0020
-3d40c8007d20572a
-4bffffd0614a00b8
-4bfffc2c38600000
+4e8000207d20572a
+392000003d40c800
+4bffffe4614a104c
+392000003d40c800
+4bffffd4614a100c
+0000000000000000
+7c0004ac00000000
+792ac2227d201e2a
+9944000299240003
+79294622792a8422
+9924000099440001
+7c0004ac39230004
+394000047d204e2a
+7d4903a679290020
+9d24ffff38840008
+4200fff87929c202
+000000004e800020
 0000000000000000
-2c03000000000000
-3929000178690020
-3920000140800008
-3929ffff2c290001
-600000004d820020
-000000004bfffff0
+786900202c030000
+4080000839290001
+2c29000139200001
+4d8200203929ffff
+4bfffff060000000
 0000000000000000
-3842b2103c4c0001
-fbe1fff87c0802a6
-f821ffd1f8010010
-392000013fe0c800
-7d23183063ff1018
-7c0004ac7bff0020
-3d40c8007c60ff2a
-794a0020614a102c
-7d20572a7c0004ac
-7d20572a7c0004ac
-614a10343d40c800
+3c4c000100000000
+7c0802a63842b24c
+f8010010fbe1fff8
+3fe0c800f821ffd1
+63ff081839200001
+7bff00207d231830
+7c60ff2a7c0004ac
+614a082c3d40c800
 7c0004ac794a0020
-386000647d20572a
-392000004bffff65
-7d20ff2a7c0004ac
-48002afc38210030
-0100000000000000
-3c4c000100000180
-7c0802a63842b184
-918100087d908026
-f821fed148002a31
-7c7f1b783b800001
-6000000038600086
-7c9923783b028088
-83d800007cbd2b78
-3d20c8004bfffb21
-7fde167061290014
-792900207fde0194
-7fd607b47fde00d0
-7fde07b43bde0020
-7f804f2a7c0004ac
-4bfffb293860000f
-612910083d20c800
+7c0004ac7d20572a
+3d40c8007d20572a
+794a0020614a0834
+7d20572a7c0004ac
+4bffff6538600064
+7c0004ac39200000
+382100307d20ff2a
+0000000048002b10
+0000018001000000
+3842b1c03c4c0001
+7d9080267c0802a6
+48002a4591810008
+3d40c800f821fec1
+7c7f1b78614a100c
+83a2800860000000
+7cbc2b78f8810098
+7fbd1670794a0020
+7d3d00d07fbd0194
+9121009023bd0020
+7c0004ac39200086
+3d20c8007d20572a
+612910103bc00001
 7c0004ac79290020
-386000647f804f2a
-4bfffeb13ea0c800
-62b5100c3e62ffff
-3e42ffff3e82ffff
+3860000f7fc04f2a
+3d20c8004bfffb15
+7929002061290808
+7fc04f2a7c0004ac
+3ee0c80038600064
+3b4100804bfffea9
+62f7101c3ea2ffff
+3e82ffff3ec2ffff
+6000000060000000
 3e02ffff3e22ffff
-3b4100802e3d0000
-3b6000003b800000
-7ab500203a737c68
-3a947c783ae10060
-3a317c983a527c80
-419200143a107c88
-7e639b787f64db78
-600000004bfff3e5
-39e000007f63db78
-386000644bfffe89
-4bfffe4139c00001
-418101207c1e7800
-7e43937841920010
-600000004bfff3b5
-3920ffff2c1e0000
-38e000007bca0020
-3ba0ffff7d3fe12e
-38a0000039e00000
-3896001f38c00000
-40800008394a0001
-2c2a000139400001
-394affff7ce907b4
-7f63db7840820188
-386000644bfffe19
-600000004bfffdd5
-7d29e2aa3922808c
-418001d42c090000
-3ba000007d3fe12e
-7c09e8007d3fe02e
-40920214418101a4
-3b5affff393b0001
-7d3b07b42c090004
-4082ff283b9c0004
-4bfff9a538600006
+3bc000002e3c0000
+7f58d3783b600000
+7af700203ab57c38
+3a947c503ad67c48
+3a4280083a628050
+3a107c583a317c68
+419200147f7c07b4
+7ea3ab787f84e378
+600000004bfff405
+3b2000007f83e378
+386000644bfffe6d
+4bfffe2539e00001
+7c1dc80039c10060
+4192001041810130
+4bfff3d17e83a378
+3920ffff60000000
+38e000002c1d0000
+7d3ff12e3b20ffff
+39e0000081210090
+38c0000038a00000
+3869001f38810060
+392900017ba90020
+3920000140800008
+7ce83b782c290001
+408201803929ffff
+4bfffdf17f83e378
+4bfffdad38600064
+2c0900007d3e982e
+7d3ff12e418001d4
+7d3ff02e3b200000
+418101a87c09c800
+3b7b000140920210
+2c1b00043b5affff
+4082ff243bde0004
+392000063d40c800
+794a0020614a100c
+7d20572a7c0004ac
 392000013d40c800
-794a0020614a0014
+794a0020614a1010
 7d20572a7c0004ac
-4bfff9c13860000f
+4bfff9893860000f
 392000003d40c800
-794a0020614a1008
+794a0020614a0808
 7d20572a7c0004ac
 3bff001039200004
 386000017d2903a6
 2c090000853ffffc
 3860000040800008
-382101304200fff0
-7d90812081810008
-3ba0000048002870
-3940000038800000
-f8810090f9410098
-7dc0af2a7c0004ac
-4bfffcf938600064
-3d20c80039400008
-7d4903a6e8810090
-61290038e9410098
-792900203901007f
-7ce04e2a7c0004ac
-392900049ce80001
-893a00034200fff0
-418200502c090000
-7fbd07b43bbd0001
-7c194800392a0001
-4082ff947d2a07b4
-78840fe07c9d2050
-419200107c8fb9ae
-4bfff2117e83a378
-7f63db7860000000
-4bfff9bd39ef0001
-4bfffc7138600064
-388400014bfffe30
-4bffffb47c8407b4
-7d07b8ae2c260000
-7c04480041820038
-2c2800004182000c
-7d25485040820020
-7c1d480038c00000
-4080000c7d2807b4
-7caf2b787d1d4378
-4bfffe3038e70001
-4182fff42c280000
-38c000017d254b78
-7f63db784bffffe8
-4bfff9453bbd0001
-7fbd07b438600064
-4bfffe3c4bfffbf5
-4182003c2c2f0000
-4081fe382c1d0000
-3ba000007dffe12e
-7c09e8007d3fe02e
-7f63db784081fe24
-4bfff9053bbd0001
-7fbd07b438600064
-4bffffdc4bfffbb5
-7d29167081380000
-7c09e8007d290194
-4bffffbc4080fdf4
-2c04ffff7c9fe2aa
+382101404200fff0
+818100087c6307b4
+480028547d908120
+3920000081010098
+912100a439400000
+914100a03d20c800
+910100946129080c
+7c0004ac79290020
+386000647de04f2a
+7f04c3784bfffcb9
+4bfffc517ee3bb78
+8101009488fa0003
+812100a4814100a0
+418200502c070000
+3908ffff39290001
+4082ffa82c080000
+7d2407b47d4a07b4
+78840fe07c845050
+419200107c9971ae
+4bfff2297ec3b378
+7f83e37860000000
+4bfff9893b390001
+4bfffc4d38600064
+394a00014bfffe2c
+2c0600004bffffb4
+418200387d4720ae
+418200107c034000
+2c0a0000554a063e
+7d0540504082001c
+7c19400038c00000
+7d1943784080000c
+38e700017caf2b78
+554a063e4bfffe38
+4182fff02c0a0000
+38c000017ce53b78
+7f83e3784bffffe4
+4bfff9113b390001
+4bfffbd538600064
+2c0f00004bfffe3c
+2c19000041820038
+7dfff12e4081fe38
+7d3ff02e3b200000
+4081fe247c09c800
+3b3900017f83e378
+386000644bfff8d5
+4bffffe04bfffb99
+7d29167081320000
+7c09c8007d290194
+4bffffc04080fdf8
+2c04ffff7c9ff02e
 7e03837840820014
-600000004bfff10d
-7e238b784bfffdd8
-600000004bfff0fd
-000000004bfffdc8
-0000128003000000
-3842ada03c4c0001
-4800268d7c0802a6
-3ce08020f821ff91
-60e700033bc10020
-7fcaf3787c7c1b78
-78e700203be00004
-3920000039000008
-7888f8427d0903a6
+600000004bfff12d
+7c8407b44bfffddc
+4bfff1197e238b78
+4bfffdc860000000
+0300000000000000
+3c4c000100001280
+7c0802a63842adbc
+f821ff6148002669
+60a500033ca08020
+394000007c7d1b78
+78a5002038c1001f
+3be1002039000008
+7ce652147d0903a6
+7888f86239200008
 7c8400d0788407e0
-7c8642787c843838
-7cca49ae7cc43378
-4200ffe039290001
-394a0008393fffff
-4082ffc4793f0021
-4bfff70538600000
-392000003d40c800
-794a0020614a0014
+7c8428383929ffff
+7d0443787c884278
+4200ffe09d070001
+282a0020394a0008
+3d40c8004082ffc0
+794a0020614a100c
 7d20572a7c0004ac
-4bfff72138600009
-4bfffac13860000f
-3cc0c8003d20c800
-60c6018861290038
-792900207fcaf378
-38a0000878c60020
-7ca903a63909ffe0
-8ca7000138eaffff
-7ca0472a7c0004ac
-4200fff039080004
-394a000839290054
-4082ffd07c293000
-63bd10483fa0c800
-7c0004ac7bbd0020
-5463063e7c60ee2a
-7c0004ac4bfff9b1
-5463063e7c60ee2a
-7c0004ac4bfff929
-388000177fa0ee2a
-3fa0c80057a3063e
-63bd10444bfff6cd
-4bfffa213860000f
-7c0004ac7bbd0020
-5463063e7c60ee2a
-7c0004ac4bfff969
-5463063e7c60ee2a
-7c0004ac4bfff8e1
-388000257fa0ee2a
-4bfff68957a3063e
-4bfff9e13860000f
-4bfff5f538600000
-392000003d40c800
-794a0020614a0014
-7d20572a7c0004ac
-3fa00f0f3860000b
-3860000f4bfff60d
-4bfff9a963bd0f0f
-3c0055553cc0c800
-3d60333360c60038
-78c6002038a00000
-207c000338810040
-616b333360005555
-7cca337839000008
-392000007d0903a6
-7d00562a7c0004ac
-394a00047d0449ae
-4200ffec39290001
-38e0000039200008
-7d272a147d2903a6
-7c091800552907be
-7d4438ae40820058
-7d0852787d1e38ae
-5509063e790afe62
-7d4a48507d4a0038
-554af0be7d695038
-7d4952147d4a5838
-7d2952145549e13e
-552ac23e7fa94838
-552a843e7d295214
-552906be7d295214
-793f00207d29fa14
-4200ff9838e70001
-3bde000839250008
-7925002028090020
-4082ff4c38c60054
-7fe3fb7838210070
-0000000048002448
-0000048001000000
-3842aaf03c4c0001
-7d9080267c0802a6
-480023d191810008
-2e250000f821ff71
-4192001c7c7e1b78
-7c641b787c852378
-38637ca83c62ffff
-600000004bffedfd
-3f62ffff7fc3f378
-3b8000204bfff609
-3b7b7c783ba00000
-7fc3f3783880002a
-388000544bfffcf9
-7fc3f3787c7f1b78
-7d3f1a144bfffce9
-212900807d240034
-548360265484d97e
-7fa9ea147d234a14
-419200107bbd0020
-4bffed997f63db78
-7fc3f37860000000
-4bfff5f53b9cffff
-4082ffa47b9c0021
-3c62ffff41920014
-4bffed7138637cb8
-3821009060000000
-818100087fa3eb78
-480023587d908120
-0300000000000000
-3c4c000100000580
-7c0802a63842aa04
+614a10103d40c800
+7c0004ac794a0020
+386000097d20572a
+3860000f4bfff6ed
+3d20c8004bfffa99
+612910143cc0c800
+7feafb7860c61094
+78c6002079290020
+38eaffff38a00004
+390000007ca903a6
+7905400c8ca70001
+4200fff47ca82b78
+7ca04f2a7c0004ac
+38a9000438800004
+38ea00037c8903a6
+390000003bc00004
+3bdeffff8c870001
+7c8823787904400c
+7c0004ac4200fff0
+392900207c802f2a
+7c293000394a0008
+3f80c8004082ff98
+7b9c0020639c0848
+7c60e62a7c0004ac
+4bfff9295463063e
+7c60e62a7c0004ac
+4bfff8a95463063e
+7c60e62a7c0004ac
+5463063e38800017
+4bfff65d3f80c800
+3860000f639c0844
+7b9c00204bfff9c1
+7c60e62a7c0004ac
+4bfff8e15463063e
+7c60e62a7c0004ac
+4bfff8615463063e
+7c60e62a7c0004ac
+5463063e38800025
+3860000f4bfff619
+3d20c8004bfff981
+792900206129100c
+7fc04f2a7c0004ac
+612910103d20c800
+7c0004ac79290020
+3860000b7fc04f2a
+4bfff5993f80c800
+3f00c8003860000f
+639c101c4bfff941
+3f2033333ee05555
+6318109c3ec00f0f
+7b9c00203b600000
+23bd00033b410040
+6339333362f75555
+7b18002062d60f0f
+7f83e3787f44d378
+392000084bfff8a5
+7d2903a639400000
+552907be7d3b5214
+408200547c09e800
+7d3f50ae7d1a50ae
+5528063e7d294278
+7d29b8387929fe62
+7d28c8387d294050
+7d29c8385529f0be
+5509e13e7d084a14
+7d29b0387d294214
+7d2942145528c23e
+7d2942145528843e
+7fde4a14552906be
+4200ff9c394a0001
+3b7b00083b9c0020
+3bff00087c3cc000
+382100a04082ff70
+480023f47bc30020
+0100000000000000
+3c4c000100000a80
+7c0802a63842aadc
 918100087d908026
-f821ff51480022d5
+f821ff7148002395
 7c7f1b782e250000
-7cda33787c992378
-419200187cfe3b78
+7c8523784192001c
 3c62ffff7c641b78
-4bffed0938637cc0
-7f4903a660000000
+4bffede938637c78
+7fe3fb7860000000
+4bfff5a93f62ffff
+3bc000003ba00020
+3880002a3b7b7c48
+4bfffcc97fe3fb78
+7c7c1b7838800054
+4bfffcb97fe3fb78
+7c6400347c63e214
+5484d97e20630080
+7d291a1454896026
+419200147fde4a14
+7f63db787c8407b4
+600000004bffed85
+3bbdffff7fe3fb78
+2c1d00004bfff591
+419200144082ffa4
+38637c883c62ffff
+600000004bffed5d
+7bc3002038210090
+7d90812081810008
+000000004800231c
+0000058003000000
+3842a9f03c4c0001
+7d9080267c0802a6
+4800229991810008
+2e250000f821ff51
+7c9723787c7f1b78
+7cfe3b787cda3378
+7c641b7841920018
+38637c903c62ffff
+600000004bffecf5
+f84100187f4903a6
+7f4cd3787fe3fb78
+4e8004213b800000
+3880002ae8410018
+4bfffbd17fe3fb78
+7c7d1b7838800054
+4bfffbc17fe3fb78
+4192001c7fa3ea14
+3c62ffff7fa40034
+5484d97e38637c48
+600000004bffec9d
+3b7c00012c1d0000
+2c1b00204182002c
+7fc903a6418200c0
 7fe3fb78f8410018
-3b8000007f4cd378
+7f7cdb787fccf378
 e84100184e800421
-7fe3fb783880002a
-388000544bfffc01
-7fe3fb787c7d1b78
-7c7d1a144bfffbf1
-4192001c787d0020
-5464d97e7c630034
-38637c783c62ffff
-600000004bffecad
-393c00012c3d0000
-4182002c7d3b07b4
-418200cc2c090020
+7f9de3784bffff94
 f84100187fc903a6
 7fccf3787fe3fb78
-4e8004217f7cdb78
-4bffff8ce8410018
-7fc903a67f9de378
-7fe3fb78f8410018
-3afc00017fccf378
-3b00ffff7ef707b4
+3b60ffff3b3c0001
 e84100184e800421
 7fe3fb783880002a
-388000544bfffb61
-7fe3fb787c7b1b78
-7c7b1a144bfffb51
-4192001c787b0020
-5464d97e7c630034
-38637c783c62ffff
-600000004bffec0d
-418200102c3b0000
-408200082c18ffff
-393700017ef8bb78
-7d3707b42c09001f
+388000544bfffb3d
+7fe3fb787c781b78
+7f03c2144bfffb2d
+7f0400344192001c
+38637c483c62ffff
+4bffec095484d97e
+2c18000060000000
+2c1bffff41820010
+7f3bcb7840820008
+2c19001f3b390001
 7fc903a64181002c
 7fe3fb78f8410018
 4e8004217fccf378
-4bffff84e8410018
-3ba0ffff7f7cdb78
-2c1c001e4bffff54
+4bffff8ce8410018
+3ba0ffff3b800020
+2c1c001e4bffff60
 39200000395c0002
 213c001e41810008
-7d2952142c18ffff
-408200087d2907b4
-419200147d384b78
-38637cb83c62ffff
-600000004bffeb85
-7f9dc2142c390000
-7f9c01947f9c0e70
-4182001c7b9c06e0
-408200642c1dffff
-38637cc83c62ffff
-600000004bffeb55
+7d2952142c1bffff
+7d3b4b7840820008
 3c62ffff41920014
-4bffeb4138637a10
-7f4903a660000000
+4bffeb8938637c88
+2c37000060000000
+7f9c0e707f9dda14
+579c06fe7f9c0194
+2c1dffff4182001c
+3c62ffff40820064
+4bffeb5938637c98
+4192001460000000
+386379e83c62ffff
+600000004bffeb45
+7fe3fb787f4903a6
+7f4cd378f8410018
+4e8004213ba00000
+38600064e8410018
+7c1de0004bfff559
+382100b04082003c
+7d90812081810008
+7cbdd850480020cc
+7ca50e703c62ffff
+7f8407b47ca50194
+7ca507b438637ca8
+600000004bffeae5
+7fc903a64bffff8c
 f84100187fe3fb78
-3ba000007f4cd378
-e84100184e800421
-4bfff59138600064
-4082003c7c1de000
-81810008382100b0
-480020f07d908120
-3c62ffff7fbdc050
-7ca501947fa50e70
-38637cd87f84e378
-4bffeae17ca507b4
-4bffff8c60000000
-7fe3fb787fc903a6
-7fccf378f8410018
-7fbd07b43bbd0001
+3bbd00017fccf378
 e84100184e800421
-4bfff52938600064
-000000004bffff98
+4bfff4f538600064
+000000004bffff9c
 0000098003000000
-3842a7583c4c0001
+3842a7603c4c0001
 fbe1fff87c0802a6
 f821ffd1f8010010
-3fe0c80039200001
-63ff10187d231830
-7bff00205463063e
-7c60ff2a7c0004ac
-614a10303d40c800
-7c0004ac794a0020
-386000647d20572a
-392000004bfff4c5
-7d20ff2a7c0004ac
-4800205c38210030
-0100000000000000
-3c4c000100000180
-7c0802a63842a6e4
-f8010010fbe1fff8
-39200001f821ffd1
-7d2318303fe0c800
-5463063e63ff1018
+392000013fe0c800
+7d23183063ff0818
 7c0004ac7bff0020
 3d40c8007c60ff2a
-794a0020614a102c
+794a0020614a0830
 7d20572a7c0004ac
-4bfff45138600064
+4bfff49538600064
 7c0004ac39200000
 382100307d20ff2a
-0000000048001fe8
+0000000048002040
 0000018001000000
-3842a6703c4c0001
-794a00203d40c800
-7d20562a7c0004ac
-2c09000e5529063e
+3842a6f03c4c0001
+fbe1fff87c0802a6
+f821ffd1f8010010
+392000013fe0c800
+7d23183063ff0818
+7c0004ac7bff0020
+3d40c8007c60ff2a
+794a0020614a082c
+7d20572a7c0004ac
+4bfff42538600064
+7c0004ac39200000
+382100307d20ff2a
+0000000048001fd0
+0000018001000000
+3842a6803c4c0001
+612910003d20c800
+7c0004ac79290020
+280a000e7d404e2a
 7c0802a64d820020
 f821ffa1f8010010
-7c0004ac3920000e
-3c62ffff7d20572a
-4bffe97138637cf0
+7c0004ac3940000e
+3c62ffff7d404f2a
+4bffe98138637cc0
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a6083c4c0001
-794a00203d40c800
-7d20562a7c0004ac
-2c0900015529063e
+3842a6183c4c0001
+612910003d20c800
+7c0004ac79290020
+280a00017d404e2a
 7c0802a64d820020
 f821ffa1f8010010
-7c0004ac39200001
-3c62ffff7d20572a
-4bffe90938637d18
+7c0004ac39400001
+3c62ffff7d404f2a
+4bffe91938637ce8
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a5a03c4c0001
-48001e6d7c0802a6
+3842a5b03c4c0001
+48001e557c0802a6
 3c80c800f821ff31
-7884002060841004
+7884002060840804
 7c80262a7c0004ac
-3b82808860000000
-3c62ffff548915ba
-38637d40788415a8
-4bffe8a1913c0000
-6000000060000000
-2c09000081228030
-6000000041820238
-2c1fffffebe2802e
-3be0000040820008
-eba2802a60000000
-408200142c1dffff
-7fbd0e7083bc0000
-7fbd07b47fbd0194
-7fa5eb783c62ffff
-38637d607fe4fb78
-600000004bffe845
-38637d783c62ffff
-600000004bffe835
-392000013d40c800
-794a0020614a1010
-7d20572a7c0004ac
-3f60ffff38600064
-4bfff2813ee0c800
-62f71014637bffff
-3bc0ffff3ec2ffff
-7b7b00203b400000
-3b0000013aa00000
-3b2100607af70020
-7c1df8003ad67c78
-3c62ffff41810178
-38637d807fc4f378
+5484103a60000000
+908280083c62ffff
+7c8407b438637d10
+600000004bffe8b5
+8122800060000000
+418202042c090000
+83ff7ffc3fe2ffff
+408200082c1fffff
+3fa2ffff3be00000
+2c1dffff83bd7ff8
+6000000040820014
+7fbd0e7083a28008
+3c62ffff7fbd0194
+7fe407b47fa507b4
+4bffe85938637d30
+3c62ffff60000000
+4bffe84938637d48
+3d40c80060000000
+614a081039200001
+7c0004ac794a0020
+386000647d20572a
+4bfff25d3f00c800
+6000000063180814
+3bc0ffff3ea2ffff
+3b60ffff3b400000
+3b2000013b800000
+3ae100607b180020
+3ab57c483ac28008
+418101447c1df800
+7fc407b43c62ffff
+4bffe7d938637d50
+3c62ffff60000000
+38637d607fc407b4
 600000004bffe7c5
-7fc4f3783c62ffff
-4bffe7b138637d90
-2c1e000060000000
-3c62ffff4080015c
-4bffe79938637db8
-38a0000160000000
-3861006038800080
-2c2300004bfff2c5
-382100d04082018c
-7c0004ac48001d58
-386000647f00bf2a
-4bfff1d93a940001
-7c14f8007e9407b4
-7c1fa8004180ffe4
+408001282c1e0000
+38637d883c62ffff
+600000004bffe7ad
+3880008038a00001
+4bfff29d38610060
+7c691b782c030000
+382100d040820150
+48001d3c7d2307b4
+7f20c72a7c0004ac
+3a94000138600064
+7c14f8004bfff1a9
+7c1fe0004180ffe8
 4180000839200000
-38a000007d35f850
-7f23cb7838800008
-4bfff2717ea9aa14
-38e00004e93c0002
-7ce903a67eb507b4
-38c000007c641b78
-7ca501947d251670
-3900000039400000
-78c717647ca507b4
-2c07ffff7cf93aaa
-7ce72a1441820018
-7d074214394a0001
-7d0807b47d4a07b4
-4200ffd838c60001
-4182000c2c2a0000
-7d0807b47d0853d6
-7d2901947d291670
-7d290e7021290020
-7cc848507d290194
-7cc707b42c060000
-7d2940504080000c
-7c0ad0407d2707b4
-4180001c79480020
-78e900207c07d840
-7ffefb7840800010
-7d3b4b787d1a4378
-3bff00017ec3b378
-600000004bffe66d
-4bfffe887fff07b4
-4bffff007eb4ab78
-ebc2803a60000000
-3d40c8004bfffe90
-614a101039200001
+388000087d3cf850
+7ee3bb7838a00000
+4bfff2457f9c4a14
+8136000038e00004
+7ce903a638c1005c
+7c641b7839400000
+7d29167039000000
+84e600047d290194
+418200102c07ffff
+394a00017ce74a14
+4200ffe87d083a14
+418200082c0a0000
+212900207d0853d6
+7d2901947d290e70
+2c0700007ce84850
+7ce9405040800008
+418000187c0ad040
+408000107c07d840
+7d5a53787ffefb78
+7ea3ab787cfb3b78
+600000004bffe6b5
+4bfffebc3bff0001
+4bffff387f94e378
+83c2804c60000000
+3d40c8004bfffec4
+614a081039200001
 7c0004ac794a0020
 386000647d20572a
-4bfff0a13f80c800
-3be00000639c1014
+4bfff0ad3f80c800
+3be00000639c0814
 7b9c00203ba00001
-4182fe707c1ff000
+4182fea47c1ff000
 7fa0e72a7c0004ac
 3bff000138600064
-7fff07b44bfff075
-7fc3f0f84bffffe0
-4bfffe7054630ffe
-0100000000000000
-3c4c000100000c80
-7c0802a63842a294
-f821ff5148001b69
-3f02ffff3be00000
-3f42ffff3f22ffff
-3b184bb03ec2ffff
-3b5a7a103b394b60
-57fd063e3ad67dc8
-7fa3eb783b600000
-4bffee4d3ae00000
-38a000013bc00000
-7fe3fb787fc4f378
-7f07c3784bfff751
-38a000007f26cb78
-7c7c1b7838800001
-4bfff8217fe3fb78
-4bffe5597f43d378
-7c17e04060000000
-7fdbf3784080000c
-2c1e00077f97e378
-7fa3eb7841820018
-4bffee3d3bde0001
-4bffffa07fde07b4
-7fe4fb787f65db78
-3bc000007ec3b378
-600000004bffe515
-4bffedc57fa3eb78
-408200407c1ed800
-7f07c3787fe3fb78
-38a000007f26cb78
-4bfff7a938800001
-4bffe4e17f43d378
-393f000160000000
-7d3f07b42c090004
-382100b04082ff2c
-7fa3eb7848001ab0
-4bffedc53bde0001
-4bffffac7fde07b4
-0100000000000000
-3c4c000100000a80
-7c0802a63842a15c
-f821ff1148001a15
-4bfffadd3be00000
-4bffef357fe3fb78
-4bffec957fe3fb78
-4bffed2d57e3063e
-2c090004393f0001
-4082ffdc7d3f07b4
-3f60c8003c62ffff
-3f20c80038637de0
-600000004bffe44d
-3c62ffff4bfffb69
-38637df83ee0c800
-4bffe431637b1018
-6339103c60000000
-3ec2ffff62f71040
-3be000003ea2ffff
-7b7b00203ba00001
-7af700207b390020
-3ad67e203b000000
-7ffa07b43ab57e18
-7fb1f8307fb2f830
-3a6000003b80ffff
-57f4063e3bc00000
-7e20df2a7c0004ac
-7fa0cf2a7c0004ac
+4bffffe44bfff081
+57c90ffe7fdef0f8
+000000004bfffeac
+00000c8001000000
+3842a2e03c4c0001
+48001b897c0802a6
+3bc00000f821ff41
+3f02ffff3ee2ffff
+3ea2ffff3f22ffff
+3b184b143af74b60
+3ab57d983b3979e8
+3b40000057c3063e
+3ac000004bffee4d
+7fdc07b43ba00000
+38a0000157df063e
+7f83e3787fa407b4
+7ee7bb784bfff7ad
+38a000007f06c378
+7c7b1b7838800001
+4bfff87d7f83e378
+4bffe5a17f23cb78
+7c16d84060000000
+7fbaeb784080000c
+2c1d00077f76db78
+7fe3fb7841820014
+4bffee2d3bbd0001
+7f4507b44bffffa4
+7ea3ab787f84e378
+4bffe5613ba00000
+7fe3fb7860000000
+7c1dd0004bffedbd
+7ee7bb784082003c
+38a000007f06c378
+7f83e37838800001
+4bfff8053bde0001
+4bffe5297f23cb78
+2c1e000460000000
+382100c04082ff30
+7fe3fb7848001ad4
+4bffedbd3bbd0001
+000000004bffffb4
+00000b8001000000
+3842a1b03c4c0001
+48001a3d7c0802a6
+3be00000f821ff01
+7fe307b44bfffb21
+4bffef49f8610060
+4bffec99e8610060
+3bff000157e3063e
+2c1f00044bffed25
+3c62ffff4082ffdc
+38637db03f80c800
+4bffe4a13f00c800
+4bfffbad60000000
+3ee0c8003c62ffff
+639c081838637dc8
+600000004bffe485
+62f708406318083c
+3e82ffff60000000
+3be000003e62ffff
+3ac000003ba00001
+7b1800207b9c0020
+3aa2800c7af70020
+3a737de83a947df0
+7fb2f83057f0063e
+3b2000003b40ffff
+7ffb07b43bc00000
+7c0004ac7e118378
+7c0004ac7e40e72a
+7bc900207fa0c72a
+7d2903a639290001
+7c0004ac4200018c
+7e0383787ec0e72a
+4bffec6139e00000
+38a0000039c00000
+7f63db787dc407b4
+7c0f18404bfff5cd
+7c6f1b7840800008
+39ce00017e238b78
+2c0e00084bffec81
+7c0fc8404082ffd4
+7fdaf3784081000c
+3bde00027df97b78
+4082ff802c1e0008
+7fc9a82e7be91764
+408001282c1e0000
+4082011c2c1affff
+7e639b787f64db78
+600000004bffe385
+7c0004ac3bc0ffff
+7c0004ac7e40e72a
+2c1e00007fa0c72a
 392900017bc90020
-420001a47d2903a6
-7f00df2a7c0004ac
-3a0000007e83a378
-39e000004bffec69
-7de47b7838a00000
-4bfff56d7f43d378
-7c691b787c038040
-7e09837840800008
-793000207e83a378
-392f00014bffec89
-7d2f07b42c090008
-7c1098404082ffc8
-7fdcf3784081000c
-393e00027e138378
-7d3e07b42c090008
-600000004082ff70
-7be9176439428048
-2c1e00007fca4aaa
-2c1cffff40800128
-7f44d3784082011c
-4bffe3217ea3ab78
-7f9ee37860000000
-7e40df2a7c0004ac
-7fa0cf2a7c0004ac
-7bc900202c1e0000
-4080000839290001
-2c29000139200001
-408200f43929ffff
-7f00df2a7c0004ac
-283f00043bff0001
-3c62ffff4082fedc
-38637a103f42ffff
-4bffe2c13f62ffff
-3c62ffff60000000
-38637e283ec2ffff
-4bffe2a93ee2ffff
-3be0000060000000
-3b7b4b603b5a4bb0
-3af7591c3ad658a8
-3b00000057fd063e
-3b2000007fa3eb78
-3bc000004bffeb39
-7fc4f37838a00000
-4bfff43d7fe3fb78
-7f66db787f47d378
+3920000140800008
+3929ffff2c290001
+7c0004ac408200f4
+3bff00017ec0e72a
+4082fef4283f0004
+3f22ffff3c62ffff
+3f42ffff386379e8
+600000004bffe325
+3ea2ffff3c62ffff
+3ec2ffff38637df8
+600000004bffe30d
+3b394b603bc00000
+3ab558a03b5a4b14
+57c3063e3ad65910
+4bffeb513ae00000
+3ba000003b000000
+57df063e7fdc07b4
+7fa407b438a00000
+4bfff4b17f83e378
+7f46d3787f27cb78
 3880000038a00000
-7fe3fb787c7c1b78
-7c1cc0404bfff50d
-7f98e3784081000c
-2c1e00077fd9f378
-418200487fa3eb78
-4bffeb353bde0001
-4bffffac7fde07b4
-7fa0bf2a7c0004ac
-7f9ee3784bfffe54
-7f44d3787fc5f378
-4bffe2017ec3b378
-4bfffee460000000
-7fa0bf2a7c0004ac
-4bffeaa54bfffefc
-7c1ec8003bc00000
-7fe3fb7840820068
-7f66db787f47d378
+7f83e3787c7b1b78
+7c1bb8404bfff581
+7f77db784081000c
+2c1d00077fb8eb78
+418200447fe3fb78
+3bbd00014bffeb41
+7c0004ac4bffffb0
+4bfffe6c7fa0bf2a
+7fc507b47f5ed378
+7e83a3787f64db78
+600000004bffe265
+7c0004ac4bfffee4
+4bfffefc7fa0bf2a
+3ba000004bffeab5
+408200647c1dc000
+7f46d3787f27cb78
 3880000038a00000
-7fe3fb784bfff485
-7ee6bb787ec7b378
-3880000138a00001
-393f00014bfff46d
-7d3f07b42c090004
-3c62ffff4082ff10
-4bffe19138637e40
-4bfffbb960000000
-382100f04bfff841
-4800174838600001
-3bde00017fa3eb78
-7fde07b44bffea79
-000000004bffff84
-0000118001000000
-38429e103c4c0001
-480016f17c0802a6
-39200001f821ff61
-38e0ffff60000000
-3902808c60000000
-3940001091228030
-7d4903a639200000
-39290001792a1764
-4200fff47ce8512e
-6000000039400010
-3920000039028048
-38e0ffff7d4903a6
-39290001792a1764
-4200fff47ce8512e
-3ba000013d20c800
-7929002061291044
-7fa04f2a7c0004ac
-3b4000023d20c800
-7929002061291048
-7f404f2a7c0004ac
-3c62ffff3fc0c800
-38637e503c804000
-4bffe0a163de1000
-7bde002060000000
-7c0004ac4bfff6e9
-386003e87fa0f72a
-4bffeaf93be00000
+3bde00017f83e378
+7ea7ab784bfff4f9
+38a000017ec6b378
+7f83e37838800001
+2c1e00044bfff4e1
+3c62ffff4082ff14
+4bffe1f938637e10
+4bfffbd560000000
+382101004bfff899
+4800178438600001
+3bbd00017fe3fb78
+4bffff8c4bffea89
+0100000000000000
+3c4c000100001280
+7c0802a638429e7c
+f821ff6148001731
+7d0903a639000010
+6000000039200001
+6000000091228000
+3922804c3940ffff
+4200fffc95490004
+6000000039000010
+392280087d0903a6
+3940ffff3be00010
+3bffffff95490004
+3d20c8004200fff8
+612908443b800001
+7c0004ac79290020
+3d20c8007f804f2a
+612908483b200002
+7c0004ac79290020
+3fc0c8007f204f2a
+3c8040003c62ffff
+63de080038637e20
+600000004bffe11d
+4bfff7557bde0020
+7f80f72a7c0004ac
+4bffeb3d386003e8
 7fe0f72a7c0004ac
-386003e83f80c800
-4bffeae1639c0800
-7c0004ac7b9c0020
-3f60c8007fe0e72a
-7b7b0020637b0804
+3f60c800386003e8
+7b7b00204bffeb29
 7fe0df2a7c0004ac
-386000003fc0c800
-4bffe6cd63de0014
+635a00043f40c800
+7c0004ac7b5a0020
+3fa0c8007fe0d72a
+7bbd002063bd100c
+7fe0ef2a7c0004ac
+63de10103fc0c800
 7c0004ac7bde0020
-3f20c8007fe0f72a
-7b3900203920000c
-7d20cf2a7c0004ac
-6063c35038600000
-386000004bffea85
-7c0004ac4bffe699
-3920000e7fe0f72a
-7d20cf2a7c0004ac
-4bffea6138602710
-4bffe67538600200
-7f40f72a7c0004ac
-4bffe6a13860000f
-4bffe65d38600000
+3f00c8007fe0f72a
+631810003920000c
+7c0004ac7b180020
+386000007d20c72a
+4bffeabd6063c350
+7fe0ef2a7c0004ac
+7fe0f72a7c0004ac
+7c0004ac3920000e
+386027107d20c72a
+392002004bffea99
+7d20ef2a7c0004ac
+7f20f72a7c0004ac
+4bffe6c93860000f
+7fe0ef2a7c0004ac
 7c0004ac39200003
 3860000f7d20f72a
-386000064bffe685
-7c0004ac4bffe641
-3860000f7fa0f72a
-386009204bffe66d
-7c0004ac4bffe629
+392000064bffe6ad
+7d20ef2a7c0004ac
+7f80f72a7c0004ac
+4bffe6913860000f
+7c0004ac39200920
+7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bffe655
-386004004bffe9f5
-7c0004ac4bffe609
-386000037fe0f72a
-386000c84bffe635
-4bfffac14bffe9d5
-3c8000204bfff611
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100a07fa0e72a
-38c000004800151c
-3c80002038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000078001000000
-38429ba83c4c0001
+386000c84bffe675
+392004004bffea21
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bffe65138600003
+4bffe9fd386000c8
+4bfff6654bfffad1
+3c6040003c800020
+6000000048000779
+7c691b782c030000
+7c0004ac40820020
+7c0004ac7f80d72a
+382100a07f80df2a
+4800154c7d2307b4
+38a0000038c00000
+3c6040003c800020
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000880
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+38429bc83c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637e703c62ffff
-600000004bffdec5
+38637e403c62ffff
+600000004bffdee5
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffde8938637e78
+4bffdea938637e48
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637e88
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e58
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637e987ca54b92
+38637e687ca54b92
 000000004bffffa4
 0000008001000000
-38429ad83c4c0001
+38429af83c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bffdde938637ea8
+4bffde0938637e78
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffddd138637eb8
+4bffddf138637e88
 3821007060000000
-00000000480013e8
+00000000480013e0
 0000018001000000
-38429a703c4c0001
-4800135d7c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bffddf1
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bffddc1
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d000048001330
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+38429a903c4c0001
+480013557c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bffde09
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bffddb9
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f8
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384299883c4c0001
-480012797c0802a6
+384299803c4c0001
+480012497c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
+420000387cbd2b78
 4bffdcfd7bff0020
-395f000160000000
-7d4903a62fbe0000
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126838210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e00284800123c
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a638429884
-480011557d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67ec0
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384298983c4c0001
+7d8000267c0802a6
+918100084800113d
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67e90
 3c62ffff4082009c
-38637ec07b251028
-4bfffd357ba40020
-38637a103c62ffff
-600000004bffdb3d
-4bffdba53ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637ed078a51028
-4bfffccd7ba40020
-38637a103c62ffff
-600000004bffdad5
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637ed07ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fac7d838120
+38637e907b851028
+4bfffd357b240020
+386379e83c62ffff
+600000004bffdb5d
+600000004bffdbc9
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637ea07b051028
+4bfffcdd7be40020
+386379e83c62ffff
+600000004bffdb05
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010ac
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637ea07ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a63842966c
+3c4c000100000b80
+7c0802a6384296d4
 918100087d908026
-f821ff8148000f51
+f821ff7148000f89
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637ee0
-600000004bffd975
-38637ef83c62ffff
+7cbc2b7838637eb0
+600000004bffd9dd
+38637ec83c62ffff
 3c62ffff4092000c
-4bffd95938637f08
+4bffd9c138637ed8
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637f183c62ffff
-600000004bffd93d
+4bfffaad7bfde8c2
+38637ee83c62ffff
+600000004bffd9a5
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1768,467 +1755,475 @@ f821ff8148000f51
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637f20
-600000004bffd8ed
-4bfff9fd7f83e378
-38637f303c62ffff
-600000004bffd8d5
-38637a103c62ffff
-600000004bffd8c5
-600000004bffd931
-409200287cf602a6
+7f9c4b9238637ef0
+600000004bffd955
+4bfffa457f83e378
+38637f003c62ffff
+600000004bffd93d
+386379e83c62ffff
+600000004bffd92d
+600000004bffd999
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637f38
-600000004bffd83d
-4bfff94d7fe3fb78
-38637f303c62ffff
-600000004bffd825
-38637a103c62ffff
-600000004bffd815
-8181000838210080
-48000e047d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a638429464
-f821ff7148000d49
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f8000
-3b60ffff4081000c
-3c62ffff577b0420
-38637f487fc4f378
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f08
+600000004bffd8b5
+4bfff9a57fe3fb78
+38637f003c62ffff
+600000004bffd89d
+386379e83c62ffff
+600000004bffd88d
+8181000838210090
+48000e4c7d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384294f83c4c0001
+48000db57c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f80007c9a2378
+4081000c7ffbfb78
+577b04203b60ffff
+7fc4f3783c62ffff
+4bffd7f138637f18
+7fe3fb7860000000
+3c62ffff4bfff8e1
+4bffd7d938637ee8
+7f44d37860000000
+4bfff9fd7fc3f378
+7f64db7838a00000
+7fc3f3787c7c1b78
+38c000004bfffaf9
+7fe4fb7838a00001
+7fc3f3787c7d1b78
+7d3de2144bfffbc9
+7c7e1b787d291a14
+4182006c2c090000
+7b45f8823c62ffff
+38637f287f84e378
+600000004bffd775
+7b65f0823c62ffff
+38637f407fa4eb78
 600000004bffd75d
-4bfff86d7fe3fb78
-38637f183c62ffff
+7be5f0823c62ffff
+38637f587fc4f378
 600000004bffd745
-7fc3f3787f44d378
-38a000004bfff989
-7c7c1b787f64db78
-4bfffa5d7fc3f378
-38a0000138c00000
-7c7d1b787fe4fb78
-4bfffb497fc3f378
-7d291a147d3cea14
-2c0900007c7e1b78
-3c62ffff41820068
-7f84e3787b45f882
-4bffd6e138637f58
-3c62ffff60000000
-7fa4eb787b65f082
-4bffd6c938637f70
-3c62ffff60000000
-7fc4f3787be5f082
-4bffd6b138637f88
-3c62ffff60000000
-4bffd6a138637fa0
-3860000060000000
-48000c8c38210090
-38637fb03c62ffff
-600000004bffd685
-4bffffe438600001
+38637f703c62ffff
+600000004bffd735
+3821009038600000
+48000cf47c6307b4
+38637f803c62ffff
+600000004bffd715
+4bffffe038600001
 0100000000000000
 3c4c000100000680
-6000000038429324
-60000000392280cc
-8929000039428040
-4182002c2c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-7c0004ace92a0000
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-e94a00005469063e
-7d2057ea7c0004ac
-000000004e800020
+60000000384293b4
+6000000089228098
+2c09000039428090
+e92a00004182002c
+7c0004ac39290014
+712900207d204eaa
+e92a00004182ffec
+7c604faa7c0004ac
+e92a00004e800020
+7c0004ac39290010
+712900087d204eea
+5469063e4082ffec
+7c0004ace94a0000
+4e8000207d2057ea
 0000000000000000
-384292a03c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-3be3fffff821ffd1
-2c3e00008fdf0001
-3821003040820010
-48000bd038600000
-4082000c281e000a
-4bffff413860000d
-4bffff397fc3f378
-000000004bffffd0
-0000028001000000
-384292403c4c0001
-610800203d00c000
-7c0004ac79080020
-3d20c0007d0046ea
-6129000879080600
-7c0004ac79290020
-712900207d204eea
-3d20c00041820018
-7929002061290040
+3c4c000100000000
+7c0802a638429334
+fbe1fff8fbc1fff0
+f821ffd1f8010010
+8fdf00013be3ffff
+408200102c1e0000
+3860000038210030
+2c1e000a48000c3c
+3860000d4082000c
+7fc307b44bffff45
+4bffffd04bffff3d
+0100000000000000
+3c4c000100000280
+3d40c000384292d4
+794a0020614a0020
+7d4056ea7c0004ac
+794a06003d20c000
+7929002061290008
 7d204eea7c0004ac
-600000003d40c000
-38e280cc60000000
-794a0020614a2000
-3d40001cf9428040
-7d085392614a2000
-794a0fc3792af804
-3920000141820080
-614a200c3d40c000
-794a002099270000
-7c0004ac3920ff80
-e92280407d2057aa
-7d004faa7c0004ac
-7908c202e9228040
+4182001871290020
+612900403d20c000
+7c0004ac79290020
+7929f8047d204eea
+79290fc33d00c000
+7908002061082000
+f902809060000000
+610820003d00001c
+418200847d4a4392
+3920000160000000
+3d00c00099228098
+3920ff806108200c
+7c0004ac79080020
+e92280907d2047aa
+7d404faa7c0004ac
+794ac202e9228090
 7c0004ac39290004
-e92280407d004faa
+e92280907d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e9228040
+39290010e9228090
 7d404faa7c0004ac
-39400007e9228040
+39400007e9228090
 7c0004ac39290008
 4e8000207d404faa
-994700003d20c000
-612920183908ffff
-7c0004ac79290020
-4e8000207d004fea
+394affff60000000
+3d20c00099228098
+7929002061292018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9072442000028
+7d434a147ca92850
+7c844a1439050001
+392000007d0903a6
+4e80002042000018
+7d23512a7d24502a
+4bffffcc394a0008
+7d0a49ae7d0448ae
+4bffffdc39290001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 2c24000000000000
 3881fff040820008
 f864000028050024
 4d81002038600000
-78e783e43ce00001
-e944000060e72600
-28090020892a0000
-2c25000040810028
-2c0500104182003c
-3860000041820038
-394a000148000080
-4bffffd0f9440000
-712900017ce94c36
-2c2500004082ffec
-38a0000a4082ffdc
-38a0000a4bffffd4
-4082ffc828090030
-2c090078892a0001
-394a00024082ffbc
-f944000038a00010
-38c9ffd04bffffac
-280a000954ca063e
-7cc9073441810034
-4c8000207c092800
-7c6519d238e70001
-7c691a14f8e40000
-89270000e8e40000
-4082ffc82c290000
-3949ff9f4e800020
-280a0019554a063e
-3929ffa941810010
-4bffffbc7d290734
-554a063e3949ffbf
+6108ffff3d00fffe
+6108d9ff790883e4
+89490000e9240000
+40810028280a0020
+4182003c2c250000
+418200382c050010
+4800008838600000
+f924000039290001
+7d0a56344bffffd0
+4182ffec714a0001
+4082ffdc2c250000
+4bffffd438a0000a
+2c0a003038a0000a
+894900014082ffc8
+4082ffbc2c0a0078
+38a0001039290002
+4bffffacf9240000
+54e7063e38eaffd0
+4181003c28070009
+7d2a07343929ffd0
+4c8000207c0a2800
+7c6519d239080001
+f90400007d290734
+e90400007c691a14
+714900ff89480000
+4e8000204082ffc0
+54e7063e38eaff9f
+4181000c28070019
+4bffffb83929ffa9
+554a063e394affbf
 4d810020280a0019
-4bffffe43929ffc9
+4bffffa03929ffc9
 0000000000000000
-7c6a1b7800000000
-7d2a18ae38600000
-4d8200202c090000
-4bfffff038630001
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000307d2903a6
-78aa072478a9e8c2
-7d0352141d29fff8
-7ca92a147c845214
-3945000139200000
-420000187d4903a6
-7d24502a4e800020
-394a00087d23512a
-7d4448ae4bffffc4
-392900017d4849ae
-000000004bffffdc
-0000000000000000
-280900193923ff9f
-3863ffe04d810020
-4e8000207c6307b4
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428f3c
-918100087d908026
-f821ffa148000819
-7c7c1b783be00000
-3d22ffff7cbe2b78
-7cdd3378e9297fc0
-3d22fffff9210020
-f9210028e9297fc8
-2c2900007ca92b78
-2c3f000040820034
-3be0000140820008
-2e2700007c3f2040
-3b7fffff38600000
-3821006040810038
-7d90812081810008
-281d001048000800
-7929e10240820014
-7fff07b43bff0001
-7d29eb924bffffb4
-7f5ed3784bfffff0
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-600000004bffff21
-7c3df0405463063e
-7c69d9aee93c0000
-4081ffc83b7bffff
-38600001e93c0000
-fbfc00007fe9fa14
-000000004bffff84
-0000068003000000
-38428e403c4c0001
-480007297c0802a6
+38428fd03c4c0001
+480008897c0802a6
+7c7e1b78f821ffa1
+7ca32b787c9c2378
+38a0000a38800000
+eb3e00007cfd3b78
+7d3a4b787d1b4378
+4bfffe797cdf3378
+2b9d001060000000
+7c681b7839200000
+408200242c3f0000
+408200082c090000
+7d29d21439200001
+418100547c034800
+4800087038210060
+7bffe102409e0010
+4bffffcc39290001
+4bfffff47fffeb92
+2c2a00019b690000
+e93e0000394affff
+f93e000039290001
+e93e00004182ffc8
+7c28e0407d194850
+4bffffb44180ffd8
+2c0900007d294050
+794a00203949ffff
+40810010394a0001
+7c0940003d008000
+394000014082ffcc
+000000004bffffc4
+0000078001000000
+38428ed83c4c0001
+480007997c0802a6
 3bc00000f821ffb1
 7c9c23787c7f1b78
 7cbd2b78eb630000
-4bfffe217fa3eb78
-7c23f04060000000
-e95f000040810014
-7c29e0407d3b5050
-3821005041800010
-4800073038600001
-3bde00017d3df0ae
-e93f0000992a0000
-f93f000039290001
-000000004bffffb8
-0000058001000000
-38428dc03c4c0001
-480006a17c0802a6
-7c7d1b78f821ffa1
-7ca32b787c9b2378
-38a0000a38800000
-eb3d00007d3f4b78
-7cfc3b787cde3378
-4bfffc717d1a4378
-3920000060000000
-2c3e00007c6307b4
-2c2900004082002c
-3920000140820008
-7c0348007d3f4a14
-418100607d2a07b4
-3860000038210060
-281c001048000684
-7bdee10240820014
-7d2907b439290001
-7fdee3924bffffbc
-9b4800004bfffff0
-3929ffff2c290001
-394a0001e95d0000
-4182ffbcf95d0000
-7d594050e91d0000
-4180ffd87c2ad840
-7d4a18504bffffa8
-392affff2c0a0000
-3929000179290020
-3c60800040810010
-4082ffcc7c0a1800
-4bffffc439200001
+4bfffd697fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007a4
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428cbc
-f821fed148000571
-f86100607c741b79
-4182006438600000
-4182005c2c240000
-3e42ffff39210040
+3c4c000100000580
+7c0802a638428e5c
+918100087d908026
+f821ffa148000711
+2b8600103be00000
+3d22ffff7c7c1b78
+7cbe2b78e9297f90
+7caa2b787cdd3378
+3d22fffff9210020
+f9210028e9297f98
+408200342c2a0000
+408200082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8181000838210060
+480006f47d908120
+794ae102409e0010
+4bffffbc3bff0001
+4bfffff47d4aeb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdad
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428d683c4c0001
+480005f57c0802a6
+3be00000f821fee1
+f86100607c691b79
+41820060f9210068
+418200582c240000
+3e62ffff39210040
 3ae4ffff3e22ffff
-3b210020f9210078
-3a527fe03ac00000
-3a317fd83ba10060
+3b010020f9210070
+3a4000203ac00000
+3ba100603a737fb0
+e94100683a317fa8
 ebc1006089250000
-418200102c290000
-7c3fb8407ff4f050
-3920000041800020
-e8610060993e0000
-7e8307b47e941850
-4800054438210130
-3945000128090025
-38e00000408204c4
-e901007889250000
-7cea07b4f8a10068
-390700017d2741ae
-7d0807b48d250001
-4182005828090064
-4182005028090069
-4182004828090075
-4182004028090078
-4182003828090058
-4182003028090070
-4182002828090063
-4182002028090073
-4182001828090025
-418200102809004f
-38e700012809006f
-394a00024082ff88
-7d4a07b428090025
-7d5952147d194214
-9aca002099280020
-393e000140820020
-39200025f9210060
-e9210068993e0000
-4bffff0438a90002
-eb66000039260008
-3a6000207fffb850
-f92100703b010041
-3929ffd289210041
+712a00ff7feaf050
+7c3fb8404182000c
+3920000041800018
+38210120993e0000
+480005c47fe307b4
+390500012c0a0025
+38e0000040820548
+e901007089250000
+7cea3b787cb02b78
+7d2741ae8c650001
+5469063e39070001
+418200b02c090064
+4181002c28090078
+4181002c28090068
+418200982c090058
+4181008828090058
+418200882c090025
+418200802c09004f
+4bffffa438e70001
+548b063e3883ff97
+4181ffec280b000f
+396b73c43d62ffff
+7c8b22aa788415a8
+7c8903a67c845a14
+000000484e800420
+ffffffccffffffcc
+ffffffccffffffcc
+00000048ffffffcc
+ffffffcc00000048
+00000048ffffffcc
+00000048ffffffcc
+ffffffccffffffcc
+2c09006300000048
+394a00024bffff84
+7d0807b42c090025
+7d1842147d4a07b4
+986800207d585214
+408200189aca0020
+993e0000395e0001
+38b00002f9410060
+892100414bfffeb4
+7fffb850eb860000
+3aa0002039e60008
+3929ffd23b210041
 4082000c712900fd
-3b0100423a600030
-3b4000043aa00000
-3a0000013b800000
-7ddb00d039e0002d
-2809004f48000164
-3898000188f80001
-38c9ffa8418201d0
-2805002254c5063e
-3ca2ffff41810370
-78c615a838a57520
-7cc62a147cc532aa
-4e8004207cc903a6
-0000035000000148
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000024400000350
-000003500000008c
-0000035000000350
-0000008c00000338
-0000035000000350
-0000035000000328
-000001a000000350
-00000350000001ec
-0000028400000350
-0000008c00000350
-0000035000000350
-000003500000014c
-2809007500000330
-9aca00207d41e214
-418200347f6adb78
-3929ffff57491838
-7f6948397e094836
-99e8000041820020
-39290001e9210060
-7b491f24f9210060
-7dca50387d52482a
+3b2100423aa00030
+3b4000043a800000
+56b5063e3b600000
+480001687ddc00d0
+38b900012c06004f
+38e8ffa8418201dc
+2804002254e4063e
+3c82ffff418103ac
+78e715a8388474c0
+7ce722147ce43aaa
+4e8004207ce903a6
+0000038c00000150
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+000002580000038c
+0000038c0000008c
+0000038c0000038c
+0000008c00000370
+0000038c0000038c
+0000038c0000035c
+000001ac0000038c
+0000038c000001fc
+000002980000038c
+0000008c0000038c
+0000038c0000038c
+0000038c00000154
+2c06007500000368
+7d4152147b6a0020
+7f8ae3789aca0020
+5747183841820038
+38e7ffff39000001
+7f8840397d083836
+3940002d41820020
+9949ffff39290001
+7b491e68f9210060
+7dca50387d53482a
 7d465378e8810060
-f941008038e0000a
-392000007f25cb78
-7fa3eb787e689b78
+f941007838e0000a
+392000007f05c378
+7fa3eb787ea8ab78
 7c84f8507c9e2050
-e88100604bfffc31
-7ea7ab78e9410080
+e88100604bfffa79
+7a8707e0e9410078
 7c9e205038c0000a
 7c84f8507d455378
-4bfffa917fa3eb78
-893800003b180001
-2c290000e9010060
-7d5e405041820010
-4181fe887c3f5040
-4bfffe28e8c10070
-7d21e2143aa00001
-7c8af85038e00010
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffba9
-38c000107ea7ab78
-e96100807c9e2050
-4bffff787d655b78
-38e000087d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffb55f9610080
-7ea7ab78e8810060
+4bfffbc97fa3eb78
+891900003b390001
+710600ffe9210060
+7d5e485041820010
+4181fe847c3f5040
+4bfffe307de67b78
+7b6900203a800001
+7d214a1438e00010
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff9edf9610078
+7a8707e0e8810060
+7c9e205038c00010
+7d655b78e9610078
+7b6900204bffff74
+7d214a1438e00008
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff995f9610078
+7a8707e0e8810060
 7c9e205038c00008
-7d21e2144bffffac
-7f66db7838e00010
-9ac900207c8af850
-3920000239000020
-7fa3eb787f25cb78
-e88100604bfffb19
-7fa3eb787e258b78
+7b6900204bffffa8
+7d214a1438e00010
+7c8af8507f86e378
+9ac9002039000020
+392000027f05c378
+4bfff9557fa3eb78
+7e258b78e8810060
+7c9e20507fa3eb78
+4bfffa357c84f850
+7a8707e0e8810060
+7f85e37838c00010
+4bfffec87c9e2050
+390000207b690020
+38e0000a7d214a14
+7f05c37838c00001
+7c8af8509ac90020
+7fa3eb7839200000
+e92100604bfff8f9
+392900019b890000
+4bfffe94f9210060
+38a0000a7b680020
+f9410080f9210088
+388000007d014214
+9ac800207f03c378
+600000004bfff76d
+7f83e378f8610078
+600000004bfff735
+e9410080e9010078
+7c281840e9210088
+e88100604181003c
+7fa3eb787f85e378
 7c84f8507c9e2050
-e88100604bfffa81
-38c000107ea7ab78
-7c9e20507f65db78
-7d21e2144bfffed4
-38e0000a39000020
-9ac9002038c00001
-392000007f25cb78
-7fa3eb787c8af850
-e92100604bfffac1
-e92100609b690000
-f921006039290001
-7d21e2144bfffea0
-f901009038a0000a
-38800000f9410088
-9ac900207f23cb78
-600000004bfff72d
-7f63db78f8610080
-600000004bfff83d
-7c291840e9210080
-7d2348514081004c
-e9010090e9410088
-408200087d4af850
-e8c1006039200001
-7c2a38407ce83050
-38e0002040810024
-3929ffff2c290001
-e8e1006098e60000
-f8e1006038e70001
-e88100604082ffd4
-7fa3eb787f65db78
-7c84f8507c9e2050
-4bfffdfc4bfff989
-418200482807006c
-4bfffdec3b400008
-3b40000228070068
-7c9823784082fde0
-4bfffdd43b400001
-554a063e3949ffd0
-4181fdc4280a0009
-7f81e214395c0001
-795c0020993c0020
-7c9823784bfffdb0
-993e00004bffffb8
-e92100607d455378
-f921006039290001
-000000004bfffae8
+4bfffe2c4bfff979
+392900019a490000
+7c29184039000001
+f921006040820034
+7ce9f0504bffffcc
+7ce7fa147c634050
+2c2700007d4af850
+390000007c691a14
+40820008394a0001
+2c2a000139400001
+4082ffb4394affff
+4082ffc071080001
+893900014bffff8c
+4182004c2c09006c
+4bfffdbc3b400008
+3b40000289390001
+4082fdac2c090068
+3b4000017cb92b78
+3928ffd04bfffda0
+280900095529063e
+7b6900204181fd90
+7d214a143b7b0001
+4bfffd7c99090020
+4bffffb47cb92b78
+3bde0001993e0000
+fbc100607d054378
+000000004bfffa6c
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -2303,9 +2298,8 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index edd354a..9a2c35e 100644
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -1,9 +1,25 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:35
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire clk,
-	input wire rst,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:12
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire clk,
+	input  wire rst,
 	output wire pll_locked,
 	output wire [14:0] ddram_a,
 	output wire [2:0] ddram_ba,
@@ -12,9 +28,9 @@ module litedram_core(
 	output wire ddram_we_n,
 	output wire ddram_cs_n,
 	output wire [3:0] ddram_dm,
-	inout wire [31:0] ddram_dq,
-	inout wire [3:0] ddram_dqs_p,
-	inout wire [3:0] ddram_dqs_n,
+	inout  wire [31:0] ddram_dq,
+	inout  wire [3:0] ddram_dqs_p,
+	inout  wire [3:0] ddram_dqs_n,
 	output wire ddram_clk_p,
 	output wire ddram_clk_n,
 	output wire ddram_cke,
@@ -22,32 +38,38 @@ module litedram_core(
 	output wire ddram_reset_n,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [24:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [24:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [31:0] user_port_native_0_wdata_we,
-	input wire [255:0] user_port_native_0_wdata_data,
+	input  wire [31:0] user_port_native_0_wdata_we,
+	input  wire [255:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [255:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg  main_rst = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
@@ -55,7 +77,7 @@ wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
 wire main_reset;
-reg main_power_down = 1'd0;
+reg  main_power_down = 1'd0;
 wire main_locked;
 wire main_clkin;
 wire main_clkout0;
@@ -66,72 +88,72 @@ wire main_clkout2;
 wire main_clkout_buf2;
 wire main_clkout3;
 wire main_clkout_buf3;
-reg [3:0] main_reset_counter = 4'd15;
-reg main_ic_reset = 1'd1;
-reg main_k7ddrphy_rst_storage = 1'd0;
-reg main_k7ddrphy_rst_re = 1'd0;
-reg [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg main_k7ddrphy_half_sys8x_taps_re = 1'd0;
-reg main_k7ddrphy_wlevel_en_storage = 1'd0;
-reg main_k7ddrphy_wlevel_en_re = 1'd0;
-reg main_k7ddrphy_wlevel_strobe_re = 1'd0;
+reg  [3:0] main_reset_counter = 4'd15;
+reg  main_ic_reset = 1'd1;
+reg  main_k7ddrphy_rst_storage = 1'd0;
+reg  main_k7ddrphy_rst_re = 1'd0;
+reg  [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  main_k7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  main_k7ddrphy_wlevel_en_storage = 1'd0;
+reg  main_k7ddrphy_wlevel_en_re = 1'd0;
+reg  main_k7ddrphy_wlevel_strobe_re = 1'd0;
 wire main_k7ddrphy_wlevel_strobe_r;
-reg main_k7ddrphy_wlevel_strobe_we = 1'd0;
-reg main_k7ddrphy_wlevel_strobe_w = 1'd0;
-reg main_k7ddrphy_cdly_rst_re = 1'd0;
+reg  main_k7ddrphy_wlevel_strobe_we = 1'd0;
+reg  main_k7ddrphy_wlevel_strobe_w = 1'd0;
+reg  main_k7ddrphy_cdly_rst_re = 1'd0;
 wire main_k7ddrphy_cdly_rst_r;
-reg main_k7ddrphy_cdly_rst_we = 1'd0;
-reg main_k7ddrphy_cdly_rst_w = 1'd0;
-reg main_k7ddrphy_cdly_inc_re = 1'd0;
+reg  main_k7ddrphy_cdly_rst_we = 1'd0;
+reg  main_k7ddrphy_cdly_rst_w = 1'd0;
+reg  main_k7ddrphy_cdly_inc_re = 1'd0;
 wire main_k7ddrphy_cdly_inc_r;
-reg main_k7ddrphy_cdly_inc_we = 1'd0;
-reg main_k7ddrphy_cdly_inc_w = 1'd0;
-reg [3:0] main_k7ddrphy_dly_sel_storage = 4'd0;
-reg main_k7ddrphy_dly_sel_re = 1'd0;
-reg main_k7ddrphy_rdly_dq_rst_re = 1'd0;
+reg  main_k7ddrphy_cdly_inc_we = 1'd0;
+reg  main_k7ddrphy_cdly_inc_w = 1'd0;
+reg  [3:0] main_k7ddrphy_dly_sel_storage = 4'd0;
+reg  main_k7ddrphy_dly_sel_re = 1'd0;
+reg  main_k7ddrphy_rdly_dq_rst_re = 1'd0;
 wire main_k7ddrphy_rdly_dq_rst_r;
-reg main_k7ddrphy_rdly_dq_rst_we = 1'd0;
-reg main_k7ddrphy_rdly_dq_rst_w = 1'd0;
-reg main_k7ddrphy_rdly_dq_inc_re = 1'd0;
+reg  main_k7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  main_k7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  main_k7ddrphy_rdly_dq_inc_re = 1'd0;
 wire main_k7ddrphy_rdly_dq_inc_r;
-reg main_k7ddrphy_rdly_dq_inc_we = 1'd0;
-reg main_k7ddrphy_rdly_dq_inc_w = 1'd0;
-reg main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg  main_k7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  main_k7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 wire main_k7ddrphy_rdly_dq_bitslip_rst_r;
-reg main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg main_k7ddrphy_rdly_dq_bitslip_re = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_re = 1'd0;
 wire main_k7ddrphy_rdly_dq_bitslip_r;
-reg main_k7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg main_k7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg main_k7ddrphy_wdly_dq_rst_re = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  main_k7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  main_k7ddrphy_wdly_dq_rst_re = 1'd0;
 wire main_k7ddrphy_wdly_dq_rst_r;
-reg main_k7ddrphy_wdly_dq_rst_we = 1'd0;
-reg main_k7ddrphy_wdly_dq_rst_w = 1'd0;
-reg main_k7ddrphy_wdly_dq_inc_re = 1'd0;
+reg  main_k7ddrphy_wdly_dq_rst_we = 1'd0;
+reg  main_k7ddrphy_wdly_dq_rst_w = 1'd0;
+reg  main_k7ddrphy_wdly_dq_inc_re = 1'd0;
 wire main_k7ddrphy_wdly_dq_inc_r;
-reg main_k7ddrphy_wdly_dq_inc_we = 1'd0;
-reg main_k7ddrphy_wdly_dq_inc_w = 1'd0;
-reg main_k7ddrphy_wdly_dqs_rst_re = 1'd0;
+reg  main_k7ddrphy_wdly_dq_inc_we = 1'd0;
+reg  main_k7ddrphy_wdly_dq_inc_w = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_rst_re = 1'd0;
 wire main_k7ddrphy_wdly_dqs_rst_r;
-reg main_k7ddrphy_wdly_dqs_rst_we = 1'd0;
-reg main_k7ddrphy_wdly_dqs_rst_w = 1'd0;
-reg main_k7ddrphy_wdly_dqs_inc_re = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_rst_we = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_rst_w = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_inc_re = 1'd0;
 wire main_k7ddrphy_wdly_dqs_inc_r;
-reg main_k7ddrphy_wdly_dqs_inc_we = 1'd0;
-reg main_k7ddrphy_wdly_dqs_inc_w = 1'd0;
-reg main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_inc_we = 1'd0;
+reg  main_k7ddrphy_wdly_dqs_inc_w = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
 wire main_k7ddrphy_wdly_dq_bitslip_rst_r;
-reg main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg main_k7ddrphy_wdly_dq_bitslip_re = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_re = 1'd0;
 wire main_k7ddrphy_wdly_dq_bitslip_r;
-reg main_k7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg main_k7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] main_k7ddrphy_rdphase_storage = 2'd1;
-reg main_k7ddrphy_rdphase_re = 1'd0;
-reg [1:0] main_k7ddrphy_wrphase_storage = 2'd2;
-reg main_k7ddrphy_wrphase_re = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  main_k7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] main_k7ddrphy_rdphase_storage = 2'd1;
+reg  main_k7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] main_k7ddrphy_wrphase_storage = 2'd2;
+reg  main_k7ddrphy_wrphase_re = 1'd0;
 wire [14:0] main_k7ddrphy_dfi_p0_address;
 wire [2:0] main_k7ddrphy_dfi_p0_bank;
 wire main_k7ddrphy_dfi_p0_cas_n;
@@ -146,7 +168,7 @@ wire [63:0] main_k7ddrphy_dfi_p0_wrdata;
 wire main_k7ddrphy_dfi_p0_wrdata_en;
 wire [7:0] main_k7ddrphy_dfi_p0_wrdata_mask;
 wire main_k7ddrphy_dfi_p0_rddata_en;
-reg [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0;
+reg  [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0;
 wire main_k7ddrphy_dfi_p0_rddata_valid;
 wire [14:0] main_k7ddrphy_dfi_p1_address;
 wire [2:0] main_k7ddrphy_dfi_p1_bank;
@@ -162,7 +184,7 @@ wire [63:0] main_k7ddrphy_dfi_p1_wrdata;
 wire main_k7ddrphy_dfi_p1_wrdata_en;
 wire [7:0] main_k7ddrphy_dfi_p1_wrdata_mask;
 wire main_k7ddrphy_dfi_p1_rddata_en;
-reg [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0;
+reg  [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0;
 wire main_k7ddrphy_dfi_p1_rddata_valid;
 wire [14:0] main_k7ddrphy_dfi_p2_address;
 wire [2:0] main_k7ddrphy_dfi_p2_bank;
@@ -178,7 +200,7 @@ wire [63:0] main_k7ddrphy_dfi_p2_wrdata;
 wire main_k7ddrphy_dfi_p2_wrdata_en;
 wire [7:0] main_k7ddrphy_dfi_p2_wrdata_mask;
 wire main_k7ddrphy_dfi_p2_rddata_en;
-reg [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0;
+reg  [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0;
 wire main_k7ddrphy_dfi_p2_rddata_valid;
 wire [14:0] main_k7ddrphy_dfi_p3_address;
 wire [2:0] main_k7ddrphy_dfi_p3_bank;
@@ -194,7 +216,7 @@ wire [63:0] main_k7ddrphy_dfi_p3_wrdata;
 wire main_k7ddrphy_dfi_p3_wrdata_en;
 wire [7:0] main_k7ddrphy_dfi_p3_wrdata_mask;
 wire main_k7ddrphy_dfi_p3_rddata_en;
-reg [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0;
+reg  [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0;
 wire main_k7ddrphy_dfi_p3_rddata_valid;
 wire main_k7ddrphy_sd_clk_se_nodelay;
 wire main_k7ddrphy_sd_clk_se_delayed;
@@ -223,522 +245,522 @@ wire main_k7ddrphy_oq21;
 wire main_k7ddrphy_oq22;
 wire main_k7ddrphy_oq23;
 wire main_k7ddrphy_oq24;
-reg main_k7ddrphy_dqs_oe = 1'd0;
+reg  main_k7ddrphy_dqs_oe = 1'd0;
 wire main_k7ddrphy_dqs_preamble;
 wire main_k7ddrphy_dqs_postamble;
 wire main_k7ddrphy_dqs_oe_delay_tappeddelayline;
-reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg main_k7ddrphy_dqspattern0 = 1'd0;
-reg main_k7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] main_k7ddrphy_dqspattern_o = 8'd0;
+reg  main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_k7ddrphy_dqspattern0 = 1'd0;
+reg  main_k7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] main_k7ddrphy_dqspattern_o = 8'd0;
 wire main_k7ddrphy_dqs_o_no_delay0;
 wire main_k7ddrphy_dqs_o_delayed0;
 wire main_k7ddrphy_dqs_t0;
-reg [7:0] main_k7ddrphy_bitslip00 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0;
 wire main_k7ddrphy0;
 wire main_k7ddrphy_dqs_o_no_delay1;
 wire main_k7ddrphy_dqs_o_delayed1;
 wire main_k7ddrphy_dqs_t1;
-reg [7:0] main_k7ddrphy_bitslip10 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0;
 wire main_k7ddrphy1;
 wire main_k7ddrphy_dqs_o_no_delay2;
 wire main_k7ddrphy_dqs_o_delayed2;
 wire main_k7ddrphy_dqs_t2;
-reg [7:0] main_k7ddrphy_bitslip20 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0;
 wire main_k7ddrphy2;
 wire main_k7ddrphy_dqs_o_no_delay3;
 wire main_k7ddrphy_dqs_o_delayed3;
 wire main_k7ddrphy_dqs_t3;
-reg [7:0] main_k7ddrphy_bitslip30 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0;
 wire main_k7ddrphy3;
 wire main_k7ddrphy_dm_o_nodelay0;
-reg [7:0] main_k7ddrphy_bitslip01 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0;
 wire main_k7ddrphy_dm_o_nodelay1;
-reg [7:0] main_k7ddrphy_bitslip11 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0;
 wire main_k7ddrphy_dm_o_nodelay2;
-reg [7:0] main_k7ddrphy_bitslip21 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip21 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0;
 wire main_k7ddrphy_dm_o_nodelay3;
-reg [7:0] main_k7ddrphy_bitslip31 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip31 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0;
 wire main_k7ddrphy_dq_oe;
 wire main_k7ddrphy_dq_oe_delay_tappeddelayline;
-reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
 wire main_k7ddrphy_dq_o_nodelay0;
 wire main_k7ddrphy_dq_o_delayed0;
 wire main_k7ddrphy_dq_i_nodelay0;
 wire main_k7ddrphy_dq_i_delayed0;
 wire main_k7ddrphy_dq_t0;
-reg [7:0] main_k7ddrphy_bitslip02 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip03;
-reg [7:0] main_k7ddrphy_bitslip04 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay1;
 wire main_k7ddrphy_dq_o_delayed1;
 wire main_k7ddrphy_dq_i_nodelay1;
 wire main_k7ddrphy_dq_i_delayed1;
 wire main_k7ddrphy_dq_t1;
-reg [7:0] main_k7ddrphy_bitslip12 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip13;
-reg [7:0] main_k7ddrphy_bitslip14 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay2;
 wire main_k7ddrphy_dq_o_delayed2;
 wire main_k7ddrphy_dq_i_nodelay2;
 wire main_k7ddrphy_dq_i_delayed2;
 wire main_k7ddrphy_dq_t2;
-reg [7:0] main_k7ddrphy_bitslip22 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip23;
-reg [7:0] main_k7ddrphy_bitslip24 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip24 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay3;
 wire main_k7ddrphy_dq_o_delayed3;
 wire main_k7ddrphy_dq_i_nodelay3;
 wire main_k7ddrphy_dq_i_delayed3;
 wire main_k7ddrphy_dq_t3;
-reg [7:0] main_k7ddrphy_bitslip32 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip33;
-reg [7:0] main_k7ddrphy_bitslip34 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip34 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay4;
 wire main_k7ddrphy_dq_o_delayed4;
 wire main_k7ddrphy_dq_i_nodelay4;
 wire main_k7ddrphy_dq_i_delayed4;
 wire main_k7ddrphy_dq_t4;
-reg [7:0] main_k7ddrphy_bitslip40 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip41;
-reg [7:0] main_k7ddrphy_bitslip42 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay5;
 wire main_k7ddrphy_dq_o_delayed5;
 wire main_k7ddrphy_dq_i_nodelay5;
 wire main_k7ddrphy_dq_i_delayed5;
 wire main_k7ddrphy_dq_t5;
-reg [7:0] main_k7ddrphy_bitslip50 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip51;
-reg [7:0] main_k7ddrphy_bitslip52 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay6;
 wire main_k7ddrphy_dq_o_delayed6;
 wire main_k7ddrphy_dq_i_nodelay6;
 wire main_k7ddrphy_dq_i_delayed6;
 wire main_k7ddrphy_dq_t6;
-reg [7:0] main_k7ddrphy_bitslip60 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip61;
-reg [7:0] main_k7ddrphy_bitslip62 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay7;
 wire main_k7ddrphy_dq_o_delayed7;
 wire main_k7ddrphy_dq_i_nodelay7;
 wire main_k7ddrphy_dq_i_delayed7;
 wire main_k7ddrphy_dq_t7;
-reg [7:0] main_k7ddrphy_bitslip70 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip71;
-reg [7:0] main_k7ddrphy_bitslip72 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay8;
 wire main_k7ddrphy_dq_o_delayed8;
 wire main_k7ddrphy_dq_i_nodelay8;
 wire main_k7ddrphy_dq_i_delayed8;
 wire main_k7ddrphy_dq_t8;
-reg [7:0] main_k7ddrphy_bitslip80 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip81;
-reg [7:0] main_k7ddrphy_bitslip82 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay9;
 wire main_k7ddrphy_dq_o_delayed9;
 wire main_k7ddrphy_dq_i_nodelay9;
 wire main_k7ddrphy_dq_i_delayed9;
 wire main_k7ddrphy_dq_t9;
-reg [7:0] main_k7ddrphy_bitslip90 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip91;
-reg [7:0] main_k7ddrphy_bitslip92 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay10;
 wire main_k7ddrphy_dq_o_delayed10;
 wire main_k7ddrphy_dq_i_nodelay10;
 wire main_k7ddrphy_dq_i_delayed10;
 wire main_k7ddrphy_dq_t10;
-reg [7:0] main_k7ddrphy_bitslip100 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip101;
-reg [7:0] main_k7ddrphy_bitslip102 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay11;
 wire main_k7ddrphy_dq_o_delayed11;
 wire main_k7ddrphy_dq_i_nodelay11;
 wire main_k7ddrphy_dq_i_delayed11;
 wire main_k7ddrphy_dq_t11;
-reg [7:0] main_k7ddrphy_bitslip110 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip111;
-reg [7:0] main_k7ddrphy_bitslip112 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay12;
 wire main_k7ddrphy_dq_o_delayed12;
 wire main_k7ddrphy_dq_i_nodelay12;
 wire main_k7ddrphy_dq_i_delayed12;
 wire main_k7ddrphy_dq_t12;
-reg [7:0] main_k7ddrphy_bitslip120 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip121;
-reg [7:0] main_k7ddrphy_bitslip122 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay13;
 wire main_k7ddrphy_dq_o_delayed13;
 wire main_k7ddrphy_dq_i_nodelay13;
 wire main_k7ddrphy_dq_i_delayed13;
 wire main_k7ddrphy_dq_t13;
-reg [7:0] main_k7ddrphy_bitslip130 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip131;
-reg [7:0] main_k7ddrphy_bitslip132 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay14;
 wire main_k7ddrphy_dq_o_delayed14;
 wire main_k7ddrphy_dq_i_nodelay14;
 wire main_k7ddrphy_dq_i_delayed14;
 wire main_k7ddrphy_dq_t14;
-reg [7:0] main_k7ddrphy_bitslip140 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip141;
-reg [7:0] main_k7ddrphy_bitslip142 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay15;
 wire main_k7ddrphy_dq_o_delayed15;
 wire main_k7ddrphy_dq_i_nodelay15;
 wire main_k7ddrphy_dq_i_delayed15;
 wire main_k7ddrphy_dq_t15;
-reg [7:0] main_k7ddrphy_bitslip150 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip151;
-reg [7:0] main_k7ddrphy_bitslip152 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay16;
 wire main_k7ddrphy_dq_o_delayed16;
 wire main_k7ddrphy_dq_i_nodelay16;
 wire main_k7ddrphy_dq_i_delayed16;
 wire main_k7ddrphy_dq_t16;
-reg [7:0] main_k7ddrphy_bitslip160 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip160 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip161;
-reg [7:0] main_k7ddrphy_bitslip162 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip162 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay17;
 wire main_k7ddrphy_dq_o_delayed17;
 wire main_k7ddrphy_dq_i_nodelay17;
 wire main_k7ddrphy_dq_i_delayed17;
 wire main_k7ddrphy_dq_t17;
-reg [7:0] main_k7ddrphy_bitslip170 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip170 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip171;
-reg [7:0] main_k7ddrphy_bitslip172 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip172 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay18;
 wire main_k7ddrphy_dq_o_delayed18;
 wire main_k7ddrphy_dq_i_nodelay18;
 wire main_k7ddrphy_dq_i_delayed18;
 wire main_k7ddrphy_dq_t18;
-reg [7:0] main_k7ddrphy_bitslip180 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip180 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip181;
-reg [7:0] main_k7ddrphy_bitslip182 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip182 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay19;
 wire main_k7ddrphy_dq_o_delayed19;
 wire main_k7ddrphy_dq_i_nodelay19;
 wire main_k7ddrphy_dq_i_delayed19;
 wire main_k7ddrphy_dq_t19;
-reg [7:0] main_k7ddrphy_bitslip190 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip190 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip191;
-reg [7:0] main_k7ddrphy_bitslip192 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip192 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay20;
 wire main_k7ddrphy_dq_o_delayed20;
 wire main_k7ddrphy_dq_i_nodelay20;
 wire main_k7ddrphy_dq_i_delayed20;
 wire main_k7ddrphy_dq_t20;
-reg [7:0] main_k7ddrphy_bitslip200 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip200 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip201;
-reg [7:0] main_k7ddrphy_bitslip202 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip202 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay21;
 wire main_k7ddrphy_dq_o_delayed21;
 wire main_k7ddrphy_dq_i_nodelay21;
 wire main_k7ddrphy_dq_i_delayed21;
 wire main_k7ddrphy_dq_t21;
-reg [7:0] main_k7ddrphy_bitslip210 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip210 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip211;
-reg [7:0] main_k7ddrphy_bitslip212 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip212 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay22;
 wire main_k7ddrphy_dq_o_delayed22;
 wire main_k7ddrphy_dq_i_nodelay22;
 wire main_k7ddrphy_dq_i_delayed22;
 wire main_k7ddrphy_dq_t22;
-reg [7:0] main_k7ddrphy_bitslip220 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip220 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip221;
-reg [7:0] main_k7ddrphy_bitslip222 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip222 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay23;
 wire main_k7ddrphy_dq_o_delayed23;
 wire main_k7ddrphy_dq_i_nodelay23;
 wire main_k7ddrphy_dq_i_delayed23;
 wire main_k7ddrphy_dq_t23;
-reg [7:0] main_k7ddrphy_bitslip230 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip230 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip231;
-reg [7:0] main_k7ddrphy_bitslip232 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip232 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay24;
 wire main_k7ddrphy_dq_o_delayed24;
 wire main_k7ddrphy_dq_i_nodelay24;
 wire main_k7ddrphy_dq_i_delayed24;
 wire main_k7ddrphy_dq_t24;
-reg [7:0] main_k7ddrphy_bitslip240 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip240 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip241;
-reg [7:0] main_k7ddrphy_bitslip242 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip242 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay25;
 wire main_k7ddrphy_dq_o_delayed25;
 wire main_k7ddrphy_dq_i_nodelay25;
 wire main_k7ddrphy_dq_i_delayed25;
 wire main_k7ddrphy_dq_t25;
-reg [7:0] main_k7ddrphy_bitslip250 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip250 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip251;
-reg [7:0] main_k7ddrphy_bitslip252 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip252 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay26;
 wire main_k7ddrphy_dq_o_delayed26;
 wire main_k7ddrphy_dq_i_nodelay26;
 wire main_k7ddrphy_dq_i_delayed26;
 wire main_k7ddrphy_dq_t26;
-reg [7:0] main_k7ddrphy_bitslip260 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip260 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip261;
-reg [7:0] main_k7ddrphy_bitslip262 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip262 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay27;
 wire main_k7ddrphy_dq_o_delayed27;
 wire main_k7ddrphy_dq_i_nodelay27;
 wire main_k7ddrphy_dq_i_delayed27;
 wire main_k7ddrphy_dq_t27;
-reg [7:0] main_k7ddrphy_bitslip270 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip270 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip271;
-reg [7:0] main_k7ddrphy_bitslip272 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip272 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay28;
 wire main_k7ddrphy_dq_o_delayed28;
 wire main_k7ddrphy_dq_i_nodelay28;
 wire main_k7ddrphy_dq_i_delayed28;
 wire main_k7ddrphy_dq_t28;
-reg [7:0] main_k7ddrphy_bitslip280 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip280 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip281;
-reg [7:0] main_k7ddrphy_bitslip282 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip282 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay29;
 wire main_k7ddrphy_dq_o_delayed29;
 wire main_k7ddrphy_dq_i_nodelay29;
 wire main_k7ddrphy_dq_i_delayed29;
 wire main_k7ddrphy_dq_t29;
-reg [7:0] main_k7ddrphy_bitslip290 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip290 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip291;
-reg [7:0] main_k7ddrphy_bitslip292 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip292 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay30;
 wire main_k7ddrphy_dq_o_delayed30;
 wire main_k7ddrphy_dq_i_nodelay30;
 wire main_k7ddrphy_dq_i_delayed30;
 wire main_k7ddrphy_dq_t30;
-reg [7:0] main_k7ddrphy_bitslip300 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip300 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip301;
-reg [7:0] main_k7ddrphy_bitslip302 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip302 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0;
 wire main_k7ddrphy_dq_o_nodelay31;
 wire main_k7ddrphy_dq_o_delayed31;
 wire main_k7ddrphy_dq_i_nodelay31;
 wire main_k7ddrphy_dq_i_delayed31;
 wire main_k7ddrphy_dq_t31;
-reg [7:0] main_k7ddrphy_bitslip310 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0;
+reg  [7:0] main_k7ddrphy_bitslip310 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0;
 wire [7:0] main_k7ddrphy_bitslip311;
-reg [7:0] main_k7ddrphy_bitslip312 = 8'd0;
-reg [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7;
-reg [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg  [7:0] main_k7ddrphy_bitslip312 = 8'd0;
+reg  [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7;
+reg  [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 wire [14:0] main_litedramcore_inti_p0_address;
 wire [2:0] main_litedramcore_inti_p0_bank;
-reg main_litedramcore_inti_p0_cas_n = 1'd1;
-reg main_litedramcore_inti_p0_cs_n = 1'd1;
-reg main_litedramcore_inti_p0_ras_n = 1'd1;
-reg main_litedramcore_inti_p0_we_n = 1'd1;
+reg  main_litedramcore_inti_p0_cas_n = 1'd1;
+reg  main_litedramcore_inti_p0_cs_n = 1'd1;
+reg  main_litedramcore_inti_p0_ras_n = 1'd1;
+reg  main_litedramcore_inti_p0_we_n = 1'd1;
 wire main_litedramcore_inti_p0_cke;
 wire main_litedramcore_inti_p0_odt;
 wire main_litedramcore_inti_p0_reset_n;
-reg main_litedramcore_inti_p0_act_n = 1'd1;
+reg  main_litedramcore_inti_p0_act_n = 1'd1;
 wire [63:0] main_litedramcore_inti_p0_wrdata;
 wire main_litedramcore_inti_p0_wrdata_en;
 wire [7:0] main_litedramcore_inti_p0_wrdata_mask;
 wire main_litedramcore_inti_p0_rddata_en;
-reg [63:0] main_litedramcore_inti_p0_rddata = 64'd0;
-reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_inti_p0_rddata = 64'd0;
+reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p1_address;
 wire [2:0] main_litedramcore_inti_p1_bank;
-reg main_litedramcore_inti_p1_cas_n = 1'd1;
-reg main_litedramcore_inti_p1_cs_n = 1'd1;
-reg main_litedramcore_inti_p1_ras_n = 1'd1;
-reg main_litedramcore_inti_p1_we_n = 1'd1;
+reg  main_litedramcore_inti_p1_cas_n = 1'd1;
+reg  main_litedramcore_inti_p1_cs_n = 1'd1;
+reg  main_litedramcore_inti_p1_ras_n = 1'd1;
+reg  main_litedramcore_inti_p1_we_n = 1'd1;
 wire main_litedramcore_inti_p1_cke;
 wire main_litedramcore_inti_p1_odt;
 wire main_litedramcore_inti_p1_reset_n;
-reg main_litedramcore_inti_p1_act_n = 1'd1;
+reg  main_litedramcore_inti_p1_act_n = 1'd1;
 wire [63:0] main_litedramcore_inti_p1_wrdata;
 wire main_litedramcore_inti_p1_wrdata_en;
 wire [7:0] main_litedramcore_inti_p1_wrdata_mask;
 wire main_litedramcore_inti_p1_rddata_en;
-reg [63:0] main_litedramcore_inti_p1_rddata = 64'd0;
-reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_inti_p1_rddata = 64'd0;
+reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p2_address;
 wire [2:0] main_litedramcore_inti_p2_bank;
-reg main_litedramcore_inti_p2_cas_n = 1'd1;
-reg main_litedramcore_inti_p2_cs_n = 1'd1;
-reg main_litedramcore_inti_p2_ras_n = 1'd1;
-reg main_litedramcore_inti_p2_we_n = 1'd1;
+reg  main_litedramcore_inti_p2_cas_n = 1'd1;
+reg  main_litedramcore_inti_p2_cs_n = 1'd1;
+reg  main_litedramcore_inti_p2_ras_n = 1'd1;
+reg  main_litedramcore_inti_p2_we_n = 1'd1;
 wire main_litedramcore_inti_p2_cke;
 wire main_litedramcore_inti_p2_odt;
 wire main_litedramcore_inti_p2_reset_n;
-reg main_litedramcore_inti_p2_act_n = 1'd1;
+reg  main_litedramcore_inti_p2_act_n = 1'd1;
 wire [63:0] main_litedramcore_inti_p2_wrdata;
 wire main_litedramcore_inti_p2_wrdata_en;
 wire [7:0] main_litedramcore_inti_p2_wrdata_mask;
 wire main_litedramcore_inti_p2_rddata_en;
-reg [63:0] main_litedramcore_inti_p2_rddata = 64'd0;
-reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_inti_p2_rddata = 64'd0;
+reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p3_address;
 wire [2:0] main_litedramcore_inti_p3_bank;
-reg main_litedramcore_inti_p3_cas_n = 1'd1;
-reg main_litedramcore_inti_p3_cs_n = 1'd1;
-reg main_litedramcore_inti_p3_ras_n = 1'd1;
-reg main_litedramcore_inti_p3_we_n = 1'd1;
+reg  main_litedramcore_inti_p3_cas_n = 1'd1;
+reg  main_litedramcore_inti_p3_cs_n = 1'd1;
+reg  main_litedramcore_inti_p3_ras_n = 1'd1;
+reg  main_litedramcore_inti_p3_we_n = 1'd1;
 wire main_litedramcore_inti_p3_cke;
 wire main_litedramcore_inti_p3_odt;
 wire main_litedramcore_inti_p3_reset_n;
-reg main_litedramcore_inti_p3_act_n = 1'd1;
+reg  main_litedramcore_inti_p3_act_n = 1'd1;
 wire [63:0] main_litedramcore_inti_p3_wrdata;
 wire main_litedramcore_inti_p3_wrdata_en;
 wire [7:0] main_litedramcore_inti_p3_wrdata_mask;
 wire main_litedramcore_inti_p3_rddata_en;
-reg [63:0] main_litedramcore_inti_p3_rddata = 64'd0;
-reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_inti_p3_rddata = 64'd0;
+reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p0_address;
 wire [2:0] main_litedramcore_slave_p0_bank;
 wire main_litedramcore_slave_p0_cas_n;
@@ -753,8 +775,8 @@ wire [63:0] main_litedramcore_slave_p0_wrdata;
 wire main_litedramcore_slave_p0_wrdata_en;
 wire [7:0] main_litedramcore_slave_p0_wrdata_mask;
 wire main_litedramcore_slave_p0_rddata_en;
-reg [63:0] main_litedramcore_slave_p0_rddata = 64'd0;
-reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_slave_p0_rddata = 64'd0;
+reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p1_address;
 wire [2:0] main_litedramcore_slave_p1_bank;
 wire main_litedramcore_slave_p1_cas_n;
@@ -769,8 +791,8 @@ wire [63:0] main_litedramcore_slave_p1_wrdata;
 wire main_litedramcore_slave_p1_wrdata_en;
 wire [7:0] main_litedramcore_slave_p1_wrdata_mask;
 wire main_litedramcore_slave_p1_rddata_en;
-reg [63:0] main_litedramcore_slave_p1_rddata = 64'd0;
-reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_slave_p1_rddata = 64'd0;
+reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p2_address;
 wire [2:0] main_litedramcore_slave_p2_bank;
 wire main_litedramcore_slave_p2_cas_n;
@@ -785,8 +807,8 @@ wire [63:0] main_litedramcore_slave_p2_wrdata;
 wire main_litedramcore_slave_p2_wrdata_en;
 wire [7:0] main_litedramcore_slave_p2_wrdata_mask;
 wire main_litedramcore_slave_p2_rddata_en;
-reg [63:0] main_litedramcore_slave_p2_rddata = 64'd0;
-reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [63:0] main_litedramcore_slave_p2_rddata = 64'd0;
+reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p3_address;
 wire [2:0] main_litedramcore_slave_p3_bank;
 wire main_litedramcore_slave_p3_cas_n;
@@ -801,138 +823,138 @@ wire [63:0] main_litedramcore_slave_p3_wrdata;
 wire main_litedramcore_slave_p3_wrdata_en;
 wire [7:0] main_litedramcore_slave_p3_wrdata_mask;
 wire main_litedramcore_slave_p3_rddata_en;
-reg [63:0] main_litedramcore_slave_p3_rddata = 64'd0;
-reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [14:0] main_litedramcore_master_p0_address = 15'd0;
-reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg main_litedramcore_master_p0_cas_n = 1'd1;
-reg main_litedramcore_master_p0_cs_n = 1'd1;
-reg main_litedramcore_master_p0_ras_n = 1'd1;
-reg main_litedramcore_master_p0_we_n = 1'd1;
-reg main_litedramcore_master_p0_cke = 1'd0;
-reg main_litedramcore_master_p0_odt = 1'd0;
-reg main_litedramcore_master_p0_reset_n = 1'd0;
-reg main_litedramcore_master_p0_act_n = 1'd1;
-reg [63:0] main_litedramcore_master_p0_wrdata = 64'd0;
-reg main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0;
-reg main_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [63:0] main_litedramcore_slave_p3_rddata = 64'd0;
+reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [14:0] main_litedramcore_master_p0_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg  main_litedramcore_master_p0_cas_n = 1'd1;
+reg  main_litedramcore_master_p0_cs_n = 1'd1;
+reg  main_litedramcore_master_p0_ras_n = 1'd1;
+reg  main_litedramcore_master_p0_we_n = 1'd1;
+reg  main_litedramcore_master_p0_cke = 1'd0;
+reg  main_litedramcore_master_p0_odt = 1'd0;
+reg  main_litedramcore_master_p0_reset_n = 1'd0;
+reg  main_litedramcore_master_p0_act_n = 1'd1;
+reg  [63:0] main_litedramcore_master_p0_wrdata = 64'd0;
+reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0;
+reg  main_litedramcore_master_p0_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_master_p0_rddata;
 wire main_litedramcore_master_p0_rddata_valid;
-reg [14:0] main_litedramcore_master_p1_address = 15'd0;
-reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg main_litedramcore_master_p1_cas_n = 1'd1;
-reg main_litedramcore_master_p1_cs_n = 1'd1;
-reg main_litedramcore_master_p1_ras_n = 1'd1;
-reg main_litedramcore_master_p1_we_n = 1'd1;
-reg main_litedramcore_master_p1_cke = 1'd0;
-reg main_litedramcore_master_p1_odt = 1'd0;
-reg main_litedramcore_master_p1_reset_n = 1'd0;
-reg main_litedramcore_master_p1_act_n = 1'd1;
-reg [63:0] main_litedramcore_master_p1_wrdata = 64'd0;
-reg main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0;
-reg main_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p1_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg  main_litedramcore_master_p1_cas_n = 1'd1;
+reg  main_litedramcore_master_p1_cs_n = 1'd1;
+reg  main_litedramcore_master_p1_ras_n = 1'd1;
+reg  main_litedramcore_master_p1_we_n = 1'd1;
+reg  main_litedramcore_master_p1_cke = 1'd0;
+reg  main_litedramcore_master_p1_odt = 1'd0;
+reg  main_litedramcore_master_p1_reset_n = 1'd0;
+reg  main_litedramcore_master_p1_act_n = 1'd1;
+reg  [63:0] main_litedramcore_master_p1_wrdata = 64'd0;
+reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0;
+reg  main_litedramcore_master_p1_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_master_p1_rddata;
 wire main_litedramcore_master_p1_rddata_valid;
-reg [14:0] main_litedramcore_master_p2_address = 15'd0;
-reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg main_litedramcore_master_p2_cas_n = 1'd1;
-reg main_litedramcore_master_p2_cs_n = 1'd1;
-reg main_litedramcore_master_p2_ras_n = 1'd1;
-reg main_litedramcore_master_p2_we_n = 1'd1;
-reg main_litedramcore_master_p2_cke = 1'd0;
-reg main_litedramcore_master_p2_odt = 1'd0;
-reg main_litedramcore_master_p2_reset_n = 1'd0;
-reg main_litedramcore_master_p2_act_n = 1'd1;
-reg [63:0] main_litedramcore_master_p2_wrdata = 64'd0;
-reg main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0;
-reg main_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p2_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg  main_litedramcore_master_p2_cas_n = 1'd1;
+reg  main_litedramcore_master_p2_cs_n = 1'd1;
+reg  main_litedramcore_master_p2_ras_n = 1'd1;
+reg  main_litedramcore_master_p2_we_n = 1'd1;
+reg  main_litedramcore_master_p2_cke = 1'd0;
+reg  main_litedramcore_master_p2_odt = 1'd0;
+reg  main_litedramcore_master_p2_reset_n = 1'd0;
+reg  main_litedramcore_master_p2_act_n = 1'd1;
+reg  [63:0] main_litedramcore_master_p2_wrdata = 64'd0;
+reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0;
+reg  main_litedramcore_master_p2_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_master_p2_rddata;
 wire main_litedramcore_master_p2_rddata_valid;
-reg [14:0] main_litedramcore_master_p3_address = 15'd0;
-reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg main_litedramcore_master_p3_cas_n = 1'd1;
-reg main_litedramcore_master_p3_cs_n = 1'd1;
-reg main_litedramcore_master_p3_ras_n = 1'd1;
-reg main_litedramcore_master_p3_we_n = 1'd1;
-reg main_litedramcore_master_p3_cke = 1'd0;
-reg main_litedramcore_master_p3_odt = 1'd0;
-reg main_litedramcore_master_p3_reset_n = 1'd0;
-reg main_litedramcore_master_p3_act_n = 1'd1;
-reg [63:0] main_litedramcore_master_p3_wrdata = 64'd0;
-reg main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0;
-reg main_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p3_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg  main_litedramcore_master_p3_cas_n = 1'd1;
+reg  main_litedramcore_master_p3_cs_n = 1'd1;
+reg  main_litedramcore_master_p3_ras_n = 1'd1;
+reg  main_litedramcore_master_p3_we_n = 1'd1;
+reg  main_litedramcore_master_p3_cke = 1'd0;
+reg  main_litedramcore_master_p3_odt = 1'd0;
+reg  main_litedramcore_master_p3_reset_n = 1'd0;
+reg  main_litedramcore_master_p3_act_n = 1'd1;
+reg  [63:0] main_litedramcore_master_p3_wrdata = 64'd0;
+reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0;
+reg  main_litedramcore_master_p3_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_master_p3_rddata;
 wire main_litedramcore_master_p3_rddata_valid;
 wire main_litedramcore_sel;
 wire main_litedramcore_cke;
 wire main_litedramcore_odt;
 wire main_litedramcore_reset_n;
-reg [3:0] main_litedramcore_storage = 4'd1;
-reg main_litedramcore_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] main_litedramcore_storage = 4'd1;
+reg  main_litedramcore_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector0_command_issue_r;
-reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0;
 wire main_litedramcore_phaseinjector0_rddata_we;
-reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector1_command_issue_r;
-reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0;
 wire main_litedramcore_phaseinjector1_rddata_we;
-reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector2_command_issue_r;
-reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0;
-reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0;
+reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0;
 wire main_litedramcore_phaseinjector2_rddata_we;
-reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector3_command_issue_r;
-reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0;
-reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0;
+reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0;
 wire main_litedramcore_phaseinjector3_rddata_we;
-reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire main_litedramcore_interface_bank0_valid;
 wire main_litedramcore_interface_bank0_ready;
 wire main_litedramcore_interface_bank0_we;
@@ -989,131 +1011,131 @@ wire [21:0] main_litedramcore_interface_bank7_addr;
 wire main_litedramcore_interface_bank7_lock;
 wire main_litedramcore_interface_bank7_wdata_ready;
 wire main_litedramcore_interface_bank7_rdata_valid;
-reg [255:0] main_litedramcore_interface_wdata = 256'd0;
-reg [31:0] main_litedramcore_interface_wdata_we = 32'd0;
+reg  [255:0] main_litedramcore_interface_wdata = 256'd0;
+reg  [31:0] main_litedramcore_interface_wdata_we = 32'd0;
 wire [255:0] main_litedramcore_interface_rdata;
-reg [14:0] main_litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg main_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p0_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p0_we_n = 1'd1;
 wire main_litedramcore_dfi_p0_cke;
 wire main_litedramcore_dfi_p0_odt;
 wire main_litedramcore_dfi_p0_reset_n;
-reg main_litedramcore_dfi_p0_act_n = 1'd1;
+reg  main_litedramcore_dfi_p0_act_n = 1'd1;
 wire [63:0] main_litedramcore_dfi_p0_wrdata;
-reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [7:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_dfi_p0_rddata;
 wire main_litedramcore_dfi_p0_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg main_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p1_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p1_we_n = 1'd1;
 wire main_litedramcore_dfi_p1_cke;
 wire main_litedramcore_dfi_p1_odt;
 wire main_litedramcore_dfi_p1_reset_n;
-reg main_litedramcore_dfi_p1_act_n = 1'd1;
+reg  main_litedramcore_dfi_p1_act_n = 1'd1;
 wire [63:0] main_litedramcore_dfi_p1_wrdata;
-reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [7:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_dfi_p1_rddata;
 wire main_litedramcore_dfi_p1_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p2_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg main_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p2_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p2_we_n = 1'd1;
 wire main_litedramcore_dfi_p2_cke;
 wire main_litedramcore_dfi_p2_odt;
 wire main_litedramcore_dfi_p2_reset_n;
-reg main_litedramcore_dfi_p2_act_n = 1'd1;
+reg  main_litedramcore_dfi_p2_act_n = 1'd1;
 wire [63:0] main_litedramcore_dfi_p2_wrdata;
-reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [7:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_dfi_p2_rddata;
 wire main_litedramcore_dfi_p2_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p3_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg main_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p3_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p3_we_n = 1'd1;
 wire main_litedramcore_dfi_p3_cke;
 wire main_litedramcore_dfi_p3_odt;
 wire main_litedramcore_dfi_p3_reset_n;
-reg main_litedramcore_dfi_p3_act_n = 1'd1;
+reg  main_litedramcore_dfi_p3_act_n = 1'd1;
 wire [63:0] main_litedramcore_dfi_p3_wrdata;
-reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [7:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [63:0] main_litedramcore_dfi_p3_rddata;
 wire main_litedramcore_dfi_p3_rddata_valid;
-reg main_litedramcore_cmd_valid = 1'd0;
-reg main_litedramcore_cmd_ready = 1'd0;
-reg main_litedramcore_cmd_last = 1'd0;
-reg [14:0] main_litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg main_litedramcore_cmd_payload_cas = 1'd0;
-reg main_litedramcore_cmd_payload_ras = 1'd0;
-reg main_litedramcore_cmd_payload_we = 1'd0;
-reg main_litedramcore_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_cmd_valid = 1'd0;
+reg  main_litedramcore_cmd_ready = 1'd0;
+reg  main_litedramcore_cmd_last = 1'd0;
+reg  [14:0] main_litedramcore_cmd_payload_a = 15'd0;
+reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg  main_litedramcore_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_cmd_payload_we = 1'd0;
+reg  main_litedramcore_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_cmd_payload_is_write = 1'd0;
 wire main_litedramcore_wants_refresh;
 wire main_litedramcore_wants_zqcs;
 wire main_litedramcore_timer_wait;
 wire main_litedramcore_timer_done0;
 wire [9:0] main_litedramcore_timer_count0;
 wire main_litedramcore_timer_done1;
-reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
 wire main_litedramcore_postponer_req_i;
-reg main_litedramcore_postponer_req_o = 1'd0;
-reg main_litedramcore_postponer_count = 1'd0;
-reg main_litedramcore_sequencer_start0 = 1'd0;
+reg  main_litedramcore_postponer_req_o = 1'd0;
+reg  main_litedramcore_postponer_count = 1'd0;
+reg  main_litedramcore_sequencer_start0 = 1'd0;
 wire main_litedramcore_sequencer_done0;
 wire main_litedramcore_sequencer_start1;
-reg main_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg main_litedramcore_sequencer_count = 1'd0;
+reg  main_litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
+reg  main_litedramcore_sequencer_count = 1'd0;
 wire main_litedramcore_zqcs_timer_wait;
 wire main_litedramcore_zqcs_timer_done0;
 wire [26:0] main_litedramcore_zqcs_timer_count0;
 wire main_litedramcore_zqcs_timer_done1;
-reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg main_litedramcore_zqcs_executer_start = 1'd0;
-reg main_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  main_litedramcore_zqcs_executer_start = 1'd0;
+reg  main_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
 wire main_litedramcore_bankmachine0_req_valid;
 wire main_litedramcore_bankmachine0_req_ready;
 wire main_litedramcore_bankmachine0_req_we;
 wire [21:0] main_litedramcore_bankmachine0_req_addr;
 wire main_litedramcore_bankmachine0_req_lock;
-reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine0_refresh_req;
-reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -1128,11 +1150,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -1153,51 +1175,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine0_row = 15'd0;
-reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine0_row = 15'd0;
+reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
 wire main_litedramcore_bankmachine0_row_hit;
-reg main_litedramcore_bankmachine0_row_open = 1'd0;
-reg main_litedramcore_bankmachine0_row_close = 1'd0;
-reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine0_row_open = 1'd0;
+reg  main_litedramcore_bankmachine0_row_close = 1'd0;
+reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine1_req_valid;
 wire main_litedramcore_bankmachine1_req_ready;
 wire main_litedramcore_bankmachine1_req_we;
 wire [21:0] main_litedramcore_bankmachine1_req_addr;
 wire main_litedramcore_bankmachine1_req_lock;
-reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine1_refresh_req;
-reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -1212,11 +1234,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -1237,51 +1259,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine1_row = 15'd0;
-reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine1_row = 15'd0;
+reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
 wire main_litedramcore_bankmachine1_row_hit;
-reg main_litedramcore_bankmachine1_row_open = 1'd0;
-reg main_litedramcore_bankmachine1_row_close = 1'd0;
-reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine1_row_open = 1'd0;
+reg  main_litedramcore_bankmachine1_row_close = 1'd0;
+reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine2_req_valid;
 wire main_litedramcore_bankmachine2_req_ready;
 wire main_litedramcore_bankmachine2_req_we;
 wire [21:0] main_litedramcore_bankmachine2_req_addr;
 wire main_litedramcore_bankmachine2_req_lock;
-reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine2_refresh_req;
-reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -1296,11 +1318,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1321,51 +1343,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine2_row = 15'd0;
-reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine2_row = 15'd0;
+reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
 wire main_litedramcore_bankmachine2_row_hit;
-reg main_litedramcore_bankmachine2_row_open = 1'd0;
-reg main_litedramcore_bankmachine2_row_close = 1'd0;
-reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine2_row_open = 1'd0;
+reg  main_litedramcore_bankmachine2_row_close = 1'd0;
+reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine3_req_valid;
 wire main_litedramcore_bankmachine3_req_ready;
 wire main_litedramcore_bankmachine3_req_we;
 wire [21:0] main_litedramcore_bankmachine3_req_addr;
 wire main_litedramcore_bankmachine3_req_lock;
-reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine3_refresh_req;
-reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1380,11 +1402,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1405,51 +1427,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine3_row = 15'd0;
-reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine3_row = 15'd0;
+reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
 wire main_litedramcore_bankmachine3_row_hit;
-reg main_litedramcore_bankmachine3_row_open = 1'd0;
-reg main_litedramcore_bankmachine3_row_close = 1'd0;
-reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine3_row_open = 1'd0;
+reg  main_litedramcore_bankmachine3_row_close = 1'd0;
+reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine4_req_valid;
 wire main_litedramcore_bankmachine4_req_ready;
 wire main_litedramcore_bankmachine4_req_we;
 wire [21:0] main_litedramcore_bankmachine4_req_addr;
 wire main_litedramcore_bankmachine4_req_lock;
-reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine4_refresh_req;
-reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1464,11 +1486,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1489,51 +1511,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine4_row = 15'd0;
-reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine4_row = 15'd0;
+reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
 wire main_litedramcore_bankmachine4_row_hit;
-reg main_litedramcore_bankmachine4_row_open = 1'd0;
-reg main_litedramcore_bankmachine4_row_close = 1'd0;
-reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine4_row_open = 1'd0;
+reg  main_litedramcore_bankmachine4_row_close = 1'd0;
+reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine5_req_valid;
 wire main_litedramcore_bankmachine5_req_ready;
 wire main_litedramcore_bankmachine5_req_we;
 wire [21:0] main_litedramcore_bankmachine5_req_addr;
 wire main_litedramcore_bankmachine5_req_lock;
-reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine5_refresh_req;
-reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1548,11 +1570,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1573,51 +1595,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine5_row = 15'd0;
-reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine5_row = 15'd0;
+reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
 wire main_litedramcore_bankmachine5_row_hit;
-reg main_litedramcore_bankmachine5_row_open = 1'd0;
-reg main_litedramcore_bankmachine5_row_close = 1'd0;
-reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine5_row_open = 1'd0;
+reg  main_litedramcore_bankmachine5_row_close = 1'd0;
+reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine6_req_valid;
 wire main_litedramcore_bankmachine6_req_ready;
 wire main_litedramcore_bankmachine6_req_we;
 wire [21:0] main_litedramcore_bankmachine6_req_addr;
 wire main_litedramcore_bankmachine6_req_lock;
-reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine6_refresh_req;
-reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1632,11 +1654,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1657,51 +1679,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine6_row = 15'd0;
-reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine6_row = 15'd0;
+reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
 wire main_litedramcore_bankmachine6_row_hit;
-reg main_litedramcore_bankmachine6_row_open = 1'd0;
-reg main_litedramcore_bankmachine6_row_close = 1'd0;
-reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine6_row_open = 1'd0;
+reg  main_litedramcore_bankmachine6_row_close = 1'd0;
+reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine7_req_valid;
 wire main_litedramcore_bankmachine7_req_ready;
 wire main_litedramcore_bankmachine7_req_we;
 wire [21:0] main_litedramcore_bankmachine7_req_addr;
 wire main_litedramcore_bankmachine7_req_lock;
-reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine7_refresh_req;
-reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1716,11 +1738,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1741,107 +1763,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine7_row = 15'd0;
-reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine7_row = 15'd0;
+reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
 wire main_litedramcore_bankmachine7_row_hit;
-reg main_litedramcore_bankmachine7_row_open = 1'd0;
-reg main_litedramcore_bankmachine7_row_close = 1'd0;
-reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine7_row_open = 1'd0;
+reg  main_litedramcore_bankmachine7_row_close = 1'd0;
+reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire main_litedramcore_ras_allowed;
 wire main_litedramcore_cas_allowed;
 wire [1:0] main_litedramcore_rdcmdphase;
 wire [1:0] main_litedramcore_wrcmdphase;
-reg main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_valid;
-reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire main_litedramcore_choose_cmd_cmd_payload_is_read;
 wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_cmd_request;
-reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
 wire main_litedramcore_choose_cmd_ce;
-reg main_litedramcore_choose_req_want_reads = 1'd0;
-reg main_litedramcore_choose_req_want_writes = 1'd0;
-reg main_litedramcore_choose_req_want_cmds = 1'd0;
-reg main_litedramcore_choose_req_want_activates = 1'd0;
+reg  main_litedramcore_choose_req_want_reads = 1'd0;
+reg  main_litedramcore_choose_req_want_writes = 1'd0;
+reg  main_litedramcore_choose_req_want_cmds = 1'd0;
+reg  main_litedramcore_choose_req_want_activates = 1'd0;
 wire main_litedramcore_choose_req_cmd_valid;
-reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [14:0] main_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_req_cmd_payload_is_cmd;
 wire main_litedramcore_choose_req_cmd_payload_is_read;
 wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_req_request;
-reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
 wire main_litedramcore_choose_req_ce;
-reg [14:0] main_litedramcore_nop_a = 15'd0;
-reg [2:0] main_litedramcore_nop_ba = 3'd0;
-reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg main_litedramcore_steerer0 = 1'd1;
-reg main_litedramcore_steerer1 = 1'd1;
-reg main_litedramcore_steerer2 = 1'd1;
-reg main_litedramcore_steerer3 = 1'd1;
-reg main_litedramcore_steerer4 = 1'd1;
-reg main_litedramcore_steerer5 = 1'd1;
-reg main_litedramcore_steerer6 = 1'd1;
-reg main_litedramcore_steerer7 = 1'd1;
+reg  [14:0] main_litedramcore_nop_a = 15'd0;
+reg  [2:0] main_litedramcore_nop_ba = 3'd0;
+reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg  main_litedramcore_steerer0 = 1'd1;
+reg  main_litedramcore_steerer1 = 1'd1;
+reg  main_litedramcore_steerer2 = 1'd1;
+reg  main_litedramcore_steerer3 = 1'd1;
+reg  main_litedramcore_steerer4 = 1'd1;
+reg  main_litedramcore_steerer5 = 1'd1;
+reg  main_litedramcore_steerer6 = 1'd1;
+reg  main_litedramcore_steerer7 = 1'd1;
 wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
-reg main_litedramcore_trrdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
+reg  main_litedramcore_trrdcon_count = 1'd0;
 wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] main_litedramcore_tfawcon_count;
-reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
 wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
-reg main_litedramcore_tccdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
+reg  main_litedramcore_tccdcon_count = 1'd0;
 wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
 wire main_litedramcore_read_available;
 wire main_litedramcore_write_available;
-reg main_litedramcore_en0 = 1'd0;
+reg  main_litedramcore_en0 = 1'd0;
 wire main_litedramcore_max_time0;
-reg [4:0] main_litedramcore_time0 = 5'd0;
-reg main_litedramcore_en1 = 1'd0;
+reg  [4:0] main_litedramcore_time0 = 5'd0;
+reg  main_litedramcore_en1 = 1'd0;
 wire main_litedramcore_max_time1;
-reg [3:0] main_litedramcore_time1 = 4'd0;
+reg  [3:0] main_litedramcore_time1 = 4'd0;
 wire main_litedramcore_go_to_refresh;
-reg main_init_done_storage = 1'd0;
-reg main_init_done_re = 1'd0;
-reg main_init_error_storage = 1'd0;
-reg main_init_error_re = 1'd0;
+reg  main_init_done_storage = 1'd0;
+reg  main_init_done_re = 1'd0;
+reg  main_init_error_storage = 1'd0;
+reg  main_init_error_re = 1'd0;
 wire [29:0] main_wb_bus_adr;
 wire [31:0] main_wb_bus_dat_w;
 wire [31:0] main_wb_bus_dat_r;
@@ -1853,6 +1875,7 @@ wire main_wb_bus_we;
 wire [2:0] main_wb_bus_cti;
 wire [1:0] main_wb_bus_bte;
 wire main_wb_bus_err;
+wire main_user_enable;
 wire main_user_port_cmd_valid;
 wire main_user_port_cmd_ready;
 wire main_user_port_cmd_payload_we;
@@ -1873,26 +1896,26 @@ wire builder_reset5;
 wire builder_reset6;
 wire builder_reset7;
 wire builder_pll_fb;
-reg [1:0] builder_refresher_state = 2'd0;
-reg [1:0] builder_refresher_next_state = 2'd0;
-reg [3:0] builder_bankmachine0_state = 4'd0;
-reg [3:0] builder_bankmachine0_next_state = 4'd0;
-reg [3:0] builder_bankmachine1_state = 4'd0;
-reg [3:0] builder_bankmachine1_next_state = 4'd0;
-reg [3:0] builder_bankmachine2_state = 4'd0;
-reg [3:0] builder_bankmachine2_next_state = 4'd0;
-reg [3:0] builder_bankmachine3_state = 4'd0;
-reg [3:0] builder_bankmachine3_next_state = 4'd0;
-reg [3:0] builder_bankmachine4_state = 4'd0;
-reg [3:0] builder_bankmachine4_next_state = 4'd0;
-reg [3:0] builder_bankmachine5_state = 4'd0;
-reg [3:0] builder_bankmachine5_next_state = 4'd0;
-reg [3:0] builder_bankmachine6_state = 4'd0;
-reg [3:0] builder_bankmachine6_next_state = 4'd0;
-reg [3:0] builder_bankmachine7_state = 4'd0;
-reg [3:0] builder_bankmachine7_next_state = 4'd0;
-reg [3:0] builder_multiplexer_state = 4'd0;
-reg [3:0] builder_multiplexer_next_state = 4'd0;
+reg  [1:0] builder_refresher_state = 2'd0;
+reg  [1:0] builder_refresher_next_state = 2'd0;
+reg  [3:0] builder_bankmachine0_state = 4'd0;
+reg  [3:0] builder_bankmachine0_next_state = 4'd0;
+reg  [3:0] builder_bankmachine1_state = 4'd0;
+reg  [3:0] builder_bankmachine1_next_state = 4'd0;
+reg  [3:0] builder_bankmachine2_state = 4'd0;
+reg  [3:0] builder_bankmachine2_next_state = 4'd0;
+reg  [3:0] builder_bankmachine3_state = 4'd0;
+reg  [3:0] builder_bankmachine3_next_state = 4'd0;
+reg  [3:0] builder_bankmachine4_state = 4'd0;
+reg  [3:0] builder_bankmachine4_next_state = 4'd0;
+reg  [3:0] builder_bankmachine5_state = 4'd0;
+reg  [3:0] builder_bankmachine5_next_state = 4'd0;
+reg  [3:0] builder_bankmachine6_state = 4'd0;
+reg  [3:0] builder_bankmachine6_next_state = 4'd0;
+reg  [3:0] builder_bankmachine7_state = 4'd0;
+reg  [3:0] builder_bankmachine7_next_state = 4'd0;
+reg  [3:0] builder_multiplexer_state = 4'd0;
+reg  [3:0] builder_multiplexer_next_state = 4'd0;
 wire builder_roundrobin0_request;
 wire builder_roundrobin0_grant;
 wire builder_roundrobin0_ce;
@@ -1917,493 +1940,285 @@ wire builder_roundrobin6_ce;
 wire builder_roundrobin7_request;
 wire builder_roundrobin7_grant;
 wire builder_roundrobin7_ce;
-reg builder_locked0 = 1'd0;
-reg builder_locked1 = 1'd0;
-reg builder_locked2 = 1'd0;
-reg builder_locked3 = 1'd0;
-reg builder_locked4 = 1'd0;
-reg builder_locked5 = 1'd0;
-reg builder_locked6 = 1'd0;
-reg builder_locked7 = 1'd0;
-reg builder_new_master_wdata_ready0 = 1'd0;
-reg builder_new_master_wdata_ready1 = 1'd0;
-reg builder_new_master_rdata_valid0 = 1'd0;
-reg builder_new_master_rdata_valid1 = 1'd0;
-reg builder_new_master_rdata_valid2 = 1'd0;
-reg builder_new_master_rdata_valid3 = 1'd0;
-reg builder_new_master_rdata_valid4 = 1'd0;
-reg builder_new_master_rdata_valid5 = 1'd0;
-reg builder_new_master_rdata_valid6 = 1'd0;
-reg builder_new_master_rdata_valid7 = 1'd0;
-reg builder_new_master_rdata_valid8 = 1'd0;
-reg [13:0] builder_litedramcore_adr = 14'd0;
-reg builder_litedramcore_we = 1'd0;
-reg [7:0] builder_litedramcore_dat_w = 8'd0;
-wire [7:0] builder_litedramcore_dat_r;
+reg  builder_locked0 = 1'd0;
+reg  builder_locked1 = 1'd0;
+reg  builder_locked2 = 1'd0;
+reg  builder_locked3 = 1'd0;
+reg  builder_locked4 = 1'd0;
+reg  builder_locked5 = 1'd0;
+reg  builder_locked6 = 1'd0;
+reg  builder_locked7 = 1'd0;
+reg  builder_new_master_wdata_ready0 = 1'd0;
+reg  builder_new_master_wdata_ready1 = 1'd0;
+reg  builder_new_master_rdata_valid0 = 1'd0;
+reg  builder_new_master_rdata_valid1 = 1'd0;
+reg  builder_new_master_rdata_valid2 = 1'd0;
+reg  builder_new_master_rdata_valid3 = 1'd0;
+reg  builder_new_master_rdata_valid4 = 1'd0;
+reg  builder_new_master_rdata_valid5 = 1'd0;
+reg  builder_new_master_rdata_valid6 = 1'd0;
+reg  builder_new_master_rdata_valid7 = 1'd0;
+reg  builder_new_master_rdata_valid8 = 1'd0;
+reg  [13:0] builder_litedramcore_adr = 14'd0;
+reg  builder_litedramcore_we = 1'd0;
+reg  [31:0] builder_litedramcore_dat_w = 32'd0;
+wire [31:0] builder_litedramcore_dat_r;
 wire [29:0] builder_litedramcore_wishbone_adr;
 wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] builder_litedramcore_wishbone_sel;
 wire builder_litedramcore_wishbone_cyc;
 wire builder_litedramcore_wishbone_stb;
-reg builder_litedramcore_wishbone_ack = 1'd0;
+reg  builder_litedramcore_wishbone_ack = 1'd0;
 wire builder_litedramcore_wishbone_we;
 wire [2:0] builder_litedramcore_wishbone_cti;
 wire [1:0] builder_litedramcore_wishbone_bte;
-reg builder_litedramcore_wishbone_err = 1'd0;
+reg  builder_litedramcore_wishbone_err = 1'd0;
 wire [13:0] builder_interface0_bank_bus_adr;
 wire builder_interface0_bank_bus_we;
-wire [7:0] builder_interface0_bank_bus_dat_w;
-reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
-reg builder_csrbank0_init_done0_re = 1'd0;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank0_init_done0_re = 1'd0;
 wire builder_csrbank0_init_done0_r;
-reg builder_csrbank0_init_done0_we = 1'd0;
+reg  builder_csrbank0_init_done0_we = 1'd0;
 wire builder_csrbank0_init_done0_w;
-reg builder_csrbank0_init_error0_re = 1'd0;
+reg  builder_csrbank0_init_error0_re = 1'd0;
 wire builder_csrbank0_init_error0_r;
-reg builder_csrbank0_init_error0_we = 1'd0;
+reg  builder_csrbank0_init_error0_we = 1'd0;
 wire builder_csrbank0_init_error0_w;
 wire builder_csrbank0_sel;
 wire [13:0] builder_interface1_bank_bus_adr;
 wire builder_interface1_bank_bus_we;
-wire [7:0] builder_interface1_bank_bus_dat_w;
-reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
-reg builder_csrbank1_rst0_re = 1'd0;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank1_rst0_re = 1'd0;
 wire builder_csrbank1_rst0_r;
-reg builder_csrbank1_rst0_we = 1'd0;
+reg  builder_csrbank1_rst0_we = 1'd0;
 wire builder_csrbank1_rst0_w;
-reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg builder_csrbank1_wlevel_en0_re = 1'd0;
+reg  builder_csrbank1_wlevel_en0_re = 1'd0;
 wire builder_csrbank1_wlevel_en0_r;
-reg builder_csrbank1_wlevel_en0_we = 1'd0;
+reg  builder_csrbank1_wlevel_en0_we = 1'd0;
 wire builder_csrbank1_wlevel_en0_w;
-reg builder_csrbank1_dly_sel0_re = 1'd0;
+reg  builder_csrbank1_dly_sel0_re = 1'd0;
 wire [3:0] builder_csrbank1_dly_sel0_r;
-reg builder_csrbank1_dly_sel0_we = 1'd0;
+reg  builder_csrbank1_dly_sel0_we = 1'd0;
 wire [3:0] builder_csrbank1_dly_sel0_w;
-reg builder_csrbank1_rdphase0_re = 1'd0;
+reg  builder_csrbank1_rdphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_r;
-reg builder_csrbank1_rdphase0_we = 1'd0;
+reg  builder_csrbank1_rdphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_w;
-reg builder_csrbank1_wrphase0_re = 1'd0;
+reg  builder_csrbank1_wrphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_r;
-reg builder_csrbank1_wrphase0_we = 1'd0;
+reg  builder_csrbank1_wrphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_w;
 wire builder_csrbank1_sel;
 wire [13:0] builder_interface2_bank_bus_adr;
 wire builder_interface2_bank_bus_we;
-wire [7:0] builder_interface2_bank_bus_dat_w;
-reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
-reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank2_dfii_control0_re = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_r;
-reg builder_csrbank2_dfii_control0_we = 1'd0;
+reg  builder_csrbank2_dfii_control0_we = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_w;
-reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi0_address1_r;
-reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi0_address1_w;
-reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
-reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
-reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi0_address0_r;
+reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi0_address0_w;
+reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg builder_csrbank2_dfii_pi0_wrdata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_r;
-reg builder_csrbank2_dfii_pi0_wrdata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_w;
-reg builder_csrbank2_dfii_pi0_wrdata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_r;
-reg builder_csrbank2_dfii_pi0_wrdata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_w;
-reg builder_csrbank2_dfii_pi0_wrdata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_r;
-reg builder_csrbank2_dfii_pi0_wrdata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_w;
-reg builder_csrbank2_dfii_pi0_wrdata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_r;
-reg builder_csrbank2_dfii_pi0_wrdata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_w;
-reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
-reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
-reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
-reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
-reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg builder_csrbank2_dfii_pi0_rddata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata7_r;
-reg builder_csrbank2_dfii_pi0_rddata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata7_w;
-reg builder_csrbank2_dfii_pi0_rddata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata6_r;
-reg builder_csrbank2_dfii_pi0_rddata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata6_w;
-reg builder_csrbank2_dfii_pi0_rddata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata5_r;
-reg builder_csrbank2_dfii_pi0_rddata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata5_w;
-reg builder_csrbank2_dfii_pi0_rddata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata4_r;
-reg builder_csrbank2_dfii_pi0_rddata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata4_w;
-reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
-reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
-reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
-reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
-reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_r;
+reg  builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_w;
+reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg  builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata1_r;
+reg  builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata1_w;
+reg  builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata0_r;
+reg  builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata0_w;
+reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi1_address1_r;
-reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi1_address1_w;
-reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
-reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
-reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi1_address0_r;
+reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi1_address0_w;
+reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg builder_csrbank2_dfii_pi1_wrdata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_r;
-reg builder_csrbank2_dfii_pi1_wrdata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_w;
-reg builder_csrbank2_dfii_pi1_wrdata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_r;
-reg builder_csrbank2_dfii_pi1_wrdata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_w;
-reg builder_csrbank2_dfii_pi1_wrdata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_r;
-reg builder_csrbank2_dfii_pi1_wrdata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_w;
-reg builder_csrbank2_dfii_pi1_wrdata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_r;
-reg builder_csrbank2_dfii_pi1_wrdata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_w;
-reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
-reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
-reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
-reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
-reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg builder_csrbank2_dfii_pi1_rddata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata7_r;
-reg builder_csrbank2_dfii_pi1_rddata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata7_w;
-reg builder_csrbank2_dfii_pi1_rddata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata6_r;
-reg builder_csrbank2_dfii_pi1_rddata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata6_w;
-reg builder_csrbank2_dfii_pi1_rddata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata5_r;
-reg builder_csrbank2_dfii_pi1_rddata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata5_w;
-reg builder_csrbank2_dfii_pi1_rddata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata4_r;
-reg builder_csrbank2_dfii_pi1_rddata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata4_w;
-reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
-reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
-reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
-reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
-reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_r;
+reg  builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_w;
+reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg  builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata1_r;
+reg  builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata1_w;
+reg  builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata0_r;
+reg  builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata0_w;
+reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi2_address1_r;
-reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi2_address1_w;
-reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
-reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
-reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi2_address0_r;
+reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi2_address0_w;
+reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg builder_csrbank2_dfii_pi2_wrdata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_r;
-reg builder_csrbank2_dfii_pi2_wrdata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_w;
-reg builder_csrbank2_dfii_pi2_wrdata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_r;
-reg builder_csrbank2_dfii_pi2_wrdata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_w;
-reg builder_csrbank2_dfii_pi2_wrdata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_r;
-reg builder_csrbank2_dfii_pi2_wrdata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_w;
-reg builder_csrbank2_dfii_pi2_wrdata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_r;
-reg builder_csrbank2_dfii_pi2_wrdata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_w;
-reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
-reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
-reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
-reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
-reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg builder_csrbank2_dfii_pi2_rddata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata7_r;
-reg builder_csrbank2_dfii_pi2_rddata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata7_w;
-reg builder_csrbank2_dfii_pi2_rddata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata6_r;
-reg builder_csrbank2_dfii_pi2_rddata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata6_w;
-reg builder_csrbank2_dfii_pi2_rddata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata5_r;
-reg builder_csrbank2_dfii_pi2_rddata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata5_w;
-reg builder_csrbank2_dfii_pi2_rddata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata4_r;
-reg builder_csrbank2_dfii_pi2_rddata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata4_w;
-reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
-reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
-reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
-reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
-reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_r;
+reg  builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_w;
+reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg  builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata1_r;
+reg  builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata1_w;
+reg  builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata0_r;
+reg  builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi3_address1_r;
-reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi3_address1_w;
-reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
-reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
-reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi3_address0_r;
+reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi3_address0_w;
+reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg builder_csrbank2_dfii_pi3_wrdata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_r;
-reg builder_csrbank2_dfii_pi3_wrdata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_w;
-reg builder_csrbank2_dfii_pi3_wrdata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_r;
-reg builder_csrbank2_dfii_pi3_wrdata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_w;
-reg builder_csrbank2_dfii_pi3_wrdata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_r;
-reg builder_csrbank2_dfii_pi3_wrdata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_w;
-reg builder_csrbank2_dfii_pi3_wrdata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_r;
-reg builder_csrbank2_dfii_pi3_wrdata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_w;
-reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
-reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
-reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
-reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
-reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg builder_csrbank2_dfii_pi3_rddata7_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata7_r;
-reg builder_csrbank2_dfii_pi3_rddata7_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata7_w;
-reg builder_csrbank2_dfii_pi3_rddata6_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata6_r;
-reg builder_csrbank2_dfii_pi3_rddata6_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata6_w;
-reg builder_csrbank2_dfii_pi3_rddata5_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata5_r;
-reg builder_csrbank2_dfii_pi3_rddata5_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata5_w;
-reg builder_csrbank2_dfii_pi3_rddata4_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata4_r;
-reg builder_csrbank2_dfii_pi3_rddata4_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata4_w;
-reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
-reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
-reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
-reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
-reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_r;
+reg  builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_w;
+reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg  builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata1_r;
+reg  builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata1_w;
+reg  builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata0_r;
+reg  builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata0_w;
 wire builder_csrbank2_sel;
 wire [13:0] builder_csr_interconnect_adr;
 wire builder_csr_interconnect_we;
-wire [7:0] builder_csr_interconnect_dat_w;
-wire [7:0] builder_csr_interconnect_dat_r;
-reg [1:0] builder_state = 2'd0;
-reg [1:0] builder_next_state = 2'd0;
-reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
-reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg builder_litedramcore_we_next_value2 = 1'd0;
-reg builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg builder_rhs_array_muxed0 = 1'd0;
-reg [14:0] builder_rhs_array_muxed1 = 15'd0;
-reg [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg builder_rhs_array_muxed3 = 1'd0;
-reg builder_rhs_array_muxed4 = 1'd0;
-reg builder_rhs_array_muxed5 = 1'd0;
-reg builder_t_array_muxed0 = 1'd0;
-reg builder_t_array_muxed1 = 1'd0;
-reg builder_t_array_muxed2 = 1'd0;
-reg builder_rhs_array_muxed6 = 1'd0;
-reg [14:0] builder_rhs_array_muxed7 = 15'd0;
-reg [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg builder_rhs_array_muxed9 = 1'd0;
-reg builder_rhs_array_muxed10 = 1'd0;
-reg builder_rhs_array_muxed11 = 1'd0;
-reg builder_t_array_muxed3 = 1'd0;
-reg builder_t_array_muxed4 = 1'd0;
-reg builder_t_array_muxed5 = 1'd0;
-reg [21:0] builder_rhs_array_muxed12 = 22'd0;
-reg builder_rhs_array_muxed13 = 1'd0;
-reg builder_rhs_array_muxed14 = 1'd0;
-reg [21:0] builder_rhs_array_muxed15 = 22'd0;
-reg builder_rhs_array_muxed16 = 1'd0;
-reg builder_rhs_array_muxed17 = 1'd0;
-reg [21:0] builder_rhs_array_muxed18 = 22'd0;
-reg builder_rhs_array_muxed19 = 1'd0;
-reg builder_rhs_array_muxed20 = 1'd0;
-reg [21:0] builder_rhs_array_muxed21 = 22'd0;
-reg builder_rhs_array_muxed22 = 1'd0;
-reg builder_rhs_array_muxed23 = 1'd0;
-reg [21:0] builder_rhs_array_muxed24 = 22'd0;
-reg builder_rhs_array_muxed25 = 1'd0;
-reg builder_rhs_array_muxed26 = 1'd0;
-reg [21:0] builder_rhs_array_muxed27 = 22'd0;
-reg builder_rhs_array_muxed28 = 1'd0;
-reg builder_rhs_array_muxed29 = 1'd0;
-reg [21:0] builder_rhs_array_muxed30 = 22'd0;
-reg builder_rhs_array_muxed31 = 1'd0;
-reg builder_rhs_array_muxed32 = 1'd0;
-reg [21:0] builder_rhs_array_muxed33 = 22'd0;
-reg builder_rhs_array_muxed34 = 1'd0;
-reg builder_rhs_array_muxed35 = 1'd0;
-reg [2:0] builder_array_muxed0 = 3'd0;
-reg [14:0] builder_array_muxed1 = 15'd0;
-reg builder_array_muxed2 = 1'd0;
-reg builder_array_muxed3 = 1'd0;
-reg builder_array_muxed4 = 1'd0;
-reg builder_array_muxed5 = 1'd0;
-reg builder_array_muxed6 = 1'd0;
-reg [2:0] builder_array_muxed7 = 3'd0;
-reg [14:0] builder_array_muxed8 = 15'd0;
-reg builder_array_muxed9 = 1'd0;
-reg builder_array_muxed10 = 1'd0;
-reg builder_array_muxed11 = 1'd0;
-reg builder_array_muxed12 = 1'd0;
-reg builder_array_muxed13 = 1'd0;
-reg [2:0] builder_array_muxed14 = 3'd0;
-reg [14:0] builder_array_muxed15 = 15'd0;
-reg builder_array_muxed16 = 1'd0;
-reg builder_array_muxed17 = 1'd0;
-reg builder_array_muxed18 = 1'd0;
-reg builder_array_muxed19 = 1'd0;
-reg builder_array_muxed20 = 1'd0;
-reg [2:0] builder_array_muxed21 = 3'd0;
-reg [14:0] builder_array_muxed22 = 15'd0;
-reg builder_array_muxed23 = 1'd0;
-reg builder_array_muxed24 = 1'd0;
-reg builder_array_muxed25 = 1'd0;
-reg builder_array_muxed26 = 1'd0;
-reg builder_array_muxed27 = 1'd0;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg  [1:0] builder_state = 2'd0;
+reg  [1:0] builder_next_state = 2'd0;
+reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
+reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg  builder_litedramcore_we_next_value2 = 1'd0;
+reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg  builder_rhs_array_muxed0 = 1'd0;
+reg  [14:0] builder_rhs_array_muxed1 = 15'd0;
+reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg  builder_rhs_array_muxed3 = 1'd0;
+reg  builder_rhs_array_muxed4 = 1'd0;
+reg  builder_rhs_array_muxed5 = 1'd0;
+reg  builder_t_array_muxed0 = 1'd0;
+reg  builder_t_array_muxed1 = 1'd0;
+reg  builder_t_array_muxed2 = 1'd0;
+reg  builder_rhs_array_muxed6 = 1'd0;
+reg  [14:0] builder_rhs_array_muxed7 = 15'd0;
+reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg  builder_rhs_array_muxed9 = 1'd0;
+reg  builder_rhs_array_muxed10 = 1'd0;
+reg  builder_rhs_array_muxed11 = 1'd0;
+reg  builder_t_array_muxed3 = 1'd0;
+reg  builder_t_array_muxed4 = 1'd0;
+reg  builder_t_array_muxed5 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed12 = 22'd0;
+reg  builder_rhs_array_muxed13 = 1'd0;
+reg  builder_rhs_array_muxed14 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed15 = 22'd0;
+reg  builder_rhs_array_muxed16 = 1'd0;
+reg  builder_rhs_array_muxed17 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed18 = 22'd0;
+reg  builder_rhs_array_muxed19 = 1'd0;
+reg  builder_rhs_array_muxed20 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed21 = 22'd0;
+reg  builder_rhs_array_muxed22 = 1'd0;
+reg  builder_rhs_array_muxed23 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed24 = 22'd0;
+reg  builder_rhs_array_muxed25 = 1'd0;
+reg  builder_rhs_array_muxed26 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed27 = 22'd0;
+reg  builder_rhs_array_muxed28 = 1'd0;
+reg  builder_rhs_array_muxed29 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed30 = 22'd0;
+reg  builder_rhs_array_muxed31 = 1'd0;
+reg  builder_rhs_array_muxed32 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed33 = 22'd0;
+reg  builder_rhs_array_muxed34 = 1'd0;
+reg  builder_rhs_array_muxed35 = 1'd0;
+reg  [2:0] builder_array_muxed0 = 3'd0;
+reg  [14:0] builder_array_muxed1 = 15'd0;
+reg  builder_array_muxed2 = 1'd0;
+reg  builder_array_muxed3 = 1'd0;
+reg  builder_array_muxed4 = 1'd0;
+reg  builder_array_muxed5 = 1'd0;
+reg  builder_array_muxed6 = 1'd0;
+reg  [2:0] builder_array_muxed7 = 3'd0;
+reg  [14:0] builder_array_muxed8 = 15'd0;
+reg  builder_array_muxed9 = 1'd0;
+reg  builder_array_muxed10 = 1'd0;
+reg  builder_array_muxed11 = 1'd0;
+reg  builder_array_muxed12 = 1'd0;
+reg  builder_array_muxed13 = 1'd0;
+reg  [2:0] builder_array_muxed14 = 3'd0;
+reg  [14:0] builder_array_muxed15 = 15'd0;
+reg  builder_array_muxed16 = 1'd0;
+reg  builder_array_muxed17 = 1'd0;
+reg  builder_array_muxed18 = 1'd0;
+reg  builder_array_muxed19 = 1'd0;
+reg  builder_array_muxed20 = 1'd0;
+reg  [2:0] builder_array_muxed21 = 3'd0;
+reg  [14:0] builder_array_muxed22 = 15'd0;
+reg  builder_array_muxed23 = 1'd0;
+reg  builder_array_muxed24 = 1'd0;
+reg  builder_array_muxed25 = 1'd0;
+reg  builder_array_muxed26 = 1'd0;
+reg  builder_array_muxed27 = 1'd0;
 wire builder_xilinxasyncresetsynchronizerimpl0;
 wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl1;
@@ -2415,10 +2230,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3;
 wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl3_expr;
 
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
 assign init_done = main_init_done_storage;
 assign init_error = main_init_error_storage;
 assign main_wb_bus_adr = wb_ctrl_adr;
@@ -2434,18 +2249,19 @@ assign main_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
 assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
 assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
-assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
 assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = rst;
+assign main_reset = (rst | main_rst);
 assign pll_locked = main_locked;
 assign main_clkin = clk;
 assign iodelay_clk = main_clkout_buf0;
@@ -2454,10 +2270,6 @@ assign sys4x_clk = main_clkout_buf2;
 assign sys4x_dqs_clk = main_clkout_buf3;
 assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble);
 assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble);
-
-// synthesis translate_off
-reg dummy_d;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dfi_p0_rddata <= 64'd0;
 	main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0];
@@ -2524,14 +2336,7 @@ always @(*) begin
 	main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1];
 	main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0];
 	main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1];
-// synthesis translate_off
-	dummy_d = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_1;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dfi_p1_rddata <= 64'd0;
 	main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2];
@@ -2598,14 +2403,7 @@ always @(*) begin
 	main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3];
 	main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2];
 	main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3];
-// synthesis translate_off
-	dummy_d_1 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_2;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dfi_p2_rddata <= 64'd0;
 	main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4];
@@ -2672,14 +2470,7 @@ always @(*) begin
 	main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5];
 	main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4];
 	main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5];
-// synthesis translate_off
-	dummy_d_2 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_3;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dfi_p3_rddata <= 64'd0;
 	main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6];
@@ -2746,19 +2537,12 @@ always @(*) begin
 	main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7];
 	main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6];
 	main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7];
-// synthesis translate_off
-	dummy_d_3 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
 assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
 assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
 assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
 assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1;
-
-// synthesis translate_off
-reg dummy_d_4;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dqs_oe <= 1'd0;
 	if (main_k7ddrphy_wlevel_en_storage) begin
@@ -2766,16 +2550,9 @@ always @(*) begin
 	end else begin
 		main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe;
 	end
-// synthesis translate_off
-	dummy_d_4 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
 assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_dqspattern_o <= 8'd0;
 	main_k7ddrphy_dqspattern_o <= 7'd85;
@@ -2791,14 +2568,7 @@ always @(*) begin
 			main_k7ddrphy_dqspattern_o <= 1'd1;
 		end
 	end
-// synthesis translate_off
-	dummy_d_5 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip00 <= 8'd0;
 	case (main_k7ddrphy_bitslip0_value0)
@@ -2827,14 +2597,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_6 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip10 <= 8'd0;
 	case (main_k7ddrphy_bitslip1_value0)
@@ -2863,14 +2626,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_7 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip20 <= 8'd0;
 	case (main_k7ddrphy_bitslip2_value0)
@@ -2899,14 +2655,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_8 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip30 <= 8'd0;
 	case (main_k7ddrphy_bitslip3_value0)
@@ -2935,14 +2684,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_9 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip01 <= 8'd0;
 	case (main_k7ddrphy_bitslip0_value1)
@@ -2971,14 +2713,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_10 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip11 <= 8'd0;
 	case (main_k7ddrphy_bitslip1_value1)
@@ -3007,14 +2742,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_11 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip21 <= 8'd0;
 	case (main_k7ddrphy_bitslip2_value1)
@@ -3043,14 +2771,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_12 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip31 <= 8'd0;
 	case (main_k7ddrphy_bitslip3_value1)
@@ -3079,14 +2800,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_13 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip02 <= 8'd0;
 	case (main_k7ddrphy_bitslip0_value2)
@@ -3115,14 +2829,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_14 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip04 <= 8'd0;
 	case (main_k7ddrphy_bitslip0_value3)
@@ -3151,14 +2858,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_15 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip12 <= 8'd0;
 	case (main_k7ddrphy_bitslip1_value2)
@@ -3187,14 +2887,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_16 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip14 <= 8'd0;
 	case (main_k7ddrphy_bitslip1_value3)
@@ -3223,14 +2916,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_17 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_18;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip22 <= 8'd0;
 	case (main_k7ddrphy_bitslip2_value2)
@@ -3259,14 +2945,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_18 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_19;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip24 <= 8'd0;
 	case (main_k7ddrphy_bitslip2_value3)
@@ -3295,14 +2974,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_19 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_20;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip32 <= 8'd0;
 	case (main_k7ddrphy_bitslip3_value2)
@@ -3331,14 +3003,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_20 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_21;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip34 <= 8'd0;
 	case (main_k7ddrphy_bitslip3_value3)
@@ -3367,14 +3032,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_21 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip40 <= 8'd0;
 	case (main_k7ddrphy_bitslip4_value0)
@@ -3403,14 +3061,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_22 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip42 <= 8'd0;
 	case (main_k7ddrphy_bitslip4_value1)
@@ -3439,14 +3090,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_23 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip50 <= 8'd0;
 	case (main_k7ddrphy_bitslip5_value0)
@@ -3475,14 +3119,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_24 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip52 <= 8'd0;
 	case (main_k7ddrphy_bitslip5_value1)
@@ -3511,14 +3148,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_25 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_26;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip60 <= 8'd0;
 	case (main_k7ddrphy_bitslip6_value0)
@@ -3547,14 +3177,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_26 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip62 <= 8'd0;
 	case (main_k7ddrphy_bitslip6_value1)
@@ -3583,14 +3206,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_27 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip70 <= 8'd0;
 	case (main_k7ddrphy_bitslip7_value0)
@@ -3619,14 +3235,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_28 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip72 <= 8'd0;
 	case (main_k7ddrphy_bitslip7_value1)
@@ -3655,14 +3264,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_29 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip80 <= 8'd0;
 	case (main_k7ddrphy_bitslip8_value0)
@@ -3691,14 +3293,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_30 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_31;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip82 <= 8'd0;
 	case (main_k7ddrphy_bitslip8_value1)
@@ -3727,14 +3322,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_31 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_32;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip90 <= 8'd0;
 	case (main_k7ddrphy_bitslip9_value0)
@@ -3763,14 +3351,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_32 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_33;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip92 <= 8'd0;
 	case (main_k7ddrphy_bitslip9_value1)
@@ -3799,14 +3380,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_33 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_34;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip100 <= 8'd0;
 	case (main_k7ddrphy_bitslip10_value0)
@@ -3835,14 +3409,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_34 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_35;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip102 <= 8'd0;
 	case (main_k7ddrphy_bitslip10_value1)
@@ -3871,14 +3438,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_35 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_36;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip110 <= 8'd0;
 	case (main_k7ddrphy_bitslip11_value0)
@@ -3907,14 +3467,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_36 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_37;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip112 <= 8'd0;
 	case (main_k7ddrphy_bitslip11_value1)
@@ -3943,14 +3496,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_37 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_38;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip120 <= 8'd0;
 	case (main_k7ddrphy_bitslip12_value0)
@@ -3979,14 +3525,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_38 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip122 <= 8'd0;
 	case (main_k7ddrphy_bitslip12_value1)
@@ -4015,14 +3554,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_39 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_40;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip130 <= 8'd0;
 	case (main_k7ddrphy_bitslip13_value0)
@@ -4051,14 +3583,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_40 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_41;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip132 <= 8'd0;
 	case (main_k7ddrphy_bitslip13_value1)
@@ -4087,14 +3612,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_41 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_42;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip140 <= 8'd0;
 	case (main_k7ddrphy_bitslip14_value0)
@@ -4123,14 +3641,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_42 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_43;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip142 <= 8'd0;
 	case (main_k7ddrphy_bitslip14_value1)
@@ -4159,14 +3670,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_43 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_44;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip150 <= 8'd0;
 	case (main_k7ddrphy_bitslip15_value0)
@@ -4195,14 +3699,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_44 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_45;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip152 <= 8'd0;
 	case (main_k7ddrphy_bitslip15_value1)
@@ -4231,14 +3728,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_45 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_46;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip160 <= 8'd0;
 	case (main_k7ddrphy_bitslip16_value0)
@@ -4267,14 +3757,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_46 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_47;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip162 <= 8'd0;
 	case (main_k7ddrphy_bitslip16_value1)
@@ -4303,14 +3786,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_47 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_48;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip170 <= 8'd0;
 	case (main_k7ddrphy_bitslip17_value0)
@@ -4339,14 +3815,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_48 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_49;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip172 <= 8'd0;
 	case (main_k7ddrphy_bitslip17_value1)
@@ -4375,14 +3844,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_49 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_50;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip180 <= 8'd0;
 	case (main_k7ddrphy_bitslip18_value0)
@@ -4411,14 +3873,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_50 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_51;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip182 <= 8'd0;
 	case (main_k7ddrphy_bitslip18_value1)
@@ -4447,14 +3902,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_51 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_52;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip190 <= 8'd0;
 	case (main_k7ddrphy_bitslip19_value0)
@@ -4483,14 +3931,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_52 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_53;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip192 <= 8'd0;
 	case (main_k7ddrphy_bitslip19_value1)
@@ -4519,14 +3960,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_53 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_54;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip200 <= 8'd0;
 	case (main_k7ddrphy_bitslip20_value0)
@@ -4555,14 +3989,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_54 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_55;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip202 <= 8'd0;
 	case (main_k7ddrphy_bitslip20_value1)
@@ -4591,14 +4018,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_55 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_56;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip210 <= 8'd0;
 	case (main_k7ddrphy_bitslip21_value0)
@@ -4627,14 +4047,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_56 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_57;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip212 <= 8'd0;
 	case (main_k7ddrphy_bitslip21_value1)
@@ -4663,14 +4076,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_57 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_58;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip220 <= 8'd0;
 	case (main_k7ddrphy_bitslip22_value0)
@@ -4699,14 +4105,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_58 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_59;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip222 <= 8'd0;
 	case (main_k7ddrphy_bitslip22_value1)
@@ -4735,14 +4134,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_59 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_60;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip230 <= 8'd0;
 	case (main_k7ddrphy_bitslip23_value0)
@@ -4771,14 +4163,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_60 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_61;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip232 <= 8'd0;
 	case (main_k7ddrphy_bitslip23_value1)
@@ -4807,14 +4192,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_61 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_62;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip240 <= 8'd0;
 	case (main_k7ddrphy_bitslip24_value0)
@@ -4843,14 +4221,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_62 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_63;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip242 <= 8'd0;
 	case (main_k7ddrphy_bitslip24_value1)
@@ -4879,14 +4250,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_63 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_64;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip250 <= 8'd0;
 	case (main_k7ddrphy_bitslip25_value0)
@@ -4915,14 +4279,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_64 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_65;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip252 <= 8'd0;
 	case (main_k7ddrphy_bitslip25_value1)
@@ -4951,14 +4308,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_65 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_66;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip260 <= 8'd0;
 	case (main_k7ddrphy_bitslip26_value0)
@@ -4987,14 +4337,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_66 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_67;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip262 <= 8'd0;
 	case (main_k7ddrphy_bitslip26_value1)
@@ -5023,14 +4366,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_67 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_68;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip270 <= 8'd0;
 	case (main_k7ddrphy_bitslip27_value0)
@@ -5059,14 +4395,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_68 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_69;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip272 <= 8'd0;
 	case (main_k7ddrphy_bitslip27_value1)
@@ -5095,14 +4424,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_69 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_70;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip280 <= 8'd0;
 	case (main_k7ddrphy_bitslip28_value0)
@@ -5131,14 +4453,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_70 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_71;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip282 <= 8'd0;
 	case (main_k7ddrphy_bitslip28_value1)
@@ -5167,14 +4482,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_71 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_72;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip290 <= 8'd0;
 	case (main_k7ddrphy_bitslip29_value0)
@@ -5203,14 +4511,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_72 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_73;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip292 <= 8'd0;
 	case (main_k7ddrphy_bitslip29_value1)
@@ -5239,14 +4540,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_73 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_74;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip300 <= 8'd0;
 	case (main_k7ddrphy_bitslip30_value0)
@@ -5275,14 +4569,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_74 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip302 <= 8'd0;
 	case (main_k7ddrphy_bitslip30_value1)
@@ -5311,14 +4598,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_75 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_76;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip310 <= 8'd0;
 	case (main_k7ddrphy_bitslip31_value0)
@@ -5347,14 +4627,7 @@ always @(*) begin
 			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_76 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_77;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_bitslip312 <= 8'd0;
 	case (main_k7ddrphy_bitslip31_value1)
@@ -5383,9 +4656,6 @@ always @(*) begin
 			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_77 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
 assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
@@ -5515,10 +4785,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-
-// synthesis translate_off
-reg dummy_d_78;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_wrdata_mask <= 8'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	end else begin
+		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5526,14 +4800,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_78 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_79;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -5541,14 +4808,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
-// synthesis translate_off
-	dummy_d_79 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_80;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -5556,14 +4816,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
-// synthesis translate_off
-	dummy_d_80 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_81;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5571,14 +4824,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_81 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_82;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5586,14 +4832,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_82 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_83;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5601,28 +4840,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_83 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_84;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_84 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_85;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5630,28 +4855,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
-// synthesis translate_off
-	dummy_d_85 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_86;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_86 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_87;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5659,14 +4870,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
-// synthesis translate_off
-	dummy_d_87 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_88;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5674,14 +4878,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
-// synthesis translate_off
-	dummy_d_88 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_89;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5689,14 +4886,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5704,14 +4894,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_91;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 64'd0;
 	if (main_litedramcore_sel) begin
@@ -5719,28 +4902,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_91 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_92;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
-// synthesis translate_off
-	dummy_d_92 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_93;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5748,28 +4917,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_93 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_94;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_94 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_95;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 8'd0;
 	if (main_litedramcore_sel) begin
@@ -5777,14 +4932,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_95 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_96;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5792,14 +4940,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_96 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -5807,14 +4948,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
-// synthesis translate_off
-	dummy_d_97 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_98;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -5822,14 +4956,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_98 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_99;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5837,14 +4964,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_99 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_100;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5852,14 +4972,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5867,28 +4980,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_101 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_102;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_102 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_103;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5896,28 +4995,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
-// synthesis translate_off
-	dummy_d_103 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_104;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_104 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_105;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5925,14 +5010,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
-// synthesis translate_off
-	dummy_d_105 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_106;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5940,14 +5018,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
-// synthesis translate_off
-	dummy_d_106 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_107;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -5955,14 +5026,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_107 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_108;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -5970,14 +5034,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
-// synthesis translate_off
-	dummy_d_108 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata <= 64'd0;
 	if (main_litedramcore_sel) begin
@@ -5985,28 +5042,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_109 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_110;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
-// synthesis translate_off
-	dummy_d_110 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_111;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6014,28 +5057,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_111 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_112;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_112 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_113;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 8'd0;
 	if (main_litedramcore_sel) begin
@@ -6043,14 +5072,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_113 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6058,14 +5080,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_114 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_115;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -6073,14 +5088,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
-// synthesis translate_off
-	dummy_d_115 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_116;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -6088,14 +5096,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
-// synthesis translate_off
-	dummy_d_116 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_117;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6103,14 +5104,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_117 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_118;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6118,14 +5112,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_118 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_119;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6133,28 +5120,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_119 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_120 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6162,28 +5135,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
-// synthesis translate_off
-	dummy_d_121 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6191,14 +5150,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_123 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6206,14 +5158,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
-// synthesis translate_off
-	dummy_d_124 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6221,14 +5166,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_125 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_126;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6236,14 +5174,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
-// synthesis translate_off
-	dummy_d_126 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 64'd0;
 	if (main_litedramcore_sel) begin
@@ -6251,28 +5182,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_127 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
-// synthesis translate_off
-	dummy_d_128 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6280,28 +5197,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_129 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_130 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_131;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 8'd0;
 	if (main_litedramcore_sel) begin
@@ -6309,28 +5212,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_131 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_132;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
-	end
-// synthesis translate_off
-	dummy_d_132 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_133;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6338,43 +5220,22 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_133 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_134;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	main_litedramcore_master_p0_address <= 15'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
-// synthesis translate_off
-	dummy_d_134 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_135;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p0_address <= 15'd0;
+	main_litedramcore_inti_p1_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
+		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
-// synthesis translate_off
-	dummy_d_135 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_136;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -6382,14 +5243,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
-// synthesis translate_off
-	dummy_d_136 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_137;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6397,14 +5251,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_137 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_138;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6412,14 +5259,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_138 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_139;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6427,28 +5267,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_139 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_140 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_141;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6456,28 +5282,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_141 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_142;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_142 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_143;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6485,14 +5297,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
-// synthesis translate_off
-	dummy_d_143 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_144;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6500,14 +5312,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
-// synthesis translate_off
-	dummy_d_144 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6515,14 +5320,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_145 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -6530,14 +5328,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
-// synthesis translate_off
-	dummy_d_146 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 64'd0;
 	if (main_litedramcore_sel) begin
@@ -6545,14 +5336,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_147 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -6560,24 +5344,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 8'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
-	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
-	end
-// synthesis translate_off
-	dummy_d_149 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
 assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
@@ -6591,10 +5357,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-
-// synthesis translate_off
-reg dummy_d_150;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -6602,14 +5372,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_150 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_151;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -6617,14 +5380,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_151 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_152;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -6632,24 +5388,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_152 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_153;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
-	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_153 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
@@ -6657,10 +5395,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c
 assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
 assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_154;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -6668,14 +5410,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_154 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_155;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -6683,14 +5418,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_155 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_156;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -6698,24 +5426,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_156 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_157;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
-	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_157 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
@@ -6723,10 +5433,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c
 assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
 assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -6734,14 +5448,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_158 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_159;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -6749,14 +5456,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_159 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_160;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -6764,24 +5464,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_160 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
-	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_161 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
@@ -6789,25 +5471,22 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c
 assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
 assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
+	end
+end
+always @(*) begin
+	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
 		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
 		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_162 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -6815,14 +5494,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_163 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -6830,24 +5502,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_164 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_165;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
-	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_165 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
@@ -6924,10 +5578,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 &
 assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
 assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
 assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_166;
-// synthesis translate_on
 always @(*) begin
 	builder_refresher_next_state <= 2'd0;
 	builder_refresher_next_state <= builder_refresher_state;
@@ -6959,119 +5609,88 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_166 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_167;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
+	main_litedramcore_zqcs_executer_start <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+					main_litedramcore_zqcs_executer_start <= 1'd1;
+				end else begin
+				end
+			end
 		end
 		2'd3: begin
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_167 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_168;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
+	main_litedramcore_cmd_last <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
+					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
+				main_litedramcore_cmd_last <= 1'd1;
 			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_168 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_169;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
+	main_litedramcore_sequencer_start0 <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
+			if (main_litedramcore_cmd_ready) begin
+				main_litedramcore_sequencer_start0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
-				end else begin
-				end
-			end
 		end
 		2'd3: begin
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_169 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_170;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
+	main_litedramcore_cmd_valid <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
+					main_litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
+				main_litedramcore_cmd_valid <= 1'd0;
 			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_170 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
@@ -7087,10 +5706,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_171;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
@@ -7098,17 +5713,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_171 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
 assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
 assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_172;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
@@ -7116,9 +5724,6 @@ always @(*) begin
 			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_172 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
@@ -7137,10 +5742,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_173;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
@@ -7148,9 +5749,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_173 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
@@ -7160,10 +5758,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine0_next_state <= 4'd0;
 	builder_bankmachine0_next_state <= builder_bankmachine0_state;
@@ -7224,14 +5818,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_174 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_175;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7272,14 +5885,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_175 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7305,14 +5911,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_176 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7338,14 +5937,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_177 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_178;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7380,14 +5972,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_178 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7416,14 +6001,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_179 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7464,14 +6042,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_180 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7497,14 +6068,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7534,14 +6098,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_182 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_183;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7579,14 +6136,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_183 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_184;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7624,14 +6174,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_184 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_185;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7669,14 +6212,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_185 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_186;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7714,42 +6250,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
@@ -7765,10 +6265,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_188;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
@@ -7776,17 +6272,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_188 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
 assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
 assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_189;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
@@ -7794,9 +6283,6 @@ always @(*) begin
 			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_189 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
@@ -7815,10 +6301,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_190;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
@@ -7826,9 +6308,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_190 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
@@ -7838,10 +6317,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_191;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine1_next_state <= 4'd0;
 	builder_bankmachine1_next_state <= builder_bankmachine1_state;
@@ -7902,30 +6377,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_191 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7936,36 +6401,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_192 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_193;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7983,10 +6435,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
-							end
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7995,14 +6444,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_193 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_194;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8028,14 +6470,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_194 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_195;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8061,14 +6496,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_195 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8103,14 +6531,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_196 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8139,14 +6560,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_197 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8187,14 +6601,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_198 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_199;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8220,14 +6627,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_199 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_200;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8257,14 +6657,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_200 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_201;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8302,14 +6695,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_201 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_202;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8347,14 +6733,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_202 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_203;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -8392,16 +6771,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_203 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_204;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -8410,9 +6782,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8423,11 +6792,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_204 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
@@ -8443,10 +6824,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_205;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
@@ -8454,17 +6831,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_205 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
 assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_206;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
@@ -8472,9 +6842,6 @@ always @(*) begin
 			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_206 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
@@ -8493,10 +6860,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_207;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
@@ -8504,9 +6867,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_207 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
@@ -8516,10 +6876,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine2_next_state <= 4'd0;
 	builder_bankmachine2_next_state <= builder_bankmachine2_state;
@@ -8580,14 +6936,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_208 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_209;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8628,14 +7003,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_209 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_210;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8661,14 +7029,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_210 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_211;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8694,14 +7055,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_211 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_212;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8736,73 +7090,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_212 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_213 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8817,14 +7119,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_214 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8865,14 +7160,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_215 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_216;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8898,14 +7186,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_216 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_217;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8935,14 +7216,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_217 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -8980,14 +7254,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_218 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_219;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -9025,14 +7292,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_219 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_220;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -9070,16 +7330,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -9088,9 +7341,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9101,11 +7351,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_221 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
@@ -9121,10 +7383,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_222;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
@@ -9132,17 +7390,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_222 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
 assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
 assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_223;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
@@ -9150,9 +7401,6 @@ always @(*) begin
 			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_223 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
@@ -9171,10 +7419,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
@@ -9182,9 +7426,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_224 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
@@ -9194,10 +7435,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_225;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine3_next_state <= 4'd0;
 	builder_bankmachine3_next_state <= builder_bankmachine3_state;
@@ -9258,14 +7495,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_225 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9306,14 +7562,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_226 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9339,14 +7588,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_227 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_228;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9372,14 +7614,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_228 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_229;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9414,14 +7649,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_229 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_230;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9450,14 +7678,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9498,14 +7719,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_231 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9531,14 +7745,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_232 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9568,14 +7775,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_233 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_234;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9613,14 +7813,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_234 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_235;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -9658,16 +7851,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_235 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -9692,8 +7878,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine3_row_opened) begin
 						if (main_litedramcore_bankmachine3_row_hit) begin
 							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -9703,16 +7889,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_236 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -9737,8 +7916,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine3_row_opened) begin
 						if (main_litedramcore_bankmachine3_row_hit) begin
 							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -9748,42 +7927,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_237 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_238;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_238 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
@@ -9799,10 +7942,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_239;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
@@ -9810,17 +7949,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_239 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
 assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
 assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_240;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
@@ -9828,9 +7960,6 @@ always @(*) begin
 			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_240 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
@@ -9849,10 +7978,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_241;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
@@ -9860,9 +7985,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_241 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
@@ -9872,10 +7994,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine4_next_state <= 4'd0;
 	builder_bankmachine4_next_state <= builder_bankmachine4_state;
@@ -9936,30 +8054,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_242 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_243;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9970,36 +8078,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_243 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_244;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10017,10 +8112,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
-							end
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -10029,14 +8121,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_244 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_245;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10062,14 +8147,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_245 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10095,14 +8173,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_246 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10137,14 +8208,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_247 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10173,14 +8237,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_248 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10221,14 +8278,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_249 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_250;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10254,14 +8304,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_250 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_251;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10291,14 +8334,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_251 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_252;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10336,14 +8372,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_252 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10381,14 +8410,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_253 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_254;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -10426,16 +8448,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_254 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_255;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -10444,9 +8459,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -10457,11 +8469,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_255 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
@@ -10477,10 +8501,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_256;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
@@ -10488,17 +8508,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_256 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
 assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
 assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_257;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
@@ -10506,9 +8519,6 @@ always @(*) begin
 			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_257 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
@@ -10527,10 +8537,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_258;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
@@ -10538,9 +8544,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_258 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
@@ -10550,10 +8553,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_259;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine5_next_state <= 4'd0;
 	builder_bankmachine5_next_state <= builder_bankmachine5_state;
@@ -10614,14 +8613,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_259 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_260;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10662,14 +8680,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_260 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_261;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10695,72 +8706,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_261 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_262;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_262 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_263;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10773,14 +8732,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_263 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_264;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10815,14 +8767,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_264 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10851,14 +8796,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10899,14 +8837,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_266 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10932,14 +8863,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_267 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -10969,14 +8893,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_268 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -11014,14 +8931,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_269 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -11059,14 +8969,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_270 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -11104,16 +9007,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_271 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -11122,9 +9018,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -11135,11 +9028,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_272 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
@@ -11155,10 +9060,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
@@ -11166,17 +9067,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_273 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
 assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
 assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
@@ -11184,9 +9078,6 @@ always @(*) begin
 			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_274 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
@@ -11205,10 +9096,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
@@ -11216,9 +9103,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_275 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
@@ -11228,10 +9112,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine6_next_state <= 4'd0;
 	builder_bankmachine6_next_state <= builder_bankmachine6_state;
@@ -11292,14 +9172,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_276 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11340,14 +9239,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_277 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11373,14 +9265,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_278 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11406,14 +9291,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_279 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11448,14 +9326,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_280 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11484,14 +9355,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_281 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11532,14 +9396,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_282 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11565,59 +9422,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_283 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_284 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11647,14 +9452,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_285 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11692,14 +9490,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_286 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11737,14 +9528,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_287 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -11782,16 +9566,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_288 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -11800,9 +9577,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -11813,11 +9587,23 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_289 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
@@ -11833,10 +9619,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
@@ -11844,17 +9626,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_290 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
 assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
@@ -11862,9 +9637,6 @@ always @(*) begin
 			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_291 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
@@ -11883,10 +9655,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
@@ -11894,9 +9662,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_292 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
@@ -11906,10 +9671,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine7_next_state <= 4'd0;
 	builder_bankmachine7_next_state <= builder_bankmachine7_state;
@@ -11970,14 +9731,33 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_293 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12018,14 +9798,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_294 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12051,14 +9824,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_295 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12084,14 +9850,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12126,14 +9885,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12162,14 +9914,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12210,14 +9955,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_299 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12243,14 +9981,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_300 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12280,14 +10011,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_301 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12325,14 +10049,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_302 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12370,14 +10087,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_303 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12415,14 +10125,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_304 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12460,42 +10163,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_306 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_rdcmdphase = (main_k7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_wrcmdphase = (main_k7ddrphy_wrphase_storage - 1'd1);
@@ -12527,10 +10194,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_valids <= 8'd0;
 	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
@@ -12541,9 +10204,6 @@ always @(*) begin
 	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-// synthesis translate_off
-	dummy_d_307 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
 assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
@@ -12552,49 +10212,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
 assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
 assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
 assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
 	end
-// synthesis translate_off
-	dummy_d_308 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
 	end
-// synthesis translate_off
-	dummy_d_309 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
 	end
-// synthesis translate_off
-	dummy_d_310 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
@@ -12603,14 +10238,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
 		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_311 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
@@ -12619,14 +10247,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
 		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_312 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
@@ -12635,14 +10256,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
 		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_313 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
@@ -12651,14 +10265,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
 		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_314 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
@@ -12667,14 +10274,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
 		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_315 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
@@ -12683,14 +10283,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
 		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_316 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
@@ -12699,14 +10292,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
 		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_317 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
@@ -12715,15 +10301,8 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
 		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_318 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_valids <= 8'd0;
 	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
@@ -12734,9 +10313,6 @@ always @(*) begin
 	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-// synthesis translate_off
-	dummy_d_319 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
 assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
@@ -12745,44 +10321,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
 assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
 assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
 assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
 	end
-// synthesis translate_off
-	dummy_d_320 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
 	end
-// synthesis translate_off
-	dummy_d_321 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
 	end
-// synthesis translate_off
-	dummy_d_322 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
 assign main_litedramcore_dfi_p0_reset_n = 1'd1;
@@ -12798,10 +10353,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1;
 assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
 assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
 assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
 always @(*) begin
 	builder_multiplexer_next_state <= 4'd0;
 	builder_multiplexer_next_state <= builder_multiplexer_state;
@@ -12858,14 +10409,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_323 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel2 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
@@ -12900,14 +10485,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_324 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -12948,14 +10526,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_325 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -12983,14 +10554,7 @@ always @(*) begin
 			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_326 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13025,14 +10589,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_327 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13060,14 +10617,7 @@ always @(*) begin
 			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_328 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13095,14 +10645,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_329 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13139,14 +10682,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_330 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13174,14 +10710,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_331 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -13223,14 +10752,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_332 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -13258,14 +10780,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_333 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -13306,57 +10821,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_335 = dummy_s;
-// synthesis translate_on
 end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
@@ -13401,41 +10865,27 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
 assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 32'd0;
+	main_litedramcore_interface_wdata <= 256'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_336 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata <= 256'd0;
+	main_litedramcore_interface_wdata_we <= 32'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_337 = dummy_s;
-// synthesis translate_on
 end
 assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
 assign builder_roundrobin0_grant = 1'd0;
@@ -13446,10 +10896,6 @@ assign builder_roundrobin4_grant = 1'd0;
 assign builder_roundrobin5_grant = 1'd0;
 assign builder_roundrobin6_grant = 1'd0;
 assign builder_roundrobin7_grant = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_338;
-// synthesis translate_on
 always @(*) begin
 	builder_next_state <= 2'd0;
 	builder_next_state <= builder_state;
@@ -13466,173 +10912,114 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_338 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_339;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
+	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
+			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_339 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_340;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
+	builder_litedramcore_we_next_value2 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_340 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_341;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
+	builder_litedramcore_we_next_value_ce2 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
+			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
+				builder_litedramcore_we_next_value_ce2 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_341 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_342;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
+	builder_litedramcore_wishbone_ack <= 1'd0;
 	case (builder_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_342 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_343;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
+	builder_litedramcore_dat_w_next_value0 <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_343 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_344;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
+	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_344 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_345;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	builder_litedramcore_wishbone_dat_r <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_345 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_346;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	builder_litedramcore_adr_next_value1 <= 14'd0;
 	case (builder_state)
 		1'd1: begin
+			builder_litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_346 = dummy_s;
-// synthesis translate_on
 end
 assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
 assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
@@ -13645,576 +11032,282 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_347;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
+	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_347 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_348;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
+	builder_csrbank0_init_done0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_348 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_349;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
+	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_349 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_350;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
+	builder_csrbank0_init_error0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_350 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_351;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_351 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_352;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_352 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
-
-// synthesis translate_off
-reg dummy_d_353;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_353 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_354;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_354 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_355;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_355 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_356;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_356 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_357 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_358;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_358 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_359;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_cdly_rst_we <= 1'd0;
+	main_k7ddrphy_cdly_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_359 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_360;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_cdly_rst_re <= 1'd0;
+	main_k7ddrphy_cdly_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_360 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_361;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_cdly_inc_we <= 1'd0;
+	main_k7ddrphy_cdly_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_361 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_362;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_cdly_inc_re <= 1'd0;
+	main_k7ddrphy_cdly_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_362 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_363;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_363 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_364;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_364 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_365;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_365 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_366;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_366 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_367;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
+	main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_367 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_368;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
+	main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_368 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_369;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_369 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_370;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_370 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_371;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_371 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_372;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_372 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_373;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
 		main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_373 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_374;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
 		main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_374 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_375;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
+	main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_375 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_376;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
+	main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_376 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_377;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_rst_re <= 1'd0;
+	main_k7ddrphy_wdly_dqs_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_377 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_378;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_rst_we <= 1'd0;
+	main_k7ddrphy_wdly_dqs_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_378 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_379;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
+	main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_379 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_380;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
+	main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_380 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_381;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
 		main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_381 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_382;
-// synthesis translate_on
 always @(*) begin
 	main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
 		main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_382 = dummy_s;
-// synthesis translate_on
 end
 assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_383;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_383 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_384;
-// synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_384 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_385;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_385 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_386;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_386 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_387;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_387 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_388;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_388 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage;
 assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0];
@@ -14222,2301 +11315,435 @@ assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0];
 assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_389;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
+	builder_csrbank2_dfii_control0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_389 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_390;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
+	builder_csrbank2_dfii_control0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_390 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_391;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_391 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_392;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_392 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_393;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_393 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_394;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_394 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_395;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_395 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_396;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_396 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_397;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_397 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_398;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_398 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_399;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_399 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_400;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_400 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_401;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata7_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata7_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_401 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_402;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata7_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata7_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_402 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_403;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_403 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_404;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_404 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_405;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_405 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_406;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_406 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_407;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_407 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_408;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_408 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_409;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_409 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_410;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_410 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_411;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_411 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_412;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_412 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_413;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_413 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_414;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_414 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_415;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_415 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_416;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_416 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_417;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata7_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi0_rddata7_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_417 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_418;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata7_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi0_rddata7_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_418 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_419;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi0_rddata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_419 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_420;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi0_rddata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_420 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_421;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi0_rddata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_421 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_422;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi0_rddata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_422 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_423;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi0_rddata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_423 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_424;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi0_rddata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_424 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_425;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_425 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_426;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_426 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_427;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_427 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_428;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_428 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_429;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_429 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_430;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_430 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_431;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_431 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_432;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_432 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_433;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_433 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_434;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_434 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_435;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_435 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_436;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_436 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_437;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_437 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_438;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_438 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_439;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_439 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_440;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_440 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_441;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_441 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_442;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_442 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_443;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi1_wrdata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_443 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_444;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi1_wrdata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_444 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_445;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi1_wrdata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_445 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_446;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi1_wrdata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_446 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_447;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi1_wrdata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_447 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_448;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi1_wrdata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_448 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_449;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi1_wrdata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_449 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_450;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi1_wrdata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_450 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_451;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_451 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_452;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_452 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_453;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_453 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_454;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_454 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_455;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_455 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_456;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_456 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_457;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_457 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_458;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_458 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_459;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi1_rddata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_459 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_460;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi1_rddata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_460 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_461;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi1_rddata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_461 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_462;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi1_rddata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_462 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_463;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi1_rddata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_463 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_464;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi1_rddata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_464 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_465;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi1_rddata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_465 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_466;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi1_rddata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_466 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_467;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_467 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_468;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_468 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_469;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_469 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_470;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_470 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_471;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_471 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_472;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_472 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_473;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_473 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_474;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_474 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_475;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_475 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_476;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_476 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_477;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_477 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_478;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_478 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_479;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_479 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_480;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_480 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_481;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_481 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_482;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_482 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_483;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_483 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_484;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_484 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_485;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi2_wrdata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_485 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_486;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi2_wrdata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_486 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_487;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi2_wrdata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_487 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_488;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi2_wrdata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_488 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_489;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi2_wrdata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_489 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_490;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi2_wrdata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_490 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_491;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi2_wrdata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_491 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_492;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi2_wrdata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_492 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_493;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_493 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_494;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_494 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_495;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_495 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_496;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_496 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_497;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_497 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_498;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_498 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_499;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
 		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_499 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_500;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
 		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_500 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_501;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin
-		builder_csrbank2_dfii_pi2_rddata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_501 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_502;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin
-		builder_csrbank2_dfii_pi2_rddata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_502 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_503;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin
-		builder_csrbank2_dfii_pi2_rddata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_503 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_504;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin
-		builder_csrbank2_dfii_pi2_rddata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_504 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_505;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin
-		builder_csrbank2_dfii_pi2_rddata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_505 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_506;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin
-		builder_csrbank2_dfii_pi2_rddata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_506 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_507;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin
-		builder_csrbank2_dfii_pi2_rddata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_507 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_508;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin
-		builder_csrbank2_dfii_pi2_rddata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_508 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_509;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_509 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_510;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_510 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_511;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_511 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_512;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_512 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_513;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
 		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_513 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_514;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
 		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_514 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_515;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
 		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_515 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_516;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
 		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_516 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_517;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
 		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_517 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_518;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
 		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_518 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_519;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_519 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_520;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
 		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_520 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_521;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_521 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_522;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_522 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_523;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
 		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_523 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_524;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_524 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_525;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
 		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_525 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_526;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
 		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_526 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_527;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin
-		builder_csrbank2_dfii_pi3_wrdata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_527 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_528;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin
-		builder_csrbank2_dfii_pi3_wrdata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_528 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_529;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin
-		builder_csrbank2_dfii_pi3_wrdata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_529 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_530;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin
-		builder_csrbank2_dfii_pi3_wrdata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_530 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_531;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin
-		builder_csrbank2_dfii_pi3_wrdata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_531 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_532;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin
-		builder_csrbank2_dfii_pi3_wrdata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_532 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_533;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin
-		builder_csrbank2_dfii_pi3_wrdata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_533 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_534;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin
-		builder_csrbank2_dfii_pi3_wrdata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_534 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_535;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_535 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_536;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_536 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_537;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_537 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_538;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_538 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_539;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_539 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_540;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
 		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_540 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_541;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_541 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_542;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_542 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_rddata7_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_543;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata7_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin
-		builder_csrbank2_dfii_pi3_rddata7_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_543 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_544;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata7_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin
-		builder_csrbank2_dfii_pi3_rddata7_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_544 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_rddata6_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_545;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata6_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin
-		builder_csrbank2_dfii_pi3_rddata6_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_545 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_546;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata6_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin
-		builder_csrbank2_dfii_pi3_rddata6_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_546 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_rddata5_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_547;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata5_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin
-		builder_csrbank2_dfii_pi3_rddata5_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_547 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_548;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata5_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin
-		builder_csrbank2_dfii_pi3_rddata5_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_548 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_rddata4_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_549;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata4_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin
-		builder_csrbank2_dfii_pi3_rddata4_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_549 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_550;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata4_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin
-		builder_csrbank2_dfii_pi3_rddata4_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_550 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_551;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_551 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_552;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
+		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_552 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_553;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_553 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_554;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_554 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_555;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
 		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_555 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_556;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
 		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_556 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_557;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
 		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_557 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_558;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
 		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_558 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
@@ -16524,88 +11751,36 @@ assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
 assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
 assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
 assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata7_w = main_litedramcore_phaseinjector0_wrdata_storage[63:56];
-assign builder_csrbank2_dfii_pi0_wrdata6_w = main_litedramcore_phaseinjector0_wrdata_storage[55:48];
-assign builder_csrbank2_dfii_pi0_wrdata5_w = main_litedramcore_phaseinjector0_wrdata_storage[47:40];
-assign builder_csrbank2_dfii_pi0_wrdata4_w = main_litedramcore_phaseinjector0_wrdata_storage[39:32];
-assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi0_rddata7_w = main_litedramcore_phaseinjector0_rddata_status[63:56];
-assign builder_csrbank2_dfii_pi0_rddata6_w = main_litedramcore_phaseinjector0_rddata_status[55:48];
-assign builder_csrbank2_dfii_pi0_rddata5_w = main_litedramcore_phaseinjector0_rddata_status[47:40];
-assign builder_csrbank2_dfii_pi0_rddata4_w = main_litedramcore_phaseinjector0_rddata_status[39:32];
-assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
+assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
 assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
 assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
 assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata7_w = main_litedramcore_phaseinjector1_wrdata_storage[63:56];
-assign builder_csrbank2_dfii_pi1_wrdata6_w = main_litedramcore_phaseinjector1_wrdata_storage[55:48];
-assign builder_csrbank2_dfii_pi1_wrdata5_w = main_litedramcore_phaseinjector1_wrdata_storage[47:40];
-assign builder_csrbank2_dfii_pi1_wrdata4_w = main_litedramcore_phaseinjector1_wrdata_storage[39:32];
-assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi1_rddata7_w = main_litedramcore_phaseinjector1_rddata_status[63:56];
-assign builder_csrbank2_dfii_pi1_rddata6_w = main_litedramcore_phaseinjector1_rddata_status[55:48];
-assign builder_csrbank2_dfii_pi1_rddata5_w = main_litedramcore_phaseinjector1_rddata_status[47:40];
-assign builder_csrbank2_dfii_pi1_rddata4_w = main_litedramcore_phaseinjector1_rddata_status[39:32];
-assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
+assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
 assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
 assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
 assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata7_w = main_litedramcore_phaseinjector2_wrdata_storage[63:56];
-assign builder_csrbank2_dfii_pi2_wrdata6_w = main_litedramcore_phaseinjector2_wrdata_storage[55:48];
-assign builder_csrbank2_dfii_pi2_wrdata5_w = main_litedramcore_phaseinjector2_wrdata_storage[47:40];
-assign builder_csrbank2_dfii_pi2_wrdata4_w = main_litedramcore_phaseinjector2_wrdata_storage[39:32];
-assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi2_rddata7_w = main_litedramcore_phaseinjector2_rddata_status[63:56];
-assign builder_csrbank2_dfii_pi2_rddata6_w = main_litedramcore_phaseinjector2_rddata_status[55:48];
-assign builder_csrbank2_dfii_pi2_rddata5_w = main_litedramcore_phaseinjector2_rddata_status[47:40];
-assign builder_csrbank2_dfii_pi2_rddata4_w = main_litedramcore_phaseinjector2_rddata_status[39:32];
-assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
+assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
 assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
 assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
 assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata7_w = main_litedramcore_phaseinjector3_wrdata_storage[63:56];
-assign builder_csrbank2_dfii_pi3_wrdata6_w = main_litedramcore_phaseinjector3_wrdata_storage[55:48];
-assign builder_csrbank2_dfii_pi3_wrdata5_w = main_litedramcore_phaseinjector3_wrdata_storage[47:40];
-assign builder_csrbank2_dfii_pi3_wrdata4_w = main_litedramcore_phaseinjector3_wrdata_storage[39:32];
-assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi3_rddata7_w = main_litedramcore_phaseinjector3_rddata_status[63:56];
-assign builder_csrbank2_dfii_pi3_rddata6_w = main_litedramcore_phaseinjector3_rddata_status[55:48];
-assign builder_csrbank2_dfii_pi3_rddata5_w = main_litedramcore_phaseinjector3_rddata_status[47:40];
-assign builder_csrbank2_dfii_pi3_rddata4_w = main_litedramcore_phaseinjector3_rddata_status[39:32];
-assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
+assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
 assign builder_csr_interconnect_adr = builder_litedramcore_adr;
 assign builder_csr_interconnect_we = builder_litedramcore_we;
@@ -16621,10 +11796,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-
-// synthesis translate_off
-reg dummy_d_559;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16653,14 +11824,7 @@ always @(*) begin
 			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_559 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_560;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed1 <= 15'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16689,14 +11853,7 @@ always @(*) begin
 			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_560 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_561;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed2 <= 3'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16725,14 +11882,7 @@ always @(*) begin
 			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_561 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_562;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16761,14 +11911,7 @@ always @(*) begin
 			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_562 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_563;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16797,14 +11940,7 @@ always @(*) begin
 			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_563 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_564;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16833,14 +11969,7 @@ always @(*) begin
 			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_564 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_565;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16869,14 +11998,7 @@ always @(*) begin
 			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_565 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_566;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed1 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16905,14 +12027,7 @@ always @(*) begin
 			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_566 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_567;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed2 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -16941,14 +12056,7 @@ always @(*) begin
 			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_567 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_568;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed6 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -16977,14 +12085,7 @@ always @(*) begin
 			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_568 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_569;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed7 <= 15'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17013,14 +12114,7 @@ always @(*) begin
 			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_569 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_570;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed8 <= 3'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17049,14 +12143,7 @@ always @(*) begin
 			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_570 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_571;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed9 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17085,14 +12172,7 @@ always @(*) begin
 			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_571 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_572;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed10 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17121,14 +12201,7 @@ always @(*) begin
 			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_572 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_573;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed11 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17157,14 +12230,7 @@ always @(*) begin
 			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_573 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_574;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17193,14 +12259,7 @@ always @(*) begin
 			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_574 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_575;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17229,14 +12288,7 @@ always @(*) begin
 			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_575 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_576;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -17265,14 +12317,7 @@ always @(*) begin
 			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_576 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_577;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed12 <= 22'd0;
 	case (builder_roundrobin0_grant)
@@ -17280,14 +12325,7 @@ always @(*) begin
 			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_577 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_578;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed13 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -17295,14 +12333,7 @@ always @(*) begin
 			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_578 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_579;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed14 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -17310,14 +12341,7 @@ always @(*) begin
 			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_579 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_580;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed15 <= 22'd0;
 	case (builder_roundrobin1_grant)
@@ -17325,14 +12349,7 @@ always @(*) begin
 			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_580 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_581;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed16 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -17340,14 +12357,7 @@ always @(*) begin
 			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_581 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_582;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed17 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -17355,14 +12365,7 @@ always @(*) begin
 			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_582 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_583;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed18 <= 22'd0;
 	case (builder_roundrobin2_grant)
@@ -17370,14 +12373,7 @@ always @(*) begin
 			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_583 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_584;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed19 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -17385,14 +12381,7 @@ always @(*) begin
 			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_584 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_585;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed20 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -17400,14 +12389,7 @@ always @(*) begin
 			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_585 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_586;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed21 <= 22'd0;
 	case (builder_roundrobin3_grant)
@@ -17415,14 +12397,7 @@ always @(*) begin
 			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_586 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_587;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed22 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -17430,14 +12405,7 @@ always @(*) begin
 			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_587 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_588;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed23 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -17445,14 +12413,7 @@ always @(*) begin
 			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_588 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_589;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed24 <= 22'd0;
 	case (builder_roundrobin4_grant)
@@ -17460,14 +12421,7 @@ always @(*) begin
 			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_589 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_590;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed25 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -17475,14 +12429,7 @@ always @(*) begin
 			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_590 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_591;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed26 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -17490,14 +12437,7 @@ always @(*) begin
 			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_591 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_592;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed27 <= 22'd0;
 	case (builder_roundrobin5_grant)
@@ -17505,14 +12445,7 @@ always @(*) begin
 			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_592 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_593;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed28 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -17520,14 +12453,7 @@ always @(*) begin
 			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_593 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_594;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed29 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -17535,14 +12461,7 @@ always @(*) begin
 			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_594 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_595;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed30 <= 22'd0;
 	case (builder_roundrobin6_grant)
@@ -17550,14 +12469,7 @@ always @(*) begin
 			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_595 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_596;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed31 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -17565,14 +12477,7 @@ always @(*) begin
 			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_596 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_597;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed32 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -17580,14 +12485,7 @@ always @(*) begin
 			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_597 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_598;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed33 <= 22'd0;
 	case (builder_roundrobin7_grant)
@@ -17595,14 +12493,7 @@ always @(*) begin
 			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_598 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_599;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed34 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -17610,14 +12501,7 @@ always @(*) begin
 			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_599 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_600;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed35 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -17625,14 +12509,7 @@ always @(*) begin
 			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_600 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_601;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed0 <= 3'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17649,14 +12526,7 @@ always @(*) begin
 			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_601 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_602;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed1 <= 15'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17673,14 +12543,7 @@ always @(*) begin
 			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_602 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_603;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed2 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17697,14 +12560,7 @@ always @(*) begin
 			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_603 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_604;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed3 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17721,14 +12577,7 @@ always @(*) begin
 			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_604 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_605;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed4 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17745,14 +12594,7 @@ always @(*) begin
 			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_605 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_606;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed5 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17769,14 +12611,7 @@ always @(*) begin
 			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_606 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_607;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed6 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -17793,14 +12628,7 @@ always @(*) begin
 			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_607 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_608;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed7 <= 3'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17817,14 +12645,7 @@ always @(*) begin
 			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_608 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_609;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed8 <= 15'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17841,14 +12662,7 @@ always @(*) begin
 			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_609 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_610;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed9 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17865,14 +12679,7 @@ always @(*) begin
 			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_610 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_611;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed10 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17889,14 +12696,7 @@ always @(*) begin
 			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_611 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_612;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed11 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17913,14 +12713,7 @@ always @(*) begin
 			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_612 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_613;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed12 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17937,14 +12730,7 @@ always @(*) begin
 			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_613 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_614;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed13 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -17961,14 +12747,7 @@ always @(*) begin
 			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_614 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_615;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed14 <= 3'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -17985,14 +12764,7 @@ always @(*) begin
 			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_615 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_616;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed15 <= 15'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18009,14 +12781,7 @@ always @(*) begin
 			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_616 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_617;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed16 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18033,14 +12798,7 @@ always @(*) begin
 			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_617 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_618;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed17 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18057,14 +12815,7 @@ always @(*) begin
 			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_618 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_619;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed18 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18081,14 +12832,7 @@ always @(*) begin
 			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_619 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_620;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed19 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18105,14 +12849,7 @@ always @(*) begin
 			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_620 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_621;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed20 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -18129,14 +12866,7 @@ always @(*) begin
 			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_621 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_622;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed21 <= 3'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18153,14 +12883,7 @@ always @(*) begin
 			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_622 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_623;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed22 <= 15'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18177,14 +12900,7 @@ always @(*) begin
 			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_623 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_624;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed23 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18201,14 +12917,7 @@ always @(*) begin
 			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_624 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_625;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed24 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18225,14 +12934,7 @@ always @(*) begin
 			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_625 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_626;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed25 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18249,14 +12951,7 @@ always @(*) begin
 			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_626 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_627;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed26 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18273,14 +12968,7 @@ always @(*) begin
 			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_627 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_628;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed27 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -18297,15 +12985,17 @@ always @(*) begin
 			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_628 = dummy_s;
-// synthesis translate_on
 end
 assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge iodelay_clk) begin
 	if ((main_reset_counter != 1'd0)) begin
 		main_reset_counter <= (main_reset_counter - 1'd1);
@@ -20270,249 +14960,93 @@ always @(posedge sys_clk) begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
-			end
-			3'd4: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
 			end
-			3'd5: begin
+			3'd4: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
 			end
-			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata7_w;
-			end
-			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata6_w;
-			end
-			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata5_w;
-			end
-			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata4_w;
-			end
-			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
-			end
-			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
-			end
-			4'd12: begin
+			3'd5: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
 			end
-			4'd13: begin
+			3'd6: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
 			end
-			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata7_w;
-			end
-			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata6_w;
-			end
-			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata5_w;
-			end
-			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata4_w;
-			end
-			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
-			end
-			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
-			end
-			5'd20: begin
+			3'd7: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
 			end
-			5'd21: begin
+			4'd8: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
 			end
-			5'd22: begin
+			4'd9: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
 			end
-			5'd23: begin
+			4'd10: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
 			end
-			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
-			end
-			5'd25: begin
+			4'd11: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
 			end
-			5'd26: begin
+			4'd12: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
 			end
-			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata7_w;
-			end
-			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata6_w;
-			end
-			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata5_w;
-			end
-			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata4_w;
-			end
-			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
-			end
-			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
-			end
-			6'd33: begin
+			4'd13: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
 			end
-			6'd34: begin
+			4'd14: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
 			end
-			6'd35: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata7_w;
-			end
-			6'd36: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata6_w;
-			end
-			6'd37: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata5_w;
-			end
-			6'd38: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata4_w;
-			end
-			6'd39: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
-			end
-			6'd40: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
-			end
-			6'd41: begin
+			4'd15: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
 			end
-			6'd42: begin
+			5'd16: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
 			end
-			6'd43: begin
+			5'd17: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
 			end
-			6'd44: begin
+			5'd18: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
 			end
-			6'd45: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
-			end
-			6'd46: begin
+			5'd19: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
 			end
-			6'd47: begin
+			5'd20: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
 			end
-			6'd48: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata7_w;
-			end
-			6'd49: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata6_w;
-			end
-			6'd50: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata5_w;
-			end
-			6'd51: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata4_w;
-			end
-			6'd52: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
-			end
-			6'd53: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
-			end
-			6'd54: begin
+			5'd21: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
 			end
-			6'd55: begin
+			5'd22: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
 			end
-			6'd56: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata7_w;
-			end
-			6'd57: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata6_w;
-			end
-			6'd58: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata5_w;
-			end
-			6'd59: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata4_w;
-			end
-			6'd60: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
-			end
-			6'd61: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
-			end
-			6'd62: begin
+			5'd23: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
 			end
-			6'd63: begin
+			5'd24: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
 			end
-			7'd64: begin
+			5'd25: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
 			end
-			7'd65: begin
+			5'd26: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
 			end
-			7'd66: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
-			end
-			7'd67: begin
+			5'd27: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
 			end
-			7'd68: begin
+			5'd28: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
 			end
-			7'd69: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata7_w;
-			end
-			7'd70: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata6_w;
-			end
-			7'd71: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata5_w;
-			end
-			7'd72: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata4_w;
-			end
-			7'd73: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
-			end
-			7'd74: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
-			end
-			7'd75: begin
+			5'd29: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
 			end
-			7'd76: begin
+			5'd30: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
 			end
-			7'd77: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata7_w;
-			end
-			7'd78: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata6_w;
-			end
-			7'd79: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata5_w;
-			end
-			7'd80: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata4_w;
-			end
-			7'd81: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
-			end
-			7'd82: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
-			end
-			7'd83: begin
+			5'd31: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
 			end
-			7'd84: begin
+			6'd32: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
 			end
 		endcase
@@ -20525,40 +15059,19 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
 	end
 	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address1_re) begin
-		main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+		main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
 	end
 	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
 	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
 		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
 	end
 	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata7_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi0_wrdata7_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata6_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi0_wrdata6_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata5_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi0_wrdata5_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata4_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi0_wrdata4_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
-	end
 	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi0_wrdata1_r;
 	end
 	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
 	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
@@ -20566,40 +15079,19 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
 	end
 	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address1_re) begin
-		main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+		main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
 	end
 	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
 	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
 		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
 	end
 	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata7_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi1_wrdata7_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata6_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi1_wrdata6_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata5_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi1_wrdata5_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata4_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi1_wrdata4_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
-	end
 	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi1_wrdata1_r;
 	end
 	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
 	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
@@ -20607,40 +15099,19 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
 	end
 	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address1_re) begin
-		main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+		main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
 	end
 	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
 	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
 		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
 	end
 	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata7_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi2_wrdata7_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata6_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi2_wrdata6_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata5_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi2_wrdata5_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata4_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi2_wrdata4_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
-	end
 	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi2_wrdata1_r;
 	end
 	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
 	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
@@ -20648,40 +15119,19 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
 	end
 	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address1_re) begin
-		main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+		main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
 	end
 	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
 	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
 		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
 	end
 	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata7_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi3_wrdata7_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata6_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi3_wrdata6_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata5_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi3_wrdata5_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata4_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi3_wrdata4_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
-	end
 	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi3_wrdata1_r;
 	end
 	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
 	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
@@ -21015,6 +15465,11 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
 BUFG BUFG(
 	.I(main_clkout0),
 	.O(main_clkout_buf0)
@@ -25524,118 +19979,150 @@ IOBUF IOBUF_31(
 	.O(main_k7ddrphy_dq_i_nodelay31)
 );
 
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage[0:15];
-reg [24:0] memdat;
+reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_1[0:15];
-reg [24:0] memdat_1;
+reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_2[0:15];
-reg [24:0] memdat_2;
+reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_3[0:15];
-reg [24:0] memdat_3;
+reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_4[0:15];
-reg [24:0] memdat_4;
+reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_5[0:15];
-reg [24:0] memdat_5;
+reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_6[0:15];
-reg [24:0] memdat_6;
+reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_7[0:15];
-reg [24:0] memdat_7;
+reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 FD FD(
 	.C(main_clkin),
 	.D(main_reset),
@@ -25792,3 +20279,7 @@ PLLE2_ADV #(
 );
 
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:12.
+//------------------------------------------------------------------------------
diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 5b1a383..1b6e88e 100644
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -518,7 +518,7 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842afc4
+7c0802a63842adc4
 fbe1fff8fbc1fff0
 f821ff51f8010010
 f88100d83bc10020
@@ -527,96 +527,97 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-600000004800245d
+6000000048002159
 7fc3f3787c7f1b78
-6000000048001e69
+6000000048001b7d
 7fe3fb78382100b0
-0000000048002a54
+00000000480027d4
 0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842af203c4c0001
+3842ad203c4c0001
 7d8000267c0802a6
-9181000848002991
-48001e65f821fed1
+9181000848002711
+48001b79f821fed1
 3c62ffff60000000
-4bffff3938637b10
+4bffff3938637a90
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637b30
+63ff000838637ab0
 3c62ffff4bffff15
-38637b507bff0020
+38637ad07bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b68
+4bfffee938637ae8
 4e00000073e90002
 3c62ffff41820010
-4bfffed138637b70
+4bfffed138637af0
 4d80000073e90004
 3c62ffff41820010
-4bfffeb938637b78
+4bfffeb938637af8
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b80
+4bfffea138637b00
 4182001073e90010
-38637b903c62ffff
-73e901004bfffe8d
+38637b103c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637ba0
-3b7b7ba83f62ffff
+4bfffe7938637b20
+3b7b7b283f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bb0
+4bfffe4138637b30
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637bc8
+4bfffe1938637b48
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637be07884b282
+38637b607884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637bf87c892392
+38637b787c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637c187f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637b98
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,182 +625,161 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637c38
-4082009073890002
-38637c583c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637bb857a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637bd8
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637c70
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637c807fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847cb038a57ca0
-4bfffb8938637cb8
-6000000048000f2d
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637bf03c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637c007b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637c3038a57c20
+4bfffb897ca42b78
+6000000048000c55
 3c62ffff418e0024
-4bfffb7138637ce8
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637c60
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637d00
-38a000403c9df000
+4bfffb4938637c78
+38a000403c9af000
 3861007078840020
-6000000048001cbd
+6000000048001889
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637d18
+794a83e438637c90
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637d383c62ffff
+38637cb03c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d9888810070
+38637d1088810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637dc8
+4bfffaa938637d40
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-6000000048001c15
-38637de83c62ffff
+60000000480017e1
+38637d603c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187d503b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637d783c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff000480024a8
-7884002038a00038
-48001b917f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-48001b497f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637c68
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
+3ba000003f02ffff
+3b187cc83b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637cf0
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+4800222c7d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048001761
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+6000000048001719
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637be83c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061291004
+7c604f2a7c0004ac
+392000013d40c800
+794a0020614a1008
 7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
+000000004e800020
 0000000000000000
-3d20c80000000000
-612900045463063e
+3842a6f83c4c0001
+4182006828030002
+4182003028030003
+4082007c28030001
+6129101c3d20c800
 7c0004ac79290020
-3d40c8007c604f2a
-614a000839200001
-7c0004ac794a0020
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a8ac
-2803000341820068
-2803000141820030
-3d20c8004082007c
-7929002061290038
+3d40c8007c804f2a
+614a102039200001
+3d20c80048000024
+792900206129104c
 7c804f2a7c0004ac
 392000013d40c800
-48000024614a003c
-612900a03d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a00a439200001
-7c0004ac794a0020
-4e8000207d20572a
-6129006c3d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a007039200001
-7c8307b44bffffd0
-000000004bffff24
-0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
-7c604f2a7c0004ac
-610810143d00c800
-7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+794a0020614a1050
+7d20572a7c0004ac
+3d20c8004e800020
+7929002061291034
+7c804f2a7c0004ac
+392000013d40c800
+4bffffd0614a1038
+4bffff287c8307b4
 0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
+3d20c80000000000
+6129081039400001
+792900207d431830
 7c604f2a7c0004ac
-610810183d00c800
+610808143d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
 394000013d20c800
-7d43183061291010
+7d43183061290810
 7c0004ac79290020
 3d00c8007c604f2a
-790800206108101c
+7908002061080818
 7d40472a7c0004ac
 7c0004ac39400000
 4e8000207d404f2a
 0000000000000000
 3d20c80000000000
-6129101039400001
+6129081039400001
 792900207d431830
 7c604f2a7c0004ac
-610810203d00c800
+6108081c3d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
@@ -809,592 +789,524 @@ a12100a660000000
 4182001c28030003
 4082004028030001
 392000003d40c800
-48000010614a0048
+48000010614a1028
 392000003d40c800
-794a0020614a00b0
+794a0020614a1058
 7d20572a7c0004ac
 3d40c8004e800020
-614a007c39200000
+614a104039200000
 3d40c8004bffffe4
-614a001439200000
+614a101039200000
 000000004bffffd4
 0000000000000000
-3842a6583c4c0001
-4182006828030002
-4182003028030003
-4082007c28030001
+4182004028030002
+4182001c28030003
+4082004028030001
 392000003d40c800
-794a0020614a0040
-7d20572a7c0004ac
-614a00443d40c800
-3d40c80048000024
-614a00a839200000
-7c0004ac794a0020
-3d40c8007d20572a
-794a0020614a00ac
+48000010614a1024
+392000003d40c800
+794a0020614a1054
 7d20572a7c0004ac
 3d40c8004e800020
-614a007439200000
-7c0004ac794a0020
-3d40c8007d20572a
-4bffffd0614a0078
-4bfffc9438600000
-0000000000000000
-2c03000000000000
-3929000178690020
-3920000140800008
-3929ffff2c290001
-600000004d820020
-000000004bfffff0
-0000000000000000
-3842a5783c4c0001
-48001ffd7c0802a6
-3ce08020f821ffa1
-60e700033bc10020
-7fcaf3787c7c1b78
-78e700203be00004
-3920000039000004
-7888f8427d0903a6
+614a103c39200000
+3d40c8004bffffe4
+614a100c39200000
+000000004bffffd4
+0000000000000000
+786900202c030000
+4080000839290001
+2c29000139200001
+4d8200203929ffff
+4bfffff060000000
+0000000000000000
+3c4c000100000000
+7c0802a63842a454
+f821ffa148001e59
+60a500033ca08020
+394000007c7e1b78
+78a5002038c1001f
+3b81002039000004
+7ce652147d0903a6
+7888f86239200004
 7c8400d0788407e0
-7c8642787c843838
-7cca49ae7cc43378
-4200ffe039290001
-394a0004393fffff
-4082ffc4793f0021
-4bfffbdd38600000
-392000003d40c800
-794a0020614a0014
+7c8428383929ffff
+7d0443787c884278
+4200ffe09d070001
+282a0010394a0004
+3d40c8004082ffc0
+794a0020614a100c
 7d20572a7c0004ac
-4bfffbf938600009
-4bffff313860000f
-3ce0c8003d40c800
-60e700f8614a0028
-794a00207fc9f378
-38c0000478e70020
-7cc903a6394afff0
-8cc800013909ffff
-7cc0572a7c0004ac
-4200fff0394a0004
-39290004394a0034
-4082ffd07c2a3800
-63bd10303fa0c800
+614a10103d40c800
+7c0004ac794a0020
+386000097d20572a
+3860000f4bfffc85
+3d20c8004bffff29
+612910143cc0c800
+7f8ae37860c61074
+78c6002079290020
+38eaffff38a00004
+3be000047ca903a6
+8ca7000139000000
+7905400c3bffffff
+4200fff07ca82b78
+7ca04f2a7c0004ac
+394a000439290018
+4082ffc47c293000
+63bd08303fa0c800
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffe21
+7c0004ac4bfffe41
 5463063e7c60ee2a
-7c0004ac4bfffd99
-388000177fa0ee2a
-3fa0c80057a3063e
-63bd102c4bfffba5
-4bfffe913860000f
+7c0004ac4bfffdc1
+388000177c60ee2a
+3fa0c8005463063e
+63bd082c4bfffc21
+4bfffe7d3860000f
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffdd9
+7c0004ac4bfffdf9
 5463063e7c60ee2a
-7c0004ac4bfffd51
-388000257fa0ee2a
-4bfffb6157a3063e
-4bfffe513860000f
-4bfffacd38600000
-392000003d40c800
-794a0020614a0014
-7d20572a7c0004ac
-3ba100303860000b
-3860000f4bfffae5
-3ce0c8004bfffe1d
-60e700283d60c800
-3c8033333c005555
-616b00f83d800f0f
-78e7002038c00000
-60005555207c0001
-618c0f0f60843333
-7c0004ac796b0020
-992100307d203e2a
-7c0004ac39270004
-992100317d204e2a
-7c0004ac39270008
-992100327d204e2a
-7c0004ac3927000c
-992100337d204e2a
-38a0000039200004
-7d2532147d2903a6
-7c091800552907fe
-7d45e8ae40820058
-7d0852787d1e28ae
-5509063e790afe62
-7d4a48507d4a0038
-554af0be7c895038
-7d4952147d4a2038
-7d2952145549e13e
-552ac23e7d894838
-552a843e7d295214
-552906be7d295214
-793f00207d29fa14
-4200ff9838a50001
-38c6000438e70034
-3bde00047c275800
-4082ff3878c60020
-7fe3fb7838210060
-0000000048001d98
-0000048001000000
-3842a2a83c4c0001
-7d9080267c0802a6
-48001d2191810008
-2e250000f821ff71
-4192001c7c7e1b78
-7c641b787c852378
-38637e003c62ffff
-600000004bfff2b5
-3f62ffff7fc3f378
-3b8000204bfffa61
-3b7b7e103ba00000
-7fc3f3783880002a
-388000544bfffcd9
-7fc3f3787c7f1b78
-7d3f1a144bfffcc9
-212900807d240034
-548360265484d97e
-7fa9ea147d234a14
-419200107bbd0020
-4bfff2517f63db78
-7fc3f37860000000
-4bfffa4d3b9cffff
-4082ffa47b9c0021
-3c62ffff41920014
-4bfff22938637e18
-3821009060000000
-818100087fa3eb78
-48001ca87d908120
-0300000000000000
-3c4c000100000580
-7c0802a63842a1bc
-f821ff7148001c39
+7c0004ac4bfffd79
+388000257c60ee2a
+4bfffbdd5463063e
+4bfffe3d3860000f
+6129100c3d20c800
+7c0004ac79290020
+3d20c8007fe04f2a
+7929002061291010
+7fe04f2a7c0004ac
+23de00013860000b
+3860000f4bfffb5d
+3d00c8004bfffe01
+610810183c80c800
+3ca033333d605555
+608410783c000f0f
+7908002038c00000
+616b555538610030
+60000f0f60a53333
+7c0004ac78840020
+394100307d20462a
+392000047d20552c
+7d2903a639400000
+552907fe7d265214
+408200547c09f000
+7d3c50ae7cea18ae
+5527063e7d293a78
+7d2958387929fe62
+7d2728387d293850
+7d2928385529f0be
+54e9e13e7ce74a14
+7d2900387d293a14
+7d293a145527c23e
+7d293a145527843e
+7fff4a14552906be
+4200ff9c394a0001
+3b9c000439080018
+38c600047c282000
+382100604082ff6c
+48001c0c7be30020
+0100000000000000
+3c4c000100000480
+7c0802a63842a19c
+f821ff7148001b99
 7c7f1b783ba00000
-3880002a4bfff9a1
-4bfffc257fe3fb78
-7c7e1b7838800054
-4bfffc157fe3fb78
-7d3c07b4393d0001
-2c0300007c7e1a14
-2c0900204182001c
-7fe3fb784182007c
-4bfff9ad7f9de378
-7fbeeb784bffffbc
-3b5d00017fe3fb78
-7f5a07b44bfff999
-3880002a3b60ffff
-4bfffbc57fe3fb78
-7c7c1b7838800054
-4bfffbb57fe3fb78
-2c0300007c7c1a14
-2c1bffff41820010
-7f5bd37840820008
-2c09001f393a0001
-4181001c7d3a07b4
-4bfff9457fe3fb78
-7f9de3784bffffb4
-4bffff943bc0ffff
-395d00022c1d001e
-4181000839200000
-2c1bffff213d001e
-7d2907b47d295214
-7d3b4b7840820008
-7fbeda142c1effff
+3880002a4bfffb35
+4bfffd297fe3fb78
+3b9d000138800054
+7fe3fb787c7e1b78
+7c63f2144bfffd15
+4182001c2c030000
+418200742c1c0020
+7f9de3787fe3fb78
+4bffffc04bfffb41
+7fe3fb787fbeeb78
+4bfffb2d3b7d0001
+3880002a3b80ffff
+4bfffcd17fe3fb78
+7c7a1b7838800054
+4bfffcc17fe3fb78
+2c0300007c63d214
+2c1cffff41820010
+7f7cdb7840820008
+2c1b001f3b7b0001
+7fe3fb784181001c
+4bffffb84bfffae1
+3bc0ffff3ba00020
+2c1d001e4bffff9c
+39200000395d0002
+213d001e41810008
+7d2952142c1cffff
+7d3c4b7840820008
+7fbee2142c1effff
 7fbd01947fbd0e70
-408200387bbd06e0
-38637e203c62ffff
-600000004bfff0dd
+4082003857bd06fe
+38637d783c62ffff
+600000004bfff2cd
 3bc000007fe3fb78
-386000644bfff889
-7c1df0004bfffad5
+386000644bfffa2d
+7c1df0004bfffbe9
 3821009040820034
-7cbed85048001b48
+7cbee05048001ab8
 7ca50e703c62ffff
-7fa4eb787ca50194
-7ca507b438637e30
-600000004bfff095
+7fa407b47ca50194
+7ca507b438637d88
+600000004bfff285
 7fe3fb784bffffb8
-4bfff88d3bde0001
-7fde07b438600064
-4bffffb04bfffa85
-0100000000000000
-3c4c000100000680
-3d40c8003842a01c
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c09000e
-f80100107c0802a6
-3920000ef821ffa1
-7d20572a7c0004ac
-38637e483c62ffff
-600000004bfff01d
-e801001038210060
-4e8000207c0803a6
+4bfffa2d3bde0001
+4bfffb9d38600064
+000000004bffffb4
+0000068001000000
+3842a0103c4c0001
+612910003d20c800
+7c0004ac79290020
+280a000e7d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac3940000e
+3c62ffff7d404f2a
+4bfff21138637da0
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429fa83c4c0001
+612910003d20c800
+7c0004ac79290020
+280a00017d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac39400001
+3c62ffff7d404f2a
+4bfff1a938637dc8
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429f403c4c0001
+4800190d7c0802a6
+3f80c800f821ff01
+3ea2ffff3f00c800
+3e62ffff3e82ffff
+639c08103f22ffff
+3e42ffff63180820
+3b4000013ba00000
+3ab57df03ae00000
+3a737e083a947e00
+7b9c00203b397b28
+3a527e107b180020
+7fb0eb787ba307e0
+7f56e8304bfff925
+3a2000003be00000
+7fbe07b439e00000
+7fc4f3787de507b4
+39c000207ea3ab78
+600000004bfff0f5
+3b6000007fc3f378
+3880002a4bfff855
+4bfffa497fc3f378
+39ceffff38800054
+7fc3f378f8610060
+e92100604bfffa35
+7c6400347c634a14
+5484d97e20630080
+7c8407b454896026
+7e83a3787d291a14
+4bfff0997f7b4a14
+7fc3f37860000000
+2c0e00004bfff849
+7e639b784082ffa4
+600000004bfff07d
+4bfffc997fc3f378
+4bfff0697f23cb78
+7c11d84060000000
+7dff7b784080000c
+2c0f00077f71db78
+7c0004ac4182002c
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+39ef00017ee0e72a
+3ba000014bffff28
+7fe507b44bffff00
+7e4393787fc4f378
+4bfff0117bff0020
+7a0307e060000000
+393f00014bfff80d
+420000287d2903a6
+4bfffc197fc3f378
+4bffefe97f23cb78
+2c1d000160000000
+382101004082ffb4
+7c0004ac480017b8
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+4bffffc07ee0e72a
 0100000000000000
-3c4c000100000080
-3d40c80038429fb4
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c090001
-f80100107c0802a6
-39200001f821ffa1
-7d20572a7c0004ac
-38637e703c62ffff
-600000004bffefb5
-e801001038210060
+3c4c000100001280
+7c0802a638429d64
+f821ffa1f8010010
+386000004bfffd49
+386000004bfff6fd
+386000014bfff78d
+386000014bfff6ed
+3c62ffff4bfff77d
+4bffef6938637e28
+4bfffde560000000
+382100604bfffd79
+e801001038600001
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429f4c
-f821ff61480019c1
-3f42ffff3be00000
-3b5a7ba83f02ffff
-57fd063e3b187e98
-7fa3eb783b600000
-4bfff7b53b200000
-38a000013bc00000
-7fe3fb787fc4f378
-7c7c1b784bfffc61
-4bfffd417fe3fb78
-4bffef317f43d378
-7c19e04060000000
-7fdbf3784080000c
-2c1e00077f99e378
-7fa3eb7841820020
-4bfff7b13bde0001
-4bffffb07fde07b4
-4bffff903be00001
-7fe4fb787f65db78
-3bc000007f03c378
-600000004bffeee5
-4bfff7357fa3eb78
-408200287c1ed800
-4bfffcd17fe3fb78
-4bffeec17f43d378
-2c1f000160000000
-382100a04082ffb8
-7fa3eb7848001938
-4bfff7493bde0001
-4bffffc47fde07b4
-0100000000000000
-3c4c000100000880
-7c0802a638429e44
-f821ff1148001895
-4bfffe193f60c800
-3f20c80038600000
-386000004bfff621
-4bfff6b53ee0c800
-637b101038600001
-386000014bfff609
-4bfff69d63391024
-62f710283c62ffff
-3ec2ffff38637eb0
-600000004bffee2d
-3be000003ea2ffff
-7b7b00203ba00001
-7af700207b390020
-3ad67ed83b000000
-7ffa07b43ab57ed0
-7fb1f8307fb2f830
-3a6000003b80ffff
-57f4063e3bc00000
-7e20df2a7c0004ac
-7fa0cf2a7c0004ac
-392900017bc90020
-420000f47d2903a6
-7f00df2a7c0004ac
-3a0000007e83a378
-39e000004bfff611
-7de47b7838a00000
-4bfffabd7f43d378
-7c691b787c038040
-7e09837840800008
-793000207e83a378
-392f00014bfff62d
-7d2f07b42c090008
-7c1098404082ffc8
-7fdcf3784081000c
-393e00027e138378
-7d3e07b42c090008
-600000004082ff70
-7be91764394280d0
-2c1e00007fca4aaa
-2c1cffff40800078
-7f44d3784082006c
-4bffed297ea3ab78
-7f9ee37860000000
-7e40df2a7c0004ac
-7fa0cf2a7c0004ac
-7bc900202c1e0000
-4080000839290001
-2c29000139200001
-408200443929ffff
-7f00df2a7c0004ac
-41820040283f0001
-4bfffed83be00001
-7fa0bf2a7c0004ac
-7f9ee3784bffff04
-7f44d3787fc5f378
-4bffecb97ec3b378
-4bffff9460000000
-7fa0bf2a7c0004ac
-3c62ffff4bffffac
-4bffec9938637ba8
-3c62ffff60000000
-4bffec8938637ee0
-4bfffcf960000000
-382100f04bfffc8d
-480016d838600001
-0100000000000000
-3c4c000100001180
-7c0802a638429c1c
-f821ff6148001691
-6129102c3d20c800
-792900203b200002
+7c0802a638429cf4
+f821ff51480016e5
+6129082c3d20c800
+792900203b000002
+7f004f2a7c0004ac
+3b2000033d20c800
+7929002061290830
 7f204f2a7c0004ac
-3b4000033d20c800
-7929002061291030
-7f404f2a7c0004ac
 3c62ffff3fc0c800
-38637ef03c804000
-4bffec0963de1000
-3ba0000160000000
-7bde00204bfffba5
-7fa0f72a7c0004ac
+38637e383c804000
+4bffeee163de0800
+3b80000160000000
+7bde00204bfffc89
+7f80f72a7c0004ac
 3be00000386003e8
-7c0004ac4bfff5f5
-3f80c8007fe0f72a
-639c0800386003e8
-7b9c00204bfff5dd
-7fe0e72a7c0004ac
-637b08043f60c800
+7c0004ac4bfff7f1
+386003e87fe0f72a
+4bfff7dd3f60c800
 7c0004ac7b7b0020
-3fc0c8007fe0df2a
-63de001438600000
-7bde00204bfff231
-7fe0f72a7c0004ac
-3920000c3f00c800
-7c0004ac7b180020
-386000007d20c72a
-4bfff5816063c350
-4bfff1fd38600000
+3f40c8007fe0df2a
+7b5a0020635a0004
+7fe0d72a7c0004ac
+63bd100c3fa0c800
+7c0004ac7bbd0020
+3fc0c8007fe0ef2a
+7bde002063de1010
 7fe0f72a7c0004ac
-7c0004ac3920000e
-386027107d20c72a
-386002004bfff55d
-7c0004ac4bfff1d9
+3920000c3ee0c800
+7af7002062f71000
+7d20bf2a7c0004ac
+6063c35038600000
+7c0004ac4bfff771
+7c0004ac7fe0ef2a
+3920000e7fe0f72a
+7d20bf2a7c0004ac
+4bfff74d38602710
+7c0004ac39200200
+7c0004ac7d20ef2a
+3860000f7f00f72a
+7c0004ac4bfff485
+7c0004ac7fe0ef2a
 3860000f7f20f72a
-386000004bfff205
-7c0004ac4bfff1c1
-3860000f7f40f72a
-386000064bfff1ed
-7c0004ac4bfff1a9
-3860000f7fa0f72a
-386009304bfff1d5
-7c0004ac4bfff191
+392000064bfff46d
+7d20ef2a7c0004ac
+7f80f72a7c0004ac
+4bfff4513860000f
+7c0004ac39200930
+7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff1bd
-386004004bfff4f5
-7c0004ac4bfff171
-386000037fe0f72a
-386000c84bfff19d
-4bfffc414bfff4d5
-3c8000204bfffacd
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100a07fa0e72a
-38c0000048001518
-3c80002038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000088001000000
-38429a103c4c0001
+386000c84bfff435
+392004004bfff6d9
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfff41138600003
+4bfff6b5386000c8
+4bfffb954bfffddd
+3c6040003c800020
+6000000048000779
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100b07f80df2a
+480015487d2307b4
+38a0000038c00000
+3c6040003c800020
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000980
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+38429a883c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637f103c62ffff
-600000004bffea2d
+38637e583c62ffff
+600000004bffeca5
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffe9f138637f18
+4bffec6938637e60
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637f28
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e70
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637f387ca54b92
+38637e807ca54b92
 000000004bffffa4
 0000008001000000
-384299403c4c0001
+384299b83c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bffe95138637f48
+4bffebc938637e90
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffe93938637f58
+4bffebb138637ea0
 3821007060000000
-00000000480013e8
+00000000480013e0
 0000018001000000
-384298d83c4c0001
-4800135d7c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bffe959
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bffe929
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d000048001330
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+384299503c4c0001
+480013557c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bffebc9
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bffeb79
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f8
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384297f03c4c0001
-480012797c0802a6
+384298403c4c0001
+480012497c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
-4bffe8657bff0020
-395f000160000000
-7d4903a62fbe0000
+420000387cbd2b78
+4bffeabd7bff0020
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126838210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e00284800123c
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a6384296ec
-480011557d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67f60
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384297583c4c0001
+7d8000267c0802a6
+918100084800113d
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67ea8
 3c62ffff4082009c
-38637f607b251028
-4bfffd357ba40020
-38637ba83c62ffff
-600000004bffe6a5
-4bffe70d3ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637f7078a51028
-4bfffccd7ba40020
-38637ba83c62ffff
-600000004bffe63d
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637f707ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fac7d838120
+38637ea87b851028
+4bfffd357b240020
+38637b283c62ffff
+600000004bffe91d
+600000004bffe989
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637eb87b051028
+4bfffcdd7be40020
+38637b283c62ffff
+600000004bffe8c5
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010ac
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637eb87ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a6384294d4
+3c4c000100000b80
+7c0802a638429594
 918100087d908026
-f821ff8148000f51
+f821ff7148000f89
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637f80
-600000004bffe4dd
-38637f983c62ffff
+7cbc2b7838637ec8
+600000004bffe79d
+38637ee03c62ffff
 3c62ffff4092000c
-4bffe4c138637fa8
+4bffe78138637ef0
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637fb83c62ffff
-600000004bffe4a5
+4bfffaad7bfde8c2
+38637f003c62ffff
+600000004bffe765
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1403,467 +1315,475 @@ f821ff8148000f51
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637fc0
-600000004bffe455
-4bfff9fd7f83e378
-38637fd03c62ffff
-600000004bffe43d
-38637ba83c62ffff
-600000004bffe42d
-600000004bffe499
-409200287cf602a6
+7f9c4b9238637f08
+600000004bffe715
+4bfffa457f83e378
+38637f183c62ffff
+600000004bffe6fd
+38637b283c62ffff
+600000004bffe6ed
+600000004bffe759
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637fd8
-600000004bffe3a5
-4bfff94d7fe3fb78
-38637fd03c62ffff
-600000004bffe38d
-38637ba83c62ffff
-600000004bffe37d
-8181000838210080
-48000e047d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a6384292cc
-f821ff7148000d49
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f8000
-3b60ffff4081000c
-3c62ffff577b0420
-38637fe87fc4f378
-600000004bffe2c5
-4bfff86d7fe3fb78
-38637fb83c62ffff
-600000004bffe2ad
-7fc3f3787f44d378
-38a000004bfff989
-7c7c1b787f64db78
-4bfffa5d7fc3f378
-38a0000138c00000
-7c7d1b787fe4fb78
-4bfffb497fc3f378
-7d291a147d3cea14
-2c0900007c7e1b78
-3c62ffff41820068
-7f84e3787b45f882
-4bffe24938637ff8
-6000000060000000
-7fa4eb787b65f082
-4bffe23138628010
-6000000060000000
-7fc4f3787be5f082
-4bffe21938628028
-6000000060000000
-4bffe20938628040
-3860000060000000
-48000c8c38210090
-3862805060000000
-600000004bffe1ed
-4bffffe438600001
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f20
+600000004bffe675
+4bfff9a57fe3fb78
+38637f183c62ffff
+600000004bffe65d
+38637b283c62ffff
+600000004bffe64d
+8181000838210090
+48000e4c7d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384293b83c4c0001
+48000db57c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f80007c9a2378
+4081000c7ffbfb78
+577b04203b60ffff
+7fc4f3783c62ffff
+4bffe5b138637f30
+7fe3fb7860000000
+3c62ffff4bfff8e1
+4bffe59938637f00
+7f44d37860000000
+4bfff9fd7fc3f378
+7f64db7838a00000
+7fc3f3787c7c1b78
+38c000004bfffaf9
+7fe4fb7838a00001
+7fc3f3787c7d1b78
+7d3de2144bfffbc9
+7c7e1b787d291a14
+4182006c2c090000
+7b45f8823c62ffff
+38637f407f84e378
+600000004bffe535
+7b65f0823c62ffff
+38637f587fa4eb78
+600000004bffe51d
+7be5f0823c62ffff
+38637f707fc4f378
+600000004bffe505
+38637f883c62ffff
+600000004bffe4f5
+3821009038600000
+48000cf47c6307b4
+38637f983c62ffff
+600000004bffe4d5
+4bffffe038600001
 0100000000000000
 3c4c000100000680
-600000003842918c
-6000000039228114
-89290000394280c8
-4182002c2c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-7c0004ace92a0000
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-e94a00005469063e
-7d2057ea7c0004ac
-000000004e800020
+6000000038429274
+6000000089228018
+2c09000039428010
+e92a00004182002c
+7c0004ac39290014
+712900207d204eaa
+e92a00004182ffec
+7c604faa7c0004ac
+e92a00004e800020
+7c0004ac39290010
+712900087d204eea
+5469063e4082ffec
+7c0004ace94a0000
+4e8000207d2057ea
 0000000000000000
-384291083c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-3be3fffff821ffd1
-2c3e00008fdf0001
-3821003040820010
-48000bd038600000
-4082000c281e000a
-4bffff413860000d
-4bffff397fc3f378
-000000004bffffd0
-0000028001000000
-384290a83c4c0001
-610800203d00c000
-7c0004ac79080020
-3d20c0007d0046ea
-6129000879080600
-7c0004ac79290020
-712900207d204eea
-3d20c00041820018
-7929002061290040
+3c4c000100000000
+7c0802a6384291f4
+fbe1fff8fbc1fff0
+f821ffd1f8010010
+8fdf00013be3ffff
+408200102c1e0000
+3860000038210030
+2c1e000a48000c3c
+3860000d4082000c
+7fc307b44bffff45
+4bffffd04bffff3d
+0100000000000000
+3c4c000100000280
+3d40c00038429194
+794a0020614a0020
+7d4056ea7c0004ac
+794a06003d20c000
+7929002061290008
 7d204eea7c0004ac
-600000003d40c000
-38e2811460000000
-794a0020614a2000
-3d40001cf94280c8
-7d085392614a2000
-794a0fc3792af804
-3920000141820080
-614a200c3d40c000
-794a002099270000
-7c0004ac3920ff80
-e92280c87d2057aa
-7d004faa7c0004ac
-7908c202e92280c8
+4182001871290020
+612900403d20c000
+7c0004ac79290020
+7929f8047d204eea
+79290fc33d00c000
+7908002061082000
+f902801060000000
+610820003d00001c
+418200847d4a4392
+3920000160000000
+3d00c00099228018
+3920ff806108200c
+7c0004ac79080020
+e92280107d2047aa
+7d404faa7c0004ac
+794ac202e9228010
 7c0004ac39290004
-e92280c87d004faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e92280c8
+39290010e9228010
 7d404faa7c0004ac
-39400007e92280c8
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
-994700003d20c000
-612920183908ffff
-7c0004ac79290020
-4e8000207d004fea
+394affff60000000
+3d20c00099228018
+7929002061292018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9072442000028
+7d434a147ca92850
+7c844a1439050001
+392000007d0903a6
+4e80002042000018
+7d23512a7d24502a
+4bffffcc394a0008
+7d0a49ae7d0448ae
+4bffffdc39290001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 2c24000000000000
 3881fff040820008
 f864000028050024
 4d81002038600000
-78e783e43ce00001
-e944000060e72600
-28090020892a0000
-2c25000040810028
-2c0500104182003c
-3860000041820038
-394a000148000080
-4bffffd0f9440000
-712900017ce94c36
-2c2500004082ffec
-38a0000a4082ffdc
-38a0000a4bffffd4
-4082ffc828090030
-2c090078892a0001
-394a00024082ffbc
-f944000038a00010
-38c9ffd04bffffac
-280a000954ca063e
-7cc9073441810034
-4c8000207c092800
-7c6519d238e70001
-7c691a14f8e40000
-89270000e8e40000
-4082ffc82c290000
-3949ff9f4e800020
-280a0019554a063e
-3929ffa941810010
-4bffffbc7d290734
-554a063e3949ffbf
+6108ffff3d00fffe
+6108d9ff790883e4
+89490000e9240000
+40810028280a0020
+4182003c2c250000
+418200382c050010
+4800008838600000
+f924000039290001
+7d0a56344bffffd0
+4182ffec714a0001
+4082ffdc2c250000
+4bffffd438a0000a
+2c0a003038a0000a
+894900014082ffc8
+4082ffbc2c0a0078
+38a0001039290002
+4bffffacf9240000
+54e7063e38eaffd0
+4181003c28070009
+7d2a07343929ffd0
+4c8000207c0a2800
+7c6519d239080001
+f90400007d290734
+e90400007c691a14
+714900ff89480000
+4e8000204082ffc0
+54e7063e38eaff9f
+4181000c28070019
+4bffffb83929ffa9
+554a063e394affbf
 4d810020280a0019
-4bffffe43929ffc9
+4bffffa03929ffc9
 0000000000000000
-7c6a1b7800000000
-7d2a18ae38600000
-4d8200202c090000
-4bfffff038630001
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000307d2903a6
-78aa072478a9e8c2
-7d0352141d29fff8
-7ca92a147c845214
-3945000139200000
-420000187d4903a6
-7d24502a4e800020
-394a00087d23512a
-7d4448ae4bffffc4
-392900017d4849ae
-000000004bffffdc
-0000000000000000
-280900193923ff9f
-3863ffe04d810020
-4e8000207c6307b4
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428da4
-918100087d908026
-f821ffa148000819
-7c7c1b783be00000
-600000007cbe2b78
-7cdd3378e9228060
-60000000f9210020
-f9210028e9228068
-2c2900007ca92b78
-2c3f000040820034
-3be0000140820008
-2e2700007c3f2040
-3b7fffff38600000
-3821006040810038
-7d90812081810008
-281d001048000800
-7929e10240820014
-7fff07b43bff0001
-7d29eb924bffffb4
-7f5ed3784bfffff0
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-600000004bffff21
-7c3df0405463063e
-7c69d9aee93c0000
-4081ffc83b7bffff
-38600001e93c0000
-fbfc00007fe9fa14
-000000004bffff84
-0000068003000000
-38428ca83c4c0001
-480007297c0802a6
+38428e903c4c0001
+480008897c0802a6
+7c7e1b78f821ffa1
+7ca32b787c9c2378
+38a0000a38800000
+eb3e00007cfd3b78
+7d3a4b787d1b4378
+4bfffe797cdf3378
+2b9d001060000000
+7c681b7839200000
+408200242c3f0000
+408200082c090000
+7d29d21439200001
+418100547c034800
+4800087038210060
+7bffe102409e0010
+4bffffcc39290001
+4bfffff47fffeb92
+2c2a00019b690000
+e93e0000394affff
+f93e000039290001
+e93e00004182ffc8
+7c28e0407d194850
+4bffffb44180ffd8
+2c0900007d294050
+794a00203949ffff
+40810010394a0001
+7c0940003d008000
+394000014082ffcc
+000000004bffffc4
+0000078001000000
+38428d983c4c0001
+480007997c0802a6
 3bc00000f821ffb1
 7c9c23787c7f1b78
 7cbd2b78eb630000
-4bfffe217fa3eb78
-7c23f04060000000
-e95f000040810014
-7c29e0407d3b5050
-3821005041800010
-4800073038600001
-3bde00017d3df0ae
-e93f0000992a0000
-f93f000039290001
-000000004bffffb8
-0000058001000000
-38428c283c4c0001
-480006a17c0802a6
-7c7d1b78f821ffa1
-7ca32b787c9b2378
-38a0000a38800000
-eb3d00007d3f4b78
-7cfc3b787cde3378
-4bfffc717d1a4378
-3920000060000000
-2c3e00007c6307b4
-2c2900004082002c
-3920000140820008
-7c0348007d3f4a14
-418100607d2a07b4
-3860000038210060
-281c001048000684
-7bdee10240820014
-7d2907b439290001
-7fdee3924bffffbc
-9b4800004bfffff0
-3929ffff2c290001
-394a0001e95d0000
-4182ffbcf95d0000
-7d594050e91d0000
-4180ffd87c2ad840
-7d4a18504bffffa8
-392affff2c0a0000
-3929000179290020
-3c60800040810010
-4082ffcc7c0a1800
-4bffffc439200001
+4bfffd697fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007a4
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428b24
-f821fed148000571
-f86100607c741b79
-4182006438600000
-4182005c2c240000
-6000000039210040
-3ae4ffff60000000
-3b210020f9210078
-3a4280803ac00000
-3a2280783ba10060
+3c4c000100000580
+7c0802a638428d1c
+918100087d908026
+f821ffa148000711
+2b8600103be00000
+3d22ffff7c7c1b78
+7cbe2b78e9297fa8
+7caa2b787cdd3378
+3d22fffff9210020
+f9210028e9297fb0
+408200342c2a0000
+408200082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8181000838210060
+480006f47d908120
+794ae102409e0010
+4bffffbc3bff0001
+4bfffff47d4aeb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdad
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428c283c4c0001
+480005f57c0802a6
+3be00000f821fee1
+f86100607c691b79
+41820060f9210068
+418200582c240000
+3e62ffff39210040
+3ae4ffff3e22ffff
+3b010020f9210070
+3a4000203ac00000
+3ba100603a737fc8
+e94100683a317fc0
 ebc1006089250000
-418200102c290000
-7c3fb8407ff4f050
-3920000041800020
-e8610060993e0000
-7e8307b47e941850
-4800054438210130
-3945000128090025
-38e00000408204c4
-e901007889250000
-7cea07b4f8a10068
-390700017d2741ae
-7d0807b48d250001
-4182005828090064
-4182005028090069
-4182004828090075
-4182004028090078
-4182003828090058
-4182003028090070
-4182002828090063
-4182002028090073
-4182001828090025
-418200102809004f
-38e700012809006f
-394a00024082ff88
-7d4a07b428090025
-7d5952147d194214
-9aca002099280020
-393e000140820020
-39200025f9210060
-e9210068993e0000
-4bffff0438a90002
-eb66000039260008
-3a6000207fffb850
-f92100703b010041
-3929ffd289210041
+712a00ff7feaf050
+7c3fb8404182000c
+3920000041800018
+38210120993e0000
+480005c47fe307b4
+390500012c0a0025
+38e0000040820548
+e901007089250000
+7cea3b787cb02b78
+7d2741ae8c650001
+5469063e39070001
+418200b02c090064
+4181002c28090078
+4181002c28090068
+418200982c090058
+4181008828090058
+418200882c090025
+418200802c09004f
+4bffffa438e70001
+548b063e3883ff97
+4181ffec280b000f
+396b75043d62ffff
+7c8b22aa788415a8
+7c8903a67c845a14
+000000484e800420
+ffffffccffffffcc
+ffffffccffffffcc
+00000048ffffffcc
+ffffffcc00000048
+00000048ffffffcc
+00000048ffffffcc
+ffffffccffffffcc
+2c09006300000048
+394a00024bffff84
+7d0807b42c090025
+7d1842147d4a07b4
+986800207d585214
+408200189aca0020
+993e0000395e0001
+38b00002f9410060
+892100414bfffeb4
+7fffb850eb860000
+3aa0002039e60008
+3929ffd23b210041
 4082000c712900fd
-3b0100423a600030
-3b4000043aa00000
-3a0000013b800000
-7ddb00d039e0002d
-2809004f48000164
-3898000188f80001
-38c9ffa8418201d0
-2805002254c5063e
-3ca2ffff41810370
-78c615a838a576b8
-7cc62a147cc532aa
-4e8004207cc903a6
-0000035000000148
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000024400000350
-000003500000008c
-0000035000000350
-0000008c00000338
-0000035000000350
-0000035000000328
-000001a000000350
-00000350000001ec
-0000028400000350
-0000008c00000350
-0000035000000350
-000003500000014c
-2809007500000330
-9aca00207d41e214
-418200347f6adb78
-3929ffff57491838
-7f6948397e094836
-99e8000041820020
-39290001e9210060
-7b491f24f9210060
-7dca50387d52482a
+3b2100423aa00030
+3b4000043a800000
+56b5063e3b600000
+480001687ddc00d0
+38b900012c06004f
+38e8ffa8418201dc
+2804002254e4063e
+3c82ffff418103ac
+78e715a838847600
+7ce722147ce43aaa
+4e8004207ce903a6
+0000038c00000150
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+000002580000038c
+0000038c0000008c
+0000038c0000038c
+0000008c00000370
+0000038c0000038c
+0000038c0000035c
+000001ac0000038c
+0000038c000001fc
+000002980000038c
+0000008c0000038c
+0000038c0000038c
+0000038c00000154
+2c06007500000368
+7d4152147b6a0020
+7f8ae3789aca0020
+5747183841820038
+38e7ffff39000001
+7f8840397d083836
+3940002d41820020
+9949ffff39290001
+7b491e68f9210060
+7dca50387d53482a
 7d465378e8810060
-f941008038e0000a
-392000007f25cb78
-7fa3eb787e689b78
+f941007838e0000a
+392000007f05c378
+7fa3eb787ea8ab78
 7c84f8507c9e2050
-e88100604bfffc31
-7ea7ab78e9410080
+e88100604bfffa79
+7a8707e0e9410078
 7c9e205038c0000a
 7c84f8507d455378
-4bfffa917fa3eb78
-893800003b180001
-2c290000e9010060
-7d5e405041820010
-4181fe887c3f5040
-4bfffe28e8c10070
-7d21e2143aa00001
-7c8af85038e00010
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffba9
-38c000107ea7ab78
-e96100807c9e2050
-4bffff787d655b78
-38e000087d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffb55f9610080
-7ea7ab78e8810060
+4bfffbc97fa3eb78
+891900003b390001
+710600ffe9210060
+7d5e485041820010
+4181fe847c3f5040
+4bfffe307de67b78
+7b6900203a800001
+7d214a1438e00010
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff9edf9610078
+7a8707e0e8810060
+7c9e205038c00010
+7d655b78e9610078
+7b6900204bffff74
+7d214a1438e00008
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff995f9610078
+7a8707e0e8810060
 7c9e205038c00008
-7d21e2144bffffac
-7f66db7838e00010
-9ac900207c8af850
-3920000239000020
-7fa3eb787f25cb78
-e88100604bfffb19
-7fa3eb787e258b78
+7b6900204bffffa8
+7d214a1438e00010
+7c8af8507f86e378
+9ac9002039000020
+392000027f05c378
+4bfff9557fa3eb78
+7e258b78e8810060
+7c9e20507fa3eb78
+4bfffa357c84f850
+7a8707e0e8810060
+7f85e37838c00010
+4bfffec87c9e2050
+390000207b690020
+38e0000a7d214a14
+7f05c37838c00001
+7c8af8509ac90020
+7fa3eb7839200000
+e92100604bfff8f9
+392900019b890000
+4bfffe94f9210060
+38a0000a7b680020
+f9410080f9210088
+388000007d014214
+9ac800207f03c378
+600000004bfff76d
+7f83e378f8610078
+600000004bfff735
+e9410080e9010078
+7c281840e9210088
+e88100604181003c
+7fa3eb787f85e378
 7c84f8507c9e2050
-e88100604bfffa81
-38c000107ea7ab78
-7c9e20507f65db78
-7d21e2144bfffed4
-38e0000a39000020
-9ac9002038c00001
-392000007f25cb78
-7fa3eb787c8af850
-e92100604bfffac1
-e92100609b690000
-f921006039290001
-7d21e2144bfffea0
-f901009038a0000a
-38800000f9410088
-9ac900207f23cb78
-600000004bfff72d
-7f63db78f8610080
-600000004bfff83d
-7c291840e9210080
-7d2348514081004c
-e9010090e9410088
-408200087d4af850
-e8c1006039200001
-7c2a38407ce83050
-38e0002040810024
-3929ffff2c290001
-e8e1006098e60000
-f8e1006038e70001
-e88100604082ffd4
-7fa3eb787f65db78
-7c84f8507c9e2050
-4bfffdfc4bfff989
-418200482807006c
-4bfffdec3b400008
-3b40000228070068
-7c9823784082fde0
-4bfffdd43b400001
-554a063e3949ffd0
-4181fdc4280a0009
-7f81e214395c0001
-795c0020993c0020
-7c9823784bfffdb0
-993e00004bffffb8
-e92100607d455378
-f921006039290001
-000000004bfffae8
+4bfffe2c4bfff979
+392900019a490000
+7c29184039000001
+f921006040820034
+7ce9f0504bffffcc
+7ce7fa147c634050
+2c2700007d4af850
+390000007c691a14
+40820008394a0001
+2c2a000139400001
+4082ffb4394affff
+4082ffc071080001
+893900014bffff8c
+4182004c2c09006c
+4bfffdbc3b400008
+3b40000289390001
+4082fdac2c090068
+3b4000017cb92b78
+3928ffd04bfffda0
+280900095529063e
+7b6900204181fd90
+7d214a143b7b0001
+4bfffd7c99090020
+4bffffb47cb92b78
+3bde0001993e0000
+fbc100607d054378
+000000004bfffa6c
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -1938,9 +1858,8 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -1982,10 +1901,6 @@ ebe1fff8e8010010
 20676e69746f6f42
 415244206d6f7266
 0000000a2e2e2e4d
-62202c64256d2020
-007c203a64323025
-0000000000006425
-000000000000207c
 203a7379616c6564
 000000000000002d
 203a7379616c6564
@@ -2001,15 +1916,13 @@ ebe1fff8e8010010
 7764726168206f74
 746e6f6320657261
 0000000a2e6c6f72
+62202c64256d2020
+007c203a64323025
+0000000000006425
+000000000000207c
 203a747365622020
 302562202c64256d
 6000000000206432
-616c206574697257
-61632079636e6574
-6f6974617262696c
-00000000000a3a6e
-0000202d3a64256d
-002064253a64256d
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index 1a0ab93..e3f6682 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -1,9 +1,25 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:33
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire clk,
-	input wire rst,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:10
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire clk,
+	input  wire rst,
 	output wire pll_locked,
 	output wire [14:0] ddram_a,
 	output wire [2:0] ddram_ba,
@@ -12,9 +28,9 @@ module litedram_core(
 	output wire ddram_we_n,
 	output wire ddram_cs_n,
 	output wire [1:0] ddram_dm,
-	inout wire [15:0] ddram_dq,
-	inout wire [1:0] ddram_dqs_p,
-	inout wire [1:0] ddram_dqs_n,
+	inout  wire [15:0] ddram_dq,
+	inout  wire [1:0] ddram_dqs_p,
+	inout  wire [1:0] ddram_dqs_n,
 	output wire ddram_clk_p,
 	output wire ddram_clk_n,
 	output wire ddram_cke,
@@ -22,32 +38,38 @@ module litedram_core(
 	output wire ddram_reset_n,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [24:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [24:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [15:0] user_port_native_0_wdata_we,
-	input wire [127:0] user_port_native_0_wdata_data,
+	input  wire [15:0] user_port_native_0_wdata_we,
+	input  wire [127:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [127:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg  main_rst = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
@@ -55,7 +77,7 @@ wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
 wire main_reset;
-reg main_power_down = 1'd0;
+reg  main_power_down = 1'd0;
 wire main_locked;
 wire main_clkin;
 wire main_clkout0;
@@ -66,48 +88,48 @@ wire main_clkout2;
 wire main_clkout_buf2;
 wire main_clkout3;
 wire main_clkout_buf3;
-reg [3:0] main_reset_counter = 4'd15;
-reg main_ic_reset = 1'd1;
-reg main_a7ddrphy_rst_storage = 1'd0;
-reg main_a7ddrphy_rst_re = 1'd0;
-reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg main_a7ddrphy_wlevel_en_re = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg  [3:0] main_reset_counter = 4'd15;
+reg  main_ic_reset = 1'd1;
+reg  main_a7ddrphy_rst_storage = 1'd0;
+reg  main_a7ddrphy_rst_re = 1'd0;
+reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
+reg  main_a7ddrphy_wlevel_en_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
 wire main_a7ddrphy_wlevel_strobe_r;
-reg main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg main_a7ddrphy_dly_sel_re = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+reg  main_a7ddrphy_dly_sel_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_rst_r;
-reg main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_inc_r;
-reg main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg main_a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg main_a7ddrphy_wrphase_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg  main_a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+reg  main_a7ddrphy_wrphase_re = 1'd0;
 wire [14:0] main_a7ddrphy_dfi_p0_address;
 wire [2:0] main_a7ddrphy_dfi_p0_bank;
 wire main_a7ddrphy_dfi_p0_cas_n;
@@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
 wire main_a7ddrphy_dfi_p0_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
 wire main_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p0_rddata_valid;
 wire [14:0] main_a7ddrphy_dfi_p1_address;
 wire [2:0] main_a7ddrphy_dfi_p1_bank;
@@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
 wire main_a7ddrphy_dfi_p1_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
 wire main_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p1_rddata_valid;
 wire [14:0] main_a7ddrphy_dfi_p2_address;
 wire [2:0] main_a7ddrphy_dfi_p2_bank;
@@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
 wire main_a7ddrphy_dfi_p2_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
 wire main_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p2_rddata_valid;
 wire [14:0] main_a7ddrphy_dfi_p3_address;
 wire [2:0] main_a7ddrphy_dfi_p3_bank;
@@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
 wire main_a7ddrphy_dfi_p3_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
 wire main_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p3_rddata_valid;
 wire main_a7ddrphy_sd_clk_se_nodelay;
-reg main_a7ddrphy_dqs_oe = 1'd0;
+reg  main_a7ddrphy_dqs_oe = 1'd0;
 wire main_a7ddrphy_dqs_preamble;
 wire main_a7ddrphy_dqs_postamble;
 wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_dqspattern0 = 1'd0;
-reg main_a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dqspattern0 = 1'd0;
+reg  main_a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
 wire main_a7ddrphy_dqs_o_no_delay0;
 wire main_a7ddrphy_dqs_t0;
-reg [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
 wire main_a7ddrphy0;
 wire main_a7ddrphy_dqs_o_no_delay1;
 wire main_a7ddrphy_dqs_t1;
-reg [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
 wire main_a7ddrphy1;
-reg [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
 wire main_a7ddrphy_dq_oe;
 wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
 wire main_a7ddrphy_dq_o_nodelay0;
 wire main_a7ddrphy_dq_i_nodelay0;
 wire main_a7ddrphy_dq_i_delayed0;
 wire main_a7ddrphy_dq_t0;
-reg [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip03;
-reg [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay1;
 wire main_a7ddrphy_dq_i_nodelay1;
 wire main_a7ddrphy_dq_i_delayed1;
 wire main_a7ddrphy_dq_t1;
-reg [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip13;
-reg [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay2;
 wire main_a7ddrphy_dq_i_nodelay2;
 wire main_a7ddrphy_dq_i_delayed2;
 wire main_a7ddrphy_dq_t2;
-reg [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip21;
-reg [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay3;
 wire main_a7ddrphy_dq_i_nodelay3;
 wire main_a7ddrphy_dq_i_delayed3;
 wire main_a7ddrphy_dq_t3;
-reg [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip31;
-reg [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay4;
 wire main_a7ddrphy_dq_i_nodelay4;
 wire main_a7ddrphy_dq_i_delayed4;
 wire main_a7ddrphy_dq_t4;
-reg [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip41;
-reg [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay5;
 wire main_a7ddrphy_dq_i_nodelay5;
 wire main_a7ddrphy_dq_i_delayed5;
 wire main_a7ddrphy_dq_t5;
-reg [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip51;
-reg [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay6;
 wire main_a7ddrphy_dq_i_nodelay6;
 wire main_a7ddrphy_dq_i_delayed6;
 wire main_a7ddrphy_dq_t6;
-reg [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip61;
-reg [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay7;
 wire main_a7ddrphy_dq_i_nodelay7;
 wire main_a7ddrphy_dq_i_delayed7;
 wire main_a7ddrphy_dq_t7;
-reg [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip71;
-reg [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay8;
 wire main_a7ddrphy_dq_i_nodelay8;
 wire main_a7ddrphy_dq_i_delayed8;
 wire main_a7ddrphy_dq_t8;
-reg [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip81;
-reg [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay9;
 wire main_a7ddrphy_dq_i_nodelay9;
 wire main_a7ddrphy_dq_i_delayed9;
 wire main_a7ddrphy_dq_t9;
-reg [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip91;
-reg [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay10;
 wire main_a7ddrphy_dq_i_nodelay10;
 wire main_a7ddrphy_dq_i_delayed10;
 wire main_a7ddrphy_dq_t10;
-reg [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip101;
-reg [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay11;
 wire main_a7ddrphy_dq_i_nodelay11;
 wire main_a7ddrphy_dq_i_delayed11;
 wire main_a7ddrphy_dq_t11;
-reg [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip111;
-reg [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay12;
 wire main_a7ddrphy_dq_i_nodelay12;
 wire main_a7ddrphy_dq_i_delayed12;
 wire main_a7ddrphy_dq_t12;
-reg [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip121;
-reg [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay13;
 wire main_a7ddrphy_dq_i_nodelay13;
 wire main_a7ddrphy_dq_i_delayed13;
 wire main_a7ddrphy_dq_t13;
-reg [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip131;
-reg [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay14;
 wire main_a7ddrphy_dq_i_nodelay14;
 wire main_a7ddrphy_dq_i_delayed14;
 wire main_a7ddrphy_dq_t14;
-reg [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip141;
-reg [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay15;
 wire main_a7ddrphy_dq_i_nodelay15;
 wire main_a7ddrphy_dq_i_delayed15;
 wire main_a7ddrphy_dq_t15;
-reg [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip151;
-reg [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 wire [14:0] main_litedramcore_inti_p0_address;
 wire [2:0] main_litedramcore_inti_p0_bank;
-reg main_litedramcore_inti_p0_cas_n = 1'd1;
-reg main_litedramcore_inti_p0_cs_n = 1'd1;
-reg main_litedramcore_inti_p0_ras_n = 1'd1;
-reg main_litedramcore_inti_p0_we_n = 1'd1;
+reg  main_litedramcore_inti_p0_cas_n = 1'd1;
+reg  main_litedramcore_inti_p0_cs_n = 1'd1;
+reg  main_litedramcore_inti_p0_ras_n = 1'd1;
+reg  main_litedramcore_inti_p0_we_n = 1'd1;
 wire main_litedramcore_inti_p0_cke;
 wire main_litedramcore_inti_p0_odt;
 wire main_litedramcore_inti_p0_reset_n;
-reg main_litedramcore_inti_p0_act_n = 1'd1;
+reg  main_litedramcore_inti_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p0_wrdata;
 wire main_litedramcore_inti_p0_wrdata_en;
 wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
 wire main_litedramcore_inti_p0_rddata_en;
-reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
+reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p1_address;
 wire [2:0] main_litedramcore_inti_p1_bank;
-reg main_litedramcore_inti_p1_cas_n = 1'd1;
-reg main_litedramcore_inti_p1_cs_n = 1'd1;
-reg main_litedramcore_inti_p1_ras_n = 1'd1;
-reg main_litedramcore_inti_p1_we_n = 1'd1;
+reg  main_litedramcore_inti_p1_cas_n = 1'd1;
+reg  main_litedramcore_inti_p1_cs_n = 1'd1;
+reg  main_litedramcore_inti_p1_ras_n = 1'd1;
+reg  main_litedramcore_inti_p1_we_n = 1'd1;
 wire main_litedramcore_inti_p1_cke;
 wire main_litedramcore_inti_p1_odt;
 wire main_litedramcore_inti_p1_reset_n;
-reg main_litedramcore_inti_p1_act_n = 1'd1;
+reg  main_litedramcore_inti_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p1_wrdata;
 wire main_litedramcore_inti_p1_wrdata_en;
 wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
 wire main_litedramcore_inti_p1_rddata_en;
-reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
+reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p2_address;
 wire [2:0] main_litedramcore_inti_p2_bank;
-reg main_litedramcore_inti_p2_cas_n = 1'd1;
-reg main_litedramcore_inti_p2_cs_n = 1'd1;
-reg main_litedramcore_inti_p2_ras_n = 1'd1;
-reg main_litedramcore_inti_p2_we_n = 1'd1;
+reg  main_litedramcore_inti_p2_cas_n = 1'd1;
+reg  main_litedramcore_inti_p2_cs_n = 1'd1;
+reg  main_litedramcore_inti_p2_ras_n = 1'd1;
+reg  main_litedramcore_inti_p2_we_n = 1'd1;
 wire main_litedramcore_inti_p2_cke;
 wire main_litedramcore_inti_p2_odt;
 wire main_litedramcore_inti_p2_reset_n;
-reg main_litedramcore_inti_p2_act_n = 1'd1;
+reg  main_litedramcore_inti_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p2_wrdata;
 wire main_litedramcore_inti_p2_wrdata_en;
 wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
 wire main_litedramcore_inti_p2_rddata_en;
-reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
+reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_inti_p3_address;
 wire [2:0] main_litedramcore_inti_p3_bank;
-reg main_litedramcore_inti_p3_cas_n = 1'd1;
-reg main_litedramcore_inti_p3_cs_n = 1'd1;
-reg main_litedramcore_inti_p3_ras_n = 1'd1;
-reg main_litedramcore_inti_p3_we_n = 1'd1;
+reg  main_litedramcore_inti_p3_cas_n = 1'd1;
+reg  main_litedramcore_inti_p3_cs_n = 1'd1;
+reg  main_litedramcore_inti_p3_ras_n = 1'd1;
+reg  main_litedramcore_inti_p3_we_n = 1'd1;
 wire main_litedramcore_inti_p3_cke;
 wire main_litedramcore_inti_p3_odt;
 wire main_litedramcore_inti_p3_reset_n;
-reg main_litedramcore_inti_p3_act_n = 1'd1;
+reg  main_litedramcore_inti_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p3_wrdata;
 wire main_litedramcore_inti_p3_wrdata_en;
 wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
 wire main_litedramcore_inti_p3_rddata_en;
-reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
+reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p0_address;
 wire [2:0] main_litedramcore_slave_p0_bank;
 wire main_litedramcore_slave_p0_cas_n;
@@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata;
 wire main_litedramcore_slave_p0_wrdata_en;
 wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
 wire main_litedramcore_slave_p0_rddata_en;
-reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p1_address;
 wire [2:0] main_litedramcore_slave_p1_bank;
 wire main_litedramcore_slave_p1_cas_n;
@@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata;
 wire main_litedramcore_slave_p1_wrdata_en;
 wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
 wire main_litedramcore_slave_p1_rddata_en;
-reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p2_address;
 wire [2:0] main_litedramcore_slave_p2_bank;
 wire main_litedramcore_slave_p2_cas_n;
@@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata;
 wire main_litedramcore_slave_p2_wrdata_en;
 wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
 wire main_litedramcore_slave_p2_rddata_en;
-reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [14:0] main_litedramcore_slave_p3_address;
 wire [2:0] main_litedramcore_slave_p3_bank;
 wire main_litedramcore_slave_p3_cas_n;
@@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata;
 wire main_litedramcore_slave_p3_wrdata_en;
 wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
 wire main_litedramcore_slave_p3_rddata_en;
-reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [14:0] main_litedramcore_master_p0_address = 15'd0;
-reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg main_litedramcore_master_p0_cas_n = 1'd1;
-reg main_litedramcore_master_p0_cs_n = 1'd1;
-reg main_litedramcore_master_p0_ras_n = 1'd1;
-reg main_litedramcore_master_p0_we_n = 1'd1;
-reg main_litedramcore_master_p0_cke = 1'd0;
-reg main_litedramcore_master_p0_odt = 1'd0;
-reg main_litedramcore_master_p0_reset_n = 1'd0;
-reg main_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [14:0] main_litedramcore_master_p0_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg  main_litedramcore_master_p0_cas_n = 1'd1;
+reg  main_litedramcore_master_p0_cs_n = 1'd1;
+reg  main_litedramcore_master_p0_ras_n = 1'd1;
+reg  main_litedramcore_master_p0_we_n = 1'd1;
+reg  main_litedramcore_master_p0_cke = 1'd0;
+reg  main_litedramcore_master_p0_odt = 1'd0;
+reg  main_litedramcore_master_p0_reset_n = 1'd0;
+reg  main_litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p0_rddata;
 wire main_litedramcore_master_p0_rddata_valid;
-reg [14:0] main_litedramcore_master_p1_address = 15'd0;
-reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg main_litedramcore_master_p1_cas_n = 1'd1;
-reg main_litedramcore_master_p1_cs_n = 1'd1;
-reg main_litedramcore_master_p1_ras_n = 1'd1;
-reg main_litedramcore_master_p1_we_n = 1'd1;
-reg main_litedramcore_master_p1_cke = 1'd0;
-reg main_litedramcore_master_p1_odt = 1'd0;
-reg main_litedramcore_master_p1_reset_n = 1'd0;
-reg main_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p1_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg  main_litedramcore_master_p1_cas_n = 1'd1;
+reg  main_litedramcore_master_p1_cs_n = 1'd1;
+reg  main_litedramcore_master_p1_ras_n = 1'd1;
+reg  main_litedramcore_master_p1_we_n = 1'd1;
+reg  main_litedramcore_master_p1_cke = 1'd0;
+reg  main_litedramcore_master_p1_odt = 1'd0;
+reg  main_litedramcore_master_p1_reset_n = 1'd0;
+reg  main_litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p1_rddata;
 wire main_litedramcore_master_p1_rddata_valid;
-reg [14:0] main_litedramcore_master_p2_address = 15'd0;
-reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg main_litedramcore_master_p2_cas_n = 1'd1;
-reg main_litedramcore_master_p2_cs_n = 1'd1;
-reg main_litedramcore_master_p2_ras_n = 1'd1;
-reg main_litedramcore_master_p2_we_n = 1'd1;
-reg main_litedramcore_master_p2_cke = 1'd0;
-reg main_litedramcore_master_p2_odt = 1'd0;
-reg main_litedramcore_master_p2_reset_n = 1'd0;
-reg main_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p2_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg  main_litedramcore_master_p2_cas_n = 1'd1;
+reg  main_litedramcore_master_p2_cs_n = 1'd1;
+reg  main_litedramcore_master_p2_ras_n = 1'd1;
+reg  main_litedramcore_master_p2_we_n = 1'd1;
+reg  main_litedramcore_master_p2_cke = 1'd0;
+reg  main_litedramcore_master_p2_odt = 1'd0;
+reg  main_litedramcore_master_p2_reset_n = 1'd0;
+reg  main_litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p2_rddata;
 wire main_litedramcore_master_p2_rddata_valid;
-reg [14:0] main_litedramcore_master_p3_address = 15'd0;
-reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg main_litedramcore_master_p3_cas_n = 1'd1;
-reg main_litedramcore_master_p3_cs_n = 1'd1;
-reg main_litedramcore_master_p3_ras_n = 1'd1;
-reg main_litedramcore_master_p3_we_n = 1'd1;
-reg main_litedramcore_master_p3_cke = 1'd0;
-reg main_litedramcore_master_p3_odt = 1'd0;
-reg main_litedramcore_master_p3_reset_n = 1'd0;
-reg main_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [14:0] main_litedramcore_master_p3_address = 15'd0;
+reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg  main_litedramcore_master_p3_cas_n = 1'd1;
+reg  main_litedramcore_master_p3_cs_n = 1'd1;
+reg  main_litedramcore_master_p3_ras_n = 1'd1;
+reg  main_litedramcore_master_p3_we_n = 1'd1;
+reg  main_litedramcore_master_p3_cke = 1'd0;
+reg  main_litedramcore_master_p3_odt = 1'd0;
+reg  main_litedramcore_master_p3_reset_n = 1'd0;
+reg  main_litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p3_rddata;
 wire main_litedramcore_master_p3_rddata_valid;
 wire main_litedramcore_sel;
 wire main_litedramcore_cke;
 wire main_litedramcore_odt;
 wire main_litedramcore_reset_n;
-reg [3:0] main_litedramcore_storage = 4'd1;
-reg main_litedramcore_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] main_litedramcore_storage = 4'd1;
+reg  main_litedramcore_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector0_command_issue_r;
-reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector0_rddata_we;
-reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector1_command_issue_r;
-reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector1_rddata_we;
-reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector2_command_issue_r;
-reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector2_rddata_we;
-reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector3_command_issue_r;
-reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
-reg main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
+reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector3_rddata_we;
-reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire main_litedramcore_interface_bank0_valid;
 wire main_litedramcore_interface_bank0_ready;
 wire main_litedramcore_interface_bank0_we;
@@ -706,131 +728,131 @@ wire [21:0] main_litedramcore_interface_bank7_addr;
 wire main_litedramcore_interface_bank7_lock;
 wire main_litedramcore_interface_bank7_wdata_ready;
 wire main_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
 wire [127:0] main_litedramcore_interface_rdata;
-reg [14:0] main_litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg main_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p0_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p0_we_n = 1'd1;
 wire main_litedramcore_dfi_p0_cke;
 wire main_litedramcore_dfi_p0_odt;
 wire main_litedramcore_dfi_p0_reset_n;
-reg main_litedramcore_dfi_p0_act_n = 1'd1;
+reg  main_litedramcore_dfi_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p0_rddata;
 wire main_litedramcore_dfi_p0_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg main_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p1_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p1_we_n = 1'd1;
 wire main_litedramcore_dfi_p1_cke;
 wire main_litedramcore_dfi_p1_odt;
 wire main_litedramcore_dfi_p1_reset_n;
-reg main_litedramcore_dfi_p1_act_n = 1'd1;
+reg  main_litedramcore_dfi_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p1_rddata;
 wire main_litedramcore_dfi_p1_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p2_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg main_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p2_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p2_we_n = 1'd1;
 wire main_litedramcore_dfi_p2_cke;
 wire main_litedramcore_dfi_p2_odt;
 wire main_litedramcore_dfi_p2_reset_n;
-reg main_litedramcore_dfi_p2_act_n = 1'd1;
+reg  main_litedramcore_dfi_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p2_rddata;
 wire main_litedramcore_dfi_p2_rddata_valid;
-reg [14:0] main_litedramcore_dfi_p3_address = 15'd0;
-reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg main_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [14:0] main_litedramcore_dfi_p3_address = 15'd0;
+reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p3_we_n = 1'd1;
 wire main_litedramcore_dfi_p3_cke;
 wire main_litedramcore_dfi_p3_odt;
 wire main_litedramcore_dfi_p3_reset_n;
-reg main_litedramcore_dfi_p3_act_n = 1'd1;
+reg  main_litedramcore_dfi_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p3_rddata;
 wire main_litedramcore_dfi_p3_rddata_valid;
-reg main_litedramcore_cmd_valid = 1'd0;
-reg main_litedramcore_cmd_ready = 1'd0;
-reg main_litedramcore_cmd_last = 1'd0;
-reg [14:0] main_litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg main_litedramcore_cmd_payload_cas = 1'd0;
-reg main_litedramcore_cmd_payload_ras = 1'd0;
-reg main_litedramcore_cmd_payload_we = 1'd0;
-reg main_litedramcore_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_cmd_valid = 1'd0;
+reg  main_litedramcore_cmd_ready = 1'd0;
+reg  main_litedramcore_cmd_last = 1'd0;
+reg  [14:0] main_litedramcore_cmd_payload_a = 15'd0;
+reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg  main_litedramcore_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_cmd_payload_we = 1'd0;
+reg  main_litedramcore_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_cmd_payload_is_write = 1'd0;
 wire main_litedramcore_wants_refresh;
 wire main_litedramcore_wants_zqcs;
 wire main_litedramcore_timer_wait;
 wire main_litedramcore_timer_done0;
 wire [9:0] main_litedramcore_timer_count0;
 wire main_litedramcore_timer_done1;
-reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
 wire main_litedramcore_postponer_req_i;
-reg main_litedramcore_postponer_req_o = 1'd0;
-reg main_litedramcore_postponer_count = 1'd0;
-reg main_litedramcore_sequencer_start0 = 1'd0;
+reg  main_litedramcore_postponer_req_o = 1'd0;
+reg  main_litedramcore_postponer_count = 1'd0;
+reg  main_litedramcore_sequencer_start0 = 1'd0;
 wire main_litedramcore_sequencer_done0;
 wire main_litedramcore_sequencer_start1;
-reg main_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg main_litedramcore_sequencer_count = 1'd0;
+reg  main_litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
+reg  main_litedramcore_sequencer_count = 1'd0;
 wire main_litedramcore_zqcs_timer_wait;
 wire main_litedramcore_zqcs_timer_done0;
 wire [26:0] main_litedramcore_zqcs_timer_count0;
 wire main_litedramcore_zqcs_timer_done1;
-reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg main_litedramcore_zqcs_executer_start = 1'd0;
-reg main_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  main_litedramcore_zqcs_executer_start = 1'd0;
+reg  main_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
 wire main_litedramcore_bankmachine0_req_valid;
 wire main_litedramcore_bankmachine0_req_ready;
 wire main_litedramcore_bankmachine0_req_we;
 wire [21:0] main_litedramcore_bankmachine0_req_addr;
 wire main_litedramcore_bankmachine0_req_lock;
-reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine0_refresh_req;
-reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine0_row = 15'd0;
-reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine0_row = 15'd0;
+reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
 wire main_litedramcore_bankmachine0_row_hit;
-reg main_litedramcore_bankmachine0_row_open = 1'd0;
-reg main_litedramcore_bankmachine0_row_close = 1'd0;
-reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine0_row_open = 1'd0;
+reg  main_litedramcore_bankmachine0_row_close = 1'd0;
+reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine1_req_valid;
 wire main_litedramcore_bankmachine1_req_ready;
 wire main_litedramcore_bankmachine1_req_we;
 wire [21:0] main_litedramcore_bankmachine1_req_addr;
 wire main_litedramcore_bankmachine1_req_lock;
-reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine1_refresh_req;
-reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine1_row = 15'd0;
-reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine1_row = 15'd0;
+reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
 wire main_litedramcore_bankmachine1_row_hit;
-reg main_litedramcore_bankmachine1_row_open = 1'd0;
-reg main_litedramcore_bankmachine1_row_close = 1'd0;
-reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine1_row_open = 1'd0;
+reg  main_litedramcore_bankmachine1_row_close = 1'd0;
+reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine2_req_valid;
 wire main_litedramcore_bankmachine2_req_ready;
 wire main_litedramcore_bankmachine2_req_we;
 wire [21:0] main_litedramcore_bankmachine2_req_addr;
 wire main_litedramcore_bankmachine2_req_lock;
-reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine2_refresh_req;
-reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine2_row = 15'd0;
-reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine2_row = 15'd0;
+reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
 wire main_litedramcore_bankmachine2_row_hit;
-reg main_litedramcore_bankmachine2_row_open = 1'd0;
-reg main_litedramcore_bankmachine2_row_close = 1'd0;
-reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine2_row_open = 1'd0;
+reg  main_litedramcore_bankmachine2_row_close = 1'd0;
+reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine3_req_valid;
 wire main_litedramcore_bankmachine3_req_ready;
 wire main_litedramcore_bankmachine3_req_we;
 wire [21:0] main_litedramcore_bankmachine3_req_addr;
 wire main_litedramcore_bankmachine3_req_lock;
-reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine3_refresh_req;
-reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine3_row = 15'd0;
-reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine3_row = 15'd0;
+reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
 wire main_litedramcore_bankmachine3_row_hit;
-reg main_litedramcore_bankmachine3_row_open = 1'd0;
-reg main_litedramcore_bankmachine3_row_close = 1'd0;
-reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine3_row_open = 1'd0;
+reg  main_litedramcore_bankmachine3_row_close = 1'd0;
+reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine4_req_valid;
 wire main_litedramcore_bankmachine4_req_ready;
 wire main_litedramcore_bankmachine4_req_we;
 wire [21:0] main_litedramcore_bankmachine4_req_addr;
 wire main_litedramcore_bankmachine4_req_lock;
-reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine4_refresh_req;
-reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine4_row = 15'd0;
-reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine4_row = 15'd0;
+reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
 wire main_litedramcore_bankmachine4_row_hit;
-reg main_litedramcore_bankmachine4_row_open = 1'd0;
-reg main_litedramcore_bankmachine4_row_close = 1'd0;
-reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine4_row_open = 1'd0;
+reg  main_litedramcore_bankmachine4_row_close = 1'd0;
+reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine5_req_valid;
 wire main_litedramcore_bankmachine5_req_ready;
 wire main_litedramcore_bankmachine5_req_we;
 wire [21:0] main_litedramcore_bankmachine5_req_addr;
 wire main_litedramcore_bankmachine5_req_lock;
-reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine5_refresh_req;
-reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine5_row = 15'd0;
-reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine5_row = 15'd0;
+reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
 wire main_litedramcore_bankmachine5_row_hit;
-reg main_litedramcore_bankmachine5_row_open = 1'd0;
-reg main_litedramcore_bankmachine5_row_close = 1'd0;
-reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine5_row_open = 1'd0;
+reg  main_litedramcore_bankmachine5_row_close = 1'd0;
+reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine6_req_valid;
 wire main_litedramcore_bankmachine6_req_ready;
 wire main_litedramcore_bankmachine6_req_we;
 wire [21:0] main_litedramcore_bankmachine6_req_addr;
 wire main_litedramcore_bankmachine6_req_lock;
-reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine6_refresh_req;
-reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine6_row = 15'd0;
-reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine6_row = 15'd0;
+reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
 wire main_litedramcore_bankmachine6_row_hit;
-reg main_litedramcore_bankmachine6_row_open = 1'd0;
-reg main_litedramcore_bankmachine6_row_close = 1'd0;
-reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine6_row_open = 1'd0;
+reg  main_litedramcore_bankmachine6_row_close = 1'd0;
+reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine7_req_valid;
 wire main_litedramcore_bankmachine7_req_ready;
 wire main_litedramcore_bankmachine7_req_we;
 wire [21:0] main_litedramcore_bankmachine7_req_addr;
 wire main_litedramcore_bankmachine7_req_lock;
-reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine7_refresh_req;
-reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
 wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] main_litedramcore_bankmachine7_row = 15'd0;
-reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] main_litedramcore_bankmachine7_row = 15'd0;
+reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
 wire main_litedramcore_bankmachine7_row_hit;
-reg main_litedramcore_bankmachine7_row_open = 1'd0;
-reg main_litedramcore_bankmachine7_row_close = 1'd0;
-reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine7_row_open = 1'd0;
+reg  main_litedramcore_bankmachine7_row_close = 1'd0;
+reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire main_litedramcore_ras_allowed;
 wire main_litedramcore_cas_allowed;
 wire [1:0] main_litedramcore_rdcmdphase;
 wire [1:0] main_litedramcore_wrcmdphase;
-reg main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_valid;
-reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire main_litedramcore_choose_cmd_cmd_payload_is_read;
 wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_cmd_request;
-reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
 wire main_litedramcore_choose_cmd_ce;
-reg main_litedramcore_choose_req_want_reads = 1'd0;
-reg main_litedramcore_choose_req_want_writes = 1'd0;
-reg main_litedramcore_choose_req_want_cmds = 1'd0;
-reg main_litedramcore_choose_req_want_activates = 1'd0;
+reg  main_litedramcore_choose_req_want_reads = 1'd0;
+reg  main_litedramcore_choose_req_want_writes = 1'd0;
+reg  main_litedramcore_choose_req_want_cmds = 1'd0;
+reg  main_litedramcore_choose_req_want_activates = 1'd0;
 wire main_litedramcore_choose_req_cmd_valid;
-reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [14:0] main_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_req_cmd_payload_is_cmd;
 wire main_litedramcore_choose_req_cmd_payload_is_read;
 wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_req_request;
-reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
 wire main_litedramcore_choose_req_ce;
-reg [14:0] main_litedramcore_nop_a = 15'd0;
-reg [2:0] main_litedramcore_nop_ba = 3'd0;
-reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg main_litedramcore_steerer0 = 1'd1;
-reg main_litedramcore_steerer1 = 1'd1;
-reg main_litedramcore_steerer2 = 1'd1;
-reg main_litedramcore_steerer3 = 1'd1;
-reg main_litedramcore_steerer4 = 1'd1;
-reg main_litedramcore_steerer5 = 1'd1;
-reg main_litedramcore_steerer6 = 1'd1;
-reg main_litedramcore_steerer7 = 1'd1;
+reg  [14:0] main_litedramcore_nop_a = 15'd0;
+reg  [2:0] main_litedramcore_nop_ba = 3'd0;
+reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg  main_litedramcore_steerer0 = 1'd1;
+reg  main_litedramcore_steerer1 = 1'd1;
+reg  main_litedramcore_steerer2 = 1'd1;
+reg  main_litedramcore_steerer3 = 1'd1;
+reg  main_litedramcore_steerer4 = 1'd1;
+reg  main_litedramcore_steerer5 = 1'd1;
+reg  main_litedramcore_steerer6 = 1'd1;
+reg  main_litedramcore_steerer7 = 1'd1;
 wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
-reg main_litedramcore_trrdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
+reg  main_litedramcore_trrdcon_count = 1'd0;
 wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] main_litedramcore_tfawcon_count;
-reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
 wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
-reg main_litedramcore_tccdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
+reg  main_litedramcore_tccdcon_count = 1'd0;
 wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
 wire main_litedramcore_read_available;
 wire main_litedramcore_write_available;
-reg main_litedramcore_en0 = 1'd0;
+reg  main_litedramcore_en0 = 1'd0;
 wire main_litedramcore_max_time0;
-reg [4:0] main_litedramcore_time0 = 5'd0;
-reg main_litedramcore_en1 = 1'd0;
+reg  [4:0] main_litedramcore_time0 = 5'd0;
+reg  main_litedramcore_en1 = 1'd0;
 wire main_litedramcore_max_time1;
-reg [3:0] main_litedramcore_time1 = 4'd0;
+reg  [3:0] main_litedramcore_time1 = 4'd0;
 wire main_litedramcore_go_to_refresh;
-reg main_init_done_storage = 1'd0;
-reg main_init_done_re = 1'd0;
-reg main_init_error_storage = 1'd0;
-reg main_init_error_re = 1'd0;
+reg  main_init_done_storage = 1'd0;
+reg  main_init_done_re = 1'd0;
+reg  main_init_error_storage = 1'd0;
+reg  main_init_error_re = 1'd0;
 wire [29:0] main_wb_bus_adr;
 wire [31:0] main_wb_bus_dat_w;
 wire [31:0] main_wb_bus_dat_r;
@@ -1570,6 +1592,7 @@ wire main_wb_bus_we;
 wire [2:0] main_wb_bus_cti;
 wire [1:0] main_wb_bus_bte;
 wire main_wb_bus_err;
+wire main_user_enable;
 wire main_user_port_cmd_valid;
 wire main_user_port_cmd_ready;
 wire main_user_port_cmd_payload_we;
@@ -1590,26 +1613,26 @@ wire builder_reset5;
 wire builder_reset6;
 wire builder_reset7;
 wire builder_pll_fb;
-reg [1:0] builder_refresher_state = 2'd0;
-reg [1:0] builder_refresher_next_state = 2'd0;
-reg [3:0] builder_bankmachine0_state = 4'd0;
-reg [3:0] builder_bankmachine0_next_state = 4'd0;
-reg [3:0] builder_bankmachine1_state = 4'd0;
-reg [3:0] builder_bankmachine1_next_state = 4'd0;
-reg [3:0] builder_bankmachine2_state = 4'd0;
-reg [3:0] builder_bankmachine2_next_state = 4'd0;
-reg [3:0] builder_bankmachine3_state = 4'd0;
-reg [3:0] builder_bankmachine3_next_state = 4'd0;
-reg [3:0] builder_bankmachine4_state = 4'd0;
-reg [3:0] builder_bankmachine4_next_state = 4'd0;
-reg [3:0] builder_bankmachine5_state = 4'd0;
-reg [3:0] builder_bankmachine5_next_state = 4'd0;
-reg [3:0] builder_bankmachine6_state = 4'd0;
-reg [3:0] builder_bankmachine6_next_state = 4'd0;
-reg [3:0] builder_bankmachine7_state = 4'd0;
-reg [3:0] builder_bankmachine7_next_state = 4'd0;
-reg [3:0] builder_multiplexer_state = 4'd0;
-reg [3:0] builder_multiplexer_next_state = 4'd0;
+reg  [1:0] builder_refresher_state = 2'd0;
+reg  [1:0] builder_refresher_next_state = 2'd0;
+reg  [3:0] builder_bankmachine0_state = 4'd0;
+reg  [3:0] builder_bankmachine0_next_state = 4'd0;
+reg  [3:0] builder_bankmachine1_state = 4'd0;
+reg  [3:0] builder_bankmachine1_next_state = 4'd0;
+reg  [3:0] builder_bankmachine2_state = 4'd0;
+reg  [3:0] builder_bankmachine2_next_state = 4'd0;
+reg  [3:0] builder_bankmachine3_state = 4'd0;
+reg  [3:0] builder_bankmachine3_next_state = 4'd0;
+reg  [3:0] builder_bankmachine4_state = 4'd0;
+reg  [3:0] builder_bankmachine4_next_state = 4'd0;
+reg  [3:0] builder_bankmachine5_state = 4'd0;
+reg  [3:0] builder_bankmachine5_next_state = 4'd0;
+reg  [3:0] builder_bankmachine6_state = 4'd0;
+reg  [3:0] builder_bankmachine6_next_state = 4'd0;
+reg  [3:0] builder_bankmachine7_state = 4'd0;
+reg  [3:0] builder_bankmachine7_next_state = 4'd0;
+reg  [3:0] builder_multiplexer_state = 4'd0;
+reg  [3:0] builder_multiplexer_next_state = 4'd0;
 wire builder_roundrobin0_request;
 wire builder_roundrobin0_grant;
 wire builder_roundrobin0_ce;
@@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce;
 wire builder_roundrobin7_request;
 wire builder_roundrobin7_grant;
 wire builder_roundrobin7_ce;
-reg builder_locked0 = 1'd0;
-reg builder_locked1 = 1'd0;
-reg builder_locked2 = 1'd0;
-reg builder_locked3 = 1'd0;
-reg builder_locked4 = 1'd0;
-reg builder_locked5 = 1'd0;
-reg builder_locked6 = 1'd0;
-reg builder_locked7 = 1'd0;
-reg builder_new_master_wdata_ready0 = 1'd0;
-reg builder_new_master_wdata_ready1 = 1'd0;
-reg builder_new_master_rdata_valid0 = 1'd0;
-reg builder_new_master_rdata_valid1 = 1'd0;
-reg builder_new_master_rdata_valid2 = 1'd0;
-reg builder_new_master_rdata_valid3 = 1'd0;
-reg builder_new_master_rdata_valid4 = 1'd0;
-reg builder_new_master_rdata_valid5 = 1'd0;
-reg builder_new_master_rdata_valid6 = 1'd0;
-reg builder_new_master_rdata_valid7 = 1'd0;
-reg builder_new_master_rdata_valid8 = 1'd0;
-reg [13:0] builder_litedramcore_adr = 14'd0;
-reg builder_litedramcore_we = 1'd0;
-reg [7:0] builder_litedramcore_dat_w = 8'd0;
-wire [7:0] builder_litedramcore_dat_r;
+reg  builder_locked0 = 1'd0;
+reg  builder_locked1 = 1'd0;
+reg  builder_locked2 = 1'd0;
+reg  builder_locked3 = 1'd0;
+reg  builder_locked4 = 1'd0;
+reg  builder_locked5 = 1'd0;
+reg  builder_locked6 = 1'd0;
+reg  builder_locked7 = 1'd0;
+reg  builder_new_master_wdata_ready0 = 1'd0;
+reg  builder_new_master_wdata_ready1 = 1'd0;
+reg  builder_new_master_rdata_valid0 = 1'd0;
+reg  builder_new_master_rdata_valid1 = 1'd0;
+reg  builder_new_master_rdata_valid2 = 1'd0;
+reg  builder_new_master_rdata_valid3 = 1'd0;
+reg  builder_new_master_rdata_valid4 = 1'd0;
+reg  builder_new_master_rdata_valid5 = 1'd0;
+reg  builder_new_master_rdata_valid6 = 1'd0;
+reg  builder_new_master_rdata_valid7 = 1'd0;
+reg  builder_new_master_rdata_valid8 = 1'd0;
+reg  [13:0] builder_litedramcore_adr = 14'd0;
+reg  builder_litedramcore_we = 1'd0;
+reg  [31:0] builder_litedramcore_dat_w = 32'd0;
+wire [31:0] builder_litedramcore_dat_r;
 wire [29:0] builder_litedramcore_wishbone_adr;
 wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] builder_litedramcore_wishbone_sel;
 wire builder_litedramcore_wishbone_cyc;
 wire builder_litedramcore_wishbone_stb;
-reg builder_litedramcore_wishbone_ack = 1'd0;
+reg  builder_litedramcore_wishbone_ack = 1'd0;
 wire builder_litedramcore_wishbone_we;
 wire [2:0] builder_litedramcore_wishbone_cti;
 wire [1:0] builder_litedramcore_wishbone_bte;
-reg builder_litedramcore_wishbone_err = 1'd0;
+reg  builder_litedramcore_wishbone_err = 1'd0;
 wire [13:0] builder_interface0_bank_bus_adr;
 wire builder_interface0_bank_bus_we;
-wire [7:0] builder_interface0_bank_bus_dat_w;
-reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
-reg builder_csrbank0_init_done0_re = 1'd0;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank0_init_done0_re = 1'd0;
 wire builder_csrbank0_init_done0_r;
-reg builder_csrbank0_init_done0_we = 1'd0;
+reg  builder_csrbank0_init_done0_we = 1'd0;
 wire builder_csrbank0_init_done0_w;
-reg builder_csrbank0_init_error0_re = 1'd0;
+reg  builder_csrbank0_init_error0_re = 1'd0;
 wire builder_csrbank0_init_error0_r;
-reg builder_csrbank0_init_error0_we = 1'd0;
+reg  builder_csrbank0_init_error0_we = 1'd0;
 wire builder_csrbank0_init_error0_w;
 wire builder_csrbank0_sel;
 wire [13:0] builder_interface1_bank_bus_adr;
 wire builder_interface1_bank_bus_we;
-wire [7:0] builder_interface1_bank_bus_dat_w;
-reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
-reg builder_csrbank1_rst0_re = 1'd0;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank1_rst0_re = 1'd0;
 wire builder_csrbank1_rst0_r;
-reg builder_csrbank1_rst0_we = 1'd0;
+reg  builder_csrbank1_rst0_we = 1'd0;
 wire builder_csrbank1_rst0_w;
-reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg builder_csrbank1_wlevel_en0_re = 1'd0;
+reg  builder_csrbank1_wlevel_en0_re = 1'd0;
 wire builder_csrbank1_wlevel_en0_r;
-reg builder_csrbank1_wlevel_en0_we = 1'd0;
+reg  builder_csrbank1_wlevel_en0_we = 1'd0;
 wire builder_csrbank1_wlevel_en0_w;
-reg builder_csrbank1_dly_sel0_re = 1'd0;
+reg  builder_csrbank1_dly_sel0_re = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_r;
-reg builder_csrbank1_dly_sel0_we = 1'd0;
+reg  builder_csrbank1_dly_sel0_we = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_w;
-reg builder_csrbank1_rdphase0_re = 1'd0;
+reg  builder_csrbank1_rdphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_r;
-reg builder_csrbank1_rdphase0_we = 1'd0;
+reg  builder_csrbank1_rdphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_w;
-reg builder_csrbank1_wrphase0_re = 1'd0;
+reg  builder_csrbank1_wrphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_r;
-reg builder_csrbank1_wrphase0_we = 1'd0;
+reg  builder_csrbank1_wrphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_w;
 wire builder_csrbank1_sel;
 wire [13:0] builder_interface2_bank_bus_adr;
 wire builder_interface2_bank_bus_we;
-wire [7:0] builder_interface2_bank_bus_dat_w;
-reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
-reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank2_dfii_control0_re = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_r;
-reg builder_csrbank2_dfii_control0_we = 1'd0;
+reg  builder_csrbank2_dfii_control0_we = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_w;
-reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi0_address1_r;
-reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi0_address1_w;
-reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
-reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
-reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi0_address0_r;
+reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi0_address0_w;
+reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
-reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
-reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
-reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
-reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
-reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
-reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
-reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
-reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi1_address1_r;
-reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi1_address1_w;
-reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
-reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
-reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi1_address0_r;
+reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi1_address0_w;
+reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
-reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
-reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
-reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
-reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
-reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
-reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
-reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
-reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi2_address1_r;
-reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi2_address1_w;
-reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
-reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
-reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi2_address0_r;
+reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi2_address0_w;
+reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
-reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
-reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
-reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
-reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
-reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
-reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
-reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
-reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi3_address1_r;
-reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
-wire [6:0] builder_csrbank2_dfii_pi3_address1_w;
-reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
-reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
-reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi3_address0_r;
+reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] builder_csrbank2_dfii_pi3_address0_w;
+reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
-reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
-reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
-reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
-reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
-reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
-reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
-reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
-reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
 wire builder_csrbank2_sel;
 wire [13:0] builder_csr_interconnect_adr;
 wire builder_csr_interconnect_we;
-wire [7:0] builder_csr_interconnect_dat_w;
-wire [7:0] builder_csr_interconnect_dat_r;
-reg [1:0] builder_state = 2'd0;
-reg [1:0] builder_next_state = 2'd0;
-reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
-reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg builder_litedramcore_we_next_value2 = 1'd0;
-reg builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg builder_rhs_array_muxed0 = 1'd0;
-reg [14:0] builder_rhs_array_muxed1 = 15'd0;
-reg [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg builder_rhs_array_muxed3 = 1'd0;
-reg builder_rhs_array_muxed4 = 1'd0;
-reg builder_rhs_array_muxed5 = 1'd0;
-reg builder_t_array_muxed0 = 1'd0;
-reg builder_t_array_muxed1 = 1'd0;
-reg builder_t_array_muxed2 = 1'd0;
-reg builder_rhs_array_muxed6 = 1'd0;
-reg [14:0] builder_rhs_array_muxed7 = 15'd0;
-reg [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg builder_rhs_array_muxed9 = 1'd0;
-reg builder_rhs_array_muxed10 = 1'd0;
-reg builder_rhs_array_muxed11 = 1'd0;
-reg builder_t_array_muxed3 = 1'd0;
-reg builder_t_array_muxed4 = 1'd0;
-reg builder_t_array_muxed5 = 1'd0;
-reg [21:0] builder_rhs_array_muxed12 = 22'd0;
-reg builder_rhs_array_muxed13 = 1'd0;
-reg builder_rhs_array_muxed14 = 1'd0;
-reg [21:0] builder_rhs_array_muxed15 = 22'd0;
-reg builder_rhs_array_muxed16 = 1'd0;
-reg builder_rhs_array_muxed17 = 1'd0;
-reg [21:0] builder_rhs_array_muxed18 = 22'd0;
-reg builder_rhs_array_muxed19 = 1'd0;
-reg builder_rhs_array_muxed20 = 1'd0;
-reg [21:0] builder_rhs_array_muxed21 = 22'd0;
-reg builder_rhs_array_muxed22 = 1'd0;
-reg builder_rhs_array_muxed23 = 1'd0;
-reg [21:0] builder_rhs_array_muxed24 = 22'd0;
-reg builder_rhs_array_muxed25 = 1'd0;
-reg builder_rhs_array_muxed26 = 1'd0;
-reg [21:0] builder_rhs_array_muxed27 = 22'd0;
-reg builder_rhs_array_muxed28 = 1'd0;
-reg builder_rhs_array_muxed29 = 1'd0;
-reg [21:0] builder_rhs_array_muxed30 = 22'd0;
-reg builder_rhs_array_muxed31 = 1'd0;
-reg builder_rhs_array_muxed32 = 1'd0;
-reg [21:0] builder_rhs_array_muxed33 = 22'd0;
-reg builder_rhs_array_muxed34 = 1'd0;
-reg builder_rhs_array_muxed35 = 1'd0;
-reg [2:0] builder_array_muxed0 = 3'd0;
-reg [14:0] builder_array_muxed1 = 15'd0;
-reg builder_array_muxed2 = 1'd0;
-reg builder_array_muxed3 = 1'd0;
-reg builder_array_muxed4 = 1'd0;
-reg builder_array_muxed5 = 1'd0;
-reg builder_array_muxed6 = 1'd0;
-reg [2:0] builder_array_muxed7 = 3'd0;
-reg [14:0] builder_array_muxed8 = 15'd0;
-reg builder_array_muxed9 = 1'd0;
-reg builder_array_muxed10 = 1'd0;
-reg builder_array_muxed11 = 1'd0;
-reg builder_array_muxed12 = 1'd0;
-reg builder_array_muxed13 = 1'd0;
-reg [2:0] builder_array_muxed14 = 3'd0;
-reg [14:0] builder_array_muxed15 = 15'd0;
-reg builder_array_muxed16 = 1'd0;
-reg builder_array_muxed17 = 1'd0;
-reg builder_array_muxed18 = 1'd0;
-reg builder_array_muxed19 = 1'd0;
-reg builder_array_muxed20 = 1'd0;
-reg [2:0] builder_array_muxed21 = 3'd0;
-reg [14:0] builder_array_muxed22 = 15'd0;
-reg builder_array_muxed23 = 1'd0;
-reg builder_array_muxed24 = 1'd0;
-reg builder_array_muxed25 = 1'd0;
-reg builder_array_muxed26 = 1'd0;
-reg builder_array_muxed27 = 1'd0;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg  [1:0] builder_state = 2'd0;
+reg  [1:0] builder_next_state = 2'd0;
+reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
+reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg  builder_litedramcore_we_next_value2 = 1'd0;
+reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg  builder_rhs_array_muxed0 = 1'd0;
+reg  [14:0] builder_rhs_array_muxed1 = 15'd0;
+reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg  builder_rhs_array_muxed3 = 1'd0;
+reg  builder_rhs_array_muxed4 = 1'd0;
+reg  builder_rhs_array_muxed5 = 1'd0;
+reg  builder_t_array_muxed0 = 1'd0;
+reg  builder_t_array_muxed1 = 1'd0;
+reg  builder_t_array_muxed2 = 1'd0;
+reg  builder_rhs_array_muxed6 = 1'd0;
+reg  [14:0] builder_rhs_array_muxed7 = 15'd0;
+reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg  builder_rhs_array_muxed9 = 1'd0;
+reg  builder_rhs_array_muxed10 = 1'd0;
+reg  builder_rhs_array_muxed11 = 1'd0;
+reg  builder_t_array_muxed3 = 1'd0;
+reg  builder_t_array_muxed4 = 1'd0;
+reg  builder_t_array_muxed5 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed12 = 22'd0;
+reg  builder_rhs_array_muxed13 = 1'd0;
+reg  builder_rhs_array_muxed14 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed15 = 22'd0;
+reg  builder_rhs_array_muxed16 = 1'd0;
+reg  builder_rhs_array_muxed17 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed18 = 22'd0;
+reg  builder_rhs_array_muxed19 = 1'd0;
+reg  builder_rhs_array_muxed20 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed21 = 22'd0;
+reg  builder_rhs_array_muxed22 = 1'd0;
+reg  builder_rhs_array_muxed23 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed24 = 22'd0;
+reg  builder_rhs_array_muxed25 = 1'd0;
+reg  builder_rhs_array_muxed26 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed27 = 22'd0;
+reg  builder_rhs_array_muxed28 = 1'd0;
+reg  builder_rhs_array_muxed29 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed30 = 22'd0;
+reg  builder_rhs_array_muxed31 = 1'd0;
+reg  builder_rhs_array_muxed32 = 1'd0;
+reg  [21:0] builder_rhs_array_muxed33 = 22'd0;
+reg  builder_rhs_array_muxed34 = 1'd0;
+reg  builder_rhs_array_muxed35 = 1'd0;
+reg  [2:0] builder_array_muxed0 = 3'd0;
+reg  [14:0] builder_array_muxed1 = 15'd0;
+reg  builder_array_muxed2 = 1'd0;
+reg  builder_array_muxed3 = 1'd0;
+reg  builder_array_muxed4 = 1'd0;
+reg  builder_array_muxed5 = 1'd0;
+reg  builder_array_muxed6 = 1'd0;
+reg  [2:0] builder_array_muxed7 = 3'd0;
+reg  [14:0] builder_array_muxed8 = 15'd0;
+reg  builder_array_muxed9 = 1'd0;
+reg  builder_array_muxed10 = 1'd0;
+reg  builder_array_muxed11 = 1'd0;
+reg  builder_array_muxed12 = 1'd0;
+reg  builder_array_muxed13 = 1'd0;
+reg  [2:0] builder_array_muxed14 = 3'd0;
+reg  [14:0] builder_array_muxed15 = 15'd0;
+reg  builder_array_muxed16 = 1'd0;
+reg  builder_array_muxed17 = 1'd0;
+reg  builder_array_muxed18 = 1'd0;
+reg  builder_array_muxed19 = 1'd0;
+reg  builder_array_muxed20 = 1'd0;
+reg  [2:0] builder_array_muxed21 = 3'd0;
+reg  [14:0] builder_array_muxed22 = 15'd0;
+reg  builder_array_muxed23 = 1'd0;
+reg  builder_array_muxed24 = 1'd0;
+reg  builder_array_muxed25 = 1'd0;
+reg  builder_array_muxed26 = 1'd0;
+reg  builder_array_muxed27 = 1'd0;
 wire builder_xilinxasyncresetsynchronizerimpl0;
 wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl1;
@@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3;
 wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl3_expr;
 
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
 assign init_done = main_init_done_storage;
 assign init_error = main_init_error_storage;
 assign main_wb_bus_adr = wb_ctrl_adr;
@@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
 assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
 assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
-assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
 assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = rst;
+assign main_reset = (rst | main_rst);
 assign pll_locked = main_locked;
 assign main_clkin = clk;
 assign iodelay_clk = main_clkout_buf0;
@@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2;
 assign sys4x_dqs_clk = main_clkout_buf3;
 assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
 assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-
-// synthesis translate_off
-reg dummy_d;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
@@ -2081,14 +1989,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
 	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
 	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-// synthesis translate_off
-	dummy_d = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_1;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
@@ -2123,14 +2024,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
 	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
 	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-// synthesis translate_off
-	dummy_d_1 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_2;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
@@ -2165,14 +2059,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
 	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
 	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-// synthesis translate_off
-	dummy_d_2 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_3;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
@@ -2207,19 +2094,12 @@ always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
 	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
 	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-// synthesis translate_off
-	dummy_d_3 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-
-// synthesis translate_off
-reg dummy_d_4;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqs_oe <= 1'd0;
 	if (main_a7ddrphy_wlevel_en_storage) begin
@@ -2227,16 +2107,9 @@ always @(*) begin
 	end else begin
 		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
 	end
-// synthesis translate_off
-	dummy_d_4 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
 assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqspattern_o0 <= 8'd0;
 	main_a7ddrphy_dqspattern_o0 <= 7'd85;
@@ -2252,14 +2125,7 @@ always @(*) begin
 			main_a7ddrphy_dqspattern_o0 <= 1'd1;
 		end
 	end
-// synthesis translate_off
-	dummy_d_5 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip00 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value0)
@@ -2288,14 +2154,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_6 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip10 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value0)
@@ -2324,14 +2183,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_7 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip01 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value1)
@@ -2360,14 +2212,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_8 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip11 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value1)
@@ -2396,14 +2241,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_9 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip02 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value2)
@@ -2432,14 +2270,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_10 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip04 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value3)
@@ -2468,14 +2299,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_11 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip12 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value2)
@@ -2504,14 +2328,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_12 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip14 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value3)
@@ -2540,14 +2357,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_13 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip20 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value0)
@@ -2576,14 +2386,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_14 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip22 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value1)
@@ -2612,14 +2415,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_15 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip30 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value0)
@@ -2648,14 +2444,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_16 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip32 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value1)
@@ -2684,14 +2473,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_17 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_18;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip40 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value0)
@@ -2720,14 +2502,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_18 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_19;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip42 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value1)
@@ -2756,14 +2531,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_19 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_20;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip50 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value0)
@@ -2792,14 +2560,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_20 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_21;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip52 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value1)
@@ -2828,14 +2589,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_21 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip60 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value0)
@@ -2864,14 +2618,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_22 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip62 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value1)
@@ -2900,14 +2647,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_23 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip70 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value0)
@@ -2936,14 +2676,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_24 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip72 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value1)
@@ -2972,14 +2705,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_25 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_26;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip80 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value0)
@@ -3008,14 +2734,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_26 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip82 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value1)
@@ -3044,14 +2763,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_27 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip90 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value0)
@@ -3080,14 +2792,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_28 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip92 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value1)
@@ -3116,14 +2821,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_29 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip100 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value0)
@@ -3152,14 +2850,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_30 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_31;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip102 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value1)
@@ -3188,14 +2879,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_31 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_32;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip110 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value0)
@@ -3224,14 +2908,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_32 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_33;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip112 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value1)
@@ -3260,14 +2937,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_33 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_34;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip120 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value0)
@@ -3296,14 +2966,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_34 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_35;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip122 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value1)
@@ -3332,14 +2995,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_35 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_36;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip130 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value0)
@@ -3368,14 +3024,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_36 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_37;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip132 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value1)
@@ -3404,14 +3053,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_37 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_38;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip140 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value0)
@@ -3440,14 +3082,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_38 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip142 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value1)
@@ -3476,14 +3111,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_39 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_40;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip150 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value0)
@@ -3512,14 +3140,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_40 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_41;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip152 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value1)
@@ -3548,9 +3169,6 @@ always @(*) begin
 			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_41 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
 assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
@@ -3680,10 +3298,29 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-
-// synthesis translate_off
-reg dummy_d_42;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_cs_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	end else begin
+		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+	end
+end
+always @(*) begin
+	main_litedramcore_master_p3_ras_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	end else begin
+		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+	end
+end
+always @(*) begin
+	main_litedramcore_slave_p3_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	end else begin
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3691,28 +3328,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
-// synthesis translate_off
-	dummy_d_42 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_43;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_43 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_44;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3720,14 +3343,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_44 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_45;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3735,14 +3351,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
-// synthesis translate_off
-	dummy_d_45 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_46;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3750,14 +3359,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_46 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_47;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3765,14 +3367,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
-// synthesis translate_off
-	dummy_d_47 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_48;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -3780,28 +3375,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_48 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_49;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
-// synthesis translate_off
-	dummy_d_49 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_50;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3809,28 +3390,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_50 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_51;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_51 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_52;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3838,14 +3405,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_52 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_53;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3853,14 +3413,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_53 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_54;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -3868,14 +3421,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
-// synthesis translate_off
-	dummy_d_54 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_55;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3883,14 +3429,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
-// synthesis translate_off
-	dummy_d_55 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_56;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3898,14 +3437,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_56 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_57;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3913,43 +3445,22 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_57 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_58;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 32'd0;
+	main_litedramcore_master_p0_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
 	end else begin
+		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_58 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_59;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
+	main_litedramcore_slave_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_59 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_60;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3957,28 +3468,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_60 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_61;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_61 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_62;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3986,14 +3483,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
-// synthesis translate_off
-	dummy_d_62 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_63;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4001,14 +3491,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
-// synthesis translate_off
-	dummy_d_63 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_64;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4016,14 +3499,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_64 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_65;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4031,14 +3507,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
-// synthesis translate_off
-	dummy_d_65 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_66;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4046,28 +3515,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_66 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_67;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
-// synthesis translate_off
-	dummy_d_67 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_68;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4075,28 +3530,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_68 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_69;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_69 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_70;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4104,14 +3545,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_70 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_71;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4119,14 +3553,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_71 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_72;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -4134,14 +3561,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
-// synthesis translate_off
-	dummy_d_72 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_73;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4149,14 +3569,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
-// synthesis translate_off
-	dummy_d_73 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_74;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4164,14 +3577,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_74 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4179,14 +3585,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_75 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_76;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4194,28 +3593,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_76 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_77;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_77 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_78;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4223,28 +3608,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
-// synthesis translate_off
-	dummy_d_78 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_79;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_79 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_80;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4252,14 +3623,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
-// synthesis translate_off
-	dummy_d_80 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_81;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4267,14 +3631,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
-// synthesis translate_off
-	dummy_d_81 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_82;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4282,14 +3639,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_82 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_83;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4297,14 +3647,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
-// synthesis translate_off
-	dummy_d_83 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_84;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4312,28 +3655,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_84 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_85;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
-// synthesis translate_off
-	dummy_d_85 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_86;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4341,28 +3670,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_86 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_87;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_87 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_88;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4370,14 +3685,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_88 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_89;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4385,14 +3693,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -4400,14 +3701,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_91;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4415,14 +3709,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_91 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_92;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4430,14 +3717,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_92 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_93;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4445,14 +3725,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_93 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_94;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4460,28 +3733,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_94 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_95;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_95 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_96;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4489,28 +3748,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
-// synthesis translate_off
-	dummy_d_96 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_97 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_98;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4518,14 +3763,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
-// synthesis translate_off
-	dummy_d_98 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_99;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4533,14 +3771,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
-// synthesis translate_off
-	dummy_d_99 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_100;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4548,14 +3779,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4563,14 +3787,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
-// synthesis translate_off
-	dummy_d_101 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_102;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4578,28 +3795,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_102 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_103;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
+	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
-// synthesis translate_off
-	dummy_d_103 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_104;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4607,28 +3810,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_104 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_105;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_105 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_106;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4636,28 +3825,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_106 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_107;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
-	end
-// synthesis translate_off
-	dummy_d_107 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_108;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4665,14 +3833,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_108 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -4680,14 +3841,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
-// synthesis translate_off
-	dummy_d_109 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_110;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4695,14 +3849,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
-// synthesis translate_off
-	dummy_d_110 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_111;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4710,39 +3857,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_111 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_112;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
-	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
-	end
-// synthesis translate_off
-	dummy_d_112 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_113;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
-	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
-	end
-// synthesis translate_off
-	dummy_d_113 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
 assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
@@ -4756,65 +3870,37 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
+	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_114 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_115;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_115 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_116;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
+	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_116 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_117;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_117 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
@@ -4822,65 +3908,37 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c
 assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
 assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_118;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
+	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_118 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_119;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_119 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
+	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_120 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_121 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
@@ -4888,10 +3946,22 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c
 assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
 assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_cs_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	end else begin
+		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+	end
+end
+always @(*) begin
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4899,14 +3969,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4914,39 +3977,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_123 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
-	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
-	end
-// synthesis translate_off
-	dummy_d_124 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
-	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_125 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
@@ -4954,65 +3984,37 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c
 assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
 assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_126;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
+	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_126 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_127 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
+	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_128 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_129 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
@@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 &
 assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
 assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
 assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
 always @(*) begin
 	builder_refresher_next_state <= 2'd0;
 	builder_refresher_next_state <= builder_refresher_state;
@@ -5124,14 +4122,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_130 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_131;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_sequencer_start0 <= 1'd0;
 	case (builder_refresher_state)
@@ -5147,14 +4138,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_131 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_132;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_valid <= 1'd0;
 	case (builder_refresher_state)
@@ -5179,14 +4163,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_132 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_133;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_zqcs_executer_start <= 1'd0;
 	case (builder_refresher_state)
@@ -5205,14 +4182,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_133 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_134;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_last <= 1'd0;
 	case (builder_refresher_state)
@@ -5234,9 +4204,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_134 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
@@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_135;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
@@ -5263,17 +4226,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_135 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
 assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
 assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_136;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
@@ -5281,9 +4237,6 @@ always @(*) begin
 			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_136 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
@@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_137;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
@@ -5313,9 +4262,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_137 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
@@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_138;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine0_next_state <= 4'd0;
 	builder_bankmachine0_next_state <= builder_bankmachine0_state;
@@ -5389,14 +4331,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_138 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_139;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5437,14 +4436,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_139 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5470,14 +4462,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_140 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_141;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5507,14 +4492,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_141 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_142;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5552,14 +4530,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_142 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_143;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5597,14 +4568,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_143 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_144;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5642,14 +4606,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_144 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5687,14 +4644,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_145 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5720,14 +4670,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_146 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5768,14 +4711,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_147 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5801,14 +4737,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5834,87 +4763,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_149 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_150;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_150 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_151;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_151 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
@@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_152;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
@@ -5941,17 +4785,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_152 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
 assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
 assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_153;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
@@ -5959,9 +4796,6 @@ always @(*) begin
 			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_153 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
@@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_154;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
@@ -5991,9 +4821,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_154 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
@@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_155;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine1_next_state <= 4'd0;
 	builder_bankmachine1_next_state <= builder_bankmachine1_state;
@@ -6067,21 +4890,11 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_155 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_156;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -6103,10 +4916,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6115,64 +4925,23 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_156 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_157;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_157 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6185,18 +4954,14 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_158 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_159;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -6219,8 +4984,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6230,22 +4995,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_159 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_160;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6258,33 +5019,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
+		3'd4: begin
+			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
 	endcase
-// synthesis translate_off
-	dummy_d_160 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6309,8 +5078,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6320,16 +5089,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_161 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6354,8 +5116,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -6365,16 +5127,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_162 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6383,9 +5138,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6396,30 +5148,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_163 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6437,7 +5191,10 @@ always @(*) begin
 				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -6446,27 +5203,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_164 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_165;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6479,27 +5229,23 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_165 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_166;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6510,24 +5256,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_166 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_167;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6540,44 +5294,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_167 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_168;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6590,9 +5322,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_168 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
@@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_169;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
@@ -6619,17 +5344,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_169 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
 assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_170;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
@@ -6637,9 +5355,6 @@ always @(*) begin
 			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_170 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
@@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_171;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
@@ -6669,9 +5380,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_171 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
@@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_172;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine2_next_state <= 4'd0;
 	builder_bankmachine2_next_state <= builder_bankmachine2_state;
@@ -6745,14 +5449,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_172 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_173;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6793,14 +5554,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_173 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6826,14 +5580,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_174 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_175;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6863,14 +5610,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_175 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6908,14 +5648,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_176 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6953,14 +5686,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_177 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_178;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6998,14 +5724,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_178 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7043,14 +5762,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_179 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7076,14 +5788,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_180 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7124,14 +5829,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7157,14 +5855,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_182 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_183;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7190,106 +5881,21 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_183 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_184;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_184 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_185;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_185 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_186;
-// synthesis translate_on
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
@@ -7297,17 +5903,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
 assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
 assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
@@ -7315,9 +5914,6 @@ always @(*) begin
 			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
@@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_188;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
@@ -7347,9 +5939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_188 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
@@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_189;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine3_next_state <= 4'd0;
 	builder_bankmachine3_next_state <= builder_bankmachine3_state;
@@ -7423,14 +6008,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_189 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_190;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7471,14 +6113,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_190 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_191;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7504,14 +6139,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_191 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7541,14 +6169,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_192 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_193;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7586,14 +6207,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_193 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_194;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7631,14 +6245,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_194 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_195;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7676,14 +6283,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_195 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7721,14 +6321,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_196 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7754,14 +6347,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_197 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7802,14 +6388,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_198 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_199;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7835,14 +6414,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_199 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_200;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7868,87 +6440,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_200 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_201;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_201 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_202;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_202 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
@@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_203;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
@@ -7975,17 +6462,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_203 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
 assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
 assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_204;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
@@ -7993,9 +6473,6 @@ always @(*) begin
 			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_204 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
@@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_205;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
@@ -8025,9 +6498,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_205 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
@@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_206;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine4_next_state <= 4'd0;
 	builder_bankmachine4_next_state <= builder_bankmachine4_state;
@@ -8101,21 +6567,11 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_206 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_207;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8137,10 +6593,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8149,24 +6602,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_207 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8182,31 +6631,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_208 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_209;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8217,20 +6655,84 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_209 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_210;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
 		end
 		2'd2: begin
 		end
@@ -8264,14 +6766,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_210 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_211;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8309,14 +6804,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_211 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_212;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8354,14 +6842,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_212 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8399,14 +6880,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_213 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8432,14 +6906,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_214 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8480,14 +6947,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_215 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_216;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8513,14 +6973,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_216 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_217;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8546,87 +6999,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_217 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_218 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_219;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_219 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
@@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_220;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
@@ -8653,17 +7021,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
 assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
 assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
@@ -8671,9 +7032,6 @@ always @(*) begin
 			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_221 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
@@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_222;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
@@ -8703,9 +7057,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_222 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
@@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_223;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine5_next_state <= 4'd0;
 	builder_bankmachine5_next_state <= builder_bankmachine5_state;
@@ -8779,14 +7126,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_223 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8827,14 +7231,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_224 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_225;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8860,14 +7257,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_225 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8897,14 +7287,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_226 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8942,14 +7325,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_227 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_228;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8987,14 +7363,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_228 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_229;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9032,14 +7401,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_229 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_230;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9077,14 +7439,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9110,14 +7465,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_231 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9158,14 +7506,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_232 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9191,14 +7532,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_233 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_234;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9224,106 +7558,21 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_234 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_235;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_235 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_236 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
@@ -9331,17 +7580,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_237 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
 assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
 assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_238;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
@@ -9349,9 +7591,6 @@ always @(*) begin
 			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_238 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
@@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_239;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
@@ -9381,9 +7616,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_239 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
@@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_240;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine6_next_state <= 4'd0;
 	builder_bankmachine6_next_state <= builder_bankmachine6_state;
@@ -9457,14 +7685,71 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_240 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_241;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9505,14 +7790,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_241 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9538,14 +7816,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_242 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_243;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9575,14 +7846,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_243 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_244;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9620,14 +7884,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_244 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_245;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9665,14 +7922,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_245 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9710,14 +7960,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_246 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9755,14 +7998,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_247 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9788,14 +8024,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_248 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9836,14 +8065,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_249 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_250;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9869,14 +8091,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_250 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_251;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9902,87 +8117,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_251 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_252;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_252 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_253 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
@@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
 assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_254;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
 	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
@@ -10009,17 +8139,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_254 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
 assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_255;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
@@ -10027,9 +8150,6 @@ always @(*) begin
 			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_255 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
@@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_256;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
@@ -10059,9 +8175,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_256 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
@@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_257;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine7_next_state <= 4'd0;
 	builder_bankmachine7_next_state <= builder_bankmachine7_state;
@@ -10135,21 +8244,11 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_257 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_258;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -10171,10 +8270,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -10183,24 +8279,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_258 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_259;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -10216,31 +8308,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_259 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_260;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10251,23 +8332,87 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_260 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_261;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
 		2'd3: begin
 		end
 		3'd4: begin
@@ -10298,14 +8443,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_261 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_262;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10343,14 +8481,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_262 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_263;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10388,14 +8519,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_263 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_264;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10433,14 +8557,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_264 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10466,14 +8583,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10514,14 +8624,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_266 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10547,14 +8650,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_267 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10580,87 +8676,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_268 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_269 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_270 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
@@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_valids <= 8'd0;
 	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
@@ -10706,9 +8717,6 @@ always @(*) begin
 	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-// synthesis translate_off
-	dummy_d_271 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
 assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
@@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
 assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
 assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
 assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
 	end
-// synthesis translate_off
-	dummy_d_272 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
 	end
-// synthesis translate_off
-	dummy_d_273 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
 	end
-// synthesis translate_off
-	dummy_d_274 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
@@ -10768,14 +8751,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
 		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_275 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
@@ -10784,14 +8760,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
 		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_276 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
@@ -10800,14 +8769,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
 		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_277 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
@@ -10816,14 +8778,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
 		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_278 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
@@ -10832,14 +8787,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
 		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_279 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
@@ -10848,14 +8796,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
 		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_280 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
@@ -10864,14 +8805,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
 		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_281 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
@@ -10880,15 +8814,8 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
 		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_282 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_valids <= 8'd0;
 	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
@@ -10899,9 +8826,6 @@ always @(*) begin
 	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-// synthesis translate_off
-	dummy_d_283 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
 assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
@@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
 assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
 assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
 assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
 	end
-// synthesis translate_off
-	dummy_d_284 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
 	end
-// synthesis translate_off
-	dummy_d_285 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
 	end
-// synthesis translate_off
-	dummy_d_286 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
 assign main_litedramcore_dfi_p0_reset_n = 1'd1;
@@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1;
 assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
 assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
 assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
 always @(*) begin
 	builder_multiplexer_next_state <= 4'd0;
 	builder_multiplexer_next_state <= builder_multiplexer_state;
@@ -11023,14 +8922,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_287 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11067,14 +8959,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_288 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11102,14 +8987,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_289 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11151,27 +9029,14 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_290 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
+	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -11190,30 +9055,22 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_291 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
+	main_litedramcore_steerer_sel1 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -11232,16 +9089,16 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_292 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11282,14 +9139,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_293 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11324,14 +9174,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_294 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11372,14 +9215,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_295 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11407,14 +9243,7 @@ always @(*) begin
 			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11449,14 +9278,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11484,14 +9306,7 @@ always @(*) begin
 			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11519,9 +9334,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_299 = dummy_s;
-// synthesis translate_on
 end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
@@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
 assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11580,14 +9388,7 @@ always @(*) begin
 			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_300 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11598,9 +9399,6 @@ always @(*) begin
 			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_301 = dummy_s;
-// synthesis translate_on
 end
 assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
 assign builder_roundrobin0_grant = 1'd0;
@@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0;
 assign builder_roundrobin5_grant = 1'd0;
 assign builder_roundrobin6_grant = 1'd0;
 assign builder_roundrobin7_grant = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
 always @(*) begin
 	builder_next_state <= 2'd0;
 	builder_next_state <= builder_state;
@@ -11631,14 +9425,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_302 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value_ce2 <= 1'd0;
 	case (builder_state)
@@ -11653,14 +9440,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_303 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_wishbone_dat_r <= 32'd0;
 	case (builder_state)
@@ -11672,71 +9452,43 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_304 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
+	builder_litedramcore_dat_w_next_value0 <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_306 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	builder_litedramcore_wishbone_ack <= 1'd0;
 	case (builder_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_307 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_adr_next_value1 <= 14'd0;
 	case (builder_state)
@@ -11751,14 +9503,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_308 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (builder_state)
@@ -11773,14 +9518,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_309 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value2 <= 1'd0;
 	case (builder_state)
@@ -11795,9 +9533,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_310 = dummy_s;
-// synthesis translate_on
 end
 assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
 assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
@@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_311 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
 		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_312 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	builder_csrbank0_init_done0_re <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_313 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
 	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_314 = dummy_s;
-// synthesis translate_on
+end
+always @(*) begin
+	builder_csrbank0_init_error0_we <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_315 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_316 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_317 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_318 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_319 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_320 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_321 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_322 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_323 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_324 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_325 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_326 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_327 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_328 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_329 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_330 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_331 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_332 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_333 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_335 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_336 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_337 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_338;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_338 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_339;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_339 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_340;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_340 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
 assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
@@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_341;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_341 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_342;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_control0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
 		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_342 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_343;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_control0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_343 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_344;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_344 = dummy_s;
-// synthesis translate_on
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_345;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_345 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_346;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
 	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
 		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_346 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_347;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_347 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_348;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_348 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_349;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
 		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_349 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_350;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_350 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_351;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
 		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_351 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_352;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
 		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_352 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_353;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_353 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_354;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_354 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_355;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_355 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_356;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_357 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_358;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_358 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_359;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_359 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_360;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_360 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_361;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_361 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_362;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_362 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_363;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_363 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_364;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_364 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_365;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_365 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_366;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_366 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_367;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_367 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_368;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_368 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_369;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_369 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_370;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_370 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_371;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_371 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_372;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
 		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_372 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_373;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_373 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_374;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_374 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_375;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_375 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_376;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_376 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_377;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_377 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_378;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_378 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_379;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_379 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_380;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_380 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_381;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_381 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_382;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_382 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_383;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_383 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_384;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_384 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_385;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_385 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_386;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_386 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_387;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_387 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_388;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_388 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_389;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_389 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_390;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_390 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_391;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_391 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_392;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_392 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_393;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_393 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_394;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_394 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_395;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_395 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_396;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_396 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_397;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
 		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_397 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_398;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
 		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_398 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_399;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_399 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_400;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_400 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_401;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_401 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_402;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_402 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_403;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_403 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_404;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_404 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_405;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_405 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_406;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_406 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_407;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_407 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_408;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_408 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_409;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_409 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_410;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_410 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_411;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_411 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_412;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_412 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_413;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_413 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_414;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_414 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_415;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_416;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_416 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_417;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_417 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_418;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_418 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_419;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_419 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_420;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_420 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_421;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_421 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_422;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_422 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_423;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_423 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_424;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_424 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0];
-
-// synthesis translate_off
-reg dummy_d_425;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_425 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_426;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_426 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_427;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_427 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_428;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_428 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_429;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_429 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_430;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_430 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_431;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_431 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_432;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_432 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_433;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_433 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_434;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_434 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_435;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_435 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_436;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_436 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_437;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_437 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_438;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_438 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_439;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_439 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_440;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_440 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_441;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_441 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_442;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_442 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_443;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_443 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_444;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_444 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_445;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_445 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_446;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_446 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
@@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
 assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
 assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
 assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
 assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
 assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
 assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_csr_interconnect_adr = builder_litedramcore_adr;
 assign builder_csr_interconnect_we = builder_litedramcore_we;
 assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
@@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-
-// synthesis translate_off
-reg dummy_d_447;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13760,14 +10147,7 @@ always @(*) begin
 			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_447 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_448;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed1 <= 15'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13796,14 +10176,7 @@ always @(*) begin
 			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_448 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_449;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed2 <= 3'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13832,14 +10205,7 @@ always @(*) begin
 			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_449 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_450;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13868,14 +10234,7 @@ always @(*) begin
 			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_450 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_451;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13904,14 +10263,7 @@ always @(*) begin
 			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_451 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_452;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13940,14 +10292,7 @@ always @(*) begin
 			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_452 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_453;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13976,14 +10321,7 @@ always @(*) begin
 			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_453 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_454;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed1 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14012,14 +10350,7 @@ always @(*) begin
 			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_454 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_455;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed2 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14048,14 +10379,7 @@ always @(*) begin
 			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_455 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_456;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed6 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14084,14 +10408,7 @@ always @(*) begin
 			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_456 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_457;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed7 <= 15'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14120,14 +10437,7 @@ always @(*) begin
 			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_457 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_458;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed8 <= 3'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14156,14 +10466,7 @@ always @(*) begin
 			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_458 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_459;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed9 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14192,14 +10495,7 @@ always @(*) begin
 			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_459 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_460;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed10 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14228,14 +10524,7 @@ always @(*) begin
 			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_460 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_461;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed11 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14264,14 +10553,7 @@ always @(*) begin
 			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_461 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_462;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14300,14 +10582,7 @@ always @(*) begin
 			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_462 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_463;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14336,14 +10611,7 @@ always @(*) begin
 			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_463 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_464;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14372,14 +10640,7 @@ always @(*) begin
 			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_464 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_465;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed12 <= 22'd0;
 	case (builder_roundrobin0_grant)
@@ -14387,14 +10648,7 @@ always @(*) begin
 			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_465 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_466;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed13 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14402,14 +10656,7 @@ always @(*) begin
 			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_466 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_467;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed14 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14417,14 +10664,7 @@ always @(*) begin
 			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_467 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_468;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed15 <= 22'd0;
 	case (builder_roundrobin1_grant)
@@ -14432,14 +10672,7 @@ always @(*) begin
 			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_468 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_469;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed16 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14447,14 +10680,7 @@ always @(*) begin
 			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_469 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_470;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed17 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14462,14 +10688,7 @@ always @(*) begin
 			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_470 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_471;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed18 <= 22'd0;
 	case (builder_roundrobin2_grant)
@@ -14477,14 +10696,7 @@ always @(*) begin
 			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_471 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_472;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed19 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14492,14 +10704,7 @@ always @(*) begin
 			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_472 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_473;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed20 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14507,14 +10712,7 @@ always @(*) begin
 			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_473 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_474;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed21 <= 22'd0;
 	case (builder_roundrobin3_grant)
@@ -14522,14 +10720,7 @@ always @(*) begin
 			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_474 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_475;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed22 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14537,14 +10728,7 @@ always @(*) begin
 			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_475 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_476;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed23 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14552,14 +10736,7 @@ always @(*) begin
 			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_476 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_477;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed24 <= 22'd0;
 	case (builder_roundrobin4_grant)
@@ -14567,14 +10744,7 @@ always @(*) begin
 			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_477 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_478;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed25 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14582,14 +10752,7 @@ always @(*) begin
 			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_478 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_479;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed26 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14597,14 +10760,7 @@ always @(*) begin
 			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_479 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_480;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed27 <= 22'd0;
 	case (builder_roundrobin5_grant)
@@ -14612,14 +10768,7 @@ always @(*) begin
 			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_480 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_481;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed28 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14627,14 +10776,7 @@ always @(*) begin
 			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_481 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_482;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed29 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14642,14 +10784,7 @@ always @(*) begin
 			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_482 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_483;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed30 <= 22'd0;
 	case (builder_roundrobin6_grant)
@@ -14657,14 +10792,7 @@ always @(*) begin
 			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_483 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_484;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed31 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14672,14 +10800,7 @@ always @(*) begin
 			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_484 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_485;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed32 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14687,14 +10808,7 @@ always @(*) begin
 			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_485 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_486;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed33 <= 22'd0;
 	case (builder_roundrobin7_grant)
@@ -14702,14 +10816,7 @@ always @(*) begin
 			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_486 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_487;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed34 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14717,14 +10824,7 @@ always @(*) begin
 			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_487 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_488;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed35 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14732,14 +10832,7 @@ always @(*) begin
 			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_488 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_489;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed0 <= 3'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14756,14 +10849,7 @@ always @(*) begin
 			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_489 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_490;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed1 <= 15'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14780,14 +10866,7 @@ always @(*) begin
 			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_490 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_491;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed2 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14804,14 +10883,7 @@ always @(*) begin
 			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_491 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_492;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed3 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14828,14 +10900,7 @@ always @(*) begin
 			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_492 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_493;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed4 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14852,14 +10917,7 @@ always @(*) begin
 			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_493 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_494;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed5 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14876,14 +10934,7 @@ always @(*) begin
 			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_494 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_495;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed6 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14900,14 +10951,7 @@ always @(*) begin
 			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_495 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_496;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed7 <= 3'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14924,14 +10968,7 @@ always @(*) begin
 			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_496 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_497;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed8 <= 15'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14948,14 +10985,7 @@ always @(*) begin
 			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_497 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_498;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed9 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14972,14 +11002,7 @@ always @(*) begin
 			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_498 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_499;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed10 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14996,14 +11019,7 @@ always @(*) begin
 			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_499 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_500;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed11 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15020,14 +11036,7 @@ always @(*) begin
 			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_500 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_501;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed12 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15044,14 +11053,7 @@ always @(*) begin
 			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_501 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_502;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed13 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15068,14 +11070,7 @@ always @(*) begin
 			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_502 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_503;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed14 <= 3'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15092,14 +11087,7 @@ always @(*) begin
 			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_503 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_504;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed15 <= 15'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15116,14 +11104,7 @@ always @(*) begin
 			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_504 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_505;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed16 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15140,14 +11121,7 @@ always @(*) begin
 			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_505 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_506;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed17 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15164,14 +11138,7 @@ always @(*) begin
 			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_506 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_507;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed18 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15188,14 +11155,7 @@ always @(*) begin
 			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_507 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_508;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed19 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15212,14 +11172,7 @@ always @(*) begin
 			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_508 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_509;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed20 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15236,14 +11189,7 @@ always @(*) begin
 			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_509 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_510;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed21 <= 3'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15260,14 +11206,7 @@ always @(*) begin
 			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_510 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_511;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed22 <= 15'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15284,14 +11223,7 @@ always @(*) begin
 			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_511 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_512;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed23 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15308,14 +11240,7 @@ always @(*) begin
 			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_512 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_513;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed24 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15332,14 +11257,7 @@ always @(*) begin
 			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_513 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_514;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed25 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15356,14 +11274,7 @@ always @(*) begin
 			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_514 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_515;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed26 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15380,14 +11291,7 @@ always @(*) begin
 			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_515 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_516;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed27 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15404,15 +11308,17 @@ always @(*) begin
 			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_516 = dummy_s;
-// synthesis translate_on
 end
 assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge iodelay_clk) begin
 	if ((main_reset_counter != 1'd0)) begin
 		main_reset_counter <= (main_reset_counter - 1'd1);
@@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+			5'd24: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
 	end
 	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address1_re) begin
-		main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+		main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
 	end
 	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
 	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
 		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
 	end
 	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
 	if (builder_csrbank2_dfii_pi1_command0_re) begin
 		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
 	end
 	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address1_re) begin
-		main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+		main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
 	end
 	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
 	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
 		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
 	end
 	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
 	if (builder_csrbank2_dfii_pi2_command0_re) begin
 		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
 	end
 	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address1_re) begin
-		main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+		main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
 	end
 	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
 	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
 		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
 	end
 	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
 	if (builder_csrbank2_dfii_pi3_command0_re) begin
 		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
 	end
 	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address1_re) begin
-		main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+		main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
 	end
 	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
 	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
 		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
 	end
 	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
 		main_a7ddrphy_rst_storage <= 1'd0;
 		main_a7ddrphy_rst_re <= 1'd0;
@@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
 BUFG BUFG(
 	.I(main_clkout0),
 	.O(main_clkout_buf0)
@@ -19603,118 +15382,150 @@ IOBUF IOBUF_15(
 	.O(main_a7ddrphy_dq_i_nodelay15)
 );
 
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage[0:15];
-reg [24:0] memdat;
+reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_1[0:15];
-reg [24:0] memdat_1;
+reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_2[0:15];
-reg [24:0] memdat_2;
+reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_3[0:15];
-reg [24:0] memdat_3;
+reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_4[0:15];
-reg [24:0] memdat_4;
+reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_5[0:15];
-reg [24:0] memdat_5;
+reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_6[0:15];
-reg [24:0] memdat_6;
+reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
+// Port 1 | Read: Async | Write: ---- | 
 reg [24:0] storage_7[0:15];
-reg [24:0] memdat_7;
+reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 FD FD(
 	.C(main_clkin),
 	.D(main_reset),
@@ -19871,3 +15682,7 @@ PLLE2_ADV #(
 );
 
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:10.
+//------------------------------------------------------------------------------
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index 542287d..e0b2512 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
@@ -527,11 +527,11 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-6000000048001871
+60000000480017fd
 7fc3f3787c7f1b78
-600000004800127d
+6000000048001221
 7fe3fb78382100b0
-0000000048001e68
+0000000048001e78
 0000028001000000
 000000004e800020
 0000000000000000
@@ -540,83 +540,84 @@ f9410108f9210100
 0000000000000000
 3842a3203c4c0001
 7d8000267c0802a6
-9181000848001da5
-48001279f821fed1
+9181000848001db5
+4800121df821fed1
 3c62ffff60000000
-4bffff3938637b28
+4bffff3938637b38
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637b48
+63ff000838637b58
 3c62ffff4bffff15
-38637b687bff0020
+38637b787bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b80
+4bfffee938637b90
 4e00000073e90002
 3c62ffff41820010
-4bfffed138637b88
+4bfffed138637b98
 4d80000073e90004
 3c62ffff41820010
-4bfffeb938637b90
+4bfffeb938637ba0
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b98
+4bfffea138637ba8
 4182001073e90010
-38637ba83c62ffff
-73e901004bfffe8d
+38637bb83c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637bb8
-3b7b7bc03f62ffff
+4bfffe7938637bc8
+3b7b7bd03f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bc8
+4bfffe4138637bd8
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637be0
+4bfffe1938637bf0
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637bf87884b282
+38637c087884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637c107c892392
+38637c207c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637c307f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637c40
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,123 +625,113 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637c50
-4082009073890002
-38637c703c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637c6057a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637c80
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637c88
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637c987fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847cc838a57cb8
-4bfffb8938637cd0
-600000004800039d
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637c983c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637ca87b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637cd838a57cc8
+4bfffb897ca42b78
+6000000048000355
 3c62ffff418e0024
-4bfffb7138637d00
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637d08
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637d18
-38a000403c9df000
+4bfffb4938637d20
+38a000403c9af000
 3861007078840020
-60000000480010d1
+6000000048000f2d
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637d30
+794a83e438637d38
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637d503c62ffff
+38637d583c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637db088810070
+38637db888810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637de0
+4bfffaa938637de8
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-6000000048001029
-38637e003c62ffff
+6000000048000e85
+38637e083c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187d683b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637d903c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff000480018bc
-7884002038a00038
-48000fa57f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-48000f5d7f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637c80
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
-7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
-0000000000000000
-3d20c80000000000
-7929002061290004
+3ba000003f02ffff
+3b187d703b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637d98
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+480018d07d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048000e05
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+6000000048000dbd
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637c903c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061290804
 7c604f2a7c0004ac
 392000013d40c800
-794a0020614a0008
+794a0020614a0808
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
@@ -751,269 +742,272 @@ a12100a660000000
 4bfffff060000000
 0000000000000000
 3c4c000100000000
-3d40c80038429c7c
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c09000e
+3d20c80038429cc4
+7929002061290800
+7d404e2a7c0004ac
+4d820020280a000e
 f80100107c0802a6
-3920000ef821ffa1
-7d20572a7c0004ac
-38637e183c62ffff
-600000004bfff87d
+3940000ef821ffa1
+7d404f2a7c0004ac
+38637e203c62ffff
+600000004bfff8c5
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-3d40c80038429c14
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c090001
+3d20c80038429c5c
+7929002061290800
+7d404e2a7c0004ac
+4d820020280a0001
 f80100107c0802a6
-39200001f821ffa1
-7d20572a7c0004ac
-38637e403c62ffff
-600000004bfff815
+39400001f821ffa1
+7d404f2a7c0004ac
+38637e483c62ffff
+600000004bfff85d
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429bac
-f821ff7148001641
-3c62ffff3f80c800
-38637e683c804000
-4bfff7c9639c0800
-3bc0000060000000
-7b9c00204bffff05
-7fc0e72a7c0004ac
-637b08043f60c800
-7c0004ac7b7b0020
-3fe0c8007fc0df2a
-63ff001438600000
-7bff00204bfffe21
-7fc0ff2a7c0004ac
-3920000c3fa0c800
+7c0802a638429bf4
+f821ff7148001695
+3c62ffff3c804000
+38637e703f60c800
+4bfff8113be00000
+7b7b002060000000
+7c0004ac4bffff05
+3f40c8007fe0df2a
+7b5a0020635a0004
+7fe0d72a7c0004ac
+63bd080c3fa0c800
 7c0004ac7bbd0020
-386000007d20ef2a
-4bfffe6d6063c350
-4bfffded38600000
-7fc0ff2a7c0004ac
-7c0004ac3920000e
-386027107d20ef2a
-386002004bfffe49
-392000024bfffdc9
-7d20ff2a7c0004ac
-4bfffdf13860000f
-4bfffdad38600000
+3fc0c8007fe0ef2a
+7bde002063de0810
+7fe0f72a7c0004ac
+3920000c3f80c800
+7b9c0020639c0800
+7d20e72a7c0004ac
+6063c35038600000
+7c0004ac4bfffe61
+7c0004ac7fe0ef2a
+3920000e7fe0f72a
+7d20e72a7c0004ac
+4bfffe3d38602710
+7c0004ac39200200
+392000027d20ef2a
+7d20f72a7c0004ac
+4bfffde13860000f
+7fe0ef2a7c0004ac
 7c0004ac39200003
-3860000f7d20ff2a
-4bfffdd13ba00001
-4bfffd8d38600006
-7fa0ff2a7c0004ac
-4bfffdb93860000f
-4bfffd7538600920
-7fc0ff2a7c0004ac
-4bfffda13860000f
-4bfffdd5386000c8
-4bfffd5538600400
-7fc0ff2a7c0004ac
-4bfffd8138600003
-4bfffdb5386000c8
-388004004bfffe55
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100907fa0e72a
-38c0000048001520
-3880040038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000058001000000
-384299f83c4c0001
+3860000f7d20f72a
+392000064bfffdc5
+7d20ef2a7c0004ac
+7c0004ac3b800001
+3860000f7f80f72a
+392009204bfffda5
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfffd893860000f
+4bfffdbd386000c8
+7c0004ac39200400
+7c0004ac7d20ef2a
+386000037fe0f72a
+386000c84bfffd65
+4bfffe394bfffd99
+3c60400038800400
+6000000048000779
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100907f80df2a
+480015507d2307b4
+38a0000038c00000
+3c60400038800400
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000680
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+384299e03c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637e883c62ffff
-600000004bfff615
+38637e903c62ffff
+600000004bfff5fd
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bfff5d938637e90
+4bfff5c138637e98
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637ea0
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637ea8
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637eb07ca54b92
+38637eb87ca54b92
 000000004bffffa4
 0000008001000000
-384299283c4c0001
+384299103c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bfff53938637ec0
+4bfff52138637ec8
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bfff52138637ed0
+4bfff50938637ed8
 3821007060000000
-00000000480013e4
+00000000480013dc
 0000018001000000
-384298c03c4c0001
-480013597c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bfff541
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bfff511
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d00004800132c
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+384298a83c4c0001
+480013517c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bfff521
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bfff4d1
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f4
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384297d83c4c0001
-480012757c0802a6
+384297983c4c0001
+480012457c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
-4bfff44d7bff0020
-395f000160000000
-7d4903a62fbe0000
+420000387cbd2b78
+4bfff4157bff0020
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126438210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e002848001238
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a6384296d4
-480011517d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67ed8
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384296b03c4c0001
+7d8000267c0802a6
+9181000848001139
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67ee0
 3c62ffff4082009c
-38637ed87b251028
-4bfffd357ba40020
-38637bc03c62ffff
-600000004bfff28d
-4bfff2f53ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637ee878a51028
-4bfffccd7ba40020
-38637bc03c62ffff
-600000004bfff225
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637ee87ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fa87d838120
+38637ee07b851028
+4bfffd357b240020
+38637bd03c62ffff
+600000004bfff275
+600000004bfff2e1
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637ef07b051028
+4bfffcdd7be40020
+38637bd03c62ffff
+600000004bfff21d
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010a8
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637ef07ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a6384294bc
+3c4c000100000b80
+7c0802a6384294ec
 918100087d908026
-f821ff8148000f4d
+f821ff7148000f85
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637ef8
-600000004bfff0c5
-38637f103c62ffff
+7cbc2b7838637f00
+600000004bfff0f5
+38637f183c62ffff
 3c62ffff4092000c
-4bfff0a938637f20
+4bfff0d938637f28
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637f303c62ffff
-600000004bfff08d
+4bfffaad7bfde8c2
+38637f383c62ffff
+600000004bfff0bd
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1022,466 +1016,474 @@ f821ff8148000f4d
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637f38
-600000004bfff03d
-4bfff9fd7f83e378
-38637f483c62ffff
-600000004bfff025
-38637bc03c62ffff
-600000004bfff015
-600000004bfff081
-409200287cf602a6
+7f9c4b9238637f40
+600000004bfff06d
+4bfffa457f83e378
+38637f503c62ffff
+600000004bfff055
+38637bd03c62ffff
+600000004bfff045
+600000004bfff0b1
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637f50
-600000004bffef8d
-4bfff94d7fe3fb78
-38637f483c62ffff
-600000004bffef75
-38637bc03c62ffff
-600000004bffef65
-8181000838210080
-48000e007d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a6384292b4
-f821ff7148000d45
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f0080
-3b60008040810008
-7fc4f3783c62ffff
-4bffeeb138637f60
-7fe3fb7860000000
-3c62ffff4bfff871
-4bffee9938637f30
-7f44d37860000000
-4bfff98d7fc3f378
-7f64db7838a00000
-7fc3f3787c7c1b78
-38c000004bfffa61
-7fe4fb7838a00001
-7fc3f3787c7d1b78
-7d3cea144bfffb4d
-7c7e1b787d291a14
-418200682c090000
-7b45f8823c62ffff
-38637f707f84e378
-600000004bffee35
-7b65f0823c62ffff
-38637f887fa4eb78
-600000004bffee1d
-7be5f0823c62ffff
-38637fa07fc4f378
-600000004bffee05
-38637fb83c62ffff
-600000004bffedf5
-3821009038600000
-3c62ffff48000c8c
-4bffedd938637fc8
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f58
+600000004bffefcd
+4bfff9a57fe3fb78
+38637f503c62ffff
+600000004bffefb5
+38637bd03c62ffff
+600000004bffefa5
+8181000838210090
+48000e487d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384293103c4c0001
+48000db17c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f00807c9a2378
+408100087ffbfb78
+3c62ffff3b600080
+38637f687fc4f378
+600000004bffef0d
+4bfff8e57fe3fb78
+38637f383c62ffff
+600000004bffeef5
+7fc3f3787f44d378
+38a000004bfffa01
+7c7c1b787f64db78
+4bfffafd7fc3f378
+38a0000138c00000
+7c7d1b787fe4fb78
+4bfffbcd7fc3f378
+7d291a147d3de214
+2c0900007c7e1b78
+3c62ffff4182006c
+7f84e3787b45f882
+4bffee9138637f78
+3c62ffff60000000
+7fa4eb787b65f082
+4bffee7938637f90
+3c62ffff60000000
+7fc4f3787be5f082
+4bffee6138637fa8
+3c62ffff60000000
+4bffee5138637fc0
+3860000060000000
+7c6307b438210090
+3c62ffff48000cf4
+4bffee3138637fd0
 3860000160000000
-000000004bffffe4
+000000004bffffe0
 0000068001000000
-384291783c4c0001
-3922804860000000
-3942804060000000
-2c09000089290000
-e92a00004182002c
-7c0004ac39290014
-712900207d204eaa
-e92a00004182ffec
-7c604faa7c0004ac
-e92a00004e800020
-7c0004ac39290010
-712900087d204eea
-5469063e4082ffec
-7c0004ace94a0000
-4e8000207d2057ea
-0000000000000000
-3c4c000100000000
-7c0802a6384290f4
-fbe1fff8fbc1fff0
-f821ffd1f8010010
-8fdf00013be3ffff
-408200102c3e0000
-3860000038210030
-281e000a48000bd0
-3860000d4082000c
-7fc3f3784bffff41
-4bffffd04bffff39
-0100000000000000
-3c4c000100000280
-3d00c00038429094
-7908002061080020
-7d0046ea7c0004ac
-790806003d20c000
-7929002061290008
+384291d03c4c0001
+8922805060000000
+3942804860000000
+4182002c2c090000
+39290014e92a0000
+7d204eaa7c0004ac
+4182ffec71290020
+7c0004ace92a0000
+4e8000207c604faa
+39290010e92a0000
 7d204eea7c0004ac
-4182001871290020
-612900403d20c000
+4082ffec71290008
+e94a00005469063e
+7d2057ea7c0004ac
+000000004e800020
+0000000000000000
+384291503c4c0001
+fbc1fff07c0802a6
+f8010010fbe1fff8
+3be3fffff821ffd1
+2c1e00008fdf0001
+3821003040820010
+48000c3c38600000
+4082000c2c1e000a
+4bffff453860000d
+4bffff3d7fc307b4
+000000004bffffd0
+0000028001000000
+384290f03c4c0001
+614a00203d40c000
+7c0004ac794a0020
+3d20c0007d4056ea
+61290008794a0600
 7c0004ac79290020
-3d40c0007d204eea
-6000000060000000
-614a200038e28048
-f9428040794a0020
-614a20003d40001c
-792af8047d085392
-41820080794a0fc3
-3d40c00039200001
-99270000614a200c
-3920ff80794a0020
-7d2057aa7c0004ac
-7c0004ace9228040
-e92280407d004faa
-392900047908c202
-7d004faa7c0004ac
-39400003e9228040
+712900207d204eea
+3d20c00041820018
+7929002061290040
+7d204eea7c0004ac
+3d00c0007929f804
+6108200079290fc3
+6000000079080020
+3d00001cf9028048
+7d4a439261082000
+6000000041820084
+9922805039200001
+6108200c3d00c000
+790800203920ff80
+7d2047aa7c0004ac
+7c0004ace9228048
+e92280487d404faa
+39290004794ac202
+7d404faa7c0004ac
+39400003e9228048
 7c0004ac3929000c
-e92280407d404faa
+e92280487d404faa
 7c0004ac39290010
-e92280407d404faa
+e92280487d404faa
 3929000839400007
 7d404faa7c0004ac
-3d20c0004e800020
-3908ffff99470000
-7929002061292018
-7d004fea7c0004ac
-000000004e800020
+600000004e800020
+99228050394affff
+612920183d20c000
+7c0004ac79290020
+4e8000207d404fea
+0000000000000000
+78a9e8c200000000
+3929000139400000
+420000287d2903a6
+7ca9285078a90724
+390500017d434a14
+7d0903a67c844a14
+4200001839200000
+7d24502a4e800020
+394a00087d23512a
+7d0448ae4bffffcc
+392900017d0a49ae
+000000004bffffdc
+0000000000000000
+386000007c691b78
+2c0a00007d4918ae
+386300014d820020
+000000004bfffff0
 0000000000000000
 408200082c240000
 280500243881fff0
 38600000f8640000
-3ce000014d810020
-60e7260078e783e4
-892a0000e9440000
-4081002828090020
-4182003c2c250000
-418200382c050010
-4800008038600000
-f9440000394a0001
-7ce94c364bffffd0
-4082ffec71290001
-4082ffdc2c250000
-4bffffd438a0000a
-2809003038a0000a
-892a00014082ffc8
-4082ffbc2c090078
-38a00010394a0002
-4bffffacf9440000
-54ca063e38c9ffd0
-41810034280a0009
-7c0928007cc90734
-38e700014c800020
-f8e400007c6519d2
-e8e400007c691a14
-2c29000089270000
-4e8000204082ffc8
-554a063e3949ff9f
-41810010280a0019
-7d2907343929ffa9
-3949ffbf4bffffbc
+3d00fffe4d810020
+790883e46108ffff
+e92400006108d9ff
+280a002089490000
+2c25000040810028
+2c0500104182003c
+3860000041820038
+3929000148000088
+4bffffd0f9240000
+714a00017d0a5634
+2c2500004182ffec
+38a0000a4082ffdc
+38a0000a4bffffd4
+4082ffc82c0a0030
+2c0a007889490001
+392900024082ffbc
+f924000038a00010
+38eaffd04bffffac
+2807000954e7063e
+3929ffd04181003c
+7c0a28007d2a0734
+390800014c800020
+7d2907347c6519d2
+7c691a14f9040000
+89480000e9040000
+4082ffc0714900ff
+38eaff9f4e800020
+2807001954e7063e
+3929ffa94181000c
+394affbf4bffffb8
 280a0019554a063e
 3929ffc94d810020
-000000004bffffe4
-0000000000000000
-386000007c6a1b78
-2c0900007d2a18ae
-386300014d820020
-000000004bfffff0
+000000004bffffa0
 0000000000000000
-3940000078a9e8c2
-7d2903a639290001
-78a9e8c242000030
-1d29fff878aa0724
-7c8452147d035214
-392000007ca92a14
-7d4903a639450001
-4e80002042000018
-7d23512a7d24502a
-4bffffc4394a0008
-7d4849ae7d4448ae
-4bffffdc39290001
-0000000000000000
-3923ff9f00000000
-4d81002028090019
-7c6307b43863ffe0
-000000004e800020
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428d903c4c0001
+3c4c000100000000
+7c0802a638428dec
+f821ffa148000889
+7c9c23787c7e1b78
+388000007ca32b78
+7cfd3b7838a0000a
+7d1b4378eb3e0000
+7cdf33787d3a4b78
+600000004bfffe79
+392000002b9d0010
+2c3f00007c681b78
+2c09000040820024
+3920000140820008
+7c0348007d29d214
+3821006041810054
+409e001048000870
+392900017bffe102
+7fffeb924bffffcc
+9b6900004bfffff4
+394affff2c2a0001
+39290001e93e0000
+4182ffc8f93e0000
+7d194850e93e0000
+4180ffd87c28e040
+7d2940504bffffb4
+3949ffff2c090000
+394a0001794a0020
+3d00800040810010
+4082ffcc7c094000
+4bffffc439400001
+0100000000000000
+3c4c000100000780
+7c0802a638428cf4
+f821ffb148000799
+7c7f1b783bc00000
+eb6300007c9c2378
+7fa3eb787cbd2b78
+600000004bfffd69
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007a438210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428c783c4c0001
 7d9080267c0802a6
-4800081991810008
+4800071191810008
 3be00000f821ffa1
-7cbe2b787c7c1b78
-e9297fd83d22ffff
-f92100207cdd3378
+7c7c1b782b860010
 e9297fe03d22ffff
-7ca92b78f9210028
-408200342c290000
-408200082c3f0000
-7c3f20403be00001
-386000002e270000
-408100383b7fffff
-8181000838210060
-480008007d908120
-40820014281d0010
-3bff00017929e102
-4bffffb47fff07b4
-4bfffff07d29eb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-4bffff2141920010
-5463063e60000000
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-7fe9fa1438600001
-4bffff84fbfc0000
+7cdd33787cbe2b78
+f92100207caa2b78
+e9297fe83d22ffff
+2c2a0000f9210028
+2c1f000040820034
+3be0000140820008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d90812081810008
+409e0010480006f4
+3bff0001794ae102
+7d4aeb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdad5463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
 0300000000000000
 3c4c000100000680
-7c0802a638428c94
-f821ffb148000729
-7c7f1b783bc00000
-eb6300007c9c2378
-7fa3eb787cbd2b78
-600000004bfffe21
-408100147c23f040
-7d3b5050e95f0000
-418000107c29e040
-3860000138210050
-7d3df0ae48000730
-992a00003bde0001
-39290001e93f0000
-4bffffb8f93f0000
-0100000000000000
-3c4c000100000580
-7c0802a638428c14
-f821ffa1480006a1
-7c9b23787c7d1b78
-388000007ca32b78
-7d3f4b7838a0000a
-7cde3378eb3d0000
-7d1a43787cfc3b78
-600000004bfffc71
-7c6307b439200000
-4082002c2c3e0000
-408200082c290000
-7d3f4a1439200001
-7d2a07b47c034800
-3821006041810060
-4800068438600000
-40820014281c0010
-392900017bdee102
-4bffffbc7d2907b4
-4bfffff07fdee392
-2c2900019b480000
-e95d00003929ffff
-f95d0000394a0001
-e91d00004182ffbc
-7c2ad8407d594050
-4bffffa84180ffd8
-2c0a00007d4a1850
-79290020392affff
-4081001039290001
-7c0a18003c608000
-392000014082ffcc
-000000004bffffc4
-0000078001000000
-38428b103c4c0001
-480005717c0802a6
-7c741b79f821fed1
-38600000f8610060
-2c24000041820064
-392100404182005c
-3e22ffff3e42ffff
-f92100783ae4ffff
-3ac000003b210020
-3ba100603a527ff8
-892500003a317ff0
-2c290000ebc10060
-7ff4f05041820010
-418000207c3fb840
+7c0802a638428b84
+f821fee1480005f5
+7c691b793be00000
+f9210068f8610060
+2c24000041820060
+3921004041820058
+3e22ffff60000000
+f92100703ae4ffff
+3ac000003b010020
+3a6280003a400020
+3a317ff83ba10060
+89250000e9410068
+7feaf050ebc10060
+4182000c712a00ff
+418000187c3fb840
 993e000039200000
-7e941850e8610060
-382101307e8307b4
-2809002548000544
-408204c439450001
+7fe307b438210120
+2c0a0025480005c4
+4082054839050001
 8925000038e00000
-f8a10068e9010078
-7d2741ae7cea07b4
-8d25000139070001
-280900647d0807b4
-2809006941820058
-2809007541820050
-2809007841820048
-2809005841820040
-2809007041820038
-2809006341820030
-2809007341820028
-2809002541820020
-2809004f41820018
-2809006f41820010
-4082ff8838e70001
-28090025394a0002
-7d1942147d4a07b4
-992800207d595214
-408200209aca0020
-f9210060393e0001
-993e000039200025
-38a90002e9210068
-392600084bffff04
-7fffb850eb660000
-3b0100413a600020
-89210041f9210070
+7cb02b78e9010070
+8c6500017cea3b78
+390700017d2741ae
+2c0900645469063e
+28090078418200b0
+280900684181002c
+2c0900584181002c
+2809005841820098
+2c09002541810088
+2c09004f41820088
+38e7000141820080
+3883ff974bffffa4
+280b000f548b063e
+3d62ffff4181ffec
+788415a8396b75a8
+7c845a147c8b22aa
+4e8004207c8903a6
+ffffffcc00000048
+ffffffccffffffcc
+ffffffccffffffcc
+0000004800000048
+ffffffccffffffcc
+ffffffcc00000048
+ffffffcc00000048
+00000048ffffffcc
+4bffff842c090063
+2c090025394a0002
+7d4a07b47d0807b4
+7d5852147d184214
+9aca002098680020
+395e000140820018
+f9410060993e0000
+4bfffeb438b00002
+eb86000089210041
+39e600087fffb850
+3b2100413aa00020
 712900fd3929ffd2
-3a6000304082000c
-3aa000003b010042
-3b8000003b400004
-39e0002d3a000001
-480001647ddb00d0
-88f800012809004f
-418201d038980001
-54c5063e38c9ffa8
-4181037028050022
-38a576cc3ca2ffff
-7cc532aa78c615a8
-7cc903a67cc62a14
-000001484e800420
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000008c00000244
-0000035000000350
-0000033800000350
-000003500000008c
-0000032800000350
-0000035000000350
-000001ec000001a0
-0000035000000350
-0000035000000284
-000003500000008c
-0000014c00000350
-0000033000000350
-7d41e21428090075
-7f6adb789aca0020
-5749183841820034
-7e0948363929ffff
-418200207f694839
-e921006099e80000
-f921006039290001
-7d52482a7b491f24
+3aa000304082000c
+3a8000003b210042
+3b6000003b400004
+7ddc00d056b5063e
+2c06004f48000168
+418201dc38b90001
+54e4063e38e8ffa8
+418103ac28040022
+388476a43c82ffff
+7ce43aaa78e715a8
+7ce903a67ce72214
+000001504e800420
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000008c00000258
+0000038c0000038c
+000003700000038c
+0000038c0000008c
+0000035c0000038c
+0000038c0000038c
+000001fc000001ac
+0000038c0000038c
+0000038c00000298
+0000038c0000008c
+000001540000038c
+000003680000038c
+7b6a00202c060075
+9aca00207d415214
+418200387f8ae378
+3900000157471838
+7d08383638e7ffff
+418200207f884039
+392900013940002d
+f92100609949ffff
+7d53482a7b491e68
 e88100607dca5038
 38e0000a7d465378
-7f25cb78f9410080
-7e689b7839200000
+7f05c378f9410078
+7ea8ab7839200000
 7c9e20507fa3eb78
-4bfffc317c84f850
-e9410080e8810060
-38c0000a7ea7ab78
+4bfffa797c84f850
+e9410078e8810060
+38c0000a7a8707e0
 7d4553787c9e2050
 7fa3eb787c84f850
-3b1800014bfffa91
-e901006089380000
-418200102c290000
-7c3f50407d5e4050
-e8c100704181fe88
-3aa000014bfffe28
-38e000107d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffba9f9610080
-7ea7ab78e8810060
-7c9e205038c00010
-7d655b78e9610080
-7d21e2144bffff78
-7c8af85038e00008
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffb55
-38c000087ea7ab78
-4bffffac7c9e2050
-38e000107d21e214
-7c8af8507f66db78
-390000209ac90020
-7f25cb7839200002
-4bfffb197fa3eb78
-7e258b78e8810060
-7c9e20507fa3eb78
-4bfffa817c84f850
-7ea7ab78e8810060
-7f65db7838c00010
-4bfffed47c9e2050
-390000207d21e214
+3b3900014bfffbc9
+e921006089190000
+41820010710600ff
+7c3f50407d5e4850
+7de67b784181fe84
+3a8000014bfffe30
+38e000107b690020
+7c8af8507d214a14
+7f05c3787ea8ab78
+7b491e689ac90020
+7d73482a7fa3eb78
+7f8b583839200000
+f96100787d665b78
+e88100604bfff9ed
+38c000107a8707e0
+e96100787c9e2050
+4bffff747d655b78
+38e000087b690020
+7c8af8507d214a14
+7f05c3787ea8ab78
+7b491e689ac90020
+7d73482a7fa3eb78
+7f8b583839200000
+f96100787d665b78
+e88100604bfff995
+38c000087a8707e0
+4bffffa87c9e2050
+38e000107b690020
+7f86e3787d214a14
+390000207c8af850
+7f05c3789ac90020
+7fa3eb7839200002
+e88100604bfff955
+7fa3eb787e258b78
+7c84f8507c9e2050
+e88100604bfffa35
+38c000107a8707e0
+7c9e20507f85e378
+7b6900204bfffec8
+7d214a1439000020
 38c0000138e0000a
-7f25cb789ac90020
-7c8af85039200000
-4bfffac17fa3eb78
-9b690000e9210060
-39290001e9210060
-4bfffea0f9210060
-38a0000a7d21e214
-f9410088f9010090
-7f23cb7838800000
-4bfff72d9ac90020
-f861008060000000
-4bfff83d7f63db78
-e921008060000000
-4081004c7c291840
-e94100887d234851
-7d4af850e9010090
-3920000140820008
-7ce83050e8c10060
-408100247c2a3840
-2c29000138e00020
-98e600003929ffff
-38e70001e8e10060
-4082ffd4f8e10060
-7f65db78e8810060
+9ac900207f05c378
+392000007c8af850
+4bfff8f97fa3eb78
+9b890000e9210060
+f921006039290001
+7b6800204bfffe94
+f921008838a0000a
+7d014214f9410080
+7f03c37838800000
+4bfff76d9ac80020
+f861007860000000
+4bfff7357f83e378
+e901007860000000
+e9210088e9410080
+4181003c7c281840
+7f85e378e8810060
 7c9e20507fa3eb78
-4bfff9897c84f850
-2807006c4bfffdfc
-3b40000841820048
-280700684bfffdec
-4082fde03b400002
-3b4000017c982378
-3949ffd04bfffdd4
-280a0009554a063e
-395c00014181fdc4
-993c00207f81e214
-4bfffdb0795c0020
-4bffffb87c982378
-7d455378993e0000
-39290001e9210060
-4bfffae8f9210060
+4bfff9797c84f850
+9a4900004bfffe2c
+3900000139290001
+408200347c291840
+4bffffccf9210060
+7c6340507ce9f050
+7d4af8507ce7fa14
+7c691a142c270000
+394a000139000000
+3940000140820008
+394affff2c2a0001
+710800014082ffb4
+4bffff8c4082ffc0
+2c09006c89390001
+3b4000084182004c
+893900014bfffdbc
+2c0900683b400002
+7cb92b784082fdac
+4bfffda03b400001
+5529063e3928ffd0
+4181fd9028090009
+3b7b00017b690020
+990900207d214a14
+7cb92b784bfffd7c
+993e00004bffffb4
+7d0543783bde0001
+4bfffa6cfbc10060
 0100000000000000
 f9c1ff7000001280
 fa01ff80f9e1ff78
@@ -1557,9 +1559,8 @@ e8010010ebc1fff0
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index 398d7ad..1d6e21d 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -1,41 +1,62 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:42
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire sim_trace,
-	input wire clk,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:16
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire sim_trace,
+	input  wire clk,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [23:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [23:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [15:0] user_port_native_0_wdata_we,
-	input wire [127:0] user_port_native_0_wdata_data,
+	input  wire [15:0] user_port_native_0_wdata_we,
+	input  wire [127:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [127:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
 wire sys_clk;
 wire sys_rst;
 wire por_clk;
-reg soc_int_rst = 1'd1;
+reg  soc_int_rst = 1'd1;
 wire [13:0] soc_ddrphy_dfi_p0_address;
 wire [2:0] soc_ddrphy_dfi_p0_bank;
 wire soc_ddrphy_dfi_p0_cas_n;
@@ -100,328 +121,328 @@ wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
 wire soc_ddrphy_dfi_p3_rddata_en;
 wire [31:0] soc_ddrphy_dfi_p3_rddata;
 wire soc_ddrphy_dfi_p3_rddata_valid;
-reg soc_ddrphy_dfiphasemodel0_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_read = 1'd0;
-reg soc_ddrphy_bankmodel0_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel0_precharge = 1'd0;
+reg  soc_ddrphy_dfiphasemodel0_activate = 1'd0;
+reg  soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
+reg  soc_ddrphy_dfiphasemodel0_write = 1'd0;
+reg  soc_ddrphy_dfiphasemodel0_read = 1'd0;
+reg  soc_ddrphy_dfiphasemodel1_activate = 1'd0;
+reg  soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
+reg  soc_ddrphy_dfiphasemodel1_write = 1'd0;
+reg  soc_ddrphy_dfiphasemodel1_read = 1'd0;
+reg  soc_ddrphy_dfiphasemodel2_activate = 1'd0;
+reg  soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
+reg  soc_ddrphy_dfiphasemodel2_write = 1'd0;
+reg  soc_ddrphy_dfiphasemodel2_read = 1'd0;
+reg  soc_ddrphy_dfiphasemodel3_activate = 1'd0;
+reg  soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
+reg  soc_ddrphy_dfiphasemodel3_write = 1'd0;
+reg  soc_ddrphy_dfiphasemodel3_read = 1'd0;
+reg  soc_ddrphy_bankmodel0_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel0_precharge = 1'd0;
 wire soc_ddrphy_bankmodel0_write;
 wire [9:0] soc_ddrphy_bankmodel0_write_col;
 wire [127:0] soc_ddrphy_bankmodel0_write_data;
 wire [15:0] soc_ddrphy_bankmodel0_write_mask;
-reg soc_ddrphy_bankmodel0_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
-reg soc_ddrphy_bankmodel0_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel0_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel0_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel0_wraddr;
 wire [20:0] soc_ddrphy_bankmodel0_rdaddr;
-reg soc_ddrphy_bankmodel1_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel1_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel1_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel1_precharge = 1'd0;
 wire soc_ddrphy_bankmodel1_write;
 wire [9:0] soc_ddrphy_bankmodel1_write_col;
 wire [127:0] soc_ddrphy_bankmodel1_write_data;
 wire [15:0] soc_ddrphy_bankmodel1_write_mask;
-reg soc_ddrphy_bankmodel1_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
-reg soc_ddrphy_bankmodel1_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel1_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel1_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel1_wraddr;
 wire [20:0] soc_ddrphy_bankmodel1_rdaddr;
-reg soc_ddrphy_bankmodel2_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel2_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel2_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel2_precharge = 1'd0;
 wire soc_ddrphy_bankmodel2_write;
 wire [9:0] soc_ddrphy_bankmodel2_write_col;
 wire [127:0] soc_ddrphy_bankmodel2_write_data;
 wire [15:0] soc_ddrphy_bankmodel2_write_mask;
-reg soc_ddrphy_bankmodel2_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
-reg soc_ddrphy_bankmodel2_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel2_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel2_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel2_wraddr;
 wire [20:0] soc_ddrphy_bankmodel2_rdaddr;
-reg soc_ddrphy_bankmodel3_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel3_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel3_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel3_precharge = 1'd0;
 wire soc_ddrphy_bankmodel3_write;
 wire [9:0] soc_ddrphy_bankmodel3_write_col;
 wire [127:0] soc_ddrphy_bankmodel3_write_data;
 wire [15:0] soc_ddrphy_bankmodel3_write_mask;
-reg soc_ddrphy_bankmodel3_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
-reg soc_ddrphy_bankmodel3_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel3_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel3_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel3_wraddr;
 wire [20:0] soc_ddrphy_bankmodel3_rdaddr;
-reg soc_ddrphy_bankmodel4_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel4_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel4_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel4_precharge = 1'd0;
 wire soc_ddrphy_bankmodel4_write;
 wire [9:0] soc_ddrphy_bankmodel4_write_col;
 wire [127:0] soc_ddrphy_bankmodel4_write_data;
 wire [15:0] soc_ddrphy_bankmodel4_write_mask;
-reg soc_ddrphy_bankmodel4_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
-reg soc_ddrphy_bankmodel4_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel4_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel4_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel4_wraddr;
 wire [20:0] soc_ddrphy_bankmodel4_rdaddr;
-reg soc_ddrphy_bankmodel5_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel5_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel5_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel5_precharge = 1'd0;
 wire soc_ddrphy_bankmodel5_write;
 wire [9:0] soc_ddrphy_bankmodel5_write_col;
 wire [127:0] soc_ddrphy_bankmodel5_write_data;
 wire [15:0] soc_ddrphy_bankmodel5_write_mask;
-reg soc_ddrphy_bankmodel5_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
-reg soc_ddrphy_bankmodel5_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel5_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel5_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel5_wraddr;
 wire [20:0] soc_ddrphy_bankmodel5_rdaddr;
-reg soc_ddrphy_bankmodel6_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel6_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel6_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel6_precharge = 1'd0;
 wire soc_ddrphy_bankmodel6_write;
 wire [9:0] soc_ddrphy_bankmodel6_write_col;
 wire [127:0] soc_ddrphy_bankmodel6_write_data;
 wire [15:0] soc_ddrphy_bankmodel6_write_mask;
-reg soc_ddrphy_bankmodel6_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
-reg soc_ddrphy_bankmodel6_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel6_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel6_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel6_wraddr;
 wire [20:0] soc_ddrphy_bankmodel6_rdaddr;
-reg soc_ddrphy_bankmodel7_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel7_precharge = 1'd0;
+reg  soc_ddrphy_bankmodel7_activate = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
+reg  soc_ddrphy_bankmodel7_precharge = 1'd0;
 wire soc_ddrphy_bankmodel7_write;
 wire [9:0] soc_ddrphy_bankmodel7_write_col;
 wire [127:0] soc_ddrphy_bankmodel7_write_data;
 wire [15:0] soc_ddrphy_bankmodel7_write_mask;
-reg soc_ddrphy_bankmodel7_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
-reg soc_ddrphy_bankmodel7_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
+reg  soc_ddrphy_bankmodel7_read = 1'd0;
+reg  [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
+reg  [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
+reg  soc_ddrphy_bankmodel7_active = 1'd0;
+reg  [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
+reg  [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
+reg  [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
+reg  [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
+reg  [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
 wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
 wire [20:0] soc_ddrphy_bankmodel7_wraddr;
 wire [20:0] soc_ddrphy_bankmodel7_rdaddr;
-reg [3:0] soc_ddrphy_activates0 = 4'd0;
-reg [3:0] soc_ddrphy_precharges0 = 4'd0;
-reg soc_ddrphy_bank_write0 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
-reg [3:0] soc_ddrphy_writes0 = 4'd0;
-reg soc_ddrphy_new_bank_write0 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
-reg [3:0] soc_ddrphy_reads0 = 4'd0;
-reg [3:0] soc_ddrphy_activates1 = 4'd0;
-reg [3:0] soc_ddrphy_precharges1 = 4'd0;
-reg soc_ddrphy_bank_write1 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
-reg [3:0] soc_ddrphy_writes1 = 4'd0;
-reg soc_ddrphy_new_bank_write1 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
-reg [3:0] soc_ddrphy_reads1 = 4'd0;
-reg [3:0] soc_ddrphy_activates2 = 4'd0;
-reg [3:0] soc_ddrphy_precharges2 = 4'd0;
-reg soc_ddrphy_bank_write2 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
-reg [3:0] soc_ddrphy_writes2 = 4'd0;
-reg soc_ddrphy_new_bank_write2 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
-reg [3:0] soc_ddrphy_reads2 = 4'd0;
-reg [3:0] soc_ddrphy_activates3 = 4'd0;
-reg [3:0] soc_ddrphy_precharges3 = 4'd0;
-reg soc_ddrphy_bank_write3 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
-reg [3:0] soc_ddrphy_writes3 = 4'd0;
-reg soc_ddrphy_new_bank_write3 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
-reg [3:0] soc_ddrphy_reads3 = 4'd0;
-reg [3:0] soc_ddrphy_activates4 = 4'd0;
-reg [3:0] soc_ddrphy_precharges4 = 4'd0;
-reg soc_ddrphy_bank_write4 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
-reg [3:0] soc_ddrphy_writes4 = 4'd0;
-reg soc_ddrphy_new_bank_write4 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
-reg [3:0] soc_ddrphy_reads4 = 4'd0;
-reg [3:0] soc_ddrphy_activates5 = 4'd0;
-reg [3:0] soc_ddrphy_precharges5 = 4'd0;
-reg soc_ddrphy_bank_write5 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
-reg [3:0] soc_ddrphy_writes5 = 4'd0;
-reg soc_ddrphy_new_bank_write5 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
-reg [3:0] soc_ddrphy_reads5 = 4'd0;
-reg [3:0] soc_ddrphy_activates6 = 4'd0;
-reg [3:0] soc_ddrphy_precharges6 = 4'd0;
-reg soc_ddrphy_bank_write6 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
-reg [3:0] soc_ddrphy_writes6 = 4'd0;
-reg soc_ddrphy_new_bank_write6 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
-reg [3:0] soc_ddrphy_reads6 = 4'd0;
-reg [3:0] soc_ddrphy_activates7 = 4'd0;
-reg [3:0] soc_ddrphy_precharges7 = 4'd0;
-reg soc_ddrphy_bank_write7 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
-reg [3:0] soc_ddrphy_writes7 = 4'd0;
-reg soc_ddrphy_new_bank_write7 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
-reg [3:0] soc_ddrphy_reads7 = 4'd0;
+reg  [3:0] soc_ddrphy_activates0 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges0 = 4'd0;
+reg  soc_ddrphy_bank_write0 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
+reg  [3:0] soc_ddrphy_writes0 = 4'd0;
+reg  soc_ddrphy_new_bank_write0 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
+reg  [3:0] soc_ddrphy_reads0 = 4'd0;
+reg  [3:0] soc_ddrphy_activates1 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges1 = 4'd0;
+reg  soc_ddrphy_bank_write1 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
+reg  [3:0] soc_ddrphy_writes1 = 4'd0;
+reg  soc_ddrphy_new_bank_write1 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
+reg  [3:0] soc_ddrphy_reads1 = 4'd0;
+reg  [3:0] soc_ddrphy_activates2 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges2 = 4'd0;
+reg  soc_ddrphy_bank_write2 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
+reg  [3:0] soc_ddrphy_writes2 = 4'd0;
+reg  soc_ddrphy_new_bank_write2 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
+reg  [3:0] soc_ddrphy_reads2 = 4'd0;
+reg  [3:0] soc_ddrphy_activates3 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges3 = 4'd0;
+reg  soc_ddrphy_bank_write3 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
+reg  [3:0] soc_ddrphy_writes3 = 4'd0;
+reg  soc_ddrphy_new_bank_write3 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
+reg  [3:0] soc_ddrphy_reads3 = 4'd0;
+reg  [3:0] soc_ddrphy_activates4 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges4 = 4'd0;
+reg  soc_ddrphy_bank_write4 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
+reg  [3:0] soc_ddrphy_writes4 = 4'd0;
+reg  soc_ddrphy_new_bank_write4 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
+reg  [3:0] soc_ddrphy_reads4 = 4'd0;
+reg  [3:0] soc_ddrphy_activates5 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges5 = 4'd0;
+reg  soc_ddrphy_bank_write5 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
+reg  [3:0] soc_ddrphy_writes5 = 4'd0;
+reg  soc_ddrphy_new_bank_write5 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
+reg  [3:0] soc_ddrphy_reads5 = 4'd0;
+reg  [3:0] soc_ddrphy_activates6 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges6 = 4'd0;
+reg  soc_ddrphy_bank_write6 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
+reg  [3:0] soc_ddrphy_writes6 = 4'd0;
+reg  soc_ddrphy_new_bank_write6 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
+reg  [3:0] soc_ddrphy_reads6 = 4'd0;
+reg  [3:0] soc_ddrphy_activates7 = 4'd0;
+reg  [3:0] soc_ddrphy_precharges7 = 4'd0;
+reg  soc_ddrphy_bank_write7 = 1'd0;
+reg  [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
+reg  [3:0] soc_ddrphy_writes7 = 4'd0;
+reg  soc_ddrphy_new_bank_write7 = 1'd0;
+reg  [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
+reg  [3:0] soc_ddrphy_reads7 = 4'd0;
 wire soc_ddrphy_banks_read;
 wire [127:0] soc_ddrphy_banks_read_data;
-reg soc_ddrphy_new_banks_read0 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
-reg soc_ddrphy_new_banks_read1 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
-reg soc_ddrphy_new_banks_read2 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
-reg soc_ddrphy_new_banks_read3 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
-reg soc_ddrphy_new_banks_read4 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
-reg soc_ddrphy_new_banks_read5 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
-reg soc_ddrphy_new_banks_read6 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
-reg soc_ddrphy_new_banks_read7 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
+reg  soc_ddrphy_new_banks_read0 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
+reg  soc_ddrphy_new_banks_read1 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
+reg  soc_ddrphy_new_banks_read2 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
+reg  soc_ddrphy_new_banks_read3 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
+reg  soc_ddrphy_new_banks_read4 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
+reg  soc_ddrphy_new_banks_read5 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
+reg  soc_ddrphy_new_banks_read6 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
+reg  soc_ddrphy_new_banks_read7 = 1'd0;
+reg  [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
 wire [13:0] soc_litedramcore_inti_p0_address;
 wire [2:0] soc_litedramcore_inti_p0_bank;
-reg soc_litedramcore_inti_p0_cas_n = 1'd1;
-reg soc_litedramcore_inti_p0_cs_n = 1'd1;
-reg soc_litedramcore_inti_p0_ras_n = 1'd1;
-reg soc_litedramcore_inti_p0_we_n = 1'd1;
+reg  soc_litedramcore_inti_p0_cas_n = 1'd1;
+reg  soc_litedramcore_inti_p0_cs_n = 1'd1;
+reg  soc_litedramcore_inti_p0_ras_n = 1'd1;
+reg  soc_litedramcore_inti_p0_we_n = 1'd1;
 wire soc_litedramcore_inti_p0_cke;
 wire soc_litedramcore_inti_p0_odt;
 wire soc_litedramcore_inti_p0_reset_n;
-reg soc_litedramcore_inti_p0_act_n = 1'd1;
+reg  soc_litedramcore_inti_p0_act_n = 1'd1;
 wire [31:0] soc_litedramcore_inti_p0_wrdata;
 wire soc_litedramcore_inti_p0_wrdata_en;
 wire [3:0] soc_litedramcore_inti_p0_wrdata_mask;
 wire soc_litedramcore_inti_p0_rddata_en;
-reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
-reg soc_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
+reg  soc_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_inti_p1_address;
 wire [2:0] soc_litedramcore_inti_p1_bank;
-reg soc_litedramcore_inti_p1_cas_n = 1'd1;
-reg soc_litedramcore_inti_p1_cs_n = 1'd1;
-reg soc_litedramcore_inti_p1_ras_n = 1'd1;
-reg soc_litedramcore_inti_p1_we_n = 1'd1;
+reg  soc_litedramcore_inti_p1_cas_n = 1'd1;
+reg  soc_litedramcore_inti_p1_cs_n = 1'd1;
+reg  soc_litedramcore_inti_p1_ras_n = 1'd1;
+reg  soc_litedramcore_inti_p1_we_n = 1'd1;
 wire soc_litedramcore_inti_p1_cke;
 wire soc_litedramcore_inti_p1_odt;
 wire soc_litedramcore_inti_p1_reset_n;
-reg soc_litedramcore_inti_p1_act_n = 1'd1;
+reg  soc_litedramcore_inti_p1_act_n = 1'd1;
 wire [31:0] soc_litedramcore_inti_p1_wrdata;
 wire soc_litedramcore_inti_p1_wrdata_en;
 wire [3:0] soc_litedramcore_inti_p1_wrdata_mask;
 wire soc_litedramcore_inti_p1_rddata_en;
-reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
-reg soc_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
+reg  soc_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_inti_p2_address;
 wire [2:0] soc_litedramcore_inti_p2_bank;
-reg soc_litedramcore_inti_p2_cas_n = 1'd1;
-reg soc_litedramcore_inti_p2_cs_n = 1'd1;
-reg soc_litedramcore_inti_p2_ras_n = 1'd1;
-reg soc_litedramcore_inti_p2_we_n = 1'd1;
+reg  soc_litedramcore_inti_p2_cas_n = 1'd1;
+reg  soc_litedramcore_inti_p2_cs_n = 1'd1;
+reg  soc_litedramcore_inti_p2_ras_n = 1'd1;
+reg  soc_litedramcore_inti_p2_we_n = 1'd1;
 wire soc_litedramcore_inti_p2_cke;
 wire soc_litedramcore_inti_p2_odt;
 wire soc_litedramcore_inti_p2_reset_n;
-reg soc_litedramcore_inti_p2_act_n = 1'd1;
+reg  soc_litedramcore_inti_p2_act_n = 1'd1;
 wire [31:0] soc_litedramcore_inti_p2_wrdata;
 wire soc_litedramcore_inti_p2_wrdata_en;
 wire [3:0] soc_litedramcore_inti_p2_wrdata_mask;
 wire soc_litedramcore_inti_p2_rddata_en;
-reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
-reg soc_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
+reg  soc_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_inti_p3_address;
 wire [2:0] soc_litedramcore_inti_p3_bank;
-reg soc_litedramcore_inti_p3_cas_n = 1'd1;
-reg soc_litedramcore_inti_p3_cs_n = 1'd1;
-reg soc_litedramcore_inti_p3_ras_n = 1'd1;
-reg soc_litedramcore_inti_p3_we_n = 1'd1;
+reg  soc_litedramcore_inti_p3_cas_n = 1'd1;
+reg  soc_litedramcore_inti_p3_cs_n = 1'd1;
+reg  soc_litedramcore_inti_p3_ras_n = 1'd1;
+reg  soc_litedramcore_inti_p3_we_n = 1'd1;
 wire soc_litedramcore_inti_p3_cke;
 wire soc_litedramcore_inti_p3_odt;
 wire soc_litedramcore_inti_p3_reset_n;
-reg soc_litedramcore_inti_p3_act_n = 1'd1;
+reg  soc_litedramcore_inti_p3_act_n = 1'd1;
 wire [31:0] soc_litedramcore_inti_p3_wrdata;
 wire soc_litedramcore_inti_p3_wrdata_en;
 wire [3:0] soc_litedramcore_inti_p3_wrdata_mask;
 wire soc_litedramcore_inti_p3_rddata_en;
-reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
-reg soc_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
+reg  soc_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_slave_p0_address;
 wire [2:0] soc_litedramcore_slave_p0_bank;
 wire soc_litedramcore_slave_p0_cas_n;
@@ -436,8 +457,8 @@ wire [31:0] soc_litedramcore_slave_p0_wrdata;
 wire soc_litedramcore_slave_p0_wrdata_en;
 wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
 wire soc_litedramcore_slave_p0_rddata_en;
-reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
-reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
+reg  soc_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_slave_p1_address;
 wire [2:0] soc_litedramcore_slave_p1_bank;
 wire soc_litedramcore_slave_p1_cas_n;
@@ -452,8 +473,8 @@ wire [31:0] soc_litedramcore_slave_p1_wrdata;
 wire soc_litedramcore_slave_p1_wrdata_en;
 wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
 wire soc_litedramcore_slave_p1_rddata_en;
-reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
-reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
+reg  soc_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_slave_p2_address;
 wire [2:0] soc_litedramcore_slave_p2_bank;
 wire soc_litedramcore_slave_p2_cas_n;
@@ -468,8 +489,8 @@ wire [31:0] soc_litedramcore_slave_p2_wrdata;
 wire soc_litedramcore_slave_p2_wrdata_en;
 wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
 wire soc_litedramcore_slave_p2_rddata_en;
-reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
-reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
+reg  soc_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_slave_p3_address;
 wire [2:0] soc_litedramcore_slave_p3_bank;
 wire soc_litedramcore_slave_p3_cas_n;
@@ -484,138 +505,138 @@ wire [31:0] soc_litedramcore_slave_p3_wrdata;
 wire soc_litedramcore_slave_p3_wrdata_en;
 wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
 wire soc_litedramcore_slave_p3_rddata_en;
-reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
-reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_master_p0_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
-reg soc_litedramcore_master_p0_cas_n = 1'd1;
-reg soc_litedramcore_master_p0_cs_n = 1'd1;
-reg soc_litedramcore_master_p0_ras_n = 1'd1;
-reg soc_litedramcore_master_p0_we_n = 1'd1;
-reg soc_litedramcore_master_p0_cke = 1'd0;
-reg soc_litedramcore_master_p0_odt = 1'd0;
-reg soc_litedramcore_master_p0_reset_n = 1'd0;
-reg soc_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
-reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
+reg  soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [13:0] soc_litedramcore_master_p0_address = 14'd0;
+reg  [2:0] soc_litedramcore_master_p0_bank = 3'd0;
+reg  soc_litedramcore_master_p0_cas_n = 1'd1;
+reg  soc_litedramcore_master_p0_cs_n = 1'd1;
+reg  soc_litedramcore_master_p0_ras_n = 1'd1;
+reg  soc_litedramcore_master_p0_we_n = 1'd1;
+reg  soc_litedramcore_master_p0_cke = 1'd0;
+reg  soc_litedramcore_master_p0_odt = 1'd0;
+reg  soc_litedramcore_master_p0_reset_n = 1'd0;
+reg  soc_litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
+reg  soc_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  soc_litedramcore_master_p0_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_master_p0_rddata;
 wire soc_litedramcore_master_p0_rddata_valid;
-reg [13:0] soc_litedramcore_master_p1_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
-reg soc_litedramcore_master_p1_cas_n = 1'd1;
-reg soc_litedramcore_master_p1_cs_n = 1'd1;
-reg soc_litedramcore_master_p1_ras_n = 1'd1;
-reg soc_litedramcore_master_p1_we_n = 1'd1;
-reg soc_litedramcore_master_p1_cke = 1'd0;
-reg soc_litedramcore_master_p1_odt = 1'd0;
-reg soc_litedramcore_master_p1_reset_n = 1'd0;
-reg soc_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
-reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [13:0] soc_litedramcore_master_p1_address = 14'd0;
+reg  [2:0] soc_litedramcore_master_p1_bank = 3'd0;
+reg  soc_litedramcore_master_p1_cas_n = 1'd1;
+reg  soc_litedramcore_master_p1_cs_n = 1'd1;
+reg  soc_litedramcore_master_p1_ras_n = 1'd1;
+reg  soc_litedramcore_master_p1_we_n = 1'd1;
+reg  soc_litedramcore_master_p1_cke = 1'd0;
+reg  soc_litedramcore_master_p1_odt = 1'd0;
+reg  soc_litedramcore_master_p1_reset_n = 1'd0;
+reg  soc_litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
+reg  soc_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  soc_litedramcore_master_p1_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_master_p1_rddata;
 wire soc_litedramcore_master_p1_rddata_valid;
-reg [13:0] soc_litedramcore_master_p2_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
-reg soc_litedramcore_master_p2_cas_n = 1'd1;
-reg soc_litedramcore_master_p2_cs_n = 1'd1;
-reg soc_litedramcore_master_p2_ras_n = 1'd1;
-reg soc_litedramcore_master_p2_we_n = 1'd1;
-reg soc_litedramcore_master_p2_cke = 1'd0;
-reg soc_litedramcore_master_p2_odt = 1'd0;
-reg soc_litedramcore_master_p2_reset_n = 1'd0;
-reg soc_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
-reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [13:0] soc_litedramcore_master_p2_address = 14'd0;
+reg  [2:0] soc_litedramcore_master_p2_bank = 3'd0;
+reg  soc_litedramcore_master_p2_cas_n = 1'd1;
+reg  soc_litedramcore_master_p2_cs_n = 1'd1;
+reg  soc_litedramcore_master_p2_ras_n = 1'd1;
+reg  soc_litedramcore_master_p2_we_n = 1'd1;
+reg  soc_litedramcore_master_p2_cke = 1'd0;
+reg  soc_litedramcore_master_p2_odt = 1'd0;
+reg  soc_litedramcore_master_p2_reset_n = 1'd0;
+reg  soc_litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
+reg  soc_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  soc_litedramcore_master_p2_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_master_p2_rddata;
 wire soc_litedramcore_master_p2_rddata_valid;
-reg [13:0] soc_litedramcore_master_p3_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
-reg soc_litedramcore_master_p3_cas_n = 1'd1;
-reg soc_litedramcore_master_p3_cs_n = 1'd1;
-reg soc_litedramcore_master_p3_ras_n = 1'd1;
-reg soc_litedramcore_master_p3_we_n = 1'd1;
-reg soc_litedramcore_master_p3_cke = 1'd0;
-reg soc_litedramcore_master_p3_odt = 1'd0;
-reg soc_litedramcore_master_p3_reset_n = 1'd0;
-reg soc_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
-reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [13:0] soc_litedramcore_master_p3_address = 14'd0;
+reg  [2:0] soc_litedramcore_master_p3_bank = 3'd0;
+reg  soc_litedramcore_master_p3_cas_n = 1'd1;
+reg  soc_litedramcore_master_p3_cs_n = 1'd1;
+reg  soc_litedramcore_master_p3_ras_n = 1'd1;
+reg  soc_litedramcore_master_p3_we_n = 1'd1;
+reg  soc_litedramcore_master_p3_cke = 1'd0;
+reg  soc_litedramcore_master_p3_odt = 1'd0;
+reg  soc_litedramcore_master_p3_reset_n = 1'd0;
+reg  soc_litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
+reg  soc_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  soc_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_master_p3_rddata;
 wire soc_litedramcore_master_p3_rddata_valid;
 wire soc_litedramcore_sel;
 wire soc_litedramcore_cke;
 wire soc_litedramcore_odt;
 wire soc_litedramcore_reset_n;
-reg [3:0] soc_litedramcore_storage = 4'd1;
-reg soc_litedramcore_re = 1'd0;
-reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] soc_litedramcore_storage = 4'd1;
+reg  soc_litedramcore_re = 1'd0;
+reg  [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  soc_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire soc_litedramcore_phaseinjector0_command_issue_r;
-reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
+reg  soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg  soc_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector0_rddata_we;
-reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  soc_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire soc_litedramcore_phaseinjector1_command_issue_r;
-reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
+reg  soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg  soc_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector1_rddata_we;
-reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  soc_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire soc_litedramcore_phaseinjector2_command_issue_r;
-reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
+reg  soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg  soc_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector2_rddata_we;
-reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  soc_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire soc_litedramcore_phaseinjector3_command_issue_r;
-reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
+reg  soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg  soc_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector3_rddata_we;
-reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire soc_litedramcore_interface_bank0_valid;
 wire soc_litedramcore_interface_bank0_ready;
 wire soc_litedramcore_interface_bank0_we;
@@ -672,131 +693,131 @@ wire [20:0] soc_litedramcore_interface_bank7_addr;
 wire soc_litedramcore_interface_bank7_lock;
 wire soc_litedramcore_interface_bank7_wdata_ready;
 wire soc_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
-reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
+reg  [127:0] soc_litedramcore_interface_wdata = 128'd0;
+reg  [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
 wire [127:0] soc_litedramcore_interface_rdata;
-reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
-reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
+reg  [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
+reg  soc_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  soc_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  soc_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  soc_litedramcore_dfi_p0_we_n = 1'd1;
 wire soc_litedramcore_dfi_p0_cke;
 wire soc_litedramcore_dfi_p0_odt;
 wire soc_litedramcore_dfi_p0_reset_n;
-reg soc_litedramcore_dfi_p0_act_n = 1'd1;
+reg  soc_litedramcore_dfi_p0_act_n = 1'd1;
 wire [31:0] soc_litedramcore_dfi_p0_wrdata;
-reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
-reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  soc_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_dfi_p0_rddata;
 wire soc_litedramcore_dfi_p0_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
-reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
+reg  [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
+reg  soc_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  soc_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  soc_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  soc_litedramcore_dfi_p1_we_n = 1'd1;
 wire soc_litedramcore_dfi_p1_cke;
 wire soc_litedramcore_dfi_p1_odt;
 wire soc_litedramcore_dfi_p1_reset_n;
-reg soc_litedramcore_dfi_p1_act_n = 1'd1;
+reg  soc_litedramcore_dfi_p1_act_n = 1'd1;
 wire [31:0] soc_litedramcore_dfi_p1_wrdata;
-reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
-reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  soc_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_dfi_p1_rddata;
 wire soc_litedramcore_dfi_p1_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
-reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
+reg  [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
+reg  soc_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  soc_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  soc_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  soc_litedramcore_dfi_p2_we_n = 1'd1;
 wire soc_litedramcore_dfi_p2_cke;
 wire soc_litedramcore_dfi_p2_odt;
 wire soc_litedramcore_dfi_p2_reset_n;
-reg soc_litedramcore_dfi_p2_act_n = 1'd1;
+reg  soc_litedramcore_dfi_p2_act_n = 1'd1;
 wire [31:0] soc_litedramcore_dfi_p2_wrdata;
-reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
-reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  soc_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_dfi_p2_rddata;
 wire soc_litedramcore_dfi_p2_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
-reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
+reg  [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
+reg  soc_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  soc_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  soc_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  soc_litedramcore_dfi_p3_we_n = 1'd1;
 wire soc_litedramcore_dfi_p3_cke;
 wire soc_litedramcore_dfi_p3_odt;
 wire soc_litedramcore_dfi_p3_reset_n;
-reg soc_litedramcore_dfi_p3_act_n = 1'd1;
+reg  soc_litedramcore_dfi_p3_act_n = 1'd1;
 wire [31:0] soc_litedramcore_dfi_p3_wrdata;
-reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
-reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  soc_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_dfi_p3_rddata;
 wire soc_litedramcore_dfi_p3_rddata_valid;
-reg soc_litedramcore_cmd_valid = 1'd0;
-reg soc_litedramcore_cmd_ready = 1'd0;
-reg soc_litedramcore_cmd_last = 1'd0;
-reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
-reg soc_litedramcore_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_cmd_payload_we = 1'd0;
-reg soc_litedramcore_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_cmd_valid = 1'd0;
+reg  soc_litedramcore_cmd_ready = 1'd0;
+reg  soc_litedramcore_cmd_last = 1'd0;
+reg  [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
+reg  [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
+reg  soc_litedramcore_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_cmd_payload_is_write = 1'd0;
 wire soc_litedramcore_wants_refresh;
 wire soc_litedramcore_wants_zqcs;
 wire soc_litedramcore_timer_wait;
 wire soc_litedramcore_timer_done0;
 wire [9:0] soc_litedramcore_timer_count0;
 wire soc_litedramcore_timer_done1;
-reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] soc_litedramcore_timer_count1 = 10'd781;
 wire soc_litedramcore_postponer_req_i;
-reg soc_litedramcore_postponer_req_o = 1'd0;
-reg soc_litedramcore_postponer_count = 1'd0;
-reg soc_litedramcore_sequencer_start0 = 1'd0;
+reg  soc_litedramcore_postponer_req_o = 1'd0;
+reg  soc_litedramcore_postponer_count = 1'd0;
+reg  soc_litedramcore_sequencer_start0 = 1'd0;
 wire soc_litedramcore_sequencer_done0;
 wire soc_litedramcore_sequencer_start1;
-reg soc_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
-reg soc_litedramcore_sequencer_count = 1'd0;
+reg  soc_litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] soc_litedramcore_sequencer_counter = 6'd0;
+reg  soc_litedramcore_sequencer_count = 1'd0;
 wire soc_litedramcore_zqcs_timer_wait;
 wire soc_litedramcore_zqcs_timer_done0;
 wire [26:0] soc_litedramcore_zqcs_timer_count0;
 wire soc_litedramcore_zqcs_timer_done1;
-reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg soc_litedramcore_zqcs_executer_start = 1'd0;
-reg soc_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  soc_litedramcore_zqcs_executer_start = 1'd0;
+reg  soc_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
 wire soc_litedramcore_bankmachine0_req_valid;
 wire soc_litedramcore_bankmachine0_req_ready;
 wire soc_litedramcore_bankmachine0_req_we;
 wire [20:0] soc_litedramcore_bankmachine0_req_addr;
 wire soc_litedramcore_bankmachine0_req_lock;
-reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine0_refresh_req;
-reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
-reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -811,11 +832,11 @@ wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -836,51 +857,51 @@ wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
-reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
+reg  soc_litedramcore_bankmachine0_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine0_row_hit;
-reg soc_litedramcore_bankmachine0_row_open = 1'd0;
-reg soc_litedramcore_bankmachine0_row_close = 1'd0;
-reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine0_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine0_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine0_twtpcon_valid;
-reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine0_trccon_valid;
-reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine0_trascon_valid;
-reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine1_req_valid;
 wire soc_litedramcore_bankmachine1_req_ready;
 wire soc_litedramcore_bankmachine1_req_we;
 wire [20:0] soc_litedramcore_bankmachine1_req_addr;
 wire soc_litedramcore_bankmachine1_req_lock;
-reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine1_refresh_req;
-reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
-reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -895,11 +916,11 @@ wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -920,51 +941,51 @@ wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
-reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
+reg  soc_litedramcore_bankmachine1_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine1_row_hit;
-reg soc_litedramcore_bankmachine1_row_open = 1'd0;
-reg soc_litedramcore_bankmachine1_row_close = 1'd0;
-reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine1_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine1_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine1_twtpcon_valid;
-reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine1_trccon_valid;
-reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine1_trascon_valid;
-reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine2_req_valid;
 wire soc_litedramcore_bankmachine2_req_ready;
 wire soc_litedramcore_bankmachine2_req_we;
 wire [20:0] soc_litedramcore_bankmachine2_req_addr;
 wire soc_litedramcore_bankmachine2_req_lock;
-reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine2_refresh_req;
-reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
-reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -979,11 +1000,11 @@ wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1004,51 +1025,51 @@ wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
-reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
+reg  soc_litedramcore_bankmachine2_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine2_row_hit;
-reg soc_litedramcore_bankmachine2_row_open = 1'd0;
-reg soc_litedramcore_bankmachine2_row_close = 1'd0;
-reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine2_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine2_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine2_twtpcon_valid;
-reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine2_trccon_valid;
-reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine2_trascon_valid;
-reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine3_req_valid;
 wire soc_litedramcore_bankmachine3_req_ready;
 wire soc_litedramcore_bankmachine3_req_we;
 wire [20:0] soc_litedramcore_bankmachine3_req_addr;
 wire soc_litedramcore_bankmachine3_req_lock;
-reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine3_refresh_req;
-reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
-reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1063,11 +1084,11 @@ wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1088,51 +1109,51 @@ wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
-reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
+reg  soc_litedramcore_bankmachine3_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine3_row_hit;
-reg soc_litedramcore_bankmachine3_row_open = 1'd0;
-reg soc_litedramcore_bankmachine3_row_close = 1'd0;
-reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine3_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine3_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine3_twtpcon_valid;
-reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine3_trccon_valid;
-reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine3_trascon_valid;
-reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine4_req_valid;
 wire soc_litedramcore_bankmachine4_req_ready;
 wire soc_litedramcore_bankmachine4_req_we;
 wire [20:0] soc_litedramcore_bankmachine4_req_addr;
 wire soc_litedramcore_bankmachine4_req_lock;
-reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine4_refresh_req;
-reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
-reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1147,11 +1168,11 @@ wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1172,51 +1193,51 @@ wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
-reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
+reg  soc_litedramcore_bankmachine4_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine4_row_hit;
-reg soc_litedramcore_bankmachine4_row_open = 1'd0;
-reg soc_litedramcore_bankmachine4_row_close = 1'd0;
-reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine4_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine4_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine4_twtpcon_valid;
-reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine4_trccon_valid;
-reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine4_trascon_valid;
-reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine5_req_valid;
 wire soc_litedramcore_bankmachine5_req_ready;
 wire soc_litedramcore_bankmachine5_req_we;
 wire [20:0] soc_litedramcore_bankmachine5_req_addr;
 wire soc_litedramcore_bankmachine5_req_lock;
-reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine5_refresh_req;
-reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
-reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1231,11 +1252,11 @@ wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1256,51 +1277,51 @@ wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
-reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
+reg  soc_litedramcore_bankmachine5_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine5_row_hit;
-reg soc_litedramcore_bankmachine5_row_open = 1'd0;
-reg soc_litedramcore_bankmachine5_row_close = 1'd0;
-reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine5_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine5_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine5_twtpcon_valid;
-reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine5_trccon_valid;
-reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine5_trascon_valid;
-reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine6_req_valid;
 wire soc_litedramcore_bankmachine6_req_ready;
 wire soc_litedramcore_bankmachine6_req_we;
 wire [20:0] soc_litedramcore_bankmachine6_req_addr;
 wire soc_litedramcore_bankmachine6_req_lock;
-reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine6_refresh_req;
-reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
-reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1315,11 +1336,11 @@ wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1340,51 +1361,51 @@ wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
-reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
+reg  soc_litedramcore_bankmachine6_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine6_row_hit;
-reg soc_litedramcore_bankmachine6_row_open = 1'd0;
-reg soc_litedramcore_bankmachine6_row_close = 1'd0;
-reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine6_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine6_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine6_twtpcon_valid;
-reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine6_trccon_valid;
-reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine6_trascon_valid;
-reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire soc_litedramcore_bankmachine7_req_valid;
 wire soc_litedramcore_bankmachine7_req_ready;
 wire soc_litedramcore_bankmachine7_req_we;
 wire [20:0] soc_litedramcore_bankmachine7_req_addr;
 wire soc_litedramcore_bankmachine7_req_lock;
-reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire soc_litedramcore_bankmachine7_refresh_req;
-reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+reg  soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
 wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
-reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1399,11 +1420,11 @@ wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1424,105 +1445,105 @@ wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
-reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
+reg  soc_litedramcore_bankmachine7_row_opened = 1'd0;
 wire soc_litedramcore_bankmachine7_row_hit;
-reg soc_litedramcore_bankmachine7_row_open = 1'd0;
-reg soc_litedramcore_bankmachine7_row_close = 1'd0;
-reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  soc_litedramcore_bankmachine7_row_open = 1'd0;
+reg  soc_litedramcore_bankmachine7_row_close = 1'd0;
+reg  soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire soc_litedramcore_bankmachine7_twtpcon_valid;
-reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+reg  soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire soc_litedramcore_bankmachine7_trccon_valid;
-reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
+reg  soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire soc_litedramcore_bankmachine7_trascon_valid;
-reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
+reg  soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire soc_litedramcore_ras_allowed;
 wire soc_litedramcore_cas_allowed;
-reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
-reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
-reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  soc_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  soc_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  soc_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  soc_litedramcore_choose_cmd_want_activates = 1'd0;
 wire soc_litedramcore_choose_cmd_cmd_valid;
-reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
-reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
 wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] soc_litedramcore_choose_cmd_request;
-reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
 wire soc_litedramcore_choose_cmd_ce;
-reg soc_litedramcore_choose_req_want_reads = 1'd0;
-reg soc_litedramcore_choose_req_want_writes = 1'd0;
-reg soc_litedramcore_choose_req_want_cmds = 1'd0;
-reg soc_litedramcore_choose_req_want_activates = 1'd0;
+reg  soc_litedramcore_choose_req_want_reads = 1'd0;
+reg  soc_litedramcore_choose_req_want_writes = 1'd0;
+reg  soc_litedramcore_choose_req_want_cmds = 1'd0;
+reg  soc_litedramcore_choose_req_want_activates = 1'd0;
 wire soc_litedramcore_choose_req_cmd_valid;
-reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  soc_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [13:0] soc_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
-reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
 wire soc_litedramcore_choose_req_cmd_payload_is_read;
 wire soc_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] soc_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] soc_litedramcore_choose_req_request;
-reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] soc_litedramcore_choose_req_grant = 3'd0;
 wire soc_litedramcore_choose_req_ce;
-reg [13:0] soc_litedramcore_nop_a = 14'd0;
-reg [2:0] soc_litedramcore_nop_ba = 3'd0;
-reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
-reg soc_litedramcore_steerer0 = 1'd1;
-reg soc_litedramcore_steerer1 = 1'd1;
-reg soc_litedramcore_steerer2 = 1'd1;
-reg soc_litedramcore_steerer3 = 1'd1;
-reg soc_litedramcore_steerer4 = 1'd1;
-reg soc_litedramcore_steerer5 = 1'd1;
-reg soc_litedramcore_steerer6 = 1'd1;
-reg soc_litedramcore_steerer7 = 1'd1;
+reg  [13:0] soc_litedramcore_nop_a = 14'd0;
+reg  [2:0] soc_litedramcore_nop_ba = 3'd0;
+reg  [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
+reg  soc_litedramcore_steerer0 = 1'd1;
+reg  soc_litedramcore_steerer1 = 1'd1;
+reg  soc_litedramcore_steerer2 = 1'd1;
+reg  soc_litedramcore_steerer3 = 1'd1;
+reg  soc_litedramcore_steerer4 = 1'd1;
+reg  soc_litedramcore_steerer5 = 1'd1;
+reg  soc_litedramcore_steerer6 = 1'd1;
+reg  soc_litedramcore_steerer7 = 1'd1;
 wire soc_litedramcore_trrdcon_valid;
-reg soc_litedramcore_trrdcon_ready = 1'd0;
-reg soc_litedramcore_trrdcon_count = 1'd0;
+reg  soc_litedramcore_trrdcon_ready = 1'd0;
+reg  soc_litedramcore_trrdcon_count = 1'd0;
 wire soc_litedramcore_tfawcon_valid;
-reg soc_litedramcore_tfawcon_ready = 1'd1;
+reg  soc_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] soc_litedramcore_tfawcon_count;
-reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] soc_litedramcore_tfawcon_window = 5'd0;
 wire soc_litedramcore_tccdcon_valid;
-reg soc_litedramcore_tccdcon_ready = 1'd0;
-reg soc_litedramcore_tccdcon_count = 1'd0;
+reg  soc_litedramcore_tccdcon_ready = 1'd0;
+reg  soc_litedramcore_tccdcon_count = 1'd0;
 wire soc_litedramcore_twtrcon_valid;
-reg soc_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
+reg  soc_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] soc_litedramcore_twtrcon_count = 3'd0;
 wire soc_litedramcore_read_available;
 wire soc_litedramcore_write_available;
-reg soc_litedramcore_en0 = 1'd0;
+reg  soc_litedramcore_en0 = 1'd0;
 wire soc_litedramcore_max_time0;
-reg [4:0] soc_litedramcore_time0 = 5'd0;
-reg soc_litedramcore_en1 = 1'd0;
+reg  [4:0] soc_litedramcore_time0 = 5'd0;
+reg  soc_litedramcore_en1 = 1'd0;
 wire soc_litedramcore_max_time1;
-reg [3:0] soc_litedramcore_time1 = 4'd0;
+reg  [3:0] soc_litedramcore_time1 = 4'd0;
 wire soc_litedramcore_go_to_refresh;
-reg soc_init_done_storage = 1'd0;
-reg soc_init_done_re = 1'd0;
-reg soc_init_error_storage = 1'd0;
-reg soc_init_error_re = 1'd0;
+reg  soc_init_done_storage = 1'd0;
+reg  soc_init_done_re = 1'd0;
+reg  soc_init_error_storage = 1'd0;
+reg  soc_init_error_re = 1'd0;
 wire [29:0] soc_wb_bus_adr;
 wire [31:0] soc_wb_bus_dat_w;
 wire [31:0] soc_wb_bus_dat_r;
@@ -1534,6 +1555,7 @@ wire soc_wb_bus_we;
 wire [2:0] soc_wb_bus_cti;
 wire [1:0] soc_wb_bus_bte;
 wire soc_wb_bus_err;
+wire soc_user_enable;
 wire soc_user_port_cmd_valid;
 wire soc_user_port_cmd_ready;
 wire soc_user_port_cmd_payload_we;
@@ -1545,26 +1567,26 @@ wire [15:0] soc_user_port_wdata_payload_we;
 wire soc_user_port_rdata_valid;
 wire soc_user_port_rdata_ready;
 wire [127:0] soc_user_port_rdata_payload_data;
-reg [1:0] refresher_state = 2'd0;
-reg [1:0] refresher_next_state = 2'd0;
-reg [3:0] bankmachine0_state = 4'd0;
-reg [3:0] bankmachine0_next_state = 4'd0;
-reg [3:0] bankmachine1_state = 4'd0;
-reg [3:0] bankmachine1_next_state = 4'd0;
-reg [3:0] bankmachine2_state = 4'd0;
-reg [3:0] bankmachine2_next_state = 4'd0;
-reg [3:0] bankmachine3_state = 4'd0;
-reg [3:0] bankmachine3_next_state = 4'd0;
-reg [3:0] bankmachine4_state = 4'd0;
-reg [3:0] bankmachine4_next_state = 4'd0;
-reg [3:0] bankmachine5_state = 4'd0;
-reg [3:0] bankmachine5_next_state = 4'd0;
-reg [3:0] bankmachine6_state = 4'd0;
-reg [3:0] bankmachine6_next_state = 4'd0;
-reg [3:0] bankmachine7_state = 4'd0;
-reg [3:0] bankmachine7_next_state = 4'd0;
-reg [3:0] multiplexer_state = 4'd0;
-reg [3:0] multiplexer_next_state = 4'd0;
+reg  [1:0] refresher_state = 2'd0;
+reg  [1:0] refresher_next_state = 2'd0;
+reg  [3:0] bankmachine0_state = 4'd0;
+reg  [3:0] bankmachine0_next_state = 4'd0;
+reg  [3:0] bankmachine1_state = 4'd0;
+reg  [3:0] bankmachine1_next_state = 4'd0;
+reg  [3:0] bankmachine2_state = 4'd0;
+reg  [3:0] bankmachine2_next_state = 4'd0;
+reg  [3:0] bankmachine3_state = 4'd0;
+reg  [3:0] bankmachine3_next_state = 4'd0;
+reg  [3:0] bankmachine4_state = 4'd0;
+reg  [3:0] bankmachine4_next_state = 4'd0;
+reg  [3:0] bankmachine5_state = 4'd0;
+reg  [3:0] bankmachine5_next_state = 4'd0;
+reg  [3:0] bankmachine6_state = 4'd0;
+reg  [3:0] bankmachine6_next_state = 4'd0;
+reg  [3:0] bankmachine7_state = 4'd0;
+reg  [3:0] bankmachine7_next_state = 4'd0;
+reg  [3:0] multiplexer_state = 4'd0;
+reg  [3:0] multiplexer_next_state = 4'd0;
 wire roundrobin0_request;
 wire roundrobin0_grant;
 wire roundrobin0_ce;
@@ -1589,266 +1611,154 @@ wire roundrobin6_ce;
 wire roundrobin7_request;
 wire roundrobin7_grant;
 wire roundrobin7_ce;
-reg locked0 = 1'd0;
-reg locked1 = 1'd0;
-reg locked2 = 1'd0;
-reg locked3 = 1'd0;
-reg locked4 = 1'd0;
-reg locked5 = 1'd0;
-reg locked6 = 1'd0;
-reg locked7 = 1'd0;
-reg new_master_wdata_ready0 = 1'd0;
-reg new_master_wdata_ready1 = 1'd0;
-reg new_master_rdata_valid0 = 1'd0;
-reg new_master_rdata_valid1 = 1'd0;
-reg new_master_rdata_valid2 = 1'd0;
-reg new_master_rdata_valid3 = 1'd0;
-reg new_master_rdata_valid4 = 1'd0;
-reg new_master_rdata_valid5 = 1'd0;
-reg new_master_rdata_valid6 = 1'd0;
-reg new_master_rdata_valid7 = 1'd0;
-reg new_master_rdata_valid8 = 1'd0;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [7:0] litedramcore_dat_w = 8'd0;
-wire [7:0] litedramcore_dat_r;
+reg  locked0 = 1'd0;
+reg  locked1 = 1'd0;
+reg  locked2 = 1'd0;
+reg  locked3 = 1'd0;
+reg  locked4 = 1'd0;
+reg  locked5 = 1'd0;
+reg  locked6 = 1'd0;
+reg  locked7 = 1'd0;
+reg  new_master_wdata_ready0 = 1'd0;
+reg  new_master_wdata_ready1 = 1'd0;
+reg  new_master_rdata_valid0 = 1'd0;
+reg  new_master_rdata_valid1 = 1'd0;
+reg  new_master_rdata_valid2 = 1'd0;
+reg  new_master_rdata_valid3 = 1'd0;
+reg  new_master_rdata_valid4 = 1'd0;
+reg  new_master_rdata_valid5 = 1'd0;
+reg  new_master_rdata_valid6 = 1'd0;
+reg  new_master_rdata_valid7 = 1'd0;
+reg  new_master_rdata_valid8 = 1'd0;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
 wire [29:0] litedramcore_wishbone_adr;
 wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] litedramcore_wishbone_sel;
 wire litedramcore_wishbone_cyc;
 wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
+reg  litedramcore_wishbone_ack = 1'd0;
 wire litedramcore_wishbone_we;
 wire [2:0] litedramcore_wishbone_cti;
 wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
+reg  litedramcore_wishbone_err = 1'd0;
 wire [13:0] interface0_bank_bus_adr;
 wire interface0_bank_bus_we;
-wire [7:0] interface0_bank_bus_dat_w;
-reg [7:0] interface0_bank_bus_dat_r = 8'd0;
-reg csrbank0_init_done0_re = 1'd0;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
 wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
+reg  csrbank0_init_done0_we = 1'd0;
 wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
+reg  csrbank0_init_error0_re = 1'd0;
 wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
+reg  csrbank0_init_error0_we = 1'd0;
 wire csrbank0_init_error0_w;
 wire csrbank0_sel;
 wire [13:0] interface1_bank_bus_adr;
 wire interface1_bank_bus_we;
-wire [7:0] interface1_bank_bus_dat_w;
-reg [7:0] interface1_bank_bus_dat_r = 8'd0;
-reg csrbank1_dfii_control0_re = 1'd0;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_dfii_control0_re = 1'd0;
 wire [3:0] csrbank1_dfii_control0_r;
-reg csrbank1_dfii_control0_we = 1'd0;
+reg  csrbank1_dfii_control0_we = 1'd0;
 wire [3:0] csrbank1_dfii_control0_w;
-reg csrbank1_dfii_pi0_command0_re = 1'd0;
+reg  csrbank1_dfii_pi0_command0_re = 1'd0;
 wire [5:0] csrbank1_dfii_pi0_command0_r;
-reg csrbank1_dfii_pi0_command0_we = 1'd0;
+reg  csrbank1_dfii_pi0_command0_we = 1'd0;
 wire [5:0] csrbank1_dfii_pi0_command0_w;
-reg csrbank1_dfii_pi0_address1_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi0_address1_r;
-reg csrbank1_dfii_pi0_address1_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi0_address1_w;
-reg csrbank1_dfii_pi0_address0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_address0_r;
-reg csrbank1_dfii_pi0_address0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_address0_w;
-reg csrbank1_dfii_pi0_baddress0_re = 1'd0;
+reg  csrbank1_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi0_address0_r;
+reg  csrbank1_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi0_address0_w;
+reg  csrbank1_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] csrbank1_dfii_pi0_baddress0_r;
-reg csrbank1_dfii_pi0_baddress0_we = 1'd0;
+reg  csrbank1_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] csrbank1_dfii_pi0_baddress0_w;
-reg csrbank1_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
-reg csrbank1_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
-reg csrbank1_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
-reg csrbank1_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
-reg csrbank1_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
-reg csrbank1_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
-reg csrbank1_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
-reg csrbank1_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
-reg csrbank1_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata3_r;
-reg csrbank1_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata3_w;
-reg csrbank1_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata2_r;
-reg csrbank1_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata2_w;
-reg csrbank1_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata1_r;
-reg csrbank1_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata1_w;
-reg csrbank1_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata0_r;
-reg csrbank1_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi0_rddata0_w;
-reg csrbank1_dfii_pi1_command0_re = 1'd0;
+reg  csrbank1_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
+reg  csrbank1_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
+reg  csrbank1_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_rddata_r;
+reg  csrbank1_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_rddata_w;
+reg  csrbank1_dfii_pi1_command0_re = 1'd0;
 wire [5:0] csrbank1_dfii_pi1_command0_r;
-reg csrbank1_dfii_pi1_command0_we = 1'd0;
+reg  csrbank1_dfii_pi1_command0_we = 1'd0;
 wire [5:0] csrbank1_dfii_pi1_command0_w;
-reg csrbank1_dfii_pi1_address1_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi1_address1_r;
-reg csrbank1_dfii_pi1_address1_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi1_address1_w;
-reg csrbank1_dfii_pi1_address0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_address0_r;
-reg csrbank1_dfii_pi1_address0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_address0_w;
-reg csrbank1_dfii_pi1_baddress0_re = 1'd0;
+reg  csrbank1_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi1_address0_r;
+reg  csrbank1_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi1_address0_w;
+reg  csrbank1_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] csrbank1_dfii_pi1_baddress0_r;
-reg csrbank1_dfii_pi1_baddress0_we = 1'd0;
+reg  csrbank1_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] csrbank1_dfii_pi1_baddress0_w;
-reg csrbank1_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
-reg csrbank1_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
-reg csrbank1_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
-reg csrbank1_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
-reg csrbank1_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
-reg csrbank1_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
-reg csrbank1_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
-reg csrbank1_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
-reg csrbank1_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata3_r;
-reg csrbank1_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata3_w;
-reg csrbank1_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata2_r;
-reg csrbank1_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata2_w;
-reg csrbank1_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata1_r;
-reg csrbank1_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata1_w;
-reg csrbank1_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata0_r;
-reg csrbank1_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi1_rddata0_w;
-reg csrbank1_dfii_pi2_command0_re = 1'd0;
+reg  csrbank1_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
+reg  csrbank1_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
+reg  csrbank1_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_rddata_r;
+reg  csrbank1_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_rddata_w;
+reg  csrbank1_dfii_pi2_command0_re = 1'd0;
 wire [5:0] csrbank1_dfii_pi2_command0_r;
-reg csrbank1_dfii_pi2_command0_we = 1'd0;
+reg  csrbank1_dfii_pi2_command0_we = 1'd0;
 wire [5:0] csrbank1_dfii_pi2_command0_w;
-reg csrbank1_dfii_pi2_address1_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi2_address1_r;
-reg csrbank1_dfii_pi2_address1_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi2_address1_w;
-reg csrbank1_dfii_pi2_address0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_address0_r;
-reg csrbank1_dfii_pi2_address0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_address0_w;
-reg csrbank1_dfii_pi2_baddress0_re = 1'd0;
+reg  csrbank1_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi2_address0_r;
+reg  csrbank1_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi2_address0_w;
+reg  csrbank1_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] csrbank1_dfii_pi2_baddress0_r;
-reg csrbank1_dfii_pi2_baddress0_we = 1'd0;
+reg  csrbank1_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] csrbank1_dfii_pi2_baddress0_w;
-reg csrbank1_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
-reg csrbank1_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
-reg csrbank1_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
-reg csrbank1_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
-reg csrbank1_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
-reg csrbank1_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
-reg csrbank1_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
-reg csrbank1_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
-reg csrbank1_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata3_r;
-reg csrbank1_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata3_w;
-reg csrbank1_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata2_r;
-reg csrbank1_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata2_w;
-reg csrbank1_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata1_r;
-reg csrbank1_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata1_w;
-reg csrbank1_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata0_r;
-reg csrbank1_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi2_rddata0_w;
-reg csrbank1_dfii_pi3_command0_re = 1'd0;
+reg  csrbank1_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
+reg  csrbank1_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
+reg  csrbank1_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_rddata_r;
+reg  csrbank1_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_rddata_w;
+reg  csrbank1_dfii_pi3_command0_re = 1'd0;
 wire [5:0] csrbank1_dfii_pi3_command0_r;
-reg csrbank1_dfii_pi3_command0_we = 1'd0;
+reg  csrbank1_dfii_pi3_command0_we = 1'd0;
 wire [5:0] csrbank1_dfii_pi3_command0_w;
-reg csrbank1_dfii_pi3_address1_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi3_address1_r;
-reg csrbank1_dfii_pi3_address1_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi3_address1_w;
-reg csrbank1_dfii_pi3_address0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_address0_r;
-reg csrbank1_dfii_pi3_address0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_address0_w;
-reg csrbank1_dfii_pi3_baddress0_re = 1'd0;
+reg  csrbank1_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi3_address0_r;
+reg  csrbank1_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi3_address0_w;
+reg  csrbank1_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] csrbank1_dfii_pi3_baddress0_r;
-reg csrbank1_dfii_pi3_baddress0_we = 1'd0;
+reg  csrbank1_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] csrbank1_dfii_pi3_baddress0_w;
-reg csrbank1_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
-reg csrbank1_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
-reg csrbank1_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
-reg csrbank1_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
-reg csrbank1_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
-reg csrbank1_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
-reg csrbank1_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
-reg csrbank1_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
-reg csrbank1_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata3_r;
-reg csrbank1_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata3_w;
-reg csrbank1_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata2_r;
-reg csrbank1_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata2_w;
-reg csrbank1_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata1_r;
-reg csrbank1_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata1_w;
-reg csrbank1_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata0_r;
-reg csrbank1_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] csrbank1_dfii_pi3_rddata0_w;
+reg  csrbank1_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
+reg  csrbank1_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
+reg  csrbank1_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_rddata_r;
+reg  csrbank1_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_rddata_w;
 wire csrbank1_sel;
 wire [13:0] csr_interconnect_adr;
 wire csr_interconnect_we;
-wire [7:0] csr_interconnect_dat_w;
-wire [7:0] csr_interconnect_dat_r;
-reg [1:0] state = 2'd0;
-reg [1:0] next_state = 2'd0;
-reg [7:0] litedramcore_dat_w_next_value0 = 8'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+reg  [1:0] state = 2'd0;
+reg  [1:0] next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
 wire [24:0] slice_proxy0;
 wire [24:0] slice_proxy1;
 wire [24:0] slice_proxy2;
@@ -1865,76 +1775,80 @@ wire [24:0] slice_proxy12;
 wire [24:0] slice_proxy13;
 wire [24:0] slice_proxy14;
 wire [24:0] slice_proxy15;
-reg rhs_array_muxed0 = 1'd0;
-reg [13:0] rhs_array_muxed1 = 14'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [13:0] rhs_array_muxed7 = 14'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [20:0] rhs_array_muxed12 = 21'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [20:0] rhs_array_muxed15 = 21'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [20:0] rhs_array_muxed18 = 21'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [20:0] rhs_array_muxed21 = 21'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [20:0] rhs_array_muxed24 = 21'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [20:0] rhs_array_muxed27 = 21'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [20:0] rhs_array_muxed30 = 21'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [20:0] rhs_array_muxed33 = 21'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [13:0] array_muxed1 = 14'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [13:0] array_muxed8 = 14'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [13:0] array_muxed15 = 14'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [13:0] array_muxed22 = 14'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [13:0] rhs_array_muxed1 = 14'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [13:0] rhs_array_muxed7 = 14'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [20:0] rhs_array_muxed12 = 21'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [20:0] rhs_array_muxed15 = 21'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [20:0] rhs_array_muxed18 = 21'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [20:0] rhs_array_muxed21 = 21'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [20:0] rhs_array_muxed24 = 21'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [20:0] rhs_array_muxed27 = 21'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [20:0] rhs_array_muxed30 = 21'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [20:0] rhs_array_muxed33 = 21'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [13:0] array_muxed1 = 14'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [13:0] array_muxed8 = 14'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [13:0] array_muxed15 = 14'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [13:0] array_muxed22 = 14'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
 
 assign init_done = soc_init_done_storage;
 assign init_error = soc_init_error_storage;
@@ -1951,123 +1865,124 @@ assign soc_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = soc_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready;
+assign soc_user_enable = 1'd1;
+assign soc_user_port_cmd_valid = (user_port_native_0_cmd_valid & soc_user_enable);
+assign user_port_native_0_cmd_ready = (soc_user_port_cmd_ready & soc_user_enable);
 assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready;
+assign soc_user_port_wdata_valid = (user_port_native_0_wdata_valid & soc_user_enable);
+assign user_port_native_0_wdata_ready = (soc_user_port_wdata_ready & soc_user_enable);
 assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid;
-assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable);
+assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable);
 assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
 assign sys_clk = clk;
 assign por_clk = clk;
 assign sys_rst = soc_int_rst;
 always @(*) begin
-	soc_ddrphy_activates0 = 4'd0;
-	soc_ddrphy_activates0[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates0[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates0[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates0[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates0 <= 4'd0;
+	soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_activate = 1'd0;
+	soc_ddrphy_bankmodel0_activate_row <= 14'd0;
 	case (soc_ddrphy_activates0)
 		1'd1: begin
-			soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p0_bank == 1'd0);
+			soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p1_bank == 1'd0);
+			soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p2_bank == 1'd0);
+			soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p3_bank == 1'd0);
+			soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_activate_row = 14'd0;
+	soc_ddrphy_bankmodel0_activate <= 1'd0;
 	case (soc_ddrphy_activates0)
 		1'd1: begin
-			soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges0 = 4'd0;
-	soc_ddrphy_precharges0[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges0[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges0[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges0[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges0 <= 4'd0;
+	soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_precharge = 1'd0;
+	soc_ddrphy_bankmodel0_precharge <= 1'd0;
 	case (soc_ddrphy_precharges0)
 		1'd1: begin
-			soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes0 = 4'd0;
-	soc_ddrphy_writes0[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes0[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes0[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes0[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes0 <= 4'd0;
+	soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col0 = 10'd0;
+	soc_ddrphy_bank_write0 <= 1'd0;
 	case (soc_ddrphy_writes0)
 		1'd1: begin
-			soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write0 = 1'd0;
+	soc_ddrphy_bank_write_col0 <= 10'd0;
 	case (soc_ddrphy_writes0)
 		1'd1: begin
-			soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p0_bank == 1'd0);
+			soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p1_bank == 1'd0);
+			soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p2_bank == 1'd0);
+			soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p3_bank == 1'd0);
+			soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -2076,149 +1991,149 @@ assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0;
 assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0;
 always @(*) begin
-	soc_ddrphy_reads0 = 4'd0;
-	soc_ddrphy_reads0[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads0[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads0[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads0[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads0 <= 4'd0;
+	soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_read = 1'd0;
+	soc_ddrphy_bankmodel0_read <= 1'd0;
 	case (soc_ddrphy_reads0)
 		1'd1: begin
-			soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p0_bank == 1'd0);
+			soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p1_bank == 1'd0);
+			soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p2_bank == 1'd0);
+			soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p3_bank == 1'd0);
+			soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_read_col = 10'd0;
+	soc_ddrphy_bankmodel0_read_col <= 10'd0;
 	case (soc_ddrphy_reads0)
 		1'd1: begin
-			soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates1 = 4'd0;
-	soc_ddrphy_activates1[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates1[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates1[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates1 <= 4'd0;
+	soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate_row = 14'd0;
+	soc_ddrphy_bankmodel1_activate <= 1'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate = 1'd0;
+	soc_ddrphy_bankmodel1_activate_row <= 14'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges1 = 4'd0;
-	soc_ddrphy_precharges1[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges1[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges1[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges1[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges1 <= 4'd0;
+	soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_precharge = 1'd0;
+	soc_ddrphy_bankmodel1_precharge <= 1'd0;
 	case (soc_ddrphy_precharges1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes1 = 4'd0;
-	soc_ddrphy_writes1[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes1[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes1[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes1[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes1 <= 4'd0;
+	soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write1 = 1'd0;
+	soc_ddrphy_bank_write1 <= 1'd0;
 	case (soc_ddrphy_writes1)
 		1'd1: begin
-			soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p0_bank == 1'd1);
+			soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p1_bank == 1'd1);
+			soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p2_bank == 1'd1);
+			soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p3_bank == 1'd1);
+			soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col1 = 10'd0;
+	soc_ddrphy_bank_write_col1 <= 10'd0;
 	case (soc_ddrphy_writes1)
 		1'd1: begin
-			soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -2227,149 +2142,149 @@ assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1;
 assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1;
 always @(*) begin
-	soc_ddrphy_reads1 = 4'd0;
-	soc_ddrphy_reads1[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads1[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads1[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads1[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads1 <= 4'd0;
+	soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_read = 1'd0;
+	soc_ddrphy_bankmodel1_read_col <= 10'd0;
 	case (soc_ddrphy_reads1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p0_bank == 1'd1);
+			soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p1_bank == 1'd1);
+			soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p2_bank == 1'd1);
+			soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p3_bank == 1'd1);
+			soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_read_col = 10'd0;
+	soc_ddrphy_bankmodel1_read <= 1'd0;
 	case (soc_ddrphy_reads1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates2 = 4'd0;
-	soc_ddrphy_activates2[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates2[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates2[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates2[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates2 <= 4'd0;
+	soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_activate = 1'd0;
+	soc_ddrphy_bankmodel2_activate <= 1'd0;
 	case (soc_ddrphy_activates2)
 		1'd1: begin
-			soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p0_bank == 2'd2);
+			soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p1_bank == 2'd2);
+			soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p2_bank == 2'd2);
+			soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p3_bank == 2'd2);
+			soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_activate_row = 14'd0;
+	soc_ddrphy_bankmodel2_activate_row <= 14'd0;
 	case (soc_ddrphy_activates2)
 		1'd1: begin
-			soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges2 = 4'd0;
-	soc_ddrphy_precharges2[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges2[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges2[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges2[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges2 <= 4'd0;
+	soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_precharge = 1'd0;
+	soc_ddrphy_bankmodel2_precharge <= 1'd0;
 	case (soc_ddrphy_precharges2)
 		1'd1: begin
-			soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes2 = 4'd0;
-	soc_ddrphy_writes2[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes2[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes2[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes2[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes2 <= 4'd0;
+	soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write2 = 1'd0;
+	soc_ddrphy_bank_write_col2 <= 10'd0;
 	case (soc_ddrphy_writes2)
 		1'd1: begin
-			soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p0_bank == 2'd2);
+			soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p1_bank == 2'd2);
+			soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p2_bank == 2'd2);
+			soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p3_bank == 2'd2);
+			soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col2 = 10'd0;
+	soc_ddrphy_bank_write2 <= 1'd0;
 	case (soc_ddrphy_writes2)
 		1'd1: begin
-			soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
 		end
 	endcase
 end
@@ -2378,149 +2293,149 @@ assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2;
 assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2;
 always @(*) begin
-	soc_ddrphy_reads2 = 4'd0;
-	soc_ddrphy_reads2[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads2[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads2[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads2[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads2 <= 4'd0;
+	soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_read_col = 10'd0;
+	soc_ddrphy_bankmodel2_read <= 1'd0;
 	case (soc_ddrphy_reads2)
 		1'd1: begin
-			soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_read = 1'd0;
+	soc_ddrphy_bankmodel2_read_col <= 10'd0;
 	case (soc_ddrphy_reads2)
 		1'd1: begin
-			soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p0_bank == 2'd2);
+			soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p1_bank == 2'd2);
+			soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p2_bank == 2'd2);
+			soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p3_bank == 2'd2);
+			soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates3 = 4'd0;
-	soc_ddrphy_activates3[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates3[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates3[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates3[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates3 <= 4'd0;
+	soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_activate = 1'd0;
+	soc_ddrphy_bankmodel3_activate_row <= 14'd0;
 	case (soc_ddrphy_activates3)
 		1'd1: begin
-			soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p0_bank == 2'd3);
+			soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p1_bank == 2'd3);
+			soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p2_bank == 2'd3);
+			soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p3_bank == 2'd3);
+			soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_activate_row = 14'd0;
+	soc_ddrphy_bankmodel3_activate <= 1'd0;
 	case (soc_ddrphy_activates3)
 		1'd1: begin
-			soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges3 = 4'd0;
-	soc_ddrphy_precharges3[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges3[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges3[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges3[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges3 <= 4'd0;
+	soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_precharge = 1'd0;
+	soc_ddrphy_bankmodel3_precharge <= 1'd0;
 	case (soc_ddrphy_precharges3)
 		1'd1: begin
-			soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes3 = 4'd0;
-	soc_ddrphy_writes3[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes3[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes3[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes3[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes3 <= 4'd0;
+	soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write3 = 1'd0;
+	soc_ddrphy_bank_write3 <= 1'd0;
 	case (soc_ddrphy_writes3)
 		1'd1: begin
-			soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p0_bank == 2'd3);
+			soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p1_bank == 2'd3);
+			soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p2_bank == 2'd3);
+			soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p3_bank == 2'd3);
+			soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col3 = 10'd0;
+	soc_ddrphy_bank_write_col3 <= 10'd0;
 	case (soc_ddrphy_writes3)
 		1'd1: begin
-			soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -2529,149 +2444,149 @@ assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3;
 assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3;
 always @(*) begin
-	soc_ddrphy_reads3 = 4'd0;
-	soc_ddrphy_reads3[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads3[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads3[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads3[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads3 <= 4'd0;
+	soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_read = 1'd0;
+	soc_ddrphy_bankmodel3_read <= 1'd0;
 	case (soc_ddrphy_reads3)
 		1'd1: begin
-			soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p0_bank == 2'd3);
+			soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p1_bank == 2'd3);
+			soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p2_bank == 2'd3);
+			soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p3_bank == 2'd3);
+			soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_read_col = 10'd0;
+	soc_ddrphy_bankmodel3_read_col <= 10'd0;
 	case (soc_ddrphy_reads3)
 		1'd1: begin
-			soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates4 = 4'd0;
-	soc_ddrphy_activates4[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates4[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates4[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates4[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates4 <= 4'd0;
+	soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_activate_row = 14'd0;
+	soc_ddrphy_bankmodel4_activate <= 1'd0;
 	case (soc_ddrphy_activates4)
 		1'd1: begin
-			soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_activate = 1'd0;
+	soc_ddrphy_bankmodel4_activate_row <= 14'd0;
 	case (soc_ddrphy_activates4)
 		1'd1: begin
-			soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p0_bank == 3'd4);
+			soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p1_bank == 3'd4);
+			soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p2_bank == 3'd4);
+			soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p3_bank == 3'd4);
+			soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges4 = 4'd0;
-	soc_ddrphy_precharges4[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges4[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges4[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges4[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges4 <= 4'd0;
+	soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_precharge = 1'd0;
+	soc_ddrphy_bankmodel4_precharge <= 1'd0;
 	case (soc_ddrphy_precharges4)
 		1'd1: begin
-			soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes4 = 4'd0;
-	soc_ddrphy_writes4[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes4[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes4[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes4[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes4 <= 4'd0;
+	soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col4 = 10'd0;
+	soc_ddrphy_bank_write4 <= 1'd0;
 	case (soc_ddrphy_writes4)
 		1'd1: begin
-			soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write4 = 1'd0;
+	soc_ddrphy_bank_write_col4 <= 10'd0;
 	case (soc_ddrphy_writes4)
 		1'd1: begin
-			soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p0_bank == 3'd4);
+			soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p1_bank == 3'd4);
+			soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p2_bank == 3'd4);
+			soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p3_bank == 3'd4);
+			soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -2680,149 +2595,149 @@ assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4;
 assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4;
 always @(*) begin
-	soc_ddrphy_reads4 = 4'd0;
-	soc_ddrphy_reads4[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads4[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads4[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads4[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads4 <= 4'd0;
+	soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_read = 1'd0;
+	soc_ddrphy_bankmodel4_read <= 1'd0;
 	case (soc_ddrphy_reads4)
 		1'd1: begin
-			soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p0_bank == 3'd4);
+			soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p1_bank == 3'd4);
+			soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p2_bank == 3'd4);
+			soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p3_bank == 3'd4);
+			soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_read_col = 10'd0;
+	soc_ddrphy_bankmodel4_read_col <= 10'd0;
 	case (soc_ddrphy_reads4)
 		1'd1: begin
-			soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates5 = 4'd0;
-	soc_ddrphy_activates5[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates5[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates5[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates5[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates5 <= 4'd0;
+	soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_activate = 1'd0;
+	soc_ddrphy_bankmodel5_activate <= 1'd0;
 	case (soc_ddrphy_activates5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p0_bank == 3'd5);
+			soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p1_bank == 3'd5);
+			soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p2_bank == 3'd5);
+			soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p3_bank == 3'd5);
+			soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_activate_row = 14'd0;
+	soc_ddrphy_bankmodel5_activate_row <= 14'd0;
 	case (soc_ddrphy_activates5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges5 = 4'd0;
-	soc_ddrphy_precharges5[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges5[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges5[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges5[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges5 <= 4'd0;
+	soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_precharge = 1'd0;
+	soc_ddrphy_bankmodel5_precharge <= 1'd0;
 	case (soc_ddrphy_precharges5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes5 = 4'd0;
-	soc_ddrphy_writes5[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes5[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes5[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes5[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes5 <= 4'd0;
+	soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write5 = 1'd0;
+	soc_ddrphy_bank_write5 <= 1'd0;
 	case (soc_ddrphy_writes5)
 		1'd1: begin
-			soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p0_bank == 3'd5);
+			soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p1_bank == 3'd5);
+			soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p2_bank == 3'd5);
+			soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p3_bank == 3'd5);
+			soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col5 = 10'd0;
+	soc_ddrphy_bank_write_col5 <= 10'd0;
 	case (soc_ddrphy_writes5)
 		1'd1: begin
-			soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -2831,149 +2746,149 @@ assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5;
 assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5;
 always @(*) begin
-	soc_ddrphy_reads5 = 4'd0;
-	soc_ddrphy_reads5[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads5[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads5[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads5 <= 4'd0;
+	soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read = 1'd0;
+	soc_ddrphy_bankmodel5_read <= 1'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read_col = 10'd0;
+	soc_ddrphy_bankmodel5_read_col <= 10'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates6 = 4'd0;
-	soc_ddrphy_activates6[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates6[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates6[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates6[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates6 <= 4'd0;
+	soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_activate = 1'd0;
+	soc_ddrphy_bankmodel6_activate <= 1'd0;
 	case (soc_ddrphy_activates6)
 		1'd1: begin
-			soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p0_bank == 3'd6);
+			soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p1_bank == 3'd6);
+			soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p2_bank == 3'd6);
+			soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p3_bank == 3'd6);
+			soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_activate_row = 14'd0;
+	soc_ddrphy_bankmodel6_activate_row <= 14'd0;
 	case (soc_ddrphy_activates6)
 		1'd1: begin
-			soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges6 = 4'd0;
-	soc_ddrphy_precharges6[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges6[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges6[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges6[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges6 <= 4'd0;
+	soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_precharge = 1'd0;
+	soc_ddrphy_bankmodel6_precharge <= 1'd0;
 	case (soc_ddrphy_precharges6)
 		1'd1: begin
-			soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes6 = 4'd0;
-	soc_ddrphy_writes6[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes6[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes6[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes6[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes6 <= 4'd0;
+	soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write6 = 1'd0;
+	soc_ddrphy_bank_write_col6 <= 10'd0;
 	case (soc_ddrphy_writes6)
 		1'd1: begin
-			soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p0_bank == 3'd6);
+			soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p1_bank == 3'd6);
+			soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p2_bank == 3'd6);
+			soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p3_bank == 3'd6);
+			soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col6 = 10'd0;
+	soc_ddrphy_bank_write6 <= 1'd0;
 	case (soc_ddrphy_writes6)
 		1'd1: begin
-			soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
 		end
 	endcase
 end
@@ -2982,149 +2897,149 @@ assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6;
 assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6;
 always @(*) begin
-	soc_ddrphy_reads6 = 4'd0;
-	soc_ddrphy_reads6[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads6[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads6[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads6[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads6 <= 4'd0;
+	soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_read = 1'd0;
+	soc_ddrphy_bankmodel6_read_col <= 10'd0;
 	case (soc_ddrphy_reads6)
 		1'd1: begin
-			soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p0_bank == 3'd6);
+			soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p1_bank == 3'd6);
+			soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p2_bank == 3'd6);
+			soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p3_bank == 3'd6);
+			soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_read_col = 10'd0;
+	soc_ddrphy_bankmodel6_read <= 1'd0;
 	case (soc_ddrphy_reads6)
 		1'd1: begin
-			soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_activates7 = 4'd0;
-	soc_ddrphy_activates7[0] = soc_ddrphy_dfiphasemodel0_activate;
-	soc_ddrphy_activates7[1] = soc_ddrphy_dfiphasemodel1_activate;
-	soc_ddrphy_activates7[2] = soc_ddrphy_dfiphasemodel2_activate;
-	soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate;
+	soc_ddrphy_activates7 <= 4'd0;
+	soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate;
+	soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate;
+	soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate;
+	soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate = 1'd0;
+	soc_ddrphy_bankmodel7_activate <= 1'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate_row = 14'd0;
+	soc_ddrphy_bankmodel7_activate_row <= 14'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_precharges7 = 4'd0;
-	soc_ddrphy_precharges7[0] = soc_ddrphy_dfiphasemodel0_precharge;
-	soc_ddrphy_precharges7[1] = soc_ddrphy_dfiphasemodel1_precharge;
-	soc_ddrphy_precharges7[2] = soc_ddrphy_dfiphasemodel2_precharge;
-	soc_ddrphy_precharges7[3] = soc_ddrphy_dfiphasemodel3_precharge;
+	soc_ddrphy_precharges7 <= 4'd0;
+	soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+	soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+	soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+	soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_precharge = 1'd0;
+	soc_ddrphy_bankmodel7_precharge <= 1'd0;
 	case (soc_ddrphy_precharges7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
+			soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
+			soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
+			soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
+			soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_writes7 = 4'd0;
-	soc_ddrphy_writes7[0] = soc_ddrphy_dfiphasemodel0_write;
-	soc_ddrphy_writes7[1] = soc_ddrphy_dfiphasemodel1_write;
-	soc_ddrphy_writes7[2] = soc_ddrphy_dfiphasemodel2_write;
-	soc_ddrphy_writes7[3] = soc_ddrphy_dfiphasemodel3_write;
+	soc_ddrphy_writes7 <= 4'd0;
+	soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write;
+	soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write;
+	soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write;
+	soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-	soc_ddrphy_bank_write7 = 1'd0;
+	soc_ddrphy_bank_write7 <= 1'd0;
 	case (soc_ddrphy_writes7)
 		1'd1: begin
-			soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bank_write_col7 = 10'd0;
+	soc_ddrphy_bank_write_col7 <= 10'd0;
 	case (soc_ddrphy_writes7)
 		1'd1: begin
-			soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3133,43 +3048,43 @@ assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd
 assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7;
 assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7;
 always @(*) begin
-	soc_ddrphy_reads7 = 4'd0;
-	soc_ddrphy_reads7[0] = soc_ddrphy_dfiphasemodel0_read;
-	soc_ddrphy_reads7[1] = soc_ddrphy_dfiphasemodel1_read;
-	soc_ddrphy_reads7[2] = soc_ddrphy_dfiphasemodel2_read;
-	soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read;
+	soc_ddrphy_reads7 <= 4'd0;
+	soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read;
+	soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read;
+	soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read;
+	soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read_col = 10'd0;
+	soc_ddrphy_bankmodel7_read <= 1'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read = 1'd0;
+	soc_ddrphy_bankmodel7_read_col <= 10'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3184,418 +3099,418 @@ assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rd
 assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
 assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
 always @(*) begin
-	soc_ddrphy_dfiphasemodel0_activate = 1'd0;
+	soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
-		soc_ddrphy_dfiphasemodel0_activate = soc_ddrphy_dfi_p0_we_n;
+		soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
+	soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
-		soc_ddrphy_dfiphasemodel0_precharge = (~soc_ddrphy_dfi_p0_we_n);
+		soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel0_read = 1'd0;
+	soc_ddrphy_dfiphasemodel0_write <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
-		soc_ddrphy_dfiphasemodel0_read = soc_ddrphy_dfi_p0_we_n;
+		soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel0_write = 1'd0;
+	soc_ddrphy_dfiphasemodel0_read <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
-		soc_ddrphy_dfiphasemodel0_write = (~soc_ddrphy_dfi_p0_we_n);
+		soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel1_activate = 1'd0;
+	soc_ddrphy_dfiphasemodel1_activate <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
-		soc_ddrphy_dfiphasemodel1_activate = soc_ddrphy_dfi_p1_we_n;
+		soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
+	soc_ddrphy_dfiphasemodel1_precharge <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
-		soc_ddrphy_dfiphasemodel1_precharge = (~soc_ddrphy_dfi_p1_we_n);
+		soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel1_write = 1'd0;
+	soc_ddrphy_dfiphasemodel1_write <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
-		soc_ddrphy_dfiphasemodel1_write = (~soc_ddrphy_dfi_p1_we_n);
+		soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel1_read = 1'd0;
+	soc_ddrphy_dfiphasemodel1_read <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
-		soc_ddrphy_dfiphasemodel1_read = soc_ddrphy_dfi_p1_we_n;
+		soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
+	soc_ddrphy_dfiphasemodel2_activate <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
-		soc_ddrphy_dfiphasemodel2_precharge = (~soc_ddrphy_dfi_p2_we_n);
+		soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel2_activate = 1'd0;
+	soc_ddrphy_dfiphasemodel2_precharge <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
-		soc_ddrphy_dfiphasemodel2_activate = soc_ddrphy_dfi_p2_we_n;
+		soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel2_write = 1'd0;
+	soc_ddrphy_dfiphasemodel2_read <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
-		soc_ddrphy_dfiphasemodel2_write = (~soc_ddrphy_dfi_p2_we_n);
+		soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel2_read = 1'd0;
+	soc_ddrphy_dfiphasemodel2_write <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
-		soc_ddrphy_dfiphasemodel2_read = soc_ddrphy_dfi_p2_we_n;
+		soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel3_activate = 1'd0;
+	soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
-		soc_ddrphy_dfiphasemodel3_activate = soc_ddrphy_dfi_p3_we_n;
+		soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
+	soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
-		soc_ddrphy_dfiphasemodel3_precharge = (~soc_ddrphy_dfi_p3_we_n);
+		soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel3_write = 1'd0;
+	soc_ddrphy_dfiphasemodel3_write <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
-		soc_ddrphy_dfiphasemodel3_write = (~soc_ddrphy_dfi_p3_we_n);
+		soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n);
 	end
 end
 always @(*) begin
-	soc_ddrphy_dfiphasemodel3_read = 1'd0;
+	soc_ddrphy_dfiphasemodel3_read <= 1'd0;
 	if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
-		soc_ddrphy_dfiphasemodel3_read = soc_ddrphy_dfi_p3_we_n;
+		soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n;
 	end
 end
 assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
 assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel0_read_data = 128'd0;
+	soc_ddrphy_bankmodel0_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel0_active) begin
 		if (soc_ddrphy_bankmodel0_read) begin
-			soc_ddrphy_bankmodel0_read_data = soc_ddrphy_bankmodel0_read_port_dat_r;
+			soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel0_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel0_active) begin
-		soc_ddrphy_bankmodel0_write_port_adr = soc_ddrphy_bankmodel0_wraddr;
+		soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel0_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel0_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel0_write_port_we = ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
+			soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel0_write_port_we = soc_ddrphy_bankmodel0_write;
+			soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel0_active) begin
-		soc_ddrphy_bankmodel0_write_port_dat_w = soc_ddrphy_bankmodel0_write_data;
+		soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel0_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel0_active) begin
 		if (soc_ddrphy_bankmodel0_read) begin
-			soc_ddrphy_bankmodel0_read_port_adr = soc_ddrphy_bankmodel0_rdaddr;
+			soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr;
 		end
 	end
 end
 assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
 assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel1_read_data = 128'd0;
+	soc_ddrphy_bankmodel1_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
 		if (soc_ddrphy_bankmodel1_read) begin
-			soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
+			soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel1_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
-		soc_ddrphy_bankmodel1_write_port_adr = soc_ddrphy_bankmodel1_wraddr;
+		soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel1_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel1_write_port_we = ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
+			soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel1_write_port_we = soc_ddrphy_bankmodel1_write;
+			soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
-		soc_ddrphy_bankmodel1_write_port_dat_w = soc_ddrphy_bankmodel1_write_data;
+		soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel1_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
 		if (soc_ddrphy_bankmodel1_read) begin
-			soc_ddrphy_bankmodel1_read_port_adr = soc_ddrphy_bankmodel1_rdaddr;
+			soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr;
 		end
 	end
 end
 assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
 assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel2_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel2_active) begin
-		soc_ddrphy_bankmodel2_write_port_adr = soc_ddrphy_bankmodel2_wraddr;
+		soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel2_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel2_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel2_write_port_we = ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
+			soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel2_write_port_we = soc_ddrphy_bankmodel2_write;
+			soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel2_active) begin
-		soc_ddrphy_bankmodel2_write_port_dat_w = soc_ddrphy_bankmodel2_write_data;
+		soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel2_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel2_active) begin
 		if (soc_ddrphy_bankmodel2_read) begin
-			soc_ddrphy_bankmodel2_read_port_adr = soc_ddrphy_bankmodel2_rdaddr;
+			soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel2_read_data = 128'd0;
+	soc_ddrphy_bankmodel2_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel2_active) begin
 		if (soc_ddrphy_bankmodel2_read) begin
-			soc_ddrphy_bankmodel2_read_data = soc_ddrphy_bankmodel2_read_port_dat_r;
+			soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r;
 		end
 	end
 end
 assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
 assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel3_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
+	if (soc_ddrphy_bankmodel3_active) begin
+		soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
+	end
+end
+always @(*) begin
+	soc_ddrphy_bankmodel3_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel3_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel3_write_port_we = ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
+			soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel3_write_port_we = soc_ddrphy_bankmodel3_write;
+			soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel3_active) begin
-		soc_ddrphy_bankmodel3_write_port_dat_w = soc_ddrphy_bankmodel3_write_data;
+		soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel3_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel3_active) begin
 		if (soc_ddrphy_bankmodel3_read) begin
-			soc_ddrphy_bankmodel3_read_port_adr = soc_ddrphy_bankmodel3_rdaddr;
+			soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel3_read_data = 128'd0;
+	soc_ddrphy_bankmodel3_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel3_active) begin
 		if (soc_ddrphy_bankmodel3_read) begin
-			soc_ddrphy_bankmodel3_read_data = soc_ddrphy_bankmodel3_read_port_dat_r;
+			soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r;
 		end
 	end
 end
-always @(*) begin
-	soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
-	if (soc_ddrphy_bankmodel3_active) begin
-		soc_ddrphy_bankmodel3_write_port_adr = soc_ddrphy_bankmodel3_wraddr;
-	end
-end
 assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
 assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
-		soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
+		if (4'd8) begin
+			soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
+		end else begin
+			soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
+		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
-		if (soc_ddrphy_bankmodel4_read) begin
-			soc_ddrphy_bankmodel4_read_port_adr = soc_ddrphy_bankmodel4_rdaddr;
-		end
+		soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_read_data = 128'd0;
+	soc_ddrphy_bankmodel4_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
 		if (soc_ddrphy_bankmodel4_read) begin
-			soc_ddrphy_bankmodel4_read_data = soc_ddrphy_bankmodel4_read_port_dat_r;
+			soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel4_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
-		soc_ddrphy_bankmodel4_write_port_adr = soc_ddrphy_bankmodel4_wraddr;
+		if (soc_ddrphy_bankmodel4_read) begin
+			soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r;
+		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel4_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel4_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
-		if (4'd8) begin
-			soc_ddrphy_bankmodel4_write_port_we = ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
-		end else begin
-			soc_ddrphy_bankmodel4_write_port_we = soc_ddrphy_bankmodel4_write;
-		end
+		soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr;
 	end
 end
 assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
 assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel5_read_data = 128'd0;
+	soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel5_active) begin
 		if (soc_ddrphy_bankmodel5_read) begin
-			soc_ddrphy_bankmodel5_read_data = soc_ddrphy_bankmodel5_read_port_dat_r;
+			soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel5_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel5_active) begin
-		soc_ddrphy_bankmodel5_write_port_adr = soc_ddrphy_bankmodel5_wraddr;
+		if (soc_ddrphy_bankmodel5_read) begin
+			soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r;
+		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel5_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel5_active) begin
-		if (4'd8) begin
-			soc_ddrphy_bankmodel5_write_port_we = ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
-		end else begin
-			soc_ddrphy_bankmodel5_write_port_we = soc_ddrphy_bankmodel5_write;
-		end
+		soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel5_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel5_active) begin
-		soc_ddrphy_bankmodel5_write_port_dat_w = soc_ddrphy_bankmodel5_write_data;
+		if (4'd8) begin
+			soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
+		end else begin
+			soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write;
+		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel5_active) begin
-		if (soc_ddrphy_bankmodel5_read) begin
-			soc_ddrphy_bankmodel5_read_port_adr = soc_ddrphy_bankmodel5_rdaddr;
-		end
+		soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data;
 	end
 end
 assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
 assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel6_read_data = 128'd0;
+	soc_ddrphy_bankmodel6_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel6_active) begin
 		if (soc_ddrphy_bankmodel6_read) begin
-			soc_ddrphy_bankmodel6_read_data = soc_ddrphy_bankmodel6_read_port_dat_r;
+			soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel6_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel6_active) begin
-		soc_ddrphy_bankmodel6_write_port_adr = soc_ddrphy_bankmodel6_wraddr;
+		soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel6_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel6_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel6_write_port_we = ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
+			soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel6_write_port_we = soc_ddrphy_bankmodel6_write;
+			soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel6_active) begin
-		soc_ddrphy_bankmodel6_write_port_dat_w = soc_ddrphy_bankmodel6_write_data;
+		soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel6_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel6_active) begin
 		if (soc_ddrphy_bankmodel6_read) begin
-			soc_ddrphy_bankmodel6_read_port_adr = soc_ddrphy_bankmodel6_rdaddr;
+			soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr;
 		end
 	end
 end
 assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
 assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
 always @(*) begin
-	soc_ddrphy_bankmodel7_read_data = 128'd0;
+	soc_ddrphy_bankmodel7_read_data <= 128'd0;
 	if (soc_ddrphy_bankmodel7_active) begin
 		if (soc_ddrphy_bankmodel7_read) begin
-			soc_ddrphy_bankmodel7_read_data = soc_ddrphy_bankmodel7_read_port_dat_r;
+			soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
+	soc_ddrphy_bankmodel7_write_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel7_active) begin
-		soc_ddrphy_bankmodel7_write_port_adr = soc_ddrphy_bankmodel7_wraddr;
+		soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_write_port_we = 16'd0;
+	soc_ddrphy_bankmodel7_write_port_we <= 16'd0;
 	if (soc_ddrphy_bankmodel7_active) begin
 		if (4'd8) begin
-			soc_ddrphy_bankmodel7_write_port_we = ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
+			soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
 		end else begin
-			soc_ddrphy_bankmodel7_write_port_we = soc_ddrphy_bankmodel7_write;
+			soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write;
 		end
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
+	soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0;
 	if (soc_ddrphy_bankmodel7_active) begin
-		soc_ddrphy_bankmodel7_write_port_dat_w = soc_ddrphy_bankmodel7_write_data;
+		soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data;
 	end
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
+	soc_ddrphy_bankmodel7_read_port_adr <= 21'd0;
 	if (soc_ddrphy_bankmodel7_active) begin
 		if (soc_ddrphy_bankmodel7_read) begin
-			soc_ddrphy_bankmodel7_read_port_adr = soc_ddrphy_bankmodel7_rdaddr;
+			soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr;
 		end
 	end
 end
@@ -3728,563 +3643,563 @@ assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
 assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
 assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
 always @(*) begin
-	soc_litedramcore_master_p0_we_n = 1'd1;
+	soc_litedramcore_master_p0_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_we_n = soc_litedramcore_slave_p0_we_n;
+		soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
 	end else begin
-		soc_litedramcore_master_p0_we_n = soc_litedramcore_inti_p0_we_n;
+		soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+	soc_litedramcore_master_p0_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid;
+		soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
 	end else begin
+		soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_cke = 1'd0;
+	soc_litedramcore_slave_p0_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cke = soc_litedramcore_slave_p0_cke;
+		soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
 	end else begin
-		soc_litedramcore_master_p0_cke = soc_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_odt = 1'd0;
+	soc_litedramcore_master_p0_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_odt = soc_litedramcore_slave_p0_odt;
+		soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
 	end else begin
-		soc_litedramcore_master_p0_odt = soc_litedramcore_inti_p0_odt;
+		soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_reset_n = 1'd0;
+	soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_reset_n = soc_litedramcore_slave_p0_reset_n;
+		soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
 	end else begin
-		soc_litedramcore_master_p0_reset_n = soc_litedramcore_inti_p0_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_act_n = 1'd1;
+	soc_litedramcore_master_p0_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_act_n = soc_litedramcore_slave_p0_act_n;
+		soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
 	end else begin
-		soc_litedramcore_master_p0_act_n = soc_litedramcore_inti_p0_act_n;
+		soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata = 32'd0;
+	soc_litedramcore_master_p0_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata = soc_litedramcore_slave_p0_wrdata;
+		soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
 	end else begin
-		soc_litedramcore_master_p0_wrdata = soc_litedramcore_inti_p0_wrdata;
+		soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_rddata = 32'd0;
+	soc_litedramcore_master_p0_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
 	end else begin
-		soc_litedramcore_inti_p1_rddata = soc_litedramcore_master_p1_rddata;
+		soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata_en = 1'd0;
+	soc_litedramcore_master_p0_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_slave_p0_wrdata_en;
+		soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
 	end else begin
-		soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_inti_p0_wrdata_en;
+		soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_rddata_valid = 1'd0;
+	soc_litedramcore_master_p0_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
 	end else begin
-		soc_litedramcore_inti_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid;
+		soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+	soc_litedramcore_inti_p1_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_slave_p0_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_inti_p0_wrdata_mask;
+		soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_rddata_en = 1'd0;
+	soc_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_rddata_en = soc_litedramcore_slave_p0_rddata_en;
+		soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
 	end else begin
-		soc_litedramcore_master_p0_rddata_en = soc_litedramcore_inti_p0_rddata_en;
+		soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_address = 14'd0;
+	soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_address = soc_litedramcore_slave_p1_address;
 	end else begin
-		soc_litedramcore_master_p1_address = soc_litedramcore_inti_p1_address;
+		soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_bank = 3'd0;
+	soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_bank = soc_litedramcore_slave_p1_bank;
+		soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p1_bank = soc_litedramcore_inti_p1_bank;
+		soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cas_n = 1'd1;
+	soc_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cas_n = soc_litedramcore_slave_p1_cas_n;
+		soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
 	end else begin
-		soc_litedramcore_master_p1_cas_n = soc_litedramcore_inti_p1_cas_n;
+		soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cs_n = 1'd1;
+	soc_litedramcore_master_p1_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cs_n = soc_litedramcore_slave_p1_cs_n;
+		soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
 	end else begin
-		soc_litedramcore_master_p1_cs_n = soc_litedramcore_inti_p1_cs_n;
+		soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_ras_n = 1'd1;
+	soc_litedramcore_master_p1_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_ras_n = soc_litedramcore_slave_p1_ras_n;
+		soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
 	end else begin
-		soc_litedramcore_master_p1_ras_n = soc_litedramcore_inti_p1_ras_n;
+		soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p1_rddata = 32'd0;
+	soc_litedramcore_master_p1_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p1_rddata = soc_litedramcore_master_p1_rddata;
+		soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
 	end else begin
+		soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_we_n = 1'd1;
+	soc_litedramcore_master_p1_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_we_n = soc_litedramcore_slave_p1_we_n;
+		soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
 	end else begin
-		soc_litedramcore_master_p1_we_n = soc_litedramcore_inti_p1_we_n;
+		soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+	soc_litedramcore_master_p1_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid;
+		soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
 	end else begin
+		soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cke = 1'd0;
+	soc_litedramcore_slave_p1_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cke = soc_litedramcore_slave_p1_cke;
+		soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
 	end else begin
-		soc_litedramcore_master_p1_cke = soc_litedramcore_inti_p1_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_odt = 1'd0;
+	soc_litedramcore_master_p1_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_odt = soc_litedramcore_slave_p1_odt;
+		soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
 	end else begin
-		soc_litedramcore_master_p1_odt = soc_litedramcore_inti_p1_odt;
+		soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_reset_n = 1'd0;
+	soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_reset_n = soc_litedramcore_slave_p1_reset_n;
+		soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
 	end else begin
-		soc_litedramcore_master_p1_reset_n = soc_litedramcore_inti_p1_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_act_n = 1'd1;
+	soc_litedramcore_master_p1_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_act_n = soc_litedramcore_slave_p1_act_n;
+		soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
 	end else begin
-		soc_litedramcore_master_p1_act_n = soc_litedramcore_inti_p1_act_n;
+		soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_wrdata = 32'd0;
+	soc_litedramcore_master_p1_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata = soc_litedramcore_slave_p1_wrdata;
+		soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
 	end else begin
-		soc_litedramcore_master_p1_wrdata = soc_litedramcore_inti_p1_wrdata;
+		soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_rddata = 32'd0;
+	soc_litedramcore_master_p1_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
 	end else begin
-		soc_litedramcore_inti_p2_rddata = soc_litedramcore_master_p2_rddata;
+		soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_wrdata_en = 1'd0;
+	soc_litedramcore_master_p1_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_slave_p1_wrdata_en;
+		soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
 	end else begin
-		soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_inti_p1_wrdata_en;
+		soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_rddata_valid = 1'd0;
+	soc_litedramcore_master_p1_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
 	end else begin
-		soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
+		soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+	soc_litedramcore_inti_p2_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_slave_p1_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_inti_p1_wrdata_mask;
+		soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_rddata_en = 1'd0;
+	soc_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_rddata_en = soc_litedramcore_slave_p1_rddata_en;
+		soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
 	end else begin
-		soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en;
+		soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_ras_n = 1'd1;
+	soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
 	end else begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
+		soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_address = 14'd0;
+	soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_address = soc_litedramcore_slave_p2_address;
+		soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p2_address = soc_litedramcore_inti_p2_address;
+		soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_bank = 3'd0;
+	soc_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_bank = soc_litedramcore_slave_p2_bank;
+		soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
 	end else begin
-		soc_litedramcore_master_p2_bank = soc_litedramcore_inti_p2_bank;
+		soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_cas_n = 1'd1;
+	soc_litedramcore_master_p2_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cas_n = soc_litedramcore_slave_p2_cas_n;
+		soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
 	end else begin
-		soc_litedramcore_master_p2_cas_n = soc_litedramcore_inti_p2_cas_n;
+		soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_cs_n = 1'd1;
+	soc_litedramcore_master_p2_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cs_n = soc_litedramcore_slave_p2_cs_n;
+		soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
 	end else begin
-		soc_litedramcore_master_p2_cs_n = soc_litedramcore_inti_p2_cs_n;
+		soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_ras_n = 1'd1;
+	soc_litedramcore_master_p2_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_ras_n = soc_litedramcore_slave_p2_ras_n;
+		soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
 	end else begin
-		soc_litedramcore_master_p2_ras_n = soc_litedramcore_inti_p2_ras_n;
+		soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p2_rddata = 32'd0;
+	soc_litedramcore_master_p2_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p2_rddata = soc_litedramcore_master_p2_rddata;
+		soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
 	end else begin
+		soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_we_n = 1'd1;
+	soc_litedramcore_master_p2_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_we_n = soc_litedramcore_slave_p2_we_n;
+		soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
 	end else begin
-		soc_litedramcore_master_p2_we_n = soc_litedramcore_inti_p2_we_n;
+		soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+	soc_litedramcore_slave_p2_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
+		soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
 	end else begin
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_cke = 1'd0;
+	soc_litedramcore_master_p2_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cke = soc_litedramcore_slave_p2_cke;
+		soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
 	end else begin
-		soc_litedramcore_master_p2_cke = soc_litedramcore_inti_p2_cke;
+		soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_odt = 1'd0;
+	soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_odt = soc_litedramcore_slave_p2_odt;
+		soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
 	end else begin
-		soc_litedramcore_master_p2_odt = soc_litedramcore_inti_p2_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_reset_n = 1'd0;
+	soc_litedramcore_master_p2_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_reset_n = soc_litedramcore_slave_p2_reset_n;
+		soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
 	end else begin
-		soc_litedramcore_master_p2_reset_n = soc_litedramcore_inti_p2_reset_n;
+		soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_act_n = 1'd1;
+	soc_litedramcore_master_p2_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_act_n = soc_litedramcore_slave_p2_act_n;
+		soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
 	end else begin
-		soc_litedramcore_master_p2_act_n = soc_litedramcore_inti_p2_act_n;
+		soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata = 32'd0;
+	soc_litedramcore_master_p2_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata = soc_litedramcore_slave_p2_wrdata;
+		soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
 	end else begin
-		soc_litedramcore_master_p2_wrdata = soc_litedramcore_inti_p2_wrdata;
+		soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_rddata = 32'd0;
+	soc_litedramcore_master_p2_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
 	end else begin
-		soc_litedramcore_inti_p3_rddata = soc_litedramcore_master_p3_rddata;
+		soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata_en = 1'd0;
+	soc_litedramcore_master_p2_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_slave_p2_wrdata_en;
+		soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
 	end else begin
-		soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_inti_p2_wrdata_en;
+		soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_rddata_valid = 1'd0;
+	soc_litedramcore_inti_p3_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
 	end else begin
-		soc_litedramcore_inti_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid;
+		soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+	soc_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_slave_p2_wrdata_mask;
+		soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
 	end else begin
-		soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_inti_p2_wrdata_mask;
+		soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_rddata_en = 1'd0;
+	soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_rddata_en = soc_litedramcore_slave_p2_rddata_en;
 	end else begin
-		soc_litedramcore_master_p2_rddata_en = soc_litedramcore_inti_p2_rddata_en;
+		soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_address = 14'd0;
+	soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_address = soc_litedramcore_slave_p3_address;
+		soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p3_address = soc_litedramcore_inti_p3_address;
+		soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_bank = 3'd0;
+	soc_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_bank = soc_litedramcore_slave_p3_bank;
+		soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
 	end else begin
-		soc_litedramcore_master_p3_bank = soc_litedramcore_inti_p3_bank;
+		soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cas_n = 1'd1;
+	soc_litedramcore_master_p3_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cas_n = soc_litedramcore_slave_p3_cas_n;
+		soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
 	end else begin
-		soc_litedramcore_master_p3_cas_n = soc_litedramcore_inti_p3_cas_n;
+		soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cs_n = 1'd1;
+	soc_litedramcore_master_p3_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cs_n = soc_litedramcore_slave_p3_cs_n;
+		soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
 	end else begin
-		soc_litedramcore_master_p3_cs_n = soc_litedramcore_inti_p3_cs_n;
+		soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_ras_n = 1'd1;
+	soc_litedramcore_master_p3_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_ras_n = soc_litedramcore_slave_p3_ras_n;
+		soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
 	end else begin
-		soc_litedramcore_master_p3_ras_n = soc_litedramcore_inti_p3_ras_n;
+		soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p3_rddata = 32'd0;
+	soc_litedramcore_master_p3_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p3_rddata = soc_litedramcore_master_p3_rddata;
+		soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
 	end else begin
+		soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_we_n = 1'd1;
+	soc_litedramcore_master_p3_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_we_n = soc_litedramcore_slave_p3_we_n;
+		soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
 	end else begin
-		soc_litedramcore_master_p3_we_n = soc_litedramcore_inti_p3_we_n;
+		soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+	soc_litedramcore_slave_p3_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid;
+		soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
 	end else begin
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cke = 1'd0;
+	soc_litedramcore_master_p3_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cke = soc_litedramcore_slave_p3_cke;
+		soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
 	end else begin
-		soc_litedramcore_master_p3_cke = soc_litedramcore_inti_p3_cke;
+		soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_odt = 1'd0;
+	soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_odt = soc_litedramcore_slave_p3_odt;
+		soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
 	end else begin
-		soc_litedramcore_master_p3_odt = soc_litedramcore_inti_p3_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_reset_n = 1'd0;
+	soc_litedramcore_master_p3_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_reset_n = soc_litedramcore_slave_p3_reset_n;
+		soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
 	end else begin
-		soc_litedramcore_master_p3_reset_n = soc_litedramcore_inti_p3_reset_n;
+		soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_act_n = 1'd1;
+	soc_litedramcore_master_p3_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_act_n = soc_litedramcore_slave_p3_act_n;
+		soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
 	end else begin
-		soc_litedramcore_master_p3_act_n = soc_litedramcore_inti_p3_act_n;
+		soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata = 32'd0;
+	soc_litedramcore_master_p3_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata = soc_litedramcore_slave_p3_wrdata;
+		soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
 	end else begin
-		soc_litedramcore_master_p3_wrdata = soc_litedramcore_inti_p3_wrdata;
+		soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_rddata = 32'd0;
+	soc_litedramcore_master_p3_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
 	end else begin
-		soc_litedramcore_inti_p0_rddata = soc_litedramcore_master_p0_rddata;
+		soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata_en = 1'd0;
+	soc_litedramcore_master_p3_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_slave_p3_wrdata_en;
+		soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
 	end else begin
-		soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_inti_p3_wrdata_en;
+		soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_rddata_valid = 1'd0;
+	soc_litedramcore_inti_p0_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
 	end else begin
-		soc_litedramcore_inti_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid;
+		soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+	soc_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_slave_p3_wrdata_mask;
+		soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
 	end else begin
-		soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_inti_p3_wrdata_mask;
+		soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_rddata_en = 1'd0;
+	soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_rddata_en = soc_litedramcore_slave_p3_rddata_en;
 	end else begin
-		soc_litedramcore_master_p3_rddata_en = soc_litedramcore_inti_p3_rddata_en;
+		soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_address = 14'd0;
+	soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_address = soc_litedramcore_slave_p0_address;
+		soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p0_address = soc_litedramcore_inti_p0_address;
+		soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_bank = 3'd0;
+	soc_litedramcore_master_p3_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_bank = soc_litedramcore_slave_p0_bank;
+		soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
 	end else begin
-		soc_litedramcore_master_p0_bank = soc_litedramcore_inti_p0_bank;
+		soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_cas_n = 1'd1;
+	soc_litedramcore_master_p0_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cas_n = soc_litedramcore_slave_p0_cas_n;
+		soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
 	end else begin
-		soc_litedramcore_master_p0_cas_n = soc_litedramcore_inti_p0_cas_n;
+		soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_cs_n = 1'd1;
+	soc_litedramcore_master_p0_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cs_n = soc_litedramcore_slave_p0_cs_n;
+		soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
 	end else begin
-		soc_litedramcore_master_p0_cs_n = soc_litedramcore_inti_p0_cs_n;
+		soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p0_rddata = 32'd0;
+	soc_litedramcore_master_p0_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p0_rddata = soc_litedramcore_master_p0_rddata;
+		soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
 	end else begin
+		soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
 	end
 end
 assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke;
@@ -4300,35 +4215,35 @@ assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
 always @(*) begin
-	soc_litedramcore_inti_p0_we_n = 1'd1;
+	soc_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_we_n = (~soc_litedramcore_phaseinjector0_command_storage[1]);
+		soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
 	end else begin
-		soc_litedramcore_inti_p0_we_n = 1'd1;
+		soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_cas_n = 1'd1;
+	soc_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_cas_n = (~soc_litedramcore_phaseinjector0_command_storage[2]);
+		soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
 	end else begin
-		soc_litedramcore_inti_p0_cas_n = 1'd1;
+		soc_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_cs_n = 1'd1;
+	soc_litedramcore_inti_p0_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_cs_n = {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
+		soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
 	end else begin
-		soc_litedramcore_inti_p0_cs_n = {1{1'd1}};
+		soc_litedramcore_inti_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_ras_n = 1'd1;
+	soc_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_ras_n = (~soc_litedramcore_phaseinjector0_command_storage[3]);
+		soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
 	end else begin
-		soc_litedramcore_inti_p0_ras_n = 1'd1;
+		soc_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
 end
 assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage;
@@ -4338,35 +4253,35 @@ assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_com
 assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
 assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p1_we_n = 1'd1;
+	soc_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_we_n = (~soc_litedramcore_phaseinjector1_command_storage[1]);
+		soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
 	end else begin
-		soc_litedramcore_inti_p1_we_n = 1'd1;
+		soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_cas_n = 1'd1;
+	soc_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_cas_n = (~soc_litedramcore_phaseinjector1_command_storage[2]);
+		soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
 	end else begin
-		soc_litedramcore_inti_p1_cas_n = 1'd1;
+		soc_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_cs_n = 1'd1;
+	soc_litedramcore_inti_p1_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_cs_n = {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
+		soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
 	end else begin
-		soc_litedramcore_inti_p1_cs_n = {1{1'd1}};
+		soc_litedramcore_inti_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_ras_n = 1'd1;
+	soc_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_ras_n = (~soc_litedramcore_phaseinjector1_command_storage[3]);
+		soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
 	end else begin
-		soc_litedramcore_inti_p1_ras_n = 1'd1;
+		soc_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
 end
 assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage;
@@ -4376,35 +4291,35 @@ assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_com
 assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
 assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p2_we_n = 1'd1;
+	soc_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_we_n = (~soc_litedramcore_phaseinjector2_command_storage[1]);
+		soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
 	end else begin
-		soc_litedramcore_inti_p2_we_n = 1'd1;
+		soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_cas_n = 1'd1;
+	soc_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_cas_n = (~soc_litedramcore_phaseinjector2_command_storage[2]);
+		soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
 	end else begin
-		soc_litedramcore_inti_p2_cas_n = 1'd1;
+		soc_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_cs_n = 1'd1;
+	soc_litedramcore_inti_p2_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_cs_n = {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
+		soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
 	end else begin
-		soc_litedramcore_inti_p2_cs_n = {1{1'd1}};
+		soc_litedramcore_inti_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_ras_n = 1'd1;
+	soc_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_ras_n = (~soc_litedramcore_phaseinjector2_command_storage[3]);
+		soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
 	end else begin
-		soc_litedramcore_inti_p2_ras_n = 1'd1;
+		soc_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
 end
 assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage;
@@ -4414,35 +4329,35 @@ assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_com
 assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
 assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p3_we_n = 1'd1;
+	soc_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_we_n = (~soc_litedramcore_phaseinjector3_command_storage[1]);
+		soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
 	end else begin
-		soc_litedramcore_inti_p3_we_n = 1'd1;
+		soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_cas_n = 1'd1;
+	soc_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_cas_n = (~soc_litedramcore_phaseinjector3_command_storage[2]);
+		soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
 	end else begin
-		soc_litedramcore_inti_p3_cas_n = 1'd1;
+		soc_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_cs_n = 1'd1;
+	soc_litedramcore_inti_p3_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_cs_n = {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
+		soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
-		soc_litedramcore_inti_p3_cs_n = {1{1'd1}};
+		soc_litedramcore_inti_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_ras_n = 1'd1;
+	soc_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_ras_n = (~soc_litedramcore_phaseinjector3_command_storage[3]);
+		soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
 	end else begin
-		soc_litedramcore_inti_p3_ras_n = 1'd1;
+		soc_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
 end
 assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage;
@@ -4521,43 +4436,43 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 =
 assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
 assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
 always @(*) begin
-	refresher_next_state = 2'd0;
-	refresher_next_state = refresher_state;
+	refresher_next_state <= 2'd0;
+	refresher_next_state <= refresher_state;
 	case (refresher_state)
 		1'd1: begin
 			if (soc_litedramcore_cmd_ready) begin
-				refresher_next_state = 2'd2;
+				refresher_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (soc_litedramcore_sequencer_done0) begin
 				if (soc_litedramcore_wants_zqcs) begin
-					refresher_next_state = 2'd3;
+					refresher_next_state <= 2'd3;
 				end else begin
-					refresher_next_state = 1'd0;
+					refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_zqcs_executer_done) begin
-				refresher_next_state = 1'd0;
+				refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
 				if (soc_litedramcore_wants_refresh) begin
-					refresher_next_state = 1'd1;
+					refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_sequencer_start0 = 1'd0;
+	soc_litedramcore_sequencer_start0 <= 1'd0;
 	case (refresher_state)
 		1'd1: begin
 			if (soc_litedramcore_cmd_ready) begin
-				soc_litedramcore_sequencer_start0 = 1'd1;
+				soc_litedramcore_sequencer_start0 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4569,24 +4484,24 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_cmd_valid = 1'd0;
+	soc_litedramcore_cmd_valid <= 1'd0;
 	case (refresher_state)
 		1'd1: begin
-			soc_litedramcore_cmd_valid = 1'd1;
+			soc_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_cmd_valid = 1'd1;
+			soc_litedramcore_cmd_valid <= 1'd1;
 			if (soc_litedramcore_sequencer_done0) begin
 				if (soc_litedramcore_wants_zqcs) begin
 				end else begin
-					soc_litedramcore_cmd_valid = 1'd0;
+					soc_litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			soc_litedramcore_cmd_valid = 1'd1;
+			soc_litedramcore_cmd_valid <= 1'd1;
 			if (soc_litedramcore_zqcs_executer_done) begin
-				soc_litedramcore_cmd_valid = 1'd0;
+				soc_litedramcore_cmd_valid <= 1'd0;
 			end
 		end
 		default: begin
@@ -4594,14 +4509,14 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_zqcs_executer_start = 1'd0;
+	soc_litedramcore_zqcs_executer_start <= 1'd0;
 	case (refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
 			if (soc_litedramcore_sequencer_done0) begin
 				if (soc_litedramcore_wants_zqcs) begin
-					soc_litedramcore_zqcs_executer_start = 1'd1;
+					soc_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
 				end
 			end
@@ -4613,7 +4528,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_cmd_last = 1'd0;
+	soc_litedramcore_cmd_last <= 1'd0;
 	case (refresher_state)
 		1'd1: begin
 		end
@@ -4621,13 +4536,13 @@ always @(*) begin
 			if (soc_litedramcore_sequencer_done0) begin
 				if (soc_litedramcore_wants_zqcs) begin
 				end else begin
-					soc_litedramcore_cmd_last = 1'd1;
+					soc_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_zqcs_executer_done) begin
-				soc_litedramcore_cmd_last = 1'd1;
+				soc_litedramcore_cmd_last <= 1'd1;
 			end
 		end
 		default: begin
@@ -4649,21 +4564,21 @@ assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_c
 assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
 assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine0_cmd_payload_a = soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine0_cmd_payload_a = ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
 assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine0_auto_precharge = (soc_litedramcore_bankmachine0_row_close == 1'd0);
+			soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
 end
@@ -4685,11 +4600,11 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
@@ -4701,60 +4616,60 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine0_next_state = 4'd0;
-	bankmachine0_next_state = bankmachine0_state;
+	bankmachine0_next_state <= 4'd0;
+	bankmachine0_next_state <= bankmachine0_state;
 	case (bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine0_cmd_ready) begin
-					bankmachine0_next_state = 3'd5;
+					bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				bankmachine0_next_state = 3'd5;
+				bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine0_trccon_ready) begin
 				if (soc_litedramcore_bankmachine0_cmd_ready) begin
-					bankmachine0_next_state = 3'd7;
+					bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
-				bankmachine0_next_state = 1'd0;
+				bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine0_next_state = 3'd6;
+			bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine0_next_state = 2'd3;
+			bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine0_next_state = 4'd8;
+			bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine0_next_state = 1'd0;
+			bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine0_refresh_req) begin
-				bankmachine0_next_state = 3'd4;
+				bankmachine0_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
 							if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
-								bankmachine0_next_state = 2'd2;
+								bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine0_next_state = 1'd1;
+							bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine0_next_state = 2'd3;
+						bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4762,12 +4677,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -4789,10 +4701,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
-							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1;
-							end else begin
-							end
+							soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4803,15 +4712,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+				soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4829,22 +4741,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
-			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4855,17 +4763,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine0_row_opened) begin
+						if (soc_litedramcore_bankmachine0_row_hit) begin
+							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -4878,34 +4804,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine0_row_opened) begin
-						if (soc_litedramcore_bankmachine0_row_hit) begin
-							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+				soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4916,26 +4834,11 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine0_row_opened) begin
-						if (soc_litedramcore_bankmachine0_row_hit) begin
-							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
@@ -4960,8 +4863,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
 							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine0_req_wdata_ready = soc_litedramcore_bankmachine0_cmd_ready;
 							end else begin
+								soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4973,7 +4876,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
@@ -4998,8 +4901,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
 							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
-								soc_litedramcore_bankmachine0_req_rdata_valid = soc_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -5011,7 +4914,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
@@ -5020,9 +4923,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
-				soc_litedramcore_bankmachine0_refresh_gnt = 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5033,23 +4933,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine0_row_opened) begin
+						if (soc_litedramcore_bankmachine0_row_hit) begin
+							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -5067,7 +4976,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
-							soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
+							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -5078,18 +4990,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_row_open = 1'd0;
+	soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_row_open = 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+				soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -5104,18 +5016,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_row_close = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine0_row_close = 1'd1;
+			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine0_row_close = 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine0_row_close = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5126,17 +5041,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine0_row_opened) begin
+						if (soc_litedramcore_bankmachine0_row_hit) begin
+							soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+	soc_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5149,37 +5079,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine0_row_opened) begin
-						if (soc_litedramcore_bankmachine0_row_hit) begin
-							soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+	soc_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (bankmachine0_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
-			end
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
-			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5208,21 +5123,21 @@ assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_c
 assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
 assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine1_cmd_payload_a = soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine1_cmd_payload_a = ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
 assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine1_auto_precharge = (soc_litedramcore_bankmachine1_row_close == 1'd0);
+			soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
 end
@@ -5244,11 +5159,11 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
@@ -5260,60 +5175,95 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine1_next_state = 4'd0;
-	bankmachine1_next_state = bankmachine1_state;
+	bankmachine1_next_state <= 4'd0;
+	bankmachine1_next_state <= bankmachine1_state;
 	case (bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine1_cmd_ready) begin
-					bankmachine1_next_state = 3'd5;
+					bankmachine1_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				bankmachine1_next_state = 3'd5;
+				bankmachine1_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
 				if (soc_litedramcore_bankmachine1_cmd_ready) begin
-					bankmachine1_next_state = 3'd7;
+					bankmachine1_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
-				bankmachine1_next_state = 1'd0;
+				bankmachine1_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine1_next_state = 3'd6;
+			bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine1_next_state = 2'd3;
+			bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine1_next_state = 4'd8;
+			bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine1_next_state = 1'd0;
+			bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine1_refresh_req) begin
-				bankmachine1_next_state = 3'd4;
+				bankmachine1_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
-								bankmachine1_next_state = 2'd2;
+								bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine1_next_state = 1'd1;
+							bankmachine1_next_state <= 1'd1;
+						end
+					end else begin
+						bankmachine1_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (soc_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine1_row_opened) begin
+						if (soc_litedramcore_bankmachine1_row_hit) begin
+							soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+						end else begin
 						end
 					end else begin
-						bankmachine1_next_state = 2'd3;
 					end
 				end
 			end
@@ -5321,11 +5271,40 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (bankmachine1_state)
+		1'd1: begin
+			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+				soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine1_trccon_ready) begin
+				soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1;
+				soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5349,7 +5328,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1;
+								soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5362,7 +5341,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5370,7 +5349,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5388,22 +5367,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+			soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5418,7 +5397,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5444,7 +5423,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
+								soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5456,7 +5435,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5481,7 +5460,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
+								soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5494,7 +5473,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5519,7 +5498,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine1_req_wdata_ready = soc_litedramcore_bankmachine1_cmd_ready;
+								soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5532,7 +5511,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5558,7 +5537,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine1_req_rdata_valid = soc_litedramcore_bankmachine1_cmd_ready;
+								soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -5570,7 +5549,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5580,7 +5559,7 @@ always @(*) begin
 		end
 		3'd4: begin
 			if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
-				soc_litedramcore_bankmachine1_refresh_gnt = 1'd1;
+				soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -5596,18 +5575,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5626,7 +5605,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
-							soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
+							soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5637,7 +5616,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_row_open = 1'd0;
+	soc_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
 		end
@@ -5645,7 +5624,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_row_open = 1'd1;
+				soc_litedramcore_bankmachine1_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5663,18 +5642,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_row_close = 1'd0;
+	soc_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (bankmachine1_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine1_row_close = 1'd1;
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine1_row_close = 1'd1;
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine1_row_close = 1'd1;
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5688,100 +5667,36 @@ always @(*) begin
 		end
 	endcase
 end
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
+assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
+assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-	case (bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine1_row_opened) begin
-						if (soc_litedramcore_bankmachine1_row_hit) begin
-							soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-	case (bankmachine1_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
-assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
-assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-	if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine2_cmd_payload_a = soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_litedramcore_bankmachine2_cmd_payload_a = ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
-assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
-assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
-	if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine2_auto_precharge = (soc_litedramcore_bankmachine2_row_close == 1'd0);
+	soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+	if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
+assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
+always @(*) begin
+	soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+			soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
 end
@@ -5803,11 +5718,11 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
@@ -5819,60 +5734,60 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine2_next_state = 4'd0;
-	bankmachine2_next_state = bankmachine2_state;
+	bankmachine2_next_state <= 4'd0;
+	bankmachine2_next_state <= bankmachine2_state;
 	case (bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine2_cmd_ready) begin
-					bankmachine2_next_state = 3'd5;
+					bankmachine2_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				bankmachine2_next_state = 3'd5;
+				bankmachine2_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine2_trccon_ready) begin
 				if (soc_litedramcore_bankmachine2_cmd_ready) begin
-					bankmachine2_next_state = 3'd7;
+					bankmachine2_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
-				bankmachine2_next_state = 1'd0;
+				bankmachine2_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine2_next_state = 3'd6;
+			bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine2_next_state = 2'd3;
+			bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine2_next_state = 4'd8;
+			bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine2_next_state = 1'd0;
+			bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine2_refresh_req) begin
-				bankmachine2_next_state = 3'd4;
+				bankmachine2_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
 							if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
-								bankmachine2_next_state = 2'd2;
+								bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine2_next_state = 1'd1;
+							bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine2_next_state = 2'd3;
+						bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5880,12 +5795,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -5907,10 +5819,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
-							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1;
-							end else begin
-							end
+							soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5921,15 +5830,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+				soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5947,22 +5859,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
-			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5973,17 +5881,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine2_row_opened) begin
+						if (soc_litedramcore_bankmachine2_row_hit) begin
+							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5996,34 +5922,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine2_row_opened) begin
-						if (soc_litedramcore_bankmachine2_row_hit) begin
-							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+				soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6034,26 +5952,11 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine2_row_opened) begin
-						if (soc_litedramcore_bankmachine2_row_hit) begin
-							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
@@ -6078,8 +5981,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
 							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine2_req_wdata_ready = soc_litedramcore_bankmachine2_cmd_ready;
 							end else begin
+								soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6091,7 +5994,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
@@ -6116,8 +6019,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
 							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
-								soc_litedramcore_bankmachine2_req_rdata_valid = soc_litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
 						end
@@ -6129,7 +6032,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
@@ -6138,9 +6041,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
-				soc_litedramcore_bankmachine2_refresh_gnt = 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6151,23 +6051,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine2_row_opened) begin
+						if (soc_litedramcore_bankmachine2_row_hit) begin
+							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6185,7 +6094,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
-							soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
+							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -6196,18 +6108,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_row_open = 1'd0;
+	soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_row_open = 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+				soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6222,18 +6134,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_row_close = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine2_row_close = 1'd1;
+			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine2_row_close = 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine2_row_close = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6244,17 +6159,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine2_row_opened) begin
+						if (soc_litedramcore_bankmachine2_row_hit) begin
+							soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+	soc_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6267,37 +6197,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine2_row_opened) begin
-						if (soc_litedramcore_bankmachine2_row_hit) begin
-							soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+	soc_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (bankmachine2_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
-			end
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
-			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6326,21 +6241,21 @@ assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_c
 assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
 assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine3_cmd_payload_a = soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine3_cmd_payload_a = ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
 assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine3_auto_precharge = (soc_litedramcore_bankmachine3_row_close == 1'd0);
+			soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
 end
@@ -6362,11 +6277,11 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
@@ -6378,60 +6293,95 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine3_next_state = 4'd0;
-	bankmachine3_next_state = bankmachine3_state;
+	bankmachine3_next_state <= 4'd0;
+	bankmachine3_next_state <= bankmachine3_state;
 	case (bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine3_cmd_ready) begin
-					bankmachine3_next_state = 3'd5;
+					bankmachine3_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				bankmachine3_next_state = 3'd5;
+				bankmachine3_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
 				if (soc_litedramcore_bankmachine3_cmd_ready) begin
-					bankmachine3_next_state = 3'd7;
+					bankmachine3_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
-				bankmachine3_next_state = 1'd0;
+				bankmachine3_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine3_next_state = 3'd6;
+			bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine3_next_state = 2'd3;
+			bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine3_next_state = 4'd8;
+			bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine3_next_state = 1'd0;
+			bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine3_refresh_req) begin
-				bankmachine3_next_state = 3'd4;
+				bankmachine3_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
-								bankmachine3_next_state = 2'd2;
+								bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine3_next_state = 1'd1;
+							bankmachine3_next_state <= 1'd1;
+						end
+					end else begin
+						bankmachine3_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (soc_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine3_row_opened) begin
+						if (soc_litedramcore_bankmachine3_row_hit) begin
+							soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+						end else begin
 						end
 					end else begin
-						bankmachine3_next_state = 2'd3;
 					end
 				end
 			end
@@ -6439,11 +6389,40 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (bankmachine3_state)
+		1'd1: begin
+			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+				soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine3_trccon_ready) begin
+				soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+				soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6467,7 +6446,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+								soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6480,7 +6459,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6488,7 +6467,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6506,22 +6485,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+			soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6536,7 +6515,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6562,7 +6541,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
+								soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6574,7 +6553,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6599,7 +6578,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
+								soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6612,7 +6591,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6637,7 +6616,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine3_req_wdata_ready = soc_litedramcore_bankmachine3_cmd_ready;
+								soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6650,7 +6629,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6676,7 +6655,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine3_req_rdata_valid = soc_litedramcore_bankmachine3_cmd_ready;
+								soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -6688,7 +6667,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6698,7 +6677,7 @@ always @(*) begin
 		end
 		3'd4: begin
 			if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
-				soc_litedramcore_bankmachine3_refresh_gnt = 1'd1;
+				soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6714,18 +6693,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6744,7 +6723,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
-							soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
+							soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6755,7 +6734,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_row_open = 1'd0;
+	soc_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
 		end
@@ -6763,7 +6742,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_row_open = 1'd1;
+				soc_litedramcore_bankmachine3_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6781,18 +6760,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_row_close = 1'd0;
+	soc_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (bankmachine3_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine3_row_close = 1'd1;
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine3_row_close = 1'd1;
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine3_row_close = 1'd1;
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6806,100 +6785,36 @@ always @(*) begin
 		end
 	endcase
 end
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
+assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
+assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-	case (bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine3_row_opened) begin
-						if (soc_litedramcore_bankmachine3_row_hit) begin
-							soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-	case (bankmachine3_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
-assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
-assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine4_cmd_payload_a = soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine4_cmd_payload_a = ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
 assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine4_auto_precharge = (soc_litedramcore_bankmachine4_row_close == 1'd0);
+			soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
 end
@@ -6921,11 +6836,11 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
@@ -6937,60 +6852,60 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine4_next_state = 4'd0;
-	bankmachine4_next_state = bankmachine4_state;
+	bankmachine4_next_state <= 4'd0;
+	bankmachine4_next_state <= bankmachine4_state;
 	case (bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine4_cmd_ready) begin
-					bankmachine4_next_state = 3'd5;
+					bankmachine4_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				bankmachine4_next_state = 3'd5;
+				bankmachine4_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine4_trccon_ready) begin
 				if (soc_litedramcore_bankmachine4_cmd_ready) begin
-					bankmachine4_next_state = 3'd7;
+					bankmachine4_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
-				bankmachine4_next_state = 1'd0;
+				bankmachine4_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine4_next_state = 3'd6;
+			bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine4_next_state = 2'd3;
+			bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine4_next_state = 4'd8;
+			bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine4_next_state = 1'd0;
+			bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine4_refresh_req) begin
-				bankmachine4_next_state = 3'd4;
+				bankmachine4_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
 							if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
-								bankmachine4_next_state = 2'd2;
+								bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine4_next_state = 1'd1;
+							bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine4_next_state = 2'd3;
+						bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6998,12 +6913,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -7025,10 +6937,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
-							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1;
-							end else begin
-							end
+							soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7039,15 +6948,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+				soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7065,22 +6977,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
-			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7091,17 +6999,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine4_row_opened) begin
+						if (soc_litedramcore_bankmachine4_row_hit) begin
+							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7114,34 +7040,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine4_row_opened) begin
-						if (soc_litedramcore_bankmachine4_row_hit) begin
-							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+				soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7152,26 +7070,11 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine4_row_opened) begin
-						if (soc_litedramcore_bankmachine4_row_hit) begin
-							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
@@ -7196,8 +7099,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
 							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine4_req_wdata_ready = soc_litedramcore_bankmachine4_cmd_ready;
 							end else begin
+								soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7209,7 +7112,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
@@ -7234,8 +7137,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
 							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
-								soc_litedramcore_bankmachine4_req_rdata_valid = soc_litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -7247,7 +7150,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
@@ -7256,9 +7159,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
-				soc_litedramcore_bankmachine4_refresh_gnt = 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7269,23 +7169,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine4_row_opened) begin
+						if (soc_litedramcore_bankmachine4_row_hit) begin
+							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7303,7 +7212,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
-							soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
+							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -7314,18 +7226,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_row_open = 1'd0;
+	soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_row_open = 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+				soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7340,18 +7252,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_row_close = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine4_row_close = 1'd1;
+			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine4_row_close = 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine4_row_close = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7362,17 +7277,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine4_row_opened) begin
+						if (soc_litedramcore_bankmachine4_row_hit) begin
+							soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+	soc_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7385,37 +7315,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine4_row_opened) begin
-						if (soc_litedramcore_bankmachine4_row_hit) begin
-							soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+	soc_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (bankmachine4_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
-			end
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
-			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7444,21 +7359,21 @@ assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_c
 assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
 assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine5_cmd_payload_a = soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine5_cmd_payload_a = ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
 assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine5_auto_precharge = (soc_litedramcore_bankmachine5_row_close == 1'd0);
+			soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
 end
@@ -7480,11 +7395,11 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
@@ -7496,60 +7411,95 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine5_next_state = 4'd0;
-	bankmachine5_next_state = bankmachine5_state;
+	bankmachine5_next_state <= 4'd0;
+	bankmachine5_next_state <= bankmachine5_state;
 	case (bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine5_cmd_ready) begin
-					bankmachine5_next_state = 3'd5;
+					bankmachine5_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				bankmachine5_next_state = 3'd5;
+				bankmachine5_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
 				if (soc_litedramcore_bankmachine5_cmd_ready) begin
-					bankmachine5_next_state = 3'd7;
+					bankmachine5_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
-				bankmachine5_next_state = 1'd0;
+				bankmachine5_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine5_next_state = 3'd6;
+			bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine5_next_state = 2'd3;
+			bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine5_next_state = 4'd8;
+			bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine5_next_state = 1'd0;
+			bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine5_refresh_req) begin
-				bankmachine5_next_state = 3'd4;
+				bankmachine5_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
-								bankmachine5_next_state = 2'd2;
+								bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine5_next_state = 1'd1;
+							bankmachine5_next_state <= 1'd1;
+						end
+					end else begin
+						bankmachine5_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (soc_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine5_row_opened) begin
+						if (soc_litedramcore_bankmachine5_row_hit) begin
+							soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+						end else begin
 						end
 					end else begin
-						bankmachine5_next_state = 2'd3;
 					end
 				end
 			end
@@ -7557,11 +7507,40 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (bankmachine5_state)
+		1'd1: begin
+			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+				soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine5_trccon_ready) begin
+				soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1;
+				soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7585,7 +7564,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1;
+								soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7598,7 +7577,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7606,7 +7585,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7624,22 +7603,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+			soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7654,7 +7633,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7680,7 +7659,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
+								soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7692,7 +7671,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7717,7 +7696,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
+								soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7730,7 +7709,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7755,7 +7734,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine5_req_wdata_ready = soc_litedramcore_bankmachine5_cmd_ready;
+								soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -7768,7 +7747,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7794,7 +7773,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine5_req_rdata_valid = soc_litedramcore_bankmachine5_cmd_ready;
+								soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
 							end
 						end else begin
 						end
@@ -7806,7 +7785,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7816,7 +7795,7 @@ always @(*) begin
 		end
 		3'd4: begin
 			if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
-				soc_litedramcore_bankmachine5_refresh_gnt = 1'd1;
+				soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -7832,18 +7811,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7862,7 +7841,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
-							soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
+							soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7873,7 +7852,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_row_open = 1'd0;
+	soc_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
 		end
@@ -7881,7 +7860,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_row_open = 1'd1;
+				soc_litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7899,18 +7878,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_row_close = 1'd0;
+	soc_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (bankmachine5_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine5_row_close = 1'd1;
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine5_row_close = 1'd1;
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine5_row_close = 1'd1;
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7924,100 +7903,36 @@ always @(*) begin
 		end
 	endcase
 end
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
+assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
+assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-	case (bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine5_row_opened) begin
-						if (soc_litedramcore_bankmachine5_row_hit) begin
-							soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-	case (bankmachine5_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
-assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
-assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine6_cmd_payload_a = soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine6_cmd_payload_a = ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
 assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine6_auto_precharge = (soc_litedramcore_bankmachine6_row_close == 1'd0);
+			soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
 end
@@ -8039,11 +7954,11 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
@@ -8055,60 +7970,60 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine6_next_state = 4'd0;
-	bankmachine6_next_state = bankmachine6_state;
+	bankmachine6_next_state <= 4'd0;
+	bankmachine6_next_state <= bankmachine6_state;
 	case (bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine6_cmd_ready) begin
-					bankmachine6_next_state = 3'd5;
+					bankmachine6_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				bankmachine6_next_state = 3'd5;
+				bankmachine6_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine6_trccon_ready) begin
 				if (soc_litedramcore_bankmachine6_cmd_ready) begin
-					bankmachine6_next_state = 3'd7;
+					bankmachine6_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
-				bankmachine6_next_state = 1'd0;
+				bankmachine6_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine6_next_state = 3'd6;
+			bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine6_next_state = 2'd3;
+			bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine6_next_state = 4'd8;
+			bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine6_next_state = 1'd0;
+			bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine6_refresh_req) begin
-				bankmachine6_next_state = 3'd4;
+				bankmachine6_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
 							if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
-								bankmachine6_next_state = 2'd2;
+								bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine6_next_state = 1'd1;
+							bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine6_next_state = 2'd3;
+						bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8116,12 +8031,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8143,10 +8055,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
-							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1;
-							end else begin
-							end
+							soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8157,15 +8066,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+				soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8183,22 +8095,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
-			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8209,17 +8117,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine6_row_opened) begin
+						if (soc_litedramcore_bankmachine6_row_hit) begin
+							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8232,34 +8158,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine6_row_opened) begin
-						if (soc_litedramcore_bankmachine6_row_hit) begin
-							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
+			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+				soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8270,26 +8188,11 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine6_row_opened) begin
-						if (soc_litedramcore_bankmachine6_row_hit) begin
-							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
@@ -8314,8 +8217,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
 							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine6_req_wdata_ready = soc_litedramcore_bankmachine6_cmd_ready;
 							end else begin
+								soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8327,7 +8230,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
@@ -8352,8 +8255,8 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
 							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
-								soc_litedramcore_bankmachine6_req_rdata_valid = soc_litedramcore_bankmachine6_cmd_ready;
 							end
 						end else begin
 						end
@@ -8365,7 +8268,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
@@ -8374,9 +8277,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
-				soc_litedramcore_bankmachine6_refresh_gnt = 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8387,23 +8287,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine6_row_opened) begin
+						if (soc_litedramcore_bankmachine6_row_hit) begin
+							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8421,7 +8330,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
-							soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
+							if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -8432,18 +8344,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_row_open = 1'd0;
+	soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_row_open = 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
+				soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8458,18 +8370,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_row_close = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine6_row_close = 1'd1;
+			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine6_row_close = 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine6_row_close = 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8480,17 +8395,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine6_row_opened) begin
+						if (soc_litedramcore_bankmachine6_row_hit) begin
+							soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+	soc_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8503,37 +8433,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (soc_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine6_row_opened) begin
-						if (soc_litedramcore_bankmachine6_row_hit) begin
-							soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+	soc_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (bankmachine6_state)
 		1'd1: begin
-			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
-			end
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
-			end
 		end
 		3'd4: begin
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8562,21 +8477,21 @@ assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_c
 assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
 assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+	soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
 	if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		soc_litedramcore_bankmachine7_cmd_payload_a = soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+		soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		soc_litedramcore_bankmachine7_cmd_payload_a = ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
 assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
 assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
 assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
 always @(*) begin
-	soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
+	soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
 		if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_litedramcore_bankmachine7_auto_precharge = (soc_litedramcore_bankmachine7_row_close == 1'd0);
+			soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
 end
@@ -8598,11 +8513,11 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = so
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+	soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+		soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+		soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
 end
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
@@ -8614,60 +8529,95 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine7_next_state = 4'd0;
-	bankmachine7_next_state = bankmachine7_state;
+	bankmachine7_next_state <= 4'd0;
+	bankmachine7_next_state <= bankmachine7_state;
 	case (bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine7_cmd_ready) begin
-					bankmachine7_next_state = 3'd5;
+					bankmachine7_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				bankmachine7_next_state = 3'd5;
+				bankmachine7_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
 				if (soc_litedramcore_bankmachine7_cmd_ready) begin
-					bankmachine7_next_state = 3'd7;
+					bankmachine7_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
-				bankmachine7_next_state = 1'd0;
+				bankmachine7_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine7_next_state = 3'd6;
+			bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine7_next_state = 2'd3;
+			bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine7_next_state = 4'd8;
+			bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine7_next_state = 1'd0;
+			bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine7_refresh_req) begin
-				bankmachine7_next_state = 3'd4;
+				bankmachine7_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
-								bankmachine7_next_state = 2'd2;
+								bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine7_next_state = 1'd1;
+							bankmachine7_next_state <= 1'd1;
+						end
+					end else begin
+						bankmachine7_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (soc_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine7_row_opened) begin
+						if (soc_litedramcore_bankmachine7_row_hit) begin
+							soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+						end else begin
 						end
 					end else begin
-						bankmachine7_next_state = 2'd3;
 					end
 				end
 			end
@@ -8675,11 +8625,40 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (bankmachine7_state)
+		1'd1: begin
+			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+				soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine7_trccon_ready) begin
+				soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+				soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -8703,7 +8682,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+								soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8716,7 +8695,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+	soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8724,7 +8703,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
+				soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8742,22 +8721,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+				soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+			soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8772,7 +8751,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8798,7 +8777,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
+								soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8810,7 +8789,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8835,7 +8814,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
+								soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8848,7 +8827,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+	soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8873,7 +8852,7 @@ always @(*) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								soc_litedramcore_bankmachine7_req_wdata_ready = soc_litedramcore_bankmachine7_cmd_ready;
+								soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -8886,7 +8865,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+	soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8912,7 +8891,7 @@ always @(*) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								soc_litedramcore_bankmachine7_req_rdata_valid = soc_litedramcore_bankmachine7_cmd_ready;
+								soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -8924,7 +8903,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+	soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8934,7 +8913,7 @@ always @(*) begin
 		end
 		3'd4: begin
 			if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
-				soc_litedramcore_bankmachine7_refresh_gnt = 1'd1;
+				soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -8950,18 +8929,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
+				soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8980,7 +8959,7 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
-							soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
+							soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8991,7 +8970,7 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_row_open = 1'd0;
+	soc_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
 		end
@@ -8999,7 +8978,7 @@ always @(*) begin
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_row_open = 1'd1;
+				soc_litedramcore_bankmachine7_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9017,82 +8996,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_row_close = 1'd0;
+	soc_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (bankmachine7_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine7_row_close = 1'd1;
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine7_row_close = 1'd1;
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine7_row_close = 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-	case (bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine7_row_opened) begin
-						if (soc_litedramcore_bankmachine7_row_hit) begin
-							soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-	case (bankmachine7_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
-			end
-		end
-		3'd4: begin
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9135,15 +9050,15 @@ assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask
 assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
 assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
 always @(*) begin
-	soc_litedramcore_choose_cmd_valids = 8'd0;
-	soc_litedramcore_choose_cmd_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
-	soc_litedramcore_choose_cmd_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids <= 8'd0;
+	soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+	soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
 end
 assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
 assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
@@ -9153,106 +9068,106 @@ assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
 assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
 assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+	soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (soc_litedramcore_choose_cmd_cmd_valid) begin
-		soc_litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0;
+		soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+	soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (soc_litedramcore_choose_cmd_cmd_valid) begin
-		soc_litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1;
+		soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+	soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (soc_litedramcore_choose_cmd_cmd_valid) begin
-		soc_litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2;
+		soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
-		soc_litedramcore_bankmachine0_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
-		soc_litedramcore_bankmachine0_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
-		soc_litedramcore_bankmachine1_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
-		soc_litedramcore_bankmachine1_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
-		soc_litedramcore_bankmachine2_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
-		soc_litedramcore_bankmachine2_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
-		soc_litedramcore_bankmachine3_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
-		soc_litedramcore_bankmachine3_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
-		soc_litedramcore_bankmachine4_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
-		soc_litedramcore_bankmachine4_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
-		soc_litedramcore_bankmachine5_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
-		soc_litedramcore_bankmachine5_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
-		soc_litedramcore_bankmachine6_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
-		soc_litedramcore_bankmachine6_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+	soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
-		soc_litedramcore_bankmachine7_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 	if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
-		soc_litedramcore_bankmachine7_cmd_ready = 1'd1;
+		soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
 assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	soc_litedramcore_choose_req_valids = 8'd0;
-	soc_litedramcore_choose_req_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
-	soc_litedramcore_choose_req_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids <= 8'd0;
+	soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+	soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
 end
 assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
 assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
@@ -9262,21 +9177,21 @@ assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
 assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
 assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+	soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (soc_litedramcore_choose_req_cmd_valid) begin
-		soc_litedramcore_choose_req_cmd_payload_cas = t_array_muxed3;
+		soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+	soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (soc_litedramcore_choose_req_cmd_valid) begin
-		soc_litedramcore_choose_req_cmd_payload_ras = t_array_muxed4;
+		soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+	soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (soc_litedramcore_choose_req_cmd_valid) begin
-		soc_litedramcore_choose_req_cmd_payload_we = t_array_muxed5;
+		soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
 assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
@@ -9294,76 +9209,69 @@ assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
 assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
 assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
 always @(*) begin
-	multiplexer_next_state = 4'd0;
-	multiplexer_next_state = multiplexer_state;
+	multiplexer_next_state <= 4'd0;
+	multiplexer_next_state <= multiplexer_state;
 	case (multiplexer_state)
 		1'd1: begin
 			if (soc_litedramcore_read_available) begin
 				if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
-					multiplexer_next_state = 2'd3;
+					multiplexer_next_state <= 2'd3;
 				end
 			end
 			if (soc_litedramcore_go_to_refresh) begin
-				multiplexer_next_state = 2'd2;
+				multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (soc_litedramcore_cmd_last) begin
-				multiplexer_next_state = 1'd0;
+				multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_twtrcon_ready) begin
-				multiplexer_next_state = 1'd0;
+				multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			multiplexer_next_state = 3'd5;
+			multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			multiplexer_next_state = 3'd6;
+			multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			multiplexer_next_state = 3'd7;
+			multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			multiplexer_next_state = 4'd8;
+			multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			multiplexer_next_state = 4'd9;
+			multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			multiplexer_next_state = 4'd10;
+			multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			multiplexer_next_state = 1'd1;
+			multiplexer_next_state <= 1'd1;
 		end
 		default: begin
 			if (soc_litedramcore_write_available) begin
 				if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
-					multiplexer_next_state = 3'd4;
+					multiplexer_next_state <= 3'd4;
 				end
 			end
 			if (soc_litedramcore_go_to_refresh) begin
-				multiplexer_next_state = 2'd2;
+				multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_steerer_sel0 = 2'd0;
+	soc_litedramcore_en1 <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_steerer_sel0 = 1'd0;
-			if (1'd0) begin
-				soc_litedramcore_steerer_sel0 = 2'd2;
-			end
-			if (1'd0) begin
-				soc_litedramcore_steerer_sel0 = 1'd1;
-			end
+			soc_litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
-			soc_litedramcore_steerer_sel0 = 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9382,29 +9290,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_steerer_sel0 = 1'd0;
-			if (1'd0) begin
-				soc_litedramcore_steerer_sel0 = 2'd2;
-			end
-			if (1'd0) begin
-				soc_litedramcore_steerer_sel0 = 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_steerer_sel1 = 2'd0;
+	soc_litedramcore_steerer_sel0 <= 2'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_steerer_sel1 = 1'd0;
+			soc_litedramcore_steerer_sel0 <= 1'd0;
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel1 = 2'd2;
+				soc_litedramcore_steerer_sel0 <= 2'd2;
 			end
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel1 = 1'd1;
+				soc_litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
+			soc_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9423,26 +9325,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_steerer_sel1 = 1'd0;
+			soc_litedramcore_steerer_sel0 <= 1'd0;
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel1 = 2'd2;
+				soc_litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if (1'd1) begin
-				soc_litedramcore_steerer_sel1 = 1'd1;
+			if (1'd0) begin
+				soc_litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_steerer_sel2 = 2'd0;
+	soc_litedramcore_steerer_sel1 <= 2'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_steerer_sel2 = 1'd0;
+			soc_litedramcore_steerer_sel1 <= 1'd0;
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel2 = 2'd2;
+				soc_litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if (1'd1) begin
-				soc_litedramcore_steerer_sel2 = 1'd1;
+			if (1'd0) begin
+				soc_litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9464,23 +9366,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_steerer_sel2 = 1'd0;
-			if (1'd1) begin
-				soc_litedramcore_steerer_sel2 = 2'd2;
-			end
+			soc_litedramcore_steerer_sel1 <= 1'd0;
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel2 = 1'd1;
+				soc_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if (1'd1) begin
+				soc_litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_cmd_want_activates = 1'd0;
+	soc_litedramcore_steerer_sel2 <= 2'd0;
 	case (multiplexer_state)
 		1'd1: begin
+			soc_litedramcore_steerer_sel2 <= 1'd0;
 			if (1'd0) begin
-			end else begin
-				soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed;
+				soc_litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if (1'd1) begin
+				soc_litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9502,23 +9407,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			soc_litedramcore_steerer_sel2 <= 1'd0;
+			if (1'd1) begin
+				soc_litedramcore_steerer_sel2 <= 2'd2;
+			end
 			if (1'd0) begin
-			end else begin
-				soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed;
+				soc_litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_steerer_sel3 = 2'd0;
+	soc_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_steerer_sel3 = 1'd0;
-			if (1'd1) begin
-				soc_litedramcore_steerer_sel3 = 2'd2;
-			end
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel3 = 1'd1;
+			end else begin
+				soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
 			end
 		end
 		2'd2: begin
@@ -9540,20 +9445,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_steerer_sel3 = 1'd0;
-			if (1'd0) begin
-				soc_litedramcore_steerer_sel3 = 2'd2;
-			end
 			if (1'd0) begin
-				soc_litedramcore_steerer_sel3 = 1'd1;
+			end else begin
+				soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_en0 = 1'd0;
+	soc_litedramcore_steerer_sel3 <= 2'd0;
 	case (multiplexer_state)
 		1'd1: begin
+			soc_litedramcore_steerer_sel3 <= 1'd0;
+			if (1'd1) begin
+				soc_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if (1'd0) begin
+				soc_litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9574,17 +9483,22 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_en0 = 1'd1;
+			soc_litedramcore_steerer_sel3 <= 1'd0;
+			if (1'd0) begin
+				soc_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if (1'd0) begin
+				soc_litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_cmd_ready = 1'd0;
+	soc_litedramcore_en0 <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			soc_litedramcore_cmd_ready = 1'd1;
 		end
 		2'd3: begin
 		end
@@ -9603,19 +9517,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			soc_litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+	soc_litedramcore_cmd_ready <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
-			end
 		end
 		2'd2: begin
+			soc_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -9634,17 +9546,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
-			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_req_want_reads = 1'd0;
+	soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -9665,15 +9577,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			soc_litedramcore_choose_req_want_reads = 1'd1;
+			if (1'd0) begin
+			end else begin
+				soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+			end
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_req_want_writes = 1'd0;
+	soc_litedramcore_choose_req_want_reads <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_choose_req_want_writes = 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9694,14 +9608,15 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			soc_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_en1 = 1'd0;
+	soc_litedramcore_choose_req_want_writes <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_en1 = 1'd1;
+			soc_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9726,13 +9641,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_req_cmd_ready = 1'd0;
+	soc_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
-				soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
 			end else begin
-				soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed;
+				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
@@ -9755,9 +9670,9 @@ always @(*) begin
 		end
 		default: begin
 			if (1'd0) begin
-				soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
 			end else begin
-				soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed;
+				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
 			end
 		end
 	endcase
@@ -9806,24 +9721,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) &
 assign soc_user_port_wdata_ready = new_master_wdata_ready1;
 assign soc_user_port_rdata_valid = new_master_rdata_valid8;
 always @(*) begin
-	soc_litedramcore_interface_wdata = 128'd0;
+	soc_litedramcore_interface_wdata <= 128'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
+			soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata = 1'd0;
+			soc_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_interface_wdata_we = 16'd0;
+	soc_litedramcore_interface_wdata_we <= 16'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
+			soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata_we = 1'd0;
+			soc_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
@@ -9837,858 +9752,494 @@ assign roundrobin5_grant = 1'd0;
 assign roundrobin6_grant = 1'd0;
 assign roundrobin7_grant = 1'd0;
 always @(*) begin
-	next_state = 2'd0;
-	next_state = state;
+	next_state <= 2'd0;
+	next_state <= state;
 	case (state)
 		1'd1: begin
-			next_state = 2'd2;
+			next_state <= 2'd2;
 		end
 		2'd2: begin
-			next_state = 1'd0;
+			next_state <= 1'd0;
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				next_state = 1'd1;
+				next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value1 = 14'd0;
+	litedramcore_adr_next_value1 <= 14'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_adr_next_value1 = 1'd0;
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value_ce1 = 1'd0;
+	litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_adr_next_value_ce1 = 1'd1;
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value_ce1 = 1'd1;
+				litedramcore_adr_next_value_ce1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value2 = 1'd0;
+	litedramcore_wishbone_dat_r <= 32'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_we_next_value2 = 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value2 = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
-			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value_ce2 = 1'd0;
+	litedramcore_we_next_value2 <= 1'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_we_next_value_ce2 = 1'd1;
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value_ce2 = 1'd1;
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_dat_r = 32'd0;
-	case (state)
-		1'd1: begin
-		end
-		2'd2: begin
-			litedramcore_wishbone_dat_r = litedramcore_dat_r;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	litedramcore_dat_w_next_value0 = 8'd0;
-	case (state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		default: begin
-			litedramcore_dat_w_next_value0 = litedramcore_wishbone_dat_w;
-		end
-	endcase
-end
-always @(*) begin
-	litedramcore_dat_w_next_value_ce0 = 1'd0;
+	litedramcore_we_next_value_ce2 <= 1'd0;
 	case (state)
 		1'd1: begin
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
-		2'd2: begin
-		end
-		default: begin
-			litedramcore_dat_w_next_value_ce0 = 1'd1;
-		end
-	endcase
-end
-always @(*) begin
-	litedramcore_wishbone_ack = 1'd0;
-	case (state)
-		1'd1: begin
-		end
-		2'd2: begin
-			litedramcore_wishbone_ack = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign litedramcore_wishbone_adr = soc_wb_bus_adr;
-assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
-assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = soc_wb_bus_sel;
-assign litedramcore_wishbone_cyc = soc_wb_bus_cyc;
-assign litedramcore_wishbone_stb = soc_wb_bus_stb;
-assign soc_wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = soc_wb_bus_we;
-assign litedramcore_wishbone_cti = soc_wb_bus_cti;
-assign litedramcore_wishbone_bte = soc_wb_bus_bte;
-assign soc_wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd1);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-always @(*) begin
-	csrbank0_init_done0_we = 1'd0;
-	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank0_init_done0_we = (~interface0_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank0_init_done0_re = 1'd0;
-	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank0_init_done0_re = interface0_bank_bus_we;
-	end
-end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-always @(*) begin
-	csrbank0_init_error0_re = 1'd0;
-	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_re = interface0_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank0_init_error0_we = 1'd0;
-	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_we = (~interface0_bank_bus_we);
-	end
-end
-assign csrbank0_init_done0_w = soc_init_done_storage;
-assign csrbank0_init_error0_w = soc_init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
-assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
-always @(*) begin
-	csrbank1_dfii_control0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dfii_control0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_control0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dfii_control0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
-always @(*) begin
-	csrbank1_dfii_pi0_command0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_command0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
-	end
-end
-assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
-always @(*) begin
-	soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		soc_litedramcore_phaseinjector0_command_issue_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		soc_litedramcore_phaseinjector0_command_issue_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
-always @(*) begin
-	csrbank1_dfii_pi0_address1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		csrbank1_dfii_pi0_address1_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_address1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		csrbank1_dfii_pi0_address1_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_address0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		csrbank1_dfii_pi0_address0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_address0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		csrbank1_dfii_pi0_address0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
-always @(*) begin
-	csrbank1_dfii_pi0_baddress0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		csrbank1_dfii_pi0_baddress0_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_baddress0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		csrbank1_dfii_pi0_baddress0_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		csrbank1_dfii_pi0_wrdata2_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		csrbank1_dfii_pi0_wrdata2_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		csrbank1_dfii_pi0_wrdata1_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		csrbank1_dfii_pi0_wrdata1_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		csrbank1_dfii_pi0_wrdata0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_wrdata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		csrbank1_dfii_pi0_wrdata0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_rddata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_rddata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_rddata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		csrbank1_dfii_pi0_rddata2_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_rddata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		csrbank1_dfii_pi0_rddata2_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_rddata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_rddata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi0_rddata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank1_dfii_pi0_rddata0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi0_rddata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank1_dfii_pi0_rddata0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
-always @(*) begin
-	csrbank1_dfii_pi1_command0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_command0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
-	end
-end
-assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
-always @(*) begin
-	soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		soc_litedramcore_phaseinjector1_command_issue_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		soc_litedramcore_phaseinjector1_command_issue_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
-always @(*) begin
-	csrbank1_dfii_pi1_address1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank1_dfii_pi1_address1_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_address1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank1_dfii_pi1_address1_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_address0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		csrbank1_dfii_pi1_address0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_address0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		csrbank1_dfii_pi1_address0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
-always @(*) begin
-	csrbank1_dfii_pi1_baddress0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		csrbank1_dfii_pi1_baddress0_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_baddress0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		csrbank1_dfii_pi1_baddress0_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
-		csrbank1_dfii_pi1_wrdata2_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
-		csrbank1_dfii_pi1_wrdata2_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-		csrbank1_dfii_pi1_wrdata1_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-		csrbank1_dfii_pi1_wrdata1_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-		csrbank1_dfii_pi1_wrdata0_re = interface1_bank_bus_we;
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_wrdata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-		csrbank1_dfii_pi1_wrdata0_we = (~interface1_bank_bus_we);
-	end
-end
-assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_rddata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
-	end
-end
-always @(*) begin
-	csrbank1_dfii_pi1_rddata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
-	end
-end
-assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbank1_dfii_pi1_rddata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
-		csrbank1_dfii_pi1_rddata2_we = (~interface1_bank_bus_we);
-	end
+		2'd2: begin
+		end
+		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
+			end
+		end
+	endcase
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
-		csrbank1_dfii_pi1_rddata2_re = interface1_bank_bus_we;
-	end
+	litedramcore_wishbone_ack <= 1'd0;
+	case (state)
+		1'd1: begin
+		end
+		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
+		end
+		default: begin
+		end
+	endcase
 end
-assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
-	end
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		default: begin
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+		end
+	endcase
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
-	end
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		default: begin
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
+		end
+	endcase
 end
-assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign litedramcore_wishbone_adr = soc_wb_bus_adr;
+assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
+assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = soc_wb_bus_sel;
+assign litedramcore_wishbone_cyc = soc_wb_bus_cyc;
+assign litedramcore_wishbone_stb = soc_wb_bus_stb;
+assign soc_wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = soc_wb_bus_we;
+assign litedramcore_wishbone_cti = soc_wb_bus_cti;
+assign litedramcore_wishbone_bte = soc_wb_bus_bte;
+assign soc_wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin
-		csrbank1_dfii_pi1_rddata0_re = interface1_bank_bus_we;
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin
-		csrbank1_dfii_pi1_rddata0_we = (~interface1_bank_bus_we);
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi2_command0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_command0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
-assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = soc_init_done_storage;
+assign csrbank0_init_error0_w = soc_init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
+	csrbank1_dfii_control0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_control0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_dfii_control0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi2_address1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin
-		csrbank1_dfii_pi2_address1_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_address1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin
-		csrbank1_dfii_pi2_address1_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
+assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi2_address0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin
-		csrbank1_dfii_pi2_address0_re = interface1_bank_bus_we;
+	soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_address0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin
-		csrbank1_dfii_pi2_address0_we = (~interface1_bank_bus_we);
+	soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-	csrbank1_dfii_pi2_baddress0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin
-		csrbank1_dfii_pi2_baddress0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_baddress0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin
-		csrbank1_dfii_pi2_baddress0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin
-		csrbank1_dfii_pi2_wrdata2_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin
-		csrbank1_dfii_pi2_wrdata2_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin
-		csrbank1_dfii_pi2_wrdata1_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi0_rddata_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin
-		csrbank1_dfii_pi2_wrdata1_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi0_rddata_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin
-		csrbank1_dfii_pi2_wrdata0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin
-		csrbank1_dfii_pi2_wrdata0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
+	soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
+	soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin
-		csrbank1_dfii_pi2_rddata2_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin
-		csrbank1_dfii_pi2_rddata2_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin
-		csrbank1_dfii_pi2_rddata0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin
-		csrbank1_dfii_pi2_rddata0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi3_command0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi1_rddata_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_command0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi1_rddata_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we);
 	end
 end
-assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
+assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin
-		soc_litedramcore_phaseinjector3_command_issue_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin
-		soc_litedramcore_phaseinjector3_command_issue_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
+assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi3_address1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin
-		csrbank1_dfii_pi3_address1_we = (~interface1_bank_bus_we);
+	soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+		soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_address1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin
-		csrbank1_dfii_pi3_address1_re = interface1_bank_bus_we;
+	soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+		soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-	csrbank1_dfii_pi3_address0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin
-		csrbank1_dfii_pi3_address0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_address0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin
-		csrbank1_dfii_pi3_address0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank1_dfii_pi3_baddress0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin
-		csrbank1_dfii_pi3_baddress0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_baddress0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin
-		csrbank1_dfii_pi3_baddress0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin
-		csrbank1_dfii_pi3_wrdata2_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi2_rddata_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin
-		csrbank1_dfii_pi3_wrdata2_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi2_rddata_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin
-		csrbank1_dfii_pi3_wrdata1_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin
-		csrbank1_dfii_pi3_wrdata1_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin
-		csrbank1_dfii_pi3_wrdata0_re = interface1_bank_bus_we;
+	soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
+		soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin
-		csrbank1_dfii_pi3_wrdata0_we = (~interface1_bank_bus_we);
+	soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
+		soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
 	end
 end
-assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata2_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin
-		csrbank1_dfii_pi3_rddata2_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata2_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin
-		csrbank1_dfii_pi3_rddata2_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata0_re = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin
-		csrbank1_dfii_pi3_rddata0_re = interface1_bank_bus_we;
+	csrbank1_dfii_pi3_rddata_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata0_we = 1'd0;
-	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin
-		csrbank1_dfii_pi3_rddata0_we = (~interface1_bank_bus_we);
+	csrbank1_dfii_pi3_rddata_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_sel = soc_litedramcore_storage[0];
@@ -10697,57 +10248,29 @@ assign soc_litedramcore_odt = soc_litedramcore_storage[2];
 assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
 assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0];
 assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank1_dfii_pi0_address1_w = soc_litedramcore_phaseinjector0_address_storage[13:8];
-assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0];
 assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank1_dfii_pi0_wrdata3_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign csrbank1_dfii_pi0_wrdata2_w = soc_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign csrbank1_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign csrbank1_dfii_pi0_rddata3_w = soc_litedramcore_phaseinjector0_rddata_status[31:24];
-assign csrbank1_dfii_pi0_rddata2_w = soc_litedramcore_phaseinjector0_rddata_status[23:16];
-assign csrbank1_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_rddata_status[15:8];
-assign csrbank1_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_rddata_status[7:0];
-assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata0_we;
+assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status[31:0];
+assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we;
 assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank1_dfii_pi1_address1_w = soc_litedramcore_phaseinjector1_address_storage[13:8];
-assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0];
 assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank1_dfii_pi1_wrdata3_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign csrbank1_dfii_pi1_wrdata2_w = soc_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign csrbank1_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign csrbank1_dfii_pi1_rddata3_w = soc_litedramcore_phaseinjector1_rddata_status[31:24];
-assign csrbank1_dfii_pi1_rddata2_w = soc_litedramcore_phaseinjector1_rddata_status[23:16];
-assign csrbank1_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_rddata_status[15:8];
-assign csrbank1_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_rddata_status[7:0];
-assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata0_we;
+assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status[31:0];
+assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we;
 assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank1_dfii_pi2_address1_w = soc_litedramcore_phaseinjector2_address_storage[13:8];
-assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0];
 assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank1_dfii_pi2_wrdata3_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign csrbank1_dfii_pi2_wrdata2_w = soc_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign csrbank1_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign csrbank1_dfii_pi2_rddata3_w = soc_litedramcore_phaseinjector2_rddata_status[31:24];
-assign csrbank1_dfii_pi2_rddata2_w = soc_litedramcore_phaseinjector2_rddata_status[23:16];
-assign csrbank1_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_rddata_status[15:8];
-assign csrbank1_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_rddata_status[7:0];
-assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata0_we;
+assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status[31:0];
+assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we;
 assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank1_dfii_pi3_address1_w = soc_litedramcore_phaseinjector3_address_storage[13:8];
-assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0];
 assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank1_dfii_pi3_wrdata3_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign csrbank1_dfii_pi3_wrdata2_w = soc_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign csrbank1_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign csrbank1_dfii_pi3_rddata3_w = soc_litedramcore_phaseinjector3_rddata_status[31:24];
-assign csrbank1_dfii_pi3_rddata2_w = soc_litedramcore_phaseinjector3_rddata_status[23:16];
-assign csrbank1_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_rddata_status[15:8];
-assign csrbank1_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_rddata_status[7:0];
-assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata0_we;
+assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0];
+assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we;
 assign csr_interconnect_adr = litedramcore_adr;
 assign csr_interconnect_we = litedramcore_we;
 assign csr_interconnect_dat_w = litedramcore_dat_w;
@@ -10776,1196 +10299,1201 @@ assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bank
 assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col);
 assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col);
 always @(*) begin
-	rhs_array_muxed0 = 1'd0;
+	rhs_array_muxed0 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed1 = 14'd0;
+	rhs_array_muxed1 <= 14'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			rhs_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed2 = 3'd0;
+	rhs_array_muxed2 <= 3'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			rhs_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed3 = 1'd0;
+	rhs_array_muxed3 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			rhs_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed4 = 1'd0;
+	rhs_array_muxed4 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			rhs_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed5 = 1'd0;
+	rhs_array_muxed5 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			rhs_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed0 = 1'd0;
+	t_array_muxed0 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			t_array_muxed0 = soc_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed1 = 1'd0;
+	t_array_muxed1 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			t_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed2 = 1'd0;
+	t_array_muxed2 <= 1'd0;
 	case (soc_litedramcore_choose_cmd_grant)
 		1'd0: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			t_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed6 = 1'd0;
+	rhs_array_muxed6 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			rhs_array_muxed6 = soc_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed7 = 14'd0;
+	rhs_array_muxed7 <= 14'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			rhs_array_muxed7 = soc_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed8 = 3'd0;
+	rhs_array_muxed8 <= 3'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			rhs_array_muxed8 = soc_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed9 = 1'd0;
+	rhs_array_muxed9 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			rhs_array_muxed9 = soc_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed10 = 1'd0;
+	rhs_array_muxed10 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			rhs_array_muxed10 = soc_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed11 = 1'd0;
+	rhs_array_muxed11 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			rhs_array_muxed11 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed3 = 1'd0;
+	t_array_muxed3 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			t_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed4 = 1'd0;
+	t_array_muxed4 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			t_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	t_array_muxed5 = 1'd0;
+	t_array_muxed5 <= 1'd0;
 	case (soc_litedramcore_choose_req_grant)
 		1'd0: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			t_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed12 = 21'd0;
+	rhs_array_muxed12 <= 21'd0;
 	case (roundrobin0_grant)
 		default: begin
-			rhs_array_muxed12 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed13 = 1'd0;
+	rhs_array_muxed13 <= 1'd0;
 	case (roundrobin0_grant)
 		default: begin
-			rhs_array_muxed13 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed14 = 1'd0;
+	rhs_array_muxed14 <= 1'd0;
 	case (roundrobin0_grant)
 		default: begin
-			rhs_array_muxed14 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed15 = 21'd0;
+	rhs_array_muxed15 <= 21'd0;
 	case (roundrobin1_grant)
 		default: begin
-			rhs_array_muxed15 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed16 = 1'd0;
+	rhs_array_muxed16 <= 1'd0;
 	case (roundrobin1_grant)
 		default: begin
-			rhs_array_muxed16 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed17 = 1'd0;
+	rhs_array_muxed17 <= 1'd0;
 	case (roundrobin1_grant)
 		default: begin
-			rhs_array_muxed17 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed18 = 21'd0;
+	rhs_array_muxed18 <= 21'd0;
 	case (roundrobin2_grant)
 		default: begin
-			rhs_array_muxed18 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed19 = 1'd0;
+	rhs_array_muxed19 <= 1'd0;
 	case (roundrobin2_grant)
 		default: begin
-			rhs_array_muxed19 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed20 = 1'd0;
+	rhs_array_muxed20 <= 1'd0;
 	case (roundrobin2_grant)
 		default: begin
-			rhs_array_muxed20 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed21 = 21'd0;
+	rhs_array_muxed21 <= 21'd0;
 	case (roundrobin3_grant)
 		default: begin
-			rhs_array_muxed21 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed22 = 1'd0;
+	rhs_array_muxed22 <= 1'd0;
 	case (roundrobin3_grant)
 		default: begin
-			rhs_array_muxed22 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed23 = 1'd0;
+	rhs_array_muxed23 <= 1'd0;
 	case (roundrobin3_grant)
 		default: begin
-			rhs_array_muxed23 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed24 = 21'd0;
+	rhs_array_muxed24 <= 21'd0;
 	case (roundrobin4_grant)
 		default: begin
-			rhs_array_muxed24 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed25 = 1'd0;
+	rhs_array_muxed25 <= 1'd0;
 	case (roundrobin4_grant)
 		default: begin
-			rhs_array_muxed25 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed26 = 1'd0;
+	rhs_array_muxed26 <= 1'd0;
 	case (roundrobin4_grant)
 		default: begin
-			rhs_array_muxed26 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed27 = 21'd0;
+	rhs_array_muxed27 <= 21'd0;
 	case (roundrobin5_grant)
 		default: begin
-			rhs_array_muxed27 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed28 = 1'd0;
+	rhs_array_muxed28 <= 1'd0;
 	case (roundrobin5_grant)
 		default: begin
-			rhs_array_muxed28 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed29 = 1'd0;
+	rhs_array_muxed29 <= 1'd0;
 	case (roundrobin5_grant)
 		default: begin
-			rhs_array_muxed29 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed30 = 21'd0;
+	rhs_array_muxed30 <= 21'd0;
 	case (roundrobin6_grant)
 		default: begin
-			rhs_array_muxed30 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed31 = 1'd0;
+	rhs_array_muxed31 <= 1'd0;
 	case (roundrobin6_grant)
 		default: begin
-			rhs_array_muxed31 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed32 = 1'd0;
+	rhs_array_muxed32 <= 1'd0;
 	case (roundrobin6_grant)
 		default: begin
-			rhs_array_muxed32 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed33 = 21'd0;
+	rhs_array_muxed33 <= 21'd0;
 	case (roundrobin7_grant)
 		default: begin
-			rhs_array_muxed33 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed34 = 1'd0;
+	rhs_array_muxed34 <= 1'd0;
 	case (roundrobin7_grant)
 		default: begin
-			rhs_array_muxed34 = soc_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	rhs_array_muxed35 = 1'd0;
+	rhs_array_muxed35 <= 1'd0;
 	case (roundrobin7_grant)
 		default: begin
-			rhs_array_muxed35 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed0 = 3'd0;
+	array_muxed0 <= 3'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed0 = soc_litedramcore_nop_ba[2:0];
+			array_muxed0 <= soc_litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			array_muxed0 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			array_muxed0 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			array_muxed0 = soc_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed1 = 14'd0;
+	array_muxed1 <= 14'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed1 = soc_litedramcore_nop_a;
+			array_muxed1 <= soc_litedramcore_nop_a;
 		end
 		1'd1: begin
-			array_muxed1 = soc_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			array_muxed1 = soc_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			array_muxed1 = soc_litedramcore_cmd_payload_a;
+			array_muxed1 <= soc_litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed2 = 1'd0;
+	array_muxed2 <= 1'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed2 = 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed2 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			array_muxed2 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			array_muxed2 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed3 = 1'd0;
+	array_muxed3 <= 1'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed3 = 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed3 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			array_muxed3 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			array_muxed3 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed4 = 1'd0;
+	array_muxed4 <= 1'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed4 = 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed4 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			array_muxed4 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			array_muxed4 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed5 = 1'd0;
+	array_muxed5 <= 1'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed5 = 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed5 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			array_muxed5 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			array_muxed5 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed6 = 1'd0;
+	array_muxed6 <= 1'd0;
 	case (soc_litedramcore_steerer_sel0)
 		1'd0: begin
-			array_muxed6 = 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed6 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			array_muxed6 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			array_muxed6 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed7 = 3'd0;
+	array_muxed7 <= 3'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed7 = soc_litedramcore_nop_ba[2:0];
+			array_muxed7 <= soc_litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			array_muxed7 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			array_muxed7 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			array_muxed7 = soc_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed8 = 14'd0;
+	array_muxed8 <= 14'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed8 = soc_litedramcore_nop_a;
+			array_muxed8 <= soc_litedramcore_nop_a;
 		end
 		1'd1: begin
-			array_muxed8 = soc_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			array_muxed8 = soc_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			array_muxed8 = soc_litedramcore_cmd_payload_a;
+			array_muxed8 <= soc_litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed9 = 1'd0;
+	array_muxed9 <= 1'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed9 = 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed9 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			array_muxed9 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			array_muxed9 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed10 = 1'd0;
+	array_muxed10 <= 1'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed10 = 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed10 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			array_muxed10 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			array_muxed10 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed11 = 1'd0;
+	array_muxed11 <= 1'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed11 = 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed11 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			array_muxed11 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			array_muxed11 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed12 = 1'd0;
+	array_muxed12 <= 1'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed12 = 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed12 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			array_muxed12 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			array_muxed12 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed13 = 1'd0;
+	array_muxed13 <= 1'd0;
 	case (soc_litedramcore_steerer_sel1)
 		1'd0: begin
-			array_muxed13 = 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed13 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			array_muxed13 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			array_muxed13 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed14 = 3'd0;
+	array_muxed14 <= 3'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed14 = soc_litedramcore_nop_ba[2:0];
+			array_muxed14 <= soc_litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			array_muxed14 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			array_muxed14 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			array_muxed14 = soc_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed15 = 14'd0;
+	array_muxed15 <= 14'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed15 = soc_litedramcore_nop_a;
+			array_muxed15 <= soc_litedramcore_nop_a;
 		end
 		1'd1: begin
-			array_muxed15 = soc_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			array_muxed15 = soc_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			array_muxed15 = soc_litedramcore_cmd_payload_a;
+			array_muxed15 <= soc_litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed16 = 1'd0;
+	array_muxed16 <= 1'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed16 = 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed16 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			array_muxed16 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			array_muxed16 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed17 = 1'd0;
+	array_muxed17 <= 1'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed17 = 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed17 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			array_muxed17 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			array_muxed17 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed18 = 1'd0;
+	array_muxed18 <= 1'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed18 = 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed18 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			array_muxed18 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			array_muxed18 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed19 = 1'd0;
+	array_muxed19 <= 1'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed19 = 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed19 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			array_muxed19 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			array_muxed19 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed20 = 1'd0;
+	array_muxed20 <= 1'd0;
 	case (soc_litedramcore_steerer_sel2)
 		1'd0: begin
-			array_muxed20 = 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed20 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			array_muxed20 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			array_muxed20 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed21 = 3'd0;
+	array_muxed21 <= 3'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed21 = soc_litedramcore_nop_ba[2:0];
+			array_muxed21 <= soc_litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			array_muxed21 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			array_muxed21 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			array_muxed21 = soc_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed22 = 14'd0;
+	array_muxed22 <= 14'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed22 = soc_litedramcore_nop_a;
+			array_muxed22 <= soc_litedramcore_nop_a;
 		end
 		1'd1: begin
-			array_muxed22 = soc_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			array_muxed22 = soc_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			array_muxed22 = soc_litedramcore_cmd_payload_a;
+			array_muxed22 <= soc_litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed23 = 1'd0;
+	array_muxed23 <= 1'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed23 = 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed23 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			array_muxed23 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			array_muxed23 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed24 = 1'd0;
+	array_muxed24 <= 1'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed24 = 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed24 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			array_muxed24 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			array_muxed24 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed25 = 1'd0;
+	array_muxed25 <= 1'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed25 = 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed25 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			array_muxed25 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			array_muxed25 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed26 = 1'd0;
+	array_muxed26 <= 1'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed26 = 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed26 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			array_muxed26 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			array_muxed26 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	array_muxed27 = 1'd0;
+	array_muxed27 <= 1'd0;
 	case (soc_litedramcore_steerer_sel3)
 		1'd0: begin
-			array_muxed27 = 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			array_muxed27 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			array_muxed27 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			array_muxed27 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge por_clk) begin
 	soc_int_rst <= 1'd0;
 end
@@ -13413,154 +12941,70 @@ always @(posedge sys_clk) begin
 				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
+				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
+				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
+			5'd24: begin
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -13572,118 +13016,70 @@ always @(posedge sys_clk) begin
 		soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
 	end
 	soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
-	if (csrbank1_dfii_pi0_address1_re) begin
-		soc_litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
-	end
 	if (csrbank1_dfii_pi0_address0_re) begin
-		soc_litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
+		soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
 	end
 	soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
 	if (csrbank1_dfii_pi0_baddress0_re) begin
 		soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
 	end
 	soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
-	if (csrbank1_dfii_pi0_wrdata3_re) begin
-		soc_litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi0_wrdata2_re) begin
-		soc_litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi0_wrdata1_re) begin
-		soc_litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi0_wrdata0_re) begin
-		soc_litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
+		soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
 	end
 	soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
-	soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata0_re;
+	soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
 	if (csrbank1_dfii_pi1_command0_re) begin
 		soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
 	end
 	soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
-	if (csrbank1_dfii_pi1_address1_re) begin
-		soc_litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
-	end
 	if (csrbank1_dfii_pi1_address0_re) begin
-		soc_litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
+		soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
 	end
 	soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
 	if (csrbank1_dfii_pi1_baddress0_re) begin
 		soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
 	end
 	soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
-	if (csrbank1_dfii_pi1_wrdata3_re) begin
-		soc_litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi1_wrdata2_re) begin
-		soc_litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi1_wrdata1_re) begin
-		soc_litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi1_wrdata0_re) begin
-		soc_litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
+		soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
 	end
 	soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
-	soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata0_re;
+	soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
 	if (csrbank1_dfii_pi2_command0_re) begin
 		soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
 	end
 	soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
-	if (csrbank1_dfii_pi2_address1_re) begin
-		soc_litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
-	end
 	if (csrbank1_dfii_pi2_address0_re) begin
-		soc_litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
+		soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
 	end
 	soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
 	if (csrbank1_dfii_pi2_baddress0_re) begin
 		soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
 	end
 	soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
-	if (csrbank1_dfii_pi2_wrdata3_re) begin
-		soc_litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi2_wrdata2_re) begin
-		soc_litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi2_wrdata1_re) begin
-		soc_litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi2_wrdata0_re) begin
-		soc_litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
+		soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
 	end
 	soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
-	soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata0_re;
+	soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
 	if (csrbank1_dfii_pi3_command0_re) begin
 		soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
 	end
 	soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
-	if (csrbank1_dfii_pi3_address1_re) begin
-		soc_litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
-	end
 	if (csrbank1_dfii_pi3_address0_re) begin
-		soc_litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
+		soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
 	end
 	soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
 	if (csrbank1_dfii_pi3_baddress0_re) begin
 		soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
 	end
 	soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
-	if (csrbank1_dfii_pi3_wrdata3_re) begin
-		soc_litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi3_wrdata2_re) begin
-		soc_litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi3_wrdata1_re) begin
-		soc_litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi3_wrdata0_re) begin
-		soc_litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
+		soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
 	end
 	soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
-	soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata0_re;
+	soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re;
 	if (sys_rst) begin
 		soc_ddrphy_bankmodel0_active <= 1'd0;
 		soc_ddrphy_bankmodel0_row <= 14'd0;
@@ -13963,8 +13359,18 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Memory mem: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem[0:2097151];
-reg [20:0] memadr;
+reg [20:0] mem_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel0_write_port_we[0])
 		mem[soc_ddrphy_bankmodel0_write_port_adr][7:0] <= soc_ddrphy_bankmodel0_write_port_dat_w[7:0];
@@ -13998,17 +13404,21 @@ always @(posedge sys_clk) begin
 		mem[soc_ddrphy_bankmodel0_write_port_adr][119:112] <= soc_ddrphy_bankmodel0_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel0_write_port_we[15])
 		mem[soc_ddrphy_bankmodel0_write_port_adr][127:120] <= soc_ddrphy_bankmodel0_write_port_dat_w[127:120];
-	memadr <= soc_ddrphy_bankmodel0_write_port_adr;
+	mem_adr0 <= soc_ddrphy_bankmodel0_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[memadr];
+assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[mem_adr0];
 assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_1: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_1[0:2097151];
-reg [20:0] memadr_1;
+reg [20:0] mem_1_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel1_write_port_we[0])
 		mem_1[soc_ddrphy_bankmodel1_write_port_adr][7:0] <= soc_ddrphy_bankmodel1_write_port_dat_w[7:0];
@@ -14042,17 +13452,21 @@ always @(posedge sys_clk) begin
 		mem_1[soc_ddrphy_bankmodel1_write_port_adr][119:112] <= soc_ddrphy_bankmodel1_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel1_write_port_we[15])
 		mem_1[soc_ddrphy_bankmodel1_write_port_adr][127:120] <= soc_ddrphy_bankmodel1_write_port_dat_w[127:120];
-	memadr_1 <= soc_ddrphy_bankmodel1_write_port_adr;
+	mem_1_adr0 <= soc_ddrphy_bankmodel1_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1];
+assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[mem_1_adr0];
 assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_2: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_2[0:2097151];
-reg [20:0] memadr_2;
+reg [20:0] mem_2_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel2_write_port_we[0])
 		mem_2[soc_ddrphy_bankmodel2_write_port_adr][7:0] <= soc_ddrphy_bankmodel2_write_port_dat_w[7:0];
@@ -14086,17 +13500,21 @@ always @(posedge sys_clk) begin
 		mem_2[soc_ddrphy_bankmodel2_write_port_adr][119:112] <= soc_ddrphy_bankmodel2_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel2_write_port_we[15])
 		mem_2[soc_ddrphy_bankmodel2_write_port_adr][127:120] <= soc_ddrphy_bankmodel2_write_port_dat_w[127:120];
-	memadr_2 <= soc_ddrphy_bankmodel2_write_port_adr;
+	mem_2_adr0 <= soc_ddrphy_bankmodel2_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2];
+assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[mem_2_adr0];
 assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_3: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_3[0:2097151];
-reg [20:0] memadr_3;
+reg [20:0] mem_3_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel3_write_port_we[0])
 		mem_3[soc_ddrphy_bankmodel3_write_port_adr][7:0] <= soc_ddrphy_bankmodel3_write_port_dat_w[7:0];
@@ -14130,17 +13548,21 @@ always @(posedge sys_clk) begin
 		mem_3[soc_ddrphy_bankmodel3_write_port_adr][119:112] <= soc_ddrphy_bankmodel3_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel3_write_port_we[15])
 		mem_3[soc_ddrphy_bankmodel3_write_port_adr][127:120] <= soc_ddrphy_bankmodel3_write_port_dat_w[127:120];
-	memadr_3 <= soc_ddrphy_bankmodel3_write_port_adr;
+	mem_3_adr0 <= soc_ddrphy_bankmodel3_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3];
+assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[mem_3_adr0];
 assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_4: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_4[0:2097151];
-reg [20:0] memadr_4;
+reg [20:0] mem_4_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel4_write_port_we[0])
 		mem_4[soc_ddrphy_bankmodel4_write_port_adr][7:0] <= soc_ddrphy_bankmodel4_write_port_dat_w[7:0];
@@ -14174,17 +13596,21 @@ always @(posedge sys_clk) begin
 		mem_4[soc_ddrphy_bankmodel4_write_port_adr][119:112] <= soc_ddrphy_bankmodel4_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel4_write_port_we[15])
 		mem_4[soc_ddrphy_bankmodel4_write_port_adr][127:120] <= soc_ddrphy_bankmodel4_write_port_dat_w[127:120];
-	memadr_4 <= soc_ddrphy_bankmodel4_write_port_adr;
+	mem_4_adr0 <= soc_ddrphy_bankmodel4_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4];
+assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[mem_4_adr0];
 assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_5: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_5[0:2097151];
-reg [20:0] memadr_5;
+reg [20:0] mem_5_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel5_write_port_we[0])
 		mem_5[soc_ddrphy_bankmodel5_write_port_adr][7:0] <= soc_ddrphy_bankmodel5_write_port_dat_w[7:0];
@@ -14218,17 +13644,21 @@ always @(posedge sys_clk) begin
 		mem_5[soc_ddrphy_bankmodel5_write_port_adr][119:112] <= soc_ddrphy_bankmodel5_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel5_write_port_we[15])
 		mem_5[soc_ddrphy_bankmodel5_write_port_adr][127:120] <= soc_ddrphy_bankmodel5_write_port_dat_w[127:120];
-	memadr_5 <= soc_ddrphy_bankmodel5_write_port_adr;
+	mem_5_adr0 <= soc_ddrphy_bankmodel5_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5];
+assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[mem_5_adr0];
 assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_6: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_6[0:2097151];
-reg [20:0] memadr_6;
+reg [20:0] mem_6_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel6_write_port_we[0])
 		mem_6[soc_ddrphy_bankmodel6_write_port_adr][7:0] <= soc_ddrphy_bankmodel6_write_port_dat_w[7:0];
@@ -14262,17 +13692,21 @@ always @(posedge sys_clk) begin
 		mem_6[soc_ddrphy_bankmodel6_write_port_adr][119:112] <= soc_ddrphy_bankmodel6_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel6_write_port_we[15])
 		mem_6[soc_ddrphy_bankmodel6_write_port_adr][127:120] <= soc_ddrphy_bankmodel6_write_port_dat_w[127:120];
-	memadr_6 <= soc_ddrphy_bankmodel6_write_port_adr;
+	mem_6_adr0 <= soc_ddrphy_bankmodel6_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6];
+assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[mem_6_adr0];
 assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory mem_7: 2097152-words x 128-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
+// Port 1 | Read: Async | Write: ---- | 
 reg [127:0] mem_7[0:2097151];
-reg [20:0] memadr_7;
+reg [20:0] mem_7_adr0;
 always @(posedge sys_clk) begin
 	if (soc_ddrphy_bankmodel7_write_port_we[0])
 		mem_7[soc_ddrphy_bankmodel7_write_port_adr][7:0] <= soc_ddrphy_bankmodel7_write_port_dat_w[7:0];
@@ -14306,125 +13740,160 @@ always @(posedge sys_clk) begin
 		mem_7[soc_ddrphy_bankmodel7_write_port_adr][119:112] <= soc_ddrphy_bankmodel7_write_port_dat_w[119:112];
 	if (soc_ddrphy_bankmodel7_write_port_we[15])
 		mem_7[soc_ddrphy_bankmodel7_write_port_adr][127:120] <= soc_ddrphy_bankmodel7_write_port_dat_w[127:120];
-	memadr_7 <= soc_ddrphy_bankmodel7_write_port_adr;
+	mem_7_adr0 <= soc_ddrphy_bankmodel7_write_port_adr;
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7];
+assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[mem_7_adr0];
 assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage[0:15];
-reg [23:0] memdat;
+reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_1[0:15];
-reg [23:0] memdat_1;
+reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_2[0:15];
-reg [23:0] memdat_2;
+reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_3[0:15];
-reg [23:0] memdat_3;
+reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_4[0:15];
-reg [23:0] memdat_4;
+reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_5[0:15];
-reg [23:0] memdat_5;
+reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_6[0:15];
-reg [23:0] memdat_6;
+reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_7[0:15];
-reg [23:0] memdat_7;
+reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:16.
+//------------------------------------------------------------------------------
diff --git a/litedram/generated/wukong-v2/litedram-initmem.vhdl b/litedram/generated/wukong-v2/litedram-initmem.vhdl
index 395602b..231249e 100644
--- a/litedram/generated/wukong-v2/litedram-initmem.vhdl
+++ b/litedram/generated/wukong-v2/litedram-initmem.vhdl
@@ -100,7 +100,7 @@ begin
         if rising_edge(clk) then
             oack <= '0';
             if (wb_in.cyc and wb_in.stb) = '1' then
-                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
                 if wb_in.we = '0' then
                    obuf <= init_ram(adr);
                 else
diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init
index 5b1a383..1b6e88e 100644
--- a/litedram/generated/wukong-v2/litedram_core.init
+++ b/litedram/generated/wukong-v2/litedram_core.init
@@ -518,7 +518,7 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842afc4
+7c0802a63842adc4
 fbe1fff8fbc1fff0
 f821ff51f8010010
 f88100d83bc10020
@@ -527,96 +527,97 @@ f8c100e87c651b78
 38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-600000004800245d
+6000000048002159
 7fc3f3787c7f1b78
-6000000048001e69
+6000000048001b7d
 7fe3fb78382100b0
-0000000048002a54
+00000000480027d4
 0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842af203c4c0001
+3842ad203c4c0001
 7d8000267c0802a6
-9181000848002991
-48001e65f821fed1
+9181000848002711
+48001b79f821fed1
 3c62ffff60000000
-4bffff3938637b10
+4bffff3938637a90
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637b30
+63ff000838637ab0
 3c62ffff4bffff15
-38637b507bff0020
+38637ad07bff0020
 7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b68
+4bfffee938637ae8
 4e00000073e90002
 3c62ffff41820010
-4bfffed138637b70
+4bfffed138637af0
 4d80000073e90004
 3c62ffff41820010
-4bfffeb938637b78
+4bfffeb938637af8
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b80
+4bfffea138637b00
 4182001073e90010
-38637b903c62ffff
-73e901004bfffe8d
+38637b103c62ffff
+73ff01004bfffe8d
 3c62ffff41820010
-4bfffe7938637ba0
-3b7b7ba83f62ffff
+4bfffe7938637b20
+3b7b7b283f62ffff
 4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bb0
+4bfffe4138637b30
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637bc8
+4bfffe1938637b48
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637be07884b282
+38637b607884b282
 3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637bf87c892392
+38637b787c892392
 418a025c4bfffdc5
-63bd00383fa0c000
-7c0004ac7bbd0020
-3d40c0007fa0eeea
+639c00383f80c000
+7c0004ac7b9c0020
+3d40c0007f80e6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-579c063e7f80feaa
-7fc0feaa7c0004ac
-7c0004ac57de063e
-4bfffd157fe0feaa
-3c62ffff57ff063e
-7fc5f3787fe6fb78
-38637c187f84e378
-7f89f3784bfffd3d
-2c0900007d29fb78
-7f89f03841820168
-2c0900ff7d29f838
-281c000141820158
-281e000240820374
-73de00bf41820010
-408201342c1e0020
+7c0004ac7fc0feaa
+7c0004ac7fa0feaa
+4bfffd1d7fe0feaa
+57e6063e3c62ffff
+57c4063e57a5063e
+57f8063e38637b98
+7fc9eb784bfffd45
+7d29fb7857b9063e
+5529063e57da063e
+418201682c090000
+7fdef8387fdee838
+2c1e00ff57de063e
+2c1a000141820154
+2c19000240820360
+73bd00bf41820010
+408201302c1d0020
 57ff063e3bffffe8
-41810124281f0001
+41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
@@ -624,182 +625,161 @@ f9410108f9210100
 7bde002063de6004
 7f40f7aa7c0004ac
 7d20ffaa7c0004ac
-7f80feaa7c0004ac
-579c063e4bfffc69
-7f84e3783c62ffff
-4bfffc9938637c38
-4082009073890002
-38637c583c62ffff
-7c0004ac4bfffc85
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc29
-392000017f40f7aa
+7fa0feaa7c0004ac
+3c62ffff4bfffc61
+38637bb857a4063e
+73a900024bfffc95
+3c62ffff40820090
+4bfffc8138637bd8
+7f40f7aa7c0004ac
+7c0004ac39200006
+4bfffc257d20ffaa
+7f40f7aa7c0004ac
+7c0004ac39200001
+392000007d20ffaa
 7d20ffaa7c0004ac
-7c0004ac39200000
-639c00027d20ffaa
-7f80ffaa7c0004ac
-7d20f7aa7c0004ac
-3b2000024bfffbf1
-7c0004ac3b400005
-7c0004ac7f20f7aa
-7c0004ac7f40ffaa
-579c063e7f80feaa
-738900014bfffbc9
-3c62ffff4082ffdc
-4bfffbf938637c70
-614a60083d40c000
-7c0004ac794a0020
-5529021e7d20562a
-61291f6b65292000
-7d20572a7c0004ac
-4bfffbc97f63db78
-3c62ffff7bbd0020
-38637c807fa4eb78
-3be000014bfffbb5
-4bfffba97f63db78
-3ca2ffff41920028
-3c62ffff3c82ffff
-38847cb038a57ca0
-4bfffb8938637cb8
-6000000048000f2d
+7c0004ac63bd0002
+7c0004ac7fa0ffaa
+4bfffbed7d20f7aa
+3b4000053b000002
+7c0004ac7ff9fb78
+7c0004ac7f00f7aa
+7c0004ac7f40cfaa
+4bfffbc57fa0feaa
+4082ffe073bd0001
+38637bf03c62ffff
+3d40c0004bfffbf5
+794a0020614a6008
+7d20562a7c0004ac
+652920005529021e
+7c0004ac61291f6b
+7f63db787d20572a
+3c62ffff4bfffbc5
+38637c007b840020
+4bfffbb17f9ae378
+7f63db783be00001
+419200244bfffba5
+3c62ffff3ca2ffff
+38637c3038a57c20
+4bfffb897ca42b78
+6000000048000c55
 3c62ffff418e0024
-4bfffb7138637ce8
-4800014038600000
-3ba000003be00000
-2c3f00004bffffb0
+4bfffb7138637c60
+4800013c38600000
+3b4000003be00000
+73ff00014bffffb4
 3c62ffff418200a4
-4bfffb4938637d00
-38a000403c9df000
+4bfffb4938637c78
+38a000403c9af000
 3861007078840020
-6000000048001cbd
+6000000048001889
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637d18
+794a83e438637c90
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
 418200802c090015
-38637d383c62ffff
+38637cb03c62ffff
 892100774bfffae5
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d9888810070
+38637d1088810070
 89210075f9210060
 3c62ffff4bfffab5
-4bfffaa938637dc8
+4bfffaa938637d40
 38a000003c80ff00
 60a5a00060846000
 3c60400078840020
-6000000048001c15
-38637de83c62ffff
+60000000480017e1
+38637d603c62ffff
 4bfffafd4bfffa7d
 ebe100904bffff08
-3bc000003f02ffff
-3b187d503b2100b0
-7bff00207fffea14
-7c09f040a12100a8
-8081008841810034
-38637d783c62ffff
-4bfffabd4bfffa3d
-2c23ffffe8610088
-382101304182ff7c
-7d83812081810008
-3c9ff000480024a8
-7884002038a00038
-48001b917f23cb78
-812100b060000000
-4082004c2c090001
-eb6100c0eb4100d0
-7fc4f378eb8100b8
-7f66db787f03c378
-3f9cf0007b450020
-7c9de2144bfff9d5
-788400207b450020
-48001b497f63db78
-a12100a660000000
-7bff00207fe9fa14
-7bde00203bde0001
-281c00204bffff50
-281e00ba4082fdd0
-281f00184082fdc8
-3c62ffff4082fdc0
-4bfff98138637c68
-000000004bfffd7c
-0000088003000000
-7869c0223d40c800
-794a0020614a000c
+3ba000003f02ffff
+3b187cc83b2100b0
+a12100a87ffafa14
+418000347c1d4840
+3c62ffff80810088
+4bfffa4138637cf0
+e86100884bfffac1
+4182ff802c23ffff
+8181000838210130
+4800222c7d838120
+38a000383c9ff000
+7f23cb7878840020
+6000000048001761
+2c090001812100b0
+eb6100d040820048
+ebc100b8eb8100c0
+7f03c3787ba40020
+7b6500207f86e378
+4bfff9d93fdef000
+7b6500207c9af214
+7f83e37878840020
+6000000048001719
+7fff4a14a12100a6
+4bffff583bbd0001
+4082fde02c1a0020
+4082fdd82c1900ba
+4082fdd02c180018
+38637be83c62ffff
+4bfffd8c4bfff98d
+0300000000000000
+3d20c80000000880
+7929002061291004
+7c604f2a7c0004ac
+392000013d40c800
+794a0020614a1008
 7d20572a7c0004ac
-612900103d20c800
-7c0004ac79290020
-4e8000207c604f2a
+000000004e800020
 0000000000000000
-3d20c80000000000
-612900045463063e
+3842a6f83c4c0001
+4182006828030002
+4182003028030003
+4082007c28030001
+6129101c3d20c800
 7c0004ac79290020
-3d40c8007c604f2a
-614a000839200001
-7c0004ac794a0020
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a8ac
-2803000341820068
-2803000141820030
-3d20c8004082007c
-7929002061290038
+3d40c8007c804f2a
+614a102039200001
+3d20c80048000024
+792900206129104c
 7c804f2a7c0004ac
 392000013d40c800
-48000024614a003c
-612900a03d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a00a439200001
-7c0004ac794a0020
-4e8000207d20572a
-6129006c3d20c800
-7c0004ac79290020
-3d40c8007c804f2a
-614a007039200001
-7c8307b44bffffd0
-000000004bffff24
-0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
-7c604f2a7c0004ac
-610810143d00c800
-7c0004ac79080020
-394000007d40472a
-7d404f2a7c0004ac
-000000004e800020
+794a0020614a1050
+7d20572a7c0004ac
+3d20c8004e800020
+7929002061291034
+7c804f2a7c0004ac
+392000013d40c800
+4bffffd0614a1038
+4bffff287c8307b4
 0000000000000000
-3d20c80039400001
-612910107d431830
-792900205463063e
+3d20c80000000000
+6129081039400001
+792900207d431830
 7c604f2a7c0004ac
-610810183d00c800
+610808143d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
 000000004e800020
 0000000000000000
 394000013d20c800
-7d43183061291010
+7d43183061290810
 7c0004ac79290020
 3d00c8007c604f2a
-790800206108101c
+7908002061080818
 7d40472a7c0004ac
 7c0004ac39400000
 4e8000207d404f2a
 0000000000000000
 3d20c80000000000
-6129101039400001
+6129081039400001
 792900207d431830
 7c604f2a7c0004ac
-610810203d00c800
+6108081c3d00c800
 7c0004ac79080020
 394000007d40472a
 7d404f2a7c0004ac
@@ -809,592 +789,524 @@ a12100a660000000
 4182001c28030003
 4082004028030001
 392000003d40c800
-48000010614a0048
+48000010614a1028
 392000003d40c800
-794a0020614a00b0
+794a0020614a1058
 7d20572a7c0004ac
 3d40c8004e800020
-614a007c39200000
+614a104039200000
 3d40c8004bffffe4
-614a001439200000
+614a101039200000
 000000004bffffd4
 0000000000000000
-3842a6583c4c0001
-4182006828030002
-4182003028030003
-4082007c28030001
+4182004028030002
+4182001c28030003
+4082004028030001
 392000003d40c800
-794a0020614a0040
-7d20572a7c0004ac
-614a00443d40c800
-3d40c80048000024
-614a00a839200000
-7c0004ac794a0020
-3d40c8007d20572a
-794a0020614a00ac
+48000010614a1024
+392000003d40c800
+794a0020614a1054
 7d20572a7c0004ac
 3d40c8004e800020
-614a007439200000
-7c0004ac794a0020
-3d40c8007d20572a
-4bffffd0614a0078
-4bfffc9438600000
-0000000000000000
-2c03000000000000
-3929000178690020
-3920000140800008
-3929ffff2c290001
-600000004d820020
-000000004bfffff0
-0000000000000000
-3842a5783c4c0001
-48001ffd7c0802a6
-3ce08020f821ffa1
-60e700033bc10020
-7fcaf3787c7c1b78
-78e700203be00004
-3920000039000004
-7888f8427d0903a6
+614a103c39200000
+3d40c8004bffffe4
+614a100c39200000
+000000004bffffd4
+0000000000000000
+786900202c030000
+4080000839290001
+2c29000139200001
+4d8200203929ffff
+4bfffff060000000
+0000000000000000
+3c4c000100000000
+7c0802a63842a454
+f821ffa148001e59
+60a500033ca08020
+394000007c7e1b78
+78a5002038c1001f
+3b81002039000004
+7ce652147d0903a6
+7888f86239200004
 7c8400d0788407e0
-7c8642787c843838
-7cca49ae7cc43378
-4200ffe039290001
-394a0004393fffff
-4082ffc4793f0021
-4bfffbdd38600000
-392000003d40c800
-794a0020614a0014
+7c8428383929ffff
+7d0443787c884278
+4200ffe09d070001
+282a0010394a0004
+3d40c8004082ffc0
+794a0020614a100c
 7d20572a7c0004ac
-4bfffbf938600009
-4bffff313860000f
-3ce0c8003d40c800
-60e700f8614a0028
-794a00207fc9f378
-38c0000478e70020
-7cc903a6394afff0
-8cc800013909ffff
-7cc0572a7c0004ac
-4200fff0394a0004
-39290004394a0034
-4082ffd07c2a3800
-63bd10303fa0c800
+614a10103d40c800
+7c0004ac794a0020
+386000097d20572a
+3860000f4bfffc85
+3d20c8004bffff29
+612910143cc0c800
+7f8ae37860c61074
+78c6002079290020
+38eaffff38a00004
+3be000047ca903a6
+8ca7000139000000
+7905400c3bffffff
+4200fff07ca82b78
+7ca04f2a7c0004ac
+394a000439290018
+4082ffc47c293000
+63bd08303fa0c800
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffe21
+7c0004ac4bfffe41
 5463063e7c60ee2a
-7c0004ac4bfffd99
-388000177fa0ee2a
-3fa0c80057a3063e
-63bd102c4bfffba5
-4bfffe913860000f
+7c0004ac4bfffdc1
+388000177c60ee2a
+3fa0c8005463063e
+63bd082c4bfffc21
+4bfffe7d3860000f
 7c0004ac7bbd0020
 5463063e7c60ee2a
-7c0004ac4bfffdd9
+7c0004ac4bfffdf9
 5463063e7c60ee2a
-7c0004ac4bfffd51
-388000257fa0ee2a
-4bfffb6157a3063e
-4bfffe513860000f
-4bfffacd38600000
-392000003d40c800
-794a0020614a0014
-7d20572a7c0004ac
-3ba100303860000b
-3860000f4bfffae5
-3ce0c8004bfffe1d
-60e700283d60c800
-3c8033333c005555
-616b00f83d800f0f
-78e7002038c00000
-60005555207c0001
-618c0f0f60843333
-7c0004ac796b0020
-992100307d203e2a
-7c0004ac39270004
-992100317d204e2a
-7c0004ac39270008
-992100327d204e2a
-7c0004ac3927000c
-992100337d204e2a
-38a0000039200004
-7d2532147d2903a6
-7c091800552907fe
-7d45e8ae40820058
-7d0852787d1e28ae
-5509063e790afe62
-7d4a48507d4a0038
-554af0be7c895038
-7d4952147d4a2038
-7d2952145549e13e
-552ac23e7d894838
-552a843e7d295214
-552906be7d295214
-793f00207d29fa14
-4200ff9838a50001
-38c6000438e70034
-3bde00047c275800
-4082ff3878c60020
-7fe3fb7838210060
-0000000048001d98
-0000048001000000
-3842a2a83c4c0001
-7d9080267c0802a6
-48001d2191810008
-2e250000f821ff71
-4192001c7c7e1b78
-7c641b787c852378
-38637e003c62ffff
-600000004bfff2b5
-3f62ffff7fc3f378
-3b8000204bfffa61
-3b7b7e103ba00000
-7fc3f3783880002a
-388000544bfffcd9
-7fc3f3787c7f1b78
-7d3f1a144bfffcc9
-212900807d240034
-548360265484d97e
-7fa9ea147d234a14
-419200107bbd0020
-4bfff2517f63db78
-7fc3f37860000000
-4bfffa4d3b9cffff
-4082ffa47b9c0021
-3c62ffff41920014
-4bfff22938637e18
-3821009060000000
-818100087fa3eb78
-48001ca87d908120
-0300000000000000
-3c4c000100000580
-7c0802a63842a1bc
-f821ff7148001c39
+7c0004ac4bfffd79
+388000257c60ee2a
+4bfffbdd5463063e
+4bfffe3d3860000f
+6129100c3d20c800
+7c0004ac79290020
+3d20c8007fe04f2a
+7929002061291010
+7fe04f2a7c0004ac
+23de00013860000b
+3860000f4bfffb5d
+3d00c8004bfffe01
+610810183c80c800
+3ca033333d605555
+608410783c000f0f
+7908002038c00000
+616b555538610030
+60000f0f60a53333
+7c0004ac78840020
+394100307d20462a
+392000047d20552c
+7d2903a639400000
+552907fe7d265214
+408200547c09f000
+7d3c50ae7cea18ae
+5527063e7d293a78
+7d2958387929fe62
+7d2728387d293850
+7d2928385529f0be
+54e9e13e7ce74a14
+7d2900387d293a14
+7d293a145527c23e
+7d293a145527843e
+7fff4a14552906be
+4200ff9c394a0001
+3b9c000439080018
+38c600047c282000
+382100604082ff6c
+48001c0c7be30020
+0100000000000000
+3c4c000100000480
+7c0802a63842a19c
+f821ff7148001b99
 7c7f1b783ba00000
-3880002a4bfff9a1
-4bfffc257fe3fb78
-7c7e1b7838800054
-4bfffc157fe3fb78
-7d3c07b4393d0001
-2c0300007c7e1a14
-2c0900204182001c
-7fe3fb784182007c
-4bfff9ad7f9de378
-7fbeeb784bffffbc
-3b5d00017fe3fb78
-7f5a07b44bfff999
-3880002a3b60ffff
-4bfffbc57fe3fb78
-7c7c1b7838800054
-4bfffbb57fe3fb78
-2c0300007c7c1a14
-2c1bffff41820010
-7f5bd37840820008
-2c09001f393a0001
-4181001c7d3a07b4
-4bfff9457fe3fb78
-7f9de3784bffffb4
-4bffff943bc0ffff
-395d00022c1d001e
-4181000839200000
-2c1bffff213d001e
-7d2907b47d295214
-7d3b4b7840820008
-7fbeda142c1effff
+3880002a4bfffb35
+4bfffd297fe3fb78
+3b9d000138800054
+7fe3fb787c7e1b78
+7c63f2144bfffd15
+4182001c2c030000
+418200742c1c0020
+7f9de3787fe3fb78
+4bffffc04bfffb41
+7fe3fb787fbeeb78
+4bfffb2d3b7d0001
+3880002a3b80ffff
+4bfffcd17fe3fb78
+7c7a1b7838800054
+4bfffcc17fe3fb78
+2c0300007c63d214
+2c1cffff41820010
+7f7cdb7840820008
+2c1b001f3b7b0001
+7fe3fb784181001c
+4bffffb84bfffae1
+3bc0ffff3ba00020
+2c1d001e4bffff9c
+39200000395d0002
+213d001e41810008
+7d2952142c1cffff
+7d3c4b7840820008
+7fbee2142c1effff
 7fbd01947fbd0e70
-408200387bbd06e0
-38637e203c62ffff
-600000004bfff0dd
+4082003857bd06fe
+38637d783c62ffff
+600000004bfff2cd
 3bc000007fe3fb78
-386000644bfff889
-7c1df0004bfffad5
+386000644bfffa2d
+7c1df0004bfffbe9
 3821009040820034
-7cbed85048001b48
+7cbee05048001ab8
 7ca50e703c62ffff
-7fa4eb787ca50194
-7ca507b438637e30
-600000004bfff095
+7fa407b47ca50194
+7ca507b438637d88
+600000004bfff285
 7fe3fb784bffffb8
-4bfff88d3bde0001
-7fde07b438600064
-4bffffb04bfffa85
-0100000000000000
-3c4c000100000680
-3d40c8003842a01c
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c09000e
-f80100107c0802a6
-3920000ef821ffa1
-7d20572a7c0004ac
-38637e483c62ffff
-600000004bfff01d
-e801001038210060
-4e8000207c0803a6
+4bfffa2d3bde0001
+4bfffb9d38600064
+000000004bffffb4
+0000068001000000
+3842a0103c4c0001
+612910003d20c800
+7c0004ac79290020
+280a000e7d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac3940000e
+3c62ffff7d404f2a
+4bfff21138637da0
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429fa83c4c0001
+612910003d20c800
+7c0004ac79290020
+280a00017d404e2a
+7c0802a64d820020
+f821ffa1f8010010
+7c0004ac39400001
+3c62ffff7d404f2a
+4bfff1a938637dc8
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429f403c4c0001
+4800190d7c0802a6
+3f80c800f821ff01
+3ea2ffff3f00c800
+3e62ffff3e82ffff
+639c08103f22ffff
+3e42ffff63180820
+3b4000013ba00000
+3ab57df03ae00000
+3a737e083a947e00
+7b9c00203b397b28
+3a527e107b180020
+7fb0eb787ba307e0
+7f56e8304bfff925
+3a2000003be00000
+7fbe07b439e00000
+7fc4f3787de507b4
+39c000207ea3ab78
+600000004bfff0f5
+3b6000007fc3f378
+3880002a4bfff855
+4bfffa497fc3f378
+39ceffff38800054
+7fc3f378f8610060
+e92100604bfffa35
+7c6400347c634a14
+5484d97e20630080
+7c8407b454896026
+7e83a3787d291a14
+4bfff0997f7b4a14
+7fc3f37860000000
+2c0e00004bfff849
+7e639b784082ffa4
+600000004bfff07d
+4bfffc997fc3f378
+4bfff0697f23cb78
+7c11d84060000000
+7dff7b784080000c
+2c0f00077f71db78
+7c0004ac4182002c
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+39ef00017ee0e72a
+3ba000014bffff28
+7fe507b44bffff00
+7e4393787fc4f378
+4bfff0117bff0020
+7a0307e060000000
+393f00014bfff80d
+420000287d2903a6
+4bfffc197fc3f378
+4bffefe97f23cb78
+2c1d000160000000
+382101004082ffb4
+7c0004ac480017b8
+7c0004ac7ec0e72a
+7c0004ac7f40c72a
+4bffffc07ee0e72a
 0100000000000000
-3c4c000100000080
-3d40c80038429fb4
-7c0004ac794a0020
-5529063e7d20562a
-4d8200202c090001
-f80100107c0802a6
-39200001f821ffa1
-7d20572a7c0004ac
-38637e703c62ffff
-600000004bffefb5
-e801001038210060
+3c4c000100001280
+7c0802a638429d64
+f821ffa1f8010010
+386000004bfffd49
+386000004bfff6fd
+386000014bfff78d
+386000014bfff6ed
+3c62ffff4bfff77d
+4bffef6938637e28
+4bfffde560000000
+382100604bfffd79
+e801001038600001
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429f4c
-f821ff61480019c1
-3f42ffff3be00000
-3b5a7ba83f02ffff
-57fd063e3b187e98
-7fa3eb783b600000
-4bfff7b53b200000
-38a000013bc00000
-7fe3fb787fc4f378
-7c7c1b784bfffc61
-4bfffd417fe3fb78
-4bffef317f43d378
-7c19e04060000000
-7fdbf3784080000c
-2c1e00077f99e378
-7fa3eb7841820020
-4bfff7b13bde0001
-4bffffb07fde07b4
-4bffff903be00001
-7fe4fb787f65db78
-3bc000007f03c378
-600000004bffeee5
-4bfff7357fa3eb78
-408200287c1ed800
-4bfffcd17fe3fb78
-4bffeec17f43d378
-2c1f000160000000
-382100a04082ffb8
-7fa3eb7848001938
-4bfff7493bde0001
-4bffffc47fde07b4
-0100000000000000
-3c4c000100000880
-7c0802a638429e44
-f821ff1148001895
-4bfffe193f60c800
-3f20c80038600000
-386000004bfff621
-4bfff6b53ee0c800
-637b101038600001
-386000014bfff609
-4bfff69d63391024
-62f710283c62ffff
-3ec2ffff38637eb0
-600000004bffee2d
-3be000003ea2ffff
-7b7b00203ba00001
-7af700207b390020
-3ad67ed83b000000
-7ffa07b43ab57ed0
-7fb1f8307fb2f830
-3a6000003b80ffff
-57f4063e3bc00000
-7e20df2a7c0004ac
-7fa0cf2a7c0004ac
-392900017bc90020
-420000f47d2903a6
-7f00df2a7c0004ac
-3a0000007e83a378
-39e000004bfff611
-7de47b7838a00000
-4bfffabd7f43d378
-7c691b787c038040
-7e09837840800008
-793000207e83a378
-392f00014bfff62d
-7d2f07b42c090008
-7c1098404082ffc8
-7fdcf3784081000c
-393e00027e138378
-7d3e07b42c090008
-600000004082ff70
-7be91764394280d0
-2c1e00007fca4aaa
-2c1cffff40800078
-7f44d3784082006c
-4bffed297ea3ab78
-7f9ee37860000000
-7e40df2a7c0004ac
-7fa0cf2a7c0004ac
-7bc900202c1e0000
-4080000839290001
-2c29000139200001
-408200443929ffff
-7f00df2a7c0004ac
-41820040283f0001
-4bfffed83be00001
-7fa0bf2a7c0004ac
-7f9ee3784bffff04
-7f44d3787fc5f378
-4bffecb97ec3b378
-4bffff9460000000
-7fa0bf2a7c0004ac
-3c62ffff4bffffac
-4bffec9938637ba8
-3c62ffff60000000
-4bffec8938637ee0
-4bfffcf960000000
-382100f04bfffc8d
-480016d838600001
-0100000000000000
-3c4c000100001180
-7c0802a638429c1c
-f821ff6148001691
-6129102c3d20c800
-792900203b200002
+7c0802a638429cf4
+f821ff51480016e5
+6129082c3d20c800
+792900203b000002
+7f004f2a7c0004ac
+3b2000033d20c800
+7929002061290830
 7f204f2a7c0004ac
-3b4000033d20c800
-7929002061291030
-7f404f2a7c0004ac
 3c62ffff3fc0c800
-38637ef03c804000
-4bffec0963de1000
-3ba0000160000000
-7bde00204bfffba5
-7fa0f72a7c0004ac
+38637e383c804000
+4bffeee163de0800
+3b80000160000000
+7bde00204bfffc89
+7f80f72a7c0004ac
 3be00000386003e8
-7c0004ac4bfff5f5
-3f80c8007fe0f72a
-639c0800386003e8
-7b9c00204bfff5dd
-7fe0e72a7c0004ac
-637b08043f60c800
+7c0004ac4bfff7f1
+386003e87fe0f72a
+4bfff7dd3f60c800
 7c0004ac7b7b0020
-3fc0c8007fe0df2a
-63de001438600000
-7bde00204bfff231
-7fe0f72a7c0004ac
-3920000c3f00c800
-7c0004ac7b180020
-386000007d20c72a
-4bfff5816063c350
-4bfff1fd38600000
+3f40c8007fe0df2a
+7b5a0020635a0004
+7fe0d72a7c0004ac
+63bd100c3fa0c800
+7c0004ac7bbd0020
+3fc0c8007fe0ef2a
+7bde002063de1010
 7fe0f72a7c0004ac
-7c0004ac3920000e
-386027107d20c72a
-386002004bfff55d
-7c0004ac4bfff1d9
+3920000c3ee0c800
+7af7002062f71000
+7d20bf2a7c0004ac
+6063c35038600000
+7c0004ac4bfff771
+7c0004ac7fe0ef2a
+3920000e7fe0f72a
+7d20bf2a7c0004ac
+4bfff74d38602710
+7c0004ac39200200
+7c0004ac7d20ef2a
+3860000f7f00f72a
+7c0004ac4bfff485
+7c0004ac7fe0ef2a
 3860000f7f20f72a
-386000004bfff205
-7c0004ac4bfff1c1
-3860000f7f40f72a
-386000064bfff1ed
-7c0004ac4bfff1a9
-3860000f7fa0f72a
-386009304bfff1d5
-7c0004ac4bfff191
+392000064bfff46d
+7d20ef2a7c0004ac
+7f80f72a7c0004ac
+4bfff4513860000f
+7c0004ac39200930
+7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff1bd
-386004004bfff4f5
-7c0004ac4bfff171
-386000037fe0f72a
-386000c84bfff19d
-4bfffc414bfff4d5
-3c8000204bfffacd
-480007a93c604000
-2c23000060000000
-7c0004ac4082001c
-7c0004ac7fa0df2a
-382100a07fa0e72a
-38c0000048001518
-3c80002038a00000
-480005693c604000
-7c0004ac60000000
-386000017fa0e72a
-000000004bffffd4
-0000088001000000
-38429a103c4c0001
+386000c84bfff435
+392004004bfff6d9
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfff41138600003
+4bfff6b5386000c8
+4bfffb954bfffddd
+3c6040003c800020
+6000000048000779
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100b07f80df2a
+480015487d2307b4
+38a0000038c00000
+3c6040003c800020
+600000004800055d
+7f80df2a7c0004ac
+4bffffd039200001
+0100000000000000
+2c24000000000980
+7869f84241820024
+7c6300d0786307e0
+5463028054630794
+786300207c634a78
+386300014e800020
+000000004bfffff4
+0000000000000000
+38429a883c4c0001
 f80100107c0802a6
 282303fff821ffa1
 7c641b7841810028
-38637f103c62ffff
-600000004bffea2d
+38637e583c62ffff
+600000004bffeca5
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffe9f138637f18
+4bffec6938637e60
 4bffffc460000000
 786465023d204000
 408000247c234840
-7863b28278855564
-38a000667c651850
-3c62ffff7ca32b92
-4bffffc838637f28
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e70
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637f387ca54b92
+38637e807ca54b92
 000000004bffffa4
 0000008001000000
-384299403c4c0001
+384299b83c4c0001
 fbe1fff87c0802a6
 f821ff91f8010010
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-4bffe95138637f48
+4bffebc938637e90
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffe93938637f58
+4bffebb138637ea0
 3821007060000000
-00000000480013e8
+00000000480013e0
 0000018001000000
-384298d83c4c0001
-4800135d7c0802a6
-3d20aaaaf821ffc1
-7c7f1b787884f082
-7c7c1b7839440001
-7c7d1b787d4903a6
-420000586129aaaa
-600000004bffe959
-7fe9fb783d00aaaa
-6108aaaa3bc00000
-408200447c29e840
-612955553d205555
-408200507c3fe840
-600000004bffe929
-614a55553d405555
-408200447c3ce840
-7fc3f37838210040
-913d000048001330
-4bffffa03bbd0004
-7c0a400081490000
-3bde00014182000c
-392900047fde07b4
-913f00004bffffa0
-4bffffa43bff0004
-7c095000813c0000
-3bde00014182000c
-3b9c00047fde07b4
-000000004bffffa0
+384299503c4c0001
+480013557c0802a6
+3d40aaaaf821ffc1
+7c7f1b7878840764
+7884f0827f832214
+7c7d1b7839040001
+7c691b787d0903a6
+42000080614aaaaa
+600000004bffebc9
+3d00aaaa7d3fe050
+7feafb787929f082
+3bc0000039290001
+6108aaaa7d2903a6
+7d3fe05042000060
+7929f0823d005555
+392900017feafb78
+7d2903a661085555
+7fffe05042000058
+600000004bffeb79
+3d2055557bfff082
+61295555395f0001
+420000407d4903a6
+7fc307b438210040
+91490000480012f8
+4bffff7839290004
+7c094000812a0000
+3bde000141820008
+4bffff8c394a0004
+394a0004910a0000
+815d00004bffffa0
+418200087c0a4800
+3bbd00043bde0001
+000000004bffffac
 0000048001000000
-384297f03c4c0001
-480012797c0802a6
+384298403c4c0001
+480012497c0802a6
 39200001f821ffc1
-2fa500007884f082
-788400207c9f07b4
-7c7d1b7839040001
+2fa50000789ff022
+7c7e1b78391f0001
 394000007d0903a6
-420000347cbe2b78
-4bffe8657bff0020
-395f000160000000
-7d4903a62fbe0000
+420000387cbd2b78
+4bffeabd7bff0020
+391f000160000000
+7d0903a62fbd0000
 3860000039200001
-4200004839000000
-4800126838210040
-7928f842419e0030
-7d2900d0792907e0
-7d2942787129d008
-7928176479470020
-7cfd412e394a0001
-4bffffa07d4a07b4
-5529043e39290001
-419e00404bffffe0
-792907e0792af842
+4200004039400000
+7c6307b438210040
+419e00284800123c
+792907e07928fc62
 7129d0087d2900d0
-792a17647d295278
-554a043e7d5d502e
-4182000c7c0a4000
-7d4307b439430001
-7d0807b439080001
-392900014bffff7c
-4bffffd05529043e
-0100000000000000
-3c4c000100000380
-7c0802a6384296ec
-480011557d800026
-f821ff5191810008
-7c7d1b782da60000
-7cd833787cbc2b78
-418e00d07899f082
-81260004eb460002
-408200542c090000
-3ec2ffff3f608020
-2e3c0000637b0003
-3be000013bc00000
-7bb700207b7b0020
-7c39f0403ad67f60
+792813a87d294278
+394a00017d5e412e
+392900014bffffa4
+419e00384bffffec
+792907e07928fc62
+7129d0087d2900d0
+792813a87d294278
+5508043e7d1e402e
+418200087c085000
+394a000138630001
+392900014bffff8c
+000000004bffffdc
+0000038001000000
+384297583c4c0001
+7d8000267c0802a6
+918100084800113d
+2e260000f821ff41
+7cba2b787c7f1b78
+789cf0827cde3378
+81260004419200c4
+2c09000082e60000
+3ec2ffff40820048
+3b6000013ba00000
+7bf800207ff9fb78
+7c3ce8403ad67ea8
 3c62ffff4082009c
-38637f607b251028
-4bfffd357ba40020
-38637ba83c62ffff
-600000004bffe6a5
-4bffe70d3ee08020
-62f7000360000000
-2d3a00002e3c0000
-3be000013bc00000
-7af700203b600000
-7c39f0407bb60020
-7fc507b47bdc0020
-2c3a00004082008c
-3c62ffff41820124
-38637f7078a51028
-4bfffccd7ba40020
-38637ba83c62ffff
-600000004bffe63d
-3b400001480000fc
-419200444bffff40
-7bff07e07be9f842
-7fffd8387fff00d0
-7bc917647fff4a78
-7ffd492e7bc50020
-4082001473c97fff
-7ee4bb7878a51028
-4bfffc757ec3b378
-4bffff203bde0001
-7bff00203bff0001
-419200504bffffcc
-7bff07e07be9f842
-7fffb8387fff00d0
-7bc917647fff4a78
-7c04f8407c9d482e
-73897fff40820038
-418a00184082001c
-7b8510283c62ffff
-38637f707ec4b378
-3bde00014bfffc19
-3bff00014bffff1c
-4bffffc07bff0020
-7f7b07b43b7b0001
-e9980008418effc4
-4182ffb82c2c0000
-5783103a7d8903a6
-f8410018e8d80010
-7fe5fb787c63ea14
-4e80042178630020
-2c230000e8410018
-382100b04182ff8c
-818100087f63db78
-48000fac7d838120
+38637ea87b851028
+4bfffd357b240020
+38637b283c62ffff
+600000004bffe91d
+600000004bffe989
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3de040
+2c17000040820084
+3c62ffff41820028
+38637eb87b051028
+4bfffcdd7be40020
+38637b283c62ffff
+600000004bffe8c5
+7f2307b4382100c0
+7d81812081810008
+3ae00001480010ac
+7b6300204bffff4c
+4bfffb917f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7ec3b3787f04c378
+3bbd00014bfffc81
+7f44d3784bffff2c
+4bfffb597ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73097fff4082ff58
+418e00184082001c
+7b0510283c62ffff
+38637eb87ea4ab78
+3bbd00014bfffc01
+4bfffef43b7b0004
 0300000000000000
-3c4c000100000a80
-7c0802a6384294d4
+3c4c000100000b80
+7c0802a638429594
 918100087d908026
-f821ff8148000f51
+f821ff7148000f89
 7c7e1b787cdd3378
 7c9f23782e3d0000
 3c62ffff7c641b78
-7cbc2b7838637f80
-600000004bffe4dd
-38637f983c62ffff
+7cbc2b7838637ec8
+600000004bffe79d
+38637ee03c62ffff
 3c62ffff4092000c
-4bffe4c138637fa8
+4bffe78138637ef0
 7fe3fb7860000000
-4bfffa657bfde8c2
-38637fb83c62ffff
-600000004bffe4a5
+4bfffaad7bfde8c2
+38637f003c62ffff
+600000004bffe765
 408200742c3c0000
 38fd00017d5602a6
 7ce903a67fc9f378
@@ -1403,467 +1315,475 @@ f821ff8148000f51
 639ce100794a0020
 7f9fe1d279290020
 3c62ffff7d295050
-7f9c4b9238637fc0
-600000004bffe455
-4bfff9fd7f83e378
-38637fd03c62ffff
-600000004bffe43d
-38637ba83c62ffff
-600000004bffe42d
-600000004bffe499
-409200287cf602a6
+7f9c4b9238637f08
+600000004bffe715
+4bfffa457f83e378
+38637f183c62ffff
+600000004bffe6fd
+38637b283c62ffff
+600000004bffe6ed
+600000004bffe759
+409200287f7602a6
 7d2903a6393d0001
-e93e000042400040
+e93e000042400030
 4bfffff43bde0008
 39290008f9090000
-7baa00204bffff74
-394a00013cc08020
-7d4903a660c60003
-3900000039200000
-4200006c78c60020
-3d2005f57c9602a6
-6129e10078e70020
-7fff49d278840020
-3c62ffff7c843850
-7fff239238637fd8
-600000004bffe3a5
-4bfff94d7fe3fb78
-38637fd03c62ffff
-600000004bffe38d
-38637ba83c62ffff
-600000004bffe37d
-8181000838210080
-48000e047d908120
-418200382c280000
-792907e0792af842
-7d2930387d2900d0
-7d49eb967d295278
-7d0807b439080001
-7d4a48507d4ae9d6
-7d5e502a794a1f48
-392900014bffff5c
-4bffffd879290020
-0300000000000000
-3c4c000100000480
-7c0802a6384292cc
-f821ff7148000d49
-282402003b400200
-7c9f23787c7e1b78
-7c9a237841810008
-7ffbfb78283f8000
-3b60ffff4081000c
-3c62ffff577b0420
-38637fe87fc4f378
-600000004bffe2c5
-4bfff86d7fe3fb78
-38637fb83c62ffff
-600000004bffe2ad
-7fc3f3787f44d378
-38a000004bfff989
-7c7c1b787f64db78
-4bfffa5d7fc3f378
-38a0000138c00000
-7c7d1b787fe4fb78
-4bfffb497fc3f378
-7d291a147d3cea14
-2c0900007c7e1b78
-3c62ffff41820068
-7f84e3787b45f882
-4bffe24938637ff8
-6000000060000000
-7fa4eb787b65f082
-4bffe23138628010
-6000000060000000
-7fc4f3787be5f082
-4bffe21938628028
-6000000060000000
-4bffe20938628040
-3860000060000000
-48000c8c38210090
-3862805060000000
-600000004bffe1ed
-4bffffe438600001
+7fbaeb784bffff74
+3b80000039400000
+4082006c7c1ae000
+3d4005f57d3602a6
+614ae1007b7b0020
+7fff51d279290020
+3c62ffff7d29d850
+7fff4b9238637f20
+600000004bffe675
+4bfff9a57fe3fb78
+38637f183c62ffff
+600000004bffe65d
+38637b283c62ffff
+600000004bffe64d
+8181000838210090
+48000e4c7d908120
+794300207f8407b4
+3b9c00014bfff925
+7c6a1b787d23eb96
+7d2918507d29e9d6
+7d3e482a79291f48
+000000004bffff68
+0000068003000000
+384293b83c4c0001
+48000db57c0802a6
+3b400200f821ff71
+7c7e1b7828240200
+418100087c9f2378
+283f80007c9a2378
+4081000c7ffbfb78
+577b04203b60ffff
+7fc4f3783c62ffff
+4bffe5b138637f30
+7fe3fb7860000000
+3c62ffff4bfff8e1
+4bffe59938637f00
+7f44d37860000000
+4bfff9fd7fc3f378
+7f64db7838a00000
+7fc3f3787c7c1b78
+38c000004bfffaf9
+7fe4fb7838a00001
+7fc3f3787c7d1b78
+7d3de2144bfffbc9
+7c7e1b787d291a14
+4182006c2c090000
+7b45f8823c62ffff
+38637f407f84e378
+600000004bffe535
+7b65f0823c62ffff
+38637f587fa4eb78
+600000004bffe51d
+7be5f0823c62ffff
+38637f707fc4f378
+600000004bffe505
+38637f883c62ffff
+600000004bffe4f5
+3821009038600000
+48000cf47c6307b4
+38637f983c62ffff
+600000004bffe4d5
+4bffffe038600001
 0100000000000000
 3c4c000100000680
-600000003842918c
-6000000039228114
-89290000394280c8
-4182002c2c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-7c0004ace92a0000
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-e94a00005469063e
-7d2057ea7c0004ac
-000000004e800020
+6000000038429274
+6000000089228018
+2c09000039428010
+e92a00004182002c
+7c0004ac39290014
+712900207d204eaa
+e92a00004182ffec
+7c604faa7c0004ac
+e92a00004e800020
+7c0004ac39290010
+712900087d204eea
+5469063e4082ffec
+7c0004ace94a0000
+4e8000207d2057ea
 0000000000000000
-384291083c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-3be3fffff821ffd1
-2c3e00008fdf0001
-3821003040820010
-48000bd038600000
-4082000c281e000a
-4bffff413860000d
-4bffff397fc3f378
-000000004bffffd0
-0000028001000000
-384290a83c4c0001
-610800203d00c000
-7c0004ac79080020
-3d20c0007d0046ea
-6129000879080600
-7c0004ac79290020
-712900207d204eea
-3d20c00041820018
-7929002061290040
+3c4c000100000000
+7c0802a6384291f4
+fbe1fff8fbc1fff0
+f821ffd1f8010010
+8fdf00013be3ffff
+408200102c1e0000
+3860000038210030
+2c1e000a48000c3c
+3860000d4082000c
+7fc307b44bffff45
+4bffffd04bffff3d
+0100000000000000
+3c4c000100000280
+3d40c00038429194
+794a0020614a0020
+7d4056ea7c0004ac
+794a06003d20c000
+7929002061290008
 7d204eea7c0004ac
-600000003d40c000
-38e2811460000000
-794a0020614a2000
-3d40001cf94280c8
-7d085392614a2000
-794a0fc3792af804
-3920000141820080
-614a200c3d40c000
-794a002099270000
-7c0004ac3920ff80
-e92280c87d2057aa
-7d004faa7c0004ac
-7908c202e92280c8
+4182001871290020
+612900403d20c000
+7c0004ac79290020
+7929f8047d204eea
+79290fc33d00c000
+7908002061082000
+f902801060000000
+610820003d00001c
+418200847d4a4392
+3920000160000000
+3d00c00099228018
+3920ff806108200c
+7c0004ac79080020
+e92280107d2047aa
+7d404faa7c0004ac
+794ac202e9228010
 7c0004ac39290004
-e92280c87d004faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e92280c8
+39290010e9228010
 7d404faa7c0004ac
-39400007e92280c8
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
-994700003d20c000
-612920183908ffff
-7c0004ac79290020
-4e8000207d004fea
+394affff60000000
+3d20c00099228018
+7929002061292018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9072442000028
+7d434a147ca92850
+7c844a1439050001
+392000007d0903a6
+4e80002042000018
+7d23512a7d24502a
+4bffffcc394a0008
+7d0a49ae7d0448ae
+4bffffdc39290001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 2c24000000000000
 3881fff040820008
 f864000028050024
 4d81002038600000
-78e783e43ce00001
-e944000060e72600
-28090020892a0000
-2c25000040810028
-2c0500104182003c
-3860000041820038
-394a000148000080
-4bffffd0f9440000
-712900017ce94c36
-2c2500004082ffec
-38a0000a4082ffdc
-38a0000a4bffffd4
-4082ffc828090030
-2c090078892a0001
-394a00024082ffbc
-f944000038a00010
-38c9ffd04bffffac
-280a000954ca063e
-7cc9073441810034
-4c8000207c092800
-7c6519d238e70001
-7c691a14f8e40000
-89270000e8e40000
-4082ffc82c290000
-3949ff9f4e800020
-280a0019554a063e
-3929ffa941810010
-4bffffbc7d290734
-554a063e3949ffbf
+6108ffff3d00fffe
+6108d9ff790883e4
+89490000e9240000
+40810028280a0020
+4182003c2c250000
+418200382c050010
+4800008838600000
+f924000039290001
+7d0a56344bffffd0
+4182ffec714a0001
+4082ffdc2c250000
+4bffffd438a0000a
+2c0a003038a0000a
+894900014082ffc8
+4082ffbc2c0a0078
+38a0001039290002
+4bffffacf9240000
+54e7063e38eaffd0
+4181003c28070009
+7d2a07343929ffd0
+4c8000207c0a2800
+7c6519d239080001
+f90400007d290734
+e90400007c691a14
+714900ff89480000
+4e8000204082ffc0
+54e7063e38eaff9f
+4181000c28070019
+4bffffb83929ffa9
+554a063e394affbf
 4d810020280a0019
-4bffffe43929ffc9
+4bffffa03929ffc9
 0000000000000000
-7c6a1b7800000000
-7d2a18ae38600000
-4d8200202c090000
-4bfffff038630001
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000307d2903a6
-78aa072478a9e8c2
-7d0352141d29fff8
-7ca92a147c845214
-3945000139200000
-420000187d4903a6
-7d24502a4e800020
-394a00087d23512a
-7d4448ae4bffffc4
-392900017d4849ae
-000000004bffffdc
-0000000000000000
-280900193923ff9f
-3863ffe04d810020
-4e8000207c6307b4
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428da4
-918100087d908026
-f821ffa148000819
-7c7c1b783be00000
-600000007cbe2b78
-7cdd3378e9228060
-60000000f9210020
-f9210028e9228068
-2c2900007ca92b78
-2c3f000040820034
-3be0000140820008
-2e2700007c3f2040
-3b7fffff38600000
-3821006040810038
-7d90812081810008
-281d001048000800
-7929e10240820014
-7fff07b43bff0001
-7d29eb924bffffb4
-7f5ed3784bfffff0
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-600000004bffff21
-7c3df0405463063e
-7c69d9aee93c0000
-4081ffc83b7bffff
-38600001e93c0000
-fbfc00007fe9fa14
-000000004bffff84
-0000068003000000
-38428ca83c4c0001
-480007297c0802a6
+38428e903c4c0001
+480008897c0802a6
+7c7e1b78f821ffa1
+7ca32b787c9c2378
+38a0000a38800000
+eb3e00007cfd3b78
+7d3a4b787d1b4378
+4bfffe797cdf3378
+2b9d001060000000
+7c681b7839200000
+408200242c3f0000
+408200082c090000
+7d29d21439200001
+418100547c034800
+4800087038210060
+7bffe102409e0010
+4bffffcc39290001
+4bfffff47fffeb92
+2c2a00019b690000
+e93e0000394affff
+f93e000039290001
+e93e00004182ffc8
+7c28e0407d194850
+4bffffb44180ffd8
+2c0900007d294050
+794a00203949ffff
+40810010394a0001
+7c0940003d008000
+394000014082ffcc
+000000004bffffc4
+0000078001000000
+38428d983c4c0001
+480007997c0802a6
 3bc00000f821ffb1
 7c9c23787c7f1b78
 7cbd2b78eb630000
-4bfffe217fa3eb78
-7c23f04060000000
-e95f000040810014
-7c29e0407d3b5050
-3821005041800010
-4800073038600001
-3bde00017d3df0ae
-e93f0000992a0000
-f93f000039290001
-000000004bffffb8
-0000058001000000
-38428c283c4c0001
-480006a17c0802a6
-7c7d1b78f821ffa1
-7ca32b787c9b2378
-38a0000a38800000
-eb3d00007d3f4b78
-7cfc3b787cde3378
-4bfffc717d1a4378
-3920000060000000
-2c3e00007c6307b4
-2c2900004082002c
-3920000140820008
-7c0348007d3f4a14
-418100607d2a07b4
-3860000038210060
-281c001048000684
-7bdee10240820014
-7d2907b439290001
-7fdee3924bffffbc
-9b4800004bfffff0
-3929ffff2c290001
-394a0001e95d0000
-4182ffbcf95d0000
-7d594050e91d0000
-4180ffd87c2ad840
-7d4a18504bffffa8
-392affff2c0a0000
-3929000179290020
-3c60800040810010
-4082ffcc7c0a1800
-4bffffc439200001
+4bfffd697fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007a4
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428b24
-f821fed148000571
-f86100607c741b79
-4182006438600000
-4182005c2c240000
-6000000039210040
-3ae4ffff60000000
-3b210020f9210078
-3a4280803ac00000
-3a2280783ba10060
+3c4c000100000580
+7c0802a638428d1c
+918100087d908026
+f821ffa148000711
+2b8600103be00000
+3d22ffff7c7c1b78
+7cbe2b78e9297fa8
+7caa2b787cdd3378
+3d22fffff9210020
+f9210028e9297fb0
+408200342c2a0000
+408200082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8181000838210060
+480006f47d908120
+794ae102409e0010
+4bffffbc3bff0001
+4bfffff47d4aeb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdad
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428c283c4c0001
+480005f57c0802a6
+3be00000f821fee1
+f86100607c691b79
+41820060f9210068
+418200582c240000
+3e62ffff39210040
+3ae4ffff3e22ffff
+3b010020f9210070
+3a4000203ac00000
+3ba100603a737fc8
+e94100683a317fc0
 ebc1006089250000
-418200102c290000
-7c3fb8407ff4f050
-3920000041800020
-e8610060993e0000
-7e8307b47e941850
-4800054438210130
-3945000128090025
-38e00000408204c4
-e901007889250000
-7cea07b4f8a10068
-390700017d2741ae
-7d0807b48d250001
-4182005828090064
-4182005028090069
-4182004828090075
-4182004028090078
-4182003828090058
-4182003028090070
-4182002828090063
-4182002028090073
-4182001828090025
-418200102809004f
-38e700012809006f
-394a00024082ff88
-7d4a07b428090025
-7d5952147d194214
-9aca002099280020
-393e000140820020
-39200025f9210060
-e9210068993e0000
-4bffff0438a90002
-eb66000039260008
-3a6000207fffb850
-f92100703b010041
-3929ffd289210041
+712a00ff7feaf050
+7c3fb8404182000c
+3920000041800018
+38210120993e0000
+480005c47fe307b4
+390500012c0a0025
+38e0000040820548
+e901007089250000
+7cea3b787cb02b78
+7d2741ae8c650001
+5469063e39070001
+418200b02c090064
+4181002c28090078
+4181002c28090068
+418200982c090058
+4181008828090058
+418200882c090025
+418200802c09004f
+4bffffa438e70001
+548b063e3883ff97
+4181ffec280b000f
+396b75043d62ffff
+7c8b22aa788415a8
+7c8903a67c845a14
+000000484e800420
+ffffffccffffffcc
+ffffffccffffffcc
+00000048ffffffcc
+ffffffcc00000048
+00000048ffffffcc
+00000048ffffffcc
+ffffffccffffffcc
+2c09006300000048
+394a00024bffff84
+7d0807b42c090025
+7d1842147d4a07b4
+986800207d585214
+408200189aca0020
+993e0000395e0001
+38b00002f9410060
+892100414bfffeb4
+7fffb850eb860000
+3aa0002039e60008
+3929ffd23b210041
 4082000c712900fd
-3b0100423a600030
-3b4000043aa00000
-3a0000013b800000
-7ddb00d039e0002d
-2809004f48000164
-3898000188f80001
-38c9ffa8418201d0
-2805002254c5063e
-3ca2ffff41810370
-78c615a838a576b8
-7cc62a147cc532aa
-4e8004207cc903a6
-0000035000000148
-0000035000000350
-0000035000000350
-0000035000000350
-0000035000000350
-0000024400000350
-000003500000008c
-0000035000000350
-0000008c00000338
-0000035000000350
-0000035000000328
-000001a000000350
-00000350000001ec
-0000028400000350
-0000008c00000350
-0000035000000350
-000003500000014c
-2809007500000330
-9aca00207d41e214
-418200347f6adb78
-3929ffff57491838
-7f6948397e094836
-99e8000041820020
-39290001e9210060
-7b491f24f9210060
-7dca50387d52482a
+3b2100423aa00030
+3b4000043a800000
+56b5063e3b600000
+480001687ddc00d0
+38b900012c06004f
+38e8ffa8418201dc
+2804002254e4063e
+3c82ffff418103ac
+78e715a838847600
+7ce722147ce43aaa
+4e8004207ce903a6
+0000038c00000150
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+0000038c0000038c
+000002580000038c
+0000038c0000008c
+0000038c0000038c
+0000008c00000370
+0000038c0000038c
+0000038c0000035c
+000001ac0000038c
+0000038c000001fc
+000002980000038c
+0000008c0000038c
+0000038c0000038c
+0000038c00000154
+2c06007500000368
+7d4152147b6a0020
+7f8ae3789aca0020
+5747183841820038
+38e7ffff39000001
+7f8840397d083836
+3940002d41820020
+9949ffff39290001
+7b491e68f9210060
+7dca50387d53482a
 7d465378e8810060
-f941008038e0000a
-392000007f25cb78
-7fa3eb787e689b78
+f941007838e0000a
+392000007f05c378
+7fa3eb787ea8ab78
 7c84f8507c9e2050
-e88100604bfffc31
-7ea7ab78e9410080
+e88100604bfffa79
+7a8707e0e9410078
 7c9e205038c0000a
 7c84f8507d455378
-4bfffa917fa3eb78
-893800003b180001
-2c290000e9010060
-7d5e405041820010
-4181fe887c3f5040
-4bfffe28e8c10070
-7d21e2143aa00001
-7c8af85038e00010
-9ac900207e689b78
-7f25cb787b491f24
-7d72482a7fa3eb78
-7f6b583839200000
-f96100807d665b78
-e88100604bfffba9
-38c000107ea7ab78
-e96100807c9e2050
-4bffff787d655b78
-38e000087d21e214
-7e689b787c8af850
-7b491f249ac90020
-7fa3eb787f25cb78
-392000007d72482a
-7d665b787f6b5838
-4bfffb55f9610080
-7ea7ab78e8810060
+4bfffbc97fa3eb78
+891900003b390001
+710600ffe9210060
+7d5e485041820010
+4181fe847c3f5040
+4bfffe307de67b78
+7b6900203a800001
+7d214a1438e00010
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff9edf9610078
+7a8707e0e8810060
+7c9e205038c00010
+7d655b78e9610078
+7b6900204bffff74
+7d214a1438e00008
+7ea8ab787c8af850
+9ac900207f05c378
+7fa3eb787b491e68
+392000007d73482a
+7d665b787f8b5838
+4bfff995f9610078
+7a8707e0e8810060
 7c9e205038c00008
-7d21e2144bffffac
-7f66db7838e00010
-9ac900207c8af850
-3920000239000020
-7fa3eb787f25cb78
-e88100604bfffb19
-7fa3eb787e258b78
+7b6900204bffffa8
+7d214a1438e00010
+7c8af8507f86e378
+9ac9002039000020
+392000027f05c378
+4bfff9557fa3eb78
+7e258b78e8810060
+7c9e20507fa3eb78
+4bfffa357c84f850
+7a8707e0e8810060
+7f85e37838c00010
+4bfffec87c9e2050
+390000207b690020
+38e0000a7d214a14
+7f05c37838c00001
+7c8af8509ac90020
+7fa3eb7839200000
+e92100604bfff8f9
+392900019b890000
+4bfffe94f9210060
+38a0000a7b680020
+f9410080f9210088
+388000007d014214
+9ac800207f03c378
+600000004bfff76d
+7f83e378f8610078
+600000004bfff735
+e9410080e9010078
+7c281840e9210088
+e88100604181003c
+7fa3eb787f85e378
 7c84f8507c9e2050
-e88100604bfffa81
-38c000107ea7ab78
-7c9e20507f65db78
-7d21e2144bfffed4
-38e0000a39000020
-9ac9002038c00001
-392000007f25cb78
-7fa3eb787c8af850
-e92100604bfffac1
-e92100609b690000
-f921006039290001
-7d21e2144bfffea0
-f901009038a0000a
-38800000f9410088
-9ac900207f23cb78
-600000004bfff72d
-7f63db78f8610080
-600000004bfff83d
-7c291840e9210080
-7d2348514081004c
-e9010090e9410088
-408200087d4af850
-e8c1006039200001
-7c2a38407ce83050
-38e0002040810024
-3929ffff2c290001
-e8e1006098e60000
-f8e1006038e70001
-e88100604082ffd4
-7fa3eb787f65db78
-7c84f8507c9e2050
-4bfffdfc4bfff989
-418200482807006c
-4bfffdec3b400008
-3b40000228070068
-7c9823784082fde0
-4bfffdd43b400001
-554a063e3949ffd0
-4181fdc4280a0009
-7f81e214395c0001
-795c0020993c0020
-7c9823784bfffdb0
-993e00004bffffb8
-e92100607d455378
-f921006039290001
-000000004bfffae8
+4bfffe2c4bfff979
+392900019a490000
+7c29184039000001
+f921006040820034
+7ce9f0504bffffcc
+7ce7fa147c634050
+2c2700007d4af850
+390000007c691a14
+40820008394a0001
+2c2a000139400001
+4082ffb4394affff
+4082ffc071080001
+893900014bffff8c
+4182004c2c09006c
+4bfffdbc3b400008
+3b40000289390001
+4082fdac2c090068
+3b4000017cb92b78
+3928ffd04bfffda0
+280900095529063e
+7b6900204181fd90
+7d214a143b7b0001
+4bfffd7c99090020
+4bffffb47cb92b78
+3bde0001993e0000
+fbc100607d054378
+000000004bfffa6c
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -1938,9 +1858,8 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-3536373832306564
+2d2d2d2d2d2d2d2d
 0000000000000000
-0032363263623561
 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -1982,10 +1901,6 @@ ebe1fff8e8010010
 20676e69746f6f42
 415244206d6f7266
 0000000a2e2e2e4d
-62202c64256d2020
-007c203a64323025
-0000000000006425
-000000000000207c
 203a7379616c6564
 000000000000002d
 203a7379616c6564
@@ -2001,15 +1916,13 @@ ebe1fff8e8010010
 7764726168206f74
 746e6f6320657261
 0000000a2e6c6f72
+62202c64256d2020
+007c203a64323025
+0000000000006425
+000000000000207c
 203a747365622020
 302562202c64256d
 6000000000206432
-616c206574697257
-61632079636e6574
-6f6974617262696c
-00000000000a3a6e
-0000202d3a64256d
-002064253a64256d
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v
index 166195f..233a914 100644
--- a/litedram/generated/wukong-v2/litedram_core.v
+++ b/litedram/generated/wukong-v2/litedram_core.v
@@ -1,9 +1,25 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:40
-//--------------------------------------------------------------------------------
-module litedram_core(
-	input wire clk,
-	input wire rst,
+// -----------------------------------------------------------------------------
+// Auto-Generated by:        __   _ __      _  __
+//                          / /  (_) /____ | |/_/
+//                         / /__/ / __/ -_)>  <
+//                        /____/_/\__/\__/_/|_|
+//                     Build your hardware, easily!
+//                   https://github.com/enjoy-digital/litex
+//
+// Filename   : litedram_core.v
+// Device     : 
+// LiteX sha1 : --------
+// Date       : 2022-01-14 08:32:15
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+	input  wire clk,
+	input  wire rst,
 	output wire pll_locked,
 	output wire [13:0] ddram_a,
 	output wire [2:0] ddram_ba,
@@ -12,9 +28,9 @@ module litedram_core(
 	output wire ddram_we_n,
 	output wire ddram_cs_n,
 	output wire [1:0] ddram_dm,
-	inout wire [15:0] ddram_dq,
-	inout wire [1:0] ddram_dqs_p,
-	inout wire [1:0] ddram_dqs_n,
+	inout  wire [15:0] ddram_dq,
+	inout  wire [1:0] ddram_dqs_p,
+	inout  wire [1:0] ddram_dqs_n,
 	output wire ddram_clk_p,
 	output wire ddram_clk_n,
 	output wire ddram_cke,
@@ -22,32 +38,38 @@ module litedram_core(
 	output wire ddram_reset_n,
 	output wire init_done,
 	output wire init_error,
-	input wire [29:0] wb_ctrl_adr,
-	input wire [31:0] wb_ctrl_dat_w,
+	input  wire [29:0] wb_ctrl_adr,
+	input  wire [31:0] wb_ctrl_dat_w,
 	output wire [31:0] wb_ctrl_dat_r,
-	input wire [3:0] wb_ctrl_sel,
-	input wire wb_ctrl_cyc,
-	input wire wb_ctrl_stb,
+	input  wire [3:0] wb_ctrl_sel,
+	input  wire wb_ctrl_cyc,
+	input  wire wb_ctrl_stb,
 	output wire wb_ctrl_ack,
-	input wire wb_ctrl_we,
-	input wire [2:0] wb_ctrl_cti,
-	input wire [1:0] wb_ctrl_bte,
+	input  wire wb_ctrl_we,
+	input  wire [2:0] wb_ctrl_cti,
+	input  wire [1:0] wb_ctrl_bte,
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input wire user_port_native_0_cmd_valid,
+	input  wire user_port_native_0_cmd_valid,
 	output wire user_port_native_0_cmd_ready,
-	input wire user_port_native_0_cmd_we,
-	input wire [23:0] user_port_native_0_cmd_addr,
-	input wire user_port_native_0_wdata_valid,
+	input  wire user_port_native_0_cmd_we,
+	input  wire [23:0] user_port_native_0_cmd_addr,
+	input  wire user_port_native_0_wdata_valid,
 	output wire user_port_native_0_wdata_ready,
-	input wire [15:0] user_port_native_0_wdata_we,
-	input wire [127:0] user_port_native_0_wdata_data,
+	input  wire [15:0] user_port_native_0_wdata_we,
+	input  wire [127:0] user_port_native_0_wdata_data,
 	output wire user_port_native_0_rdata_valid,
-	input wire user_port_native_0_rdata_ready,
+	input  wire user_port_native_0_rdata_ready,
 	output wire [127:0] user_port_native_0_rdata_data
 );
 
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg  main_rst = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
@@ -55,7 +77,7 @@ wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
 wire main_reset;
-reg main_power_down = 1'd0;
+reg  main_power_down = 1'd0;
 wire main_locked;
 wire main_clkin;
 wire main_clkout0;
@@ -66,48 +88,48 @@ wire main_clkout2;
 wire main_clkout_buf2;
 wire main_clkout3;
 wire main_clkout_buf3;
-reg [3:0] main_reset_counter = 4'd15;
-reg main_ic_reset = 1'd1;
-reg main_a7ddrphy_rst_storage = 1'd0;
-reg main_a7ddrphy_rst_re = 1'd0;
-reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg main_a7ddrphy_wlevel_en_re = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg  [3:0] main_reset_counter = 4'd15;
+reg  main_ic_reset = 1'd1;
+reg  main_a7ddrphy_rst_storage = 1'd0;
+reg  main_a7ddrphy_rst_re = 1'd0;
+reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
+reg  main_a7ddrphy_wlevel_en_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
 wire main_a7ddrphy_wlevel_strobe_r;
-reg main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg main_a7ddrphy_dly_sel_re = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+reg  main_a7ddrphy_dly_sel_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_rst_r;
-reg main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_inc_r;
-reg main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
 wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg main_a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg main_a7ddrphy_wrphase_re = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg  main_a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+reg  main_a7ddrphy_wrphase_re = 1'd0;
 wire [13:0] main_a7ddrphy_dfi_p0_address;
 wire [2:0] main_a7ddrphy_dfi_p0_bank;
 wire main_a7ddrphy_dfi_p0_cas_n;
@@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
 wire main_a7ddrphy_dfi_p0_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
 wire main_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p0_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p1_address;
 wire [2:0] main_a7ddrphy_dfi_p1_bank;
@@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
 wire main_a7ddrphy_dfi_p1_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
 wire main_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p1_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p2_address;
 wire [2:0] main_a7ddrphy_dfi_p2_bank;
@@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
 wire main_a7ddrphy_dfi_p2_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
 wire main_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p2_rddata_valid;
 wire [13:0] main_a7ddrphy_dfi_p3_address;
 wire [2:0] main_a7ddrphy_dfi_p3_bank;
@@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
 wire main_a7ddrphy_dfi_p3_wrdata_en;
 wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
 wire main_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
 wire main_a7ddrphy_dfi_p3_rddata_valid;
 wire main_a7ddrphy_sd_clk_se_nodelay;
-reg main_a7ddrphy_dqs_oe = 1'd0;
+reg  main_a7ddrphy_dqs_oe = 1'd0;
 wire main_a7ddrphy_dqs_preamble;
 wire main_a7ddrphy_dqs_postamble;
 wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_dqspattern0 = 1'd0;
-reg main_a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dqspattern0 = 1'd0;
+reg  main_a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
 wire main_a7ddrphy_dqs_o_no_delay0;
 wire main_a7ddrphy_dqs_t0;
-reg [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
 wire main_a7ddrphy0;
 wire main_a7ddrphy_dqs_o_no_delay1;
 wire main_a7ddrphy_dqs_t1;
-reg [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
 wire main_a7ddrphy1;
-reg [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
 wire main_a7ddrphy_dq_oe;
 wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
 wire main_a7ddrphy_dq_o_nodelay0;
 wire main_a7ddrphy_dq_i_nodelay0;
 wire main_a7ddrphy_dq_i_delayed0;
 wire main_a7ddrphy_dq_t0;
-reg [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip03;
-reg [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay1;
 wire main_a7ddrphy_dq_i_nodelay1;
 wire main_a7ddrphy_dq_i_delayed1;
 wire main_a7ddrphy_dq_t1;
-reg [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip13;
-reg [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay2;
 wire main_a7ddrphy_dq_i_nodelay2;
 wire main_a7ddrphy_dq_i_delayed2;
 wire main_a7ddrphy_dq_t2;
-reg [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip21;
-reg [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay3;
 wire main_a7ddrphy_dq_i_nodelay3;
 wire main_a7ddrphy_dq_i_delayed3;
 wire main_a7ddrphy_dq_t3;
-reg [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip31;
-reg [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay4;
 wire main_a7ddrphy_dq_i_nodelay4;
 wire main_a7ddrphy_dq_i_delayed4;
 wire main_a7ddrphy_dq_t4;
-reg [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip41;
-reg [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay5;
 wire main_a7ddrphy_dq_i_nodelay5;
 wire main_a7ddrphy_dq_i_delayed5;
 wire main_a7ddrphy_dq_t5;
-reg [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip51;
-reg [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay6;
 wire main_a7ddrphy_dq_i_nodelay6;
 wire main_a7ddrphy_dq_i_delayed6;
 wire main_a7ddrphy_dq_t6;
-reg [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip61;
-reg [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay7;
 wire main_a7ddrphy_dq_i_nodelay7;
 wire main_a7ddrphy_dq_i_delayed7;
 wire main_a7ddrphy_dq_t7;
-reg [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip71;
-reg [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay8;
 wire main_a7ddrphy_dq_i_nodelay8;
 wire main_a7ddrphy_dq_i_delayed8;
 wire main_a7ddrphy_dq_t8;
-reg [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip81;
-reg [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay9;
 wire main_a7ddrphy_dq_i_nodelay9;
 wire main_a7ddrphy_dq_i_delayed9;
 wire main_a7ddrphy_dq_t9;
-reg [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip91;
-reg [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay10;
 wire main_a7ddrphy_dq_i_nodelay10;
 wire main_a7ddrphy_dq_i_delayed10;
 wire main_a7ddrphy_dq_t10;
-reg [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip101;
-reg [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay11;
 wire main_a7ddrphy_dq_i_nodelay11;
 wire main_a7ddrphy_dq_i_delayed11;
 wire main_a7ddrphy_dq_t11;
-reg [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip111;
-reg [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay12;
 wire main_a7ddrphy_dq_i_nodelay12;
 wire main_a7ddrphy_dq_i_delayed12;
 wire main_a7ddrphy_dq_t12;
-reg [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip121;
-reg [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay13;
 wire main_a7ddrphy_dq_i_nodelay13;
 wire main_a7ddrphy_dq_i_delayed13;
 wire main_a7ddrphy_dq_t13;
-reg [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip131;
-reg [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay14;
 wire main_a7ddrphy_dq_i_nodelay14;
 wire main_a7ddrphy_dq_i_delayed14;
 wire main_a7ddrphy_dq_t14;
-reg [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip141;
-reg [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
 wire main_a7ddrphy_dq_o_nodelay15;
 wire main_a7ddrphy_dq_i_nodelay15;
 wire main_a7ddrphy_dq_i_delayed15;
 wire main_a7ddrphy_dq_t15;
-reg [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
 wire [7:0] main_a7ddrphy_bitslip151;
-reg [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 wire [13:0] main_litedramcore_inti_p0_address;
 wire [2:0] main_litedramcore_inti_p0_bank;
-reg main_litedramcore_inti_p0_cas_n = 1'd1;
-reg main_litedramcore_inti_p0_cs_n = 1'd1;
-reg main_litedramcore_inti_p0_ras_n = 1'd1;
-reg main_litedramcore_inti_p0_we_n = 1'd1;
+reg  main_litedramcore_inti_p0_cas_n = 1'd1;
+reg  main_litedramcore_inti_p0_cs_n = 1'd1;
+reg  main_litedramcore_inti_p0_ras_n = 1'd1;
+reg  main_litedramcore_inti_p0_we_n = 1'd1;
 wire main_litedramcore_inti_p0_cke;
 wire main_litedramcore_inti_p0_odt;
 wire main_litedramcore_inti_p0_reset_n;
-reg main_litedramcore_inti_p0_act_n = 1'd1;
+reg  main_litedramcore_inti_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p0_wrdata;
 wire main_litedramcore_inti_p0_wrdata_en;
 wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
 wire main_litedramcore_inti_p0_rddata_en;
-reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
+reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p1_address;
 wire [2:0] main_litedramcore_inti_p1_bank;
-reg main_litedramcore_inti_p1_cas_n = 1'd1;
-reg main_litedramcore_inti_p1_cs_n = 1'd1;
-reg main_litedramcore_inti_p1_ras_n = 1'd1;
-reg main_litedramcore_inti_p1_we_n = 1'd1;
+reg  main_litedramcore_inti_p1_cas_n = 1'd1;
+reg  main_litedramcore_inti_p1_cs_n = 1'd1;
+reg  main_litedramcore_inti_p1_ras_n = 1'd1;
+reg  main_litedramcore_inti_p1_we_n = 1'd1;
 wire main_litedramcore_inti_p1_cke;
 wire main_litedramcore_inti_p1_odt;
 wire main_litedramcore_inti_p1_reset_n;
-reg main_litedramcore_inti_p1_act_n = 1'd1;
+reg  main_litedramcore_inti_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p1_wrdata;
 wire main_litedramcore_inti_p1_wrdata_en;
 wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
 wire main_litedramcore_inti_p1_rddata_en;
-reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
+reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p2_address;
 wire [2:0] main_litedramcore_inti_p2_bank;
-reg main_litedramcore_inti_p2_cas_n = 1'd1;
-reg main_litedramcore_inti_p2_cs_n = 1'd1;
-reg main_litedramcore_inti_p2_ras_n = 1'd1;
-reg main_litedramcore_inti_p2_we_n = 1'd1;
+reg  main_litedramcore_inti_p2_cas_n = 1'd1;
+reg  main_litedramcore_inti_p2_cs_n = 1'd1;
+reg  main_litedramcore_inti_p2_ras_n = 1'd1;
+reg  main_litedramcore_inti_p2_we_n = 1'd1;
 wire main_litedramcore_inti_p2_cke;
 wire main_litedramcore_inti_p2_odt;
 wire main_litedramcore_inti_p2_reset_n;
-reg main_litedramcore_inti_p2_act_n = 1'd1;
+reg  main_litedramcore_inti_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p2_wrdata;
 wire main_litedramcore_inti_p2_wrdata_en;
 wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
 wire main_litedramcore_inti_p2_rddata_en;
-reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
+reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_inti_p3_address;
 wire [2:0] main_litedramcore_inti_p3_bank;
-reg main_litedramcore_inti_p3_cas_n = 1'd1;
-reg main_litedramcore_inti_p3_cs_n = 1'd1;
-reg main_litedramcore_inti_p3_ras_n = 1'd1;
-reg main_litedramcore_inti_p3_we_n = 1'd1;
+reg  main_litedramcore_inti_p3_cas_n = 1'd1;
+reg  main_litedramcore_inti_p3_cs_n = 1'd1;
+reg  main_litedramcore_inti_p3_ras_n = 1'd1;
+reg  main_litedramcore_inti_p3_we_n = 1'd1;
 wire main_litedramcore_inti_p3_cke;
 wire main_litedramcore_inti_p3_odt;
 wire main_litedramcore_inti_p3_reset_n;
-reg main_litedramcore_inti_p3_act_n = 1'd1;
+reg  main_litedramcore_inti_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_inti_p3_wrdata;
 wire main_litedramcore_inti_p3_wrdata_en;
 wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
 wire main_litedramcore_inti_p3_rddata_en;
-reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
+reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p0_address;
 wire [2:0] main_litedramcore_slave_p0_bank;
 wire main_litedramcore_slave_p0_cas_n;
@@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata;
 wire main_litedramcore_slave_p0_wrdata_en;
 wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
 wire main_litedramcore_slave_p0_rddata_en;
-reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p1_address;
 wire [2:0] main_litedramcore_slave_p1_bank;
 wire main_litedramcore_slave_p1_cas_n;
@@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata;
 wire main_litedramcore_slave_p1_wrdata_en;
 wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
 wire main_litedramcore_slave_p1_rddata_en;
-reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p2_address;
 wire [2:0] main_litedramcore_slave_p2_bank;
 wire main_litedramcore_slave_p2_cas_n;
@@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata;
 wire main_litedramcore_slave_p2_wrdata_en;
 wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
 wire main_litedramcore_slave_p2_rddata_en;
-reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
 wire [13:0] main_litedramcore_slave_p3_address;
 wire [2:0] main_litedramcore_slave_p3_bank;
 wire main_litedramcore_slave_p3_cas_n;
@@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata;
 wire main_litedramcore_slave_p3_wrdata_en;
 wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
 wire main_litedramcore_slave_p3_rddata_en;
-reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] main_litedramcore_master_p0_address = 14'd0;
-reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg main_litedramcore_master_p0_cas_n = 1'd1;
-reg main_litedramcore_master_p0_cs_n = 1'd1;
-reg main_litedramcore_master_p0_ras_n = 1'd1;
-reg main_litedramcore_master_p0_we_n = 1'd1;
-reg main_litedramcore_master_p0_cke = 1'd0;
-reg main_litedramcore_master_p0_odt = 1'd0;
-reg main_litedramcore_master_p0_reset_n = 1'd0;
-reg main_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p0_rddata_en = 1'd0;
+reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [13:0] main_litedramcore_master_p0_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg  main_litedramcore_master_p0_cas_n = 1'd1;
+reg  main_litedramcore_master_p0_cs_n = 1'd1;
+reg  main_litedramcore_master_p0_ras_n = 1'd1;
+reg  main_litedramcore_master_p0_we_n = 1'd1;
+reg  main_litedramcore_master_p0_cke = 1'd0;
+reg  main_litedramcore_master_p0_odt = 1'd0;
+reg  main_litedramcore_master_p0_reset_n = 1'd0;
+reg  main_litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p0_rddata;
 wire main_litedramcore_master_p0_rddata_valid;
-reg [13:0] main_litedramcore_master_p1_address = 14'd0;
-reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg main_litedramcore_master_p1_cas_n = 1'd1;
-reg main_litedramcore_master_p1_cs_n = 1'd1;
-reg main_litedramcore_master_p1_ras_n = 1'd1;
-reg main_litedramcore_master_p1_we_n = 1'd1;
-reg main_litedramcore_master_p1_cke = 1'd0;
-reg main_litedramcore_master_p1_odt = 1'd0;
-reg main_litedramcore_master_p1_reset_n = 1'd0;
-reg main_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p1_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p1_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg  main_litedramcore_master_p1_cas_n = 1'd1;
+reg  main_litedramcore_master_p1_cs_n = 1'd1;
+reg  main_litedramcore_master_p1_ras_n = 1'd1;
+reg  main_litedramcore_master_p1_we_n = 1'd1;
+reg  main_litedramcore_master_p1_cke = 1'd0;
+reg  main_litedramcore_master_p1_odt = 1'd0;
+reg  main_litedramcore_master_p1_reset_n = 1'd0;
+reg  main_litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p1_rddata;
 wire main_litedramcore_master_p1_rddata_valid;
-reg [13:0] main_litedramcore_master_p2_address = 14'd0;
-reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg main_litedramcore_master_p2_cas_n = 1'd1;
-reg main_litedramcore_master_p2_cs_n = 1'd1;
-reg main_litedramcore_master_p2_ras_n = 1'd1;
-reg main_litedramcore_master_p2_we_n = 1'd1;
-reg main_litedramcore_master_p2_cke = 1'd0;
-reg main_litedramcore_master_p2_odt = 1'd0;
-reg main_litedramcore_master_p2_reset_n = 1'd0;
-reg main_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p2_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p2_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg  main_litedramcore_master_p2_cas_n = 1'd1;
+reg  main_litedramcore_master_p2_cs_n = 1'd1;
+reg  main_litedramcore_master_p2_ras_n = 1'd1;
+reg  main_litedramcore_master_p2_we_n = 1'd1;
+reg  main_litedramcore_master_p2_cke = 1'd0;
+reg  main_litedramcore_master_p2_odt = 1'd0;
+reg  main_litedramcore_master_p2_reset_n = 1'd0;
+reg  main_litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p2_rddata;
 wire main_litedramcore_master_p2_rddata_valid;
-reg [13:0] main_litedramcore_master_p3_address = 14'd0;
-reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg main_litedramcore_master_p3_cas_n = 1'd1;
-reg main_litedramcore_master_p3_cs_n = 1'd1;
-reg main_litedramcore_master_p3_ras_n = 1'd1;
-reg main_litedramcore_master_p3_we_n = 1'd1;
-reg main_litedramcore_master_p3_cke = 1'd0;
-reg main_litedramcore_master_p3_odt = 1'd0;
-reg main_litedramcore_master_p3_reset_n = 1'd0;
-reg main_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg main_litedramcore_master_p3_rddata_en = 1'd0;
+reg  [13:0] main_litedramcore_master_p3_address = 14'd0;
+reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg  main_litedramcore_master_p3_cas_n = 1'd1;
+reg  main_litedramcore_master_p3_cs_n = 1'd1;
+reg  main_litedramcore_master_p3_ras_n = 1'd1;
+reg  main_litedramcore_master_p3_we_n = 1'd1;
+reg  main_litedramcore_master_p3_cke = 1'd0;
+reg  main_litedramcore_master_p3_odt = 1'd0;
+reg  main_litedramcore_master_p3_reset_n = 1'd0;
+reg  main_litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  main_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_master_p3_rddata;
 wire main_litedramcore_master_p3_rddata_valid;
 wire main_litedramcore_sel;
 wire main_litedramcore_cke;
 wire main_litedramcore_odt;
 wire main_litedramcore_reset_n;
-reg [3:0] main_litedramcore_storage = 4'd1;
-reg main_litedramcore_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg  [3:0] main_litedramcore_storage = 4'd1;
+reg  main_litedramcore_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector0_command_issue_r;
-reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector0_rddata_we;
-reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector1_command_issue_r;
-reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector1_rddata_we;
-reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector2_command_issue_r;
-reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector2_rddata_we;
-reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
 wire main_litedramcore_phaseinjector3_command_issue_r;
-reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
 wire main_litedramcore_phaseinjector3_rddata_we;
-reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
 wire main_litedramcore_interface_bank0_valid;
 wire main_litedramcore_interface_bank0_ready;
 wire main_litedramcore_interface_bank0_we;
@@ -706,131 +728,131 @@ wire [20:0] main_litedramcore_interface_bank7_addr;
 wire main_litedramcore_interface_bank7_lock;
 wire main_litedramcore_interface_bank7_wdata_ready;
 wire main_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
 wire [127:0] main_litedramcore_interface_rdata;
-reg [13:0] main_litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg main_litedramcore_dfi_p0_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p0_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p0_we_n = 1'd1;
 wire main_litedramcore_dfi_p0_cke;
 wire main_litedramcore_dfi_p0_odt;
 wire main_litedramcore_dfi_p0_reset_n;
-reg main_litedramcore_dfi_p0_act_n = 1'd1;
+reg  main_litedramcore_dfi_p0_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p0_rddata;
 wire main_litedramcore_dfi_p0_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg main_litedramcore_dfi_p1_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p1_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p1_we_n = 1'd1;
 wire main_litedramcore_dfi_p1_cke;
 wire main_litedramcore_dfi_p1_odt;
 wire main_litedramcore_dfi_p1_reset_n;
-reg main_litedramcore_dfi_p1_act_n = 1'd1;
+reg  main_litedramcore_dfi_p1_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p1_rddata;
 wire main_litedramcore_dfi_p1_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg main_litedramcore_dfi_p2_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p2_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p2_we_n = 1'd1;
 wire main_litedramcore_dfi_p2_cke;
 wire main_litedramcore_dfi_p2_odt;
 wire main_litedramcore_dfi_p2_reset_n;
-reg main_litedramcore_dfi_p2_act_n = 1'd1;
+reg  main_litedramcore_dfi_p2_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p2_rddata;
 wire main_litedramcore_dfi_p2_rddata_valid;
-reg [13:0] main_litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg main_litedramcore_dfi_p3_we_n = 1'd1;
+reg  [13:0] main_litedramcore_dfi_p3_address = 14'd0;
+reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg  main_litedramcore_dfi_p3_we_n = 1'd1;
 wire main_litedramcore_dfi_p3_cke;
 wire main_litedramcore_dfi_p3_odt;
 wire main_litedramcore_dfi_p3_reset_n;
-reg main_litedramcore_dfi_p3_act_n = 1'd1;
+reg  main_litedramcore_dfi_p3_act_n = 1'd1;
 wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
 wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
 wire [31:0] main_litedramcore_dfi_p3_rddata;
 wire main_litedramcore_dfi_p3_rddata_valid;
-reg main_litedramcore_cmd_valid = 1'd0;
-reg main_litedramcore_cmd_ready = 1'd0;
-reg main_litedramcore_cmd_last = 1'd0;
-reg [13:0] main_litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg main_litedramcore_cmd_payload_cas = 1'd0;
-reg main_litedramcore_cmd_payload_ras = 1'd0;
-reg main_litedramcore_cmd_payload_we = 1'd0;
-reg main_litedramcore_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_cmd_valid = 1'd0;
+reg  main_litedramcore_cmd_ready = 1'd0;
+reg  main_litedramcore_cmd_last = 1'd0;
+reg  [13:0] main_litedramcore_cmd_payload_a = 14'd0;
+reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg  main_litedramcore_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_cmd_payload_we = 1'd0;
+reg  main_litedramcore_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_cmd_payload_is_write = 1'd0;
 wire main_litedramcore_wants_refresh;
 wire main_litedramcore_wants_zqcs;
 wire main_litedramcore_timer_wait;
 wire main_litedramcore_timer_done0;
 wire [9:0] main_litedramcore_timer_count0;
 wire main_litedramcore_timer_done1;
-reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
 wire main_litedramcore_postponer_req_i;
-reg main_litedramcore_postponer_req_o = 1'd0;
-reg main_litedramcore_postponer_count = 1'd0;
-reg main_litedramcore_sequencer_start0 = 1'd0;
+reg  main_litedramcore_postponer_req_o = 1'd0;
+reg  main_litedramcore_postponer_count = 1'd0;
+reg  main_litedramcore_sequencer_start0 = 1'd0;
 wire main_litedramcore_sequencer_done0;
 wire main_litedramcore_sequencer_start1;
-reg main_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg main_litedramcore_sequencer_count = 1'd0;
+reg  main_litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
+reg  main_litedramcore_sequencer_count = 1'd0;
 wire main_litedramcore_zqcs_timer_wait;
 wire main_litedramcore_zqcs_timer_done0;
 wire [26:0] main_litedramcore_zqcs_timer_count0;
 wire main_litedramcore_zqcs_timer_done1;
-reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg main_litedramcore_zqcs_executer_start = 1'd0;
-reg main_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  main_litedramcore_zqcs_executer_start = 1'd0;
+reg  main_litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
 wire main_litedramcore_bankmachine0_req_valid;
 wire main_litedramcore_bankmachine0_req_ready;
 wire main_litedramcore_bankmachine0_req_we;
 wire [20:0] main_litedramcore_bankmachine0_req_addr;
 wire main_litedramcore_bankmachine0_req_lock;
-reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine0_refresh_req;
-reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
@@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
@@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine0_row = 14'd0;
-reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine0_row = 14'd0;
+reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
 wire main_litedramcore_bankmachine0_row_hit;
-reg main_litedramcore_bankmachine0_row_open = 1'd0;
-reg main_litedramcore_bankmachine0_row_close = 1'd0;
-reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine0_row_open = 1'd0;
+reg  main_litedramcore_bankmachine0_row_close = 1'd0;
+reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine1_req_valid;
 wire main_litedramcore_bankmachine1_req_ready;
 wire main_litedramcore_bankmachine1_req_we;
 wire [20:0] main_litedramcore_bankmachine1_req_addr;
 wire main_litedramcore_bankmachine1_req_lock;
-reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine1_refresh_req;
-reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
@@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
@@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine1_row = 14'd0;
-reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine1_row = 14'd0;
+reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
 wire main_litedramcore_bankmachine1_row_hit;
-reg main_litedramcore_bankmachine1_row_open = 1'd0;
-reg main_litedramcore_bankmachine1_row_close = 1'd0;
-reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine1_row_open = 1'd0;
+reg  main_litedramcore_bankmachine1_row_close = 1'd0;
+reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine2_req_valid;
 wire main_litedramcore_bankmachine2_req_ready;
 wire main_litedramcore_bankmachine2_req_we;
 wire [20:0] main_litedramcore_bankmachine2_req_addr;
 wire main_litedramcore_bankmachine2_req_lock;
-reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine2_refresh_req;
-reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
@@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
@@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine2_row = 14'd0;
-reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine2_row = 14'd0;
+reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
 wire main_litedramcore_bankmachine2_row_hit;
-reg main_litedramcore_bankmachine2_row_open = 1'd0;
-reg main_litedramcore_bankmachine2_row_close = 1'd0;
-reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine2_row_open = 1'd0;
+reg  main_litedramcore_bankmachine2_row_close = 1'd0;
+reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine3_req_valid;
 wire main_litedramcore_bankmachine3_req_ready;
 wire main_litedramcore_bankmachine3_req_we;
 wire [20:0] main_litedramcore_bankmachine3_req_addr;
 wire main_litedramcore_bankmachine3_req_lock;
-reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine3_refresh_req;
-reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
@@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
@@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine3_row = 14'd0;
-reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine3_row = 14'd0;
+reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
 wire main_litedramcore_bankmachine3_row_hit;
-reg main_litedramcore_bankmachine3_row_open = 1'd0;
-reg main_litedramcore_bankmachine3_row_close = 1'd0;
-reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine3_row_open = 1'd0;
+reg  main_litedramcore_bankmachine3_row_close = 1'd0;
+reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine4_req_valid;
 wire main_litedramcore_bankmachine4_req_ready;
 wire main_litedramcore_bankmachine4_req_we;
 wire [20:0] main_litedramcore_bankmachine4_req_addr;
 wire main_litedramcore_bankmachine4_req_lock;
-reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine4_refresh_req;
-reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
@@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
@@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine4_row = 14'd0;
-reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine4_row = 14'd0;
+reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
 wire main_litedramcore_bankmachine4_row_hit;
-reg main_litedramcore_bankmachine4_row_open = 1'd0;
-reg main_litedramcore_bankmachine4_row_close = 1'd0;
-reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine4_row_open = 1'd0;
+reg  main_litedramcore_bankmachine4_row_close = 1'd0;
+reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine5_req_valid;
 wire main_litedramcore_bankmachine5_req_ready;
 wire main_litedramcore_bankmachine5_req_we;
 wire [20:0] main_litedramcore_bankmachine5_req_addr;
 wire main_litedramcore_bankmachine5_req_lock;
-reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine5_refresh_req;
-reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
@@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
@@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine5_row = 14'd0;
-reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine5_row = 14'd0;
+reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
 wire main_litedramcore_bankmachine5_row_hit;
-reg main_litedramcore_bankmachine5_row_open = 1'd0;
-reg main_litedramcore_bankmachine5_row_close = 1'd0;
-reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine5_row_open = 1'd0;
+reg  main_litedramcore_bankmachine5_row_close = 1'd0;
+reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine6_req_valid;
 wire main_litedramcore_bankmachine6_req_ready;
 wire main_litedramcore_bankmachine6_req_we;
 wire [20:0] main_litedramcore_bankmachine6_req_addr;
 wire main_litedramcore_bankmachine6_req_lock;
-reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine6_refresh_req;
-reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
@@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
@@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine6_row = 14'd0;
-reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine6_row = 14'd0;
+reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
 wire main_litedramcore_bankmachine6_row_hit;
-reg main_litedramcore_bankmachine6_row_open = 1'd0;
-reg main_litedramcore_bankmachine6_row_close = 1'd0;
-reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine6_row_open = 1'd0;
+reg  main_litedramcore_bankmachine6_row_close = 1'd0;
+reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 wire main_litedramcore_bankmachine7_req_valid;
 wire main_litedramcore_bankmachine7_req_ready;
 wire main_litedramcore_bankmachine7_req_we;
 wire [20:0] main_litedramcore_bankmachine7_req_addr;
 wire main_litedramcore_bankmachine7_req_lock;
-reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
 wire main_litedramcore_bankmachine7_refresh_req;
-reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
 wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
@@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
 wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
 wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
@@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
 wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
 wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
 wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] main_litedramcore_bankmachine7_row = 14'd0;
-reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] main_litedramcore_bankmachine7_row = 14'd0;
+reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
 wire main_litedramcore_bankmachine7_row_hit;
-reg main_litedramcore_bankmachine7_row_open = 1'd0;
-reg main_litedramcore_bankmachine7_row_close = 1'd0;
-reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+reg  main_litedramcore_bankmachine7_row_open = 1'd0;
+reg  main_litedramcore_bankmachine7_row_close = 1'd0;
+reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
 wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 wire main_litedramcore_ras_allowed;
 wire main_litedramcore_cas_allowed;
 wire [1:0] main_litedramcore_rdcmdphase;
 wire [1:0] main_litedramcore_wrcmdphase;
-reg main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_valid;
-reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
 wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire main_litedramcore_choose_cmd_cmd_payload_is_read;
 wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_cmd_request;
-reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
 wire main_litedramcore_choose_cmd_ce;
-reg main_litedramcore_choose_req_want_reads = 1'd0;
-reg main_litedramcore_choose_req_want_writes = 1'd0;
-reg main_litedramcore_choose_req_want_cmds = 1'd0;
-reg main_litedramcore_choose_req_want_activates = 1'd0;
+reg  main_litedramcore_choose_req_want_reads = 1'd0;
+reg  main_litedramcore_choose_req_want_writes = 1'd0;
+reg  main_litedramcore_choose_req_want_cmds = 1'd0;
+reg  main_litedramcore_choose_req_want_activates = 1'd0;
 wire main_litedramcore_choose_req_cmd_valid;
-reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
 wire [13:0] main_litedramcore_choose_req_cmd_payload_a;
 wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire main_litedramcore_choose_req_cmd_payload_is_cmd;
 wire main_litedramcore_choose_req_cmd_payload_is_read;
 wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
 wire [7:0] main_litedramcore_choose_req_request;
-reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
 wire main_litedramcore_choose_req_ce;
-reg [13:0] main_litedramcore_nop_a = 14'd0;
-reg [2:0] main_litedramcore_nop_ba = 3'd0;
-reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg main_litedramcore_steerer0 = 1'd1;
-reg main_litedramcore_steerer1 = 1'd1;
-reg main_litedramcore_steerer2 = 1'd1;
-reg main_litedramcore_steerer3 = 1'd1;
-reg main_litedramcore_steerer4 = 1'd1;
-reg main_litedramcore_steerer5 = 1'd1;
-reg main_litedramcore_steerer6 = 1'd1;
-reg main_litedramcore_steerer7 = 1'd1;
+reg  [13:0] main_litedramcore_nop_a = 14'd0;
+reg  [2:0] main_litedramcore_nop_ba = 3'd0;
+reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg  main_litedramcore_steerer0 = 1'd1;
+reg  main_litedramcore_steerer1 = 1'd1;
+reg  main_litedramcore_steerer2 = 1'd1;
+reg  main_litedramcore_steerer3 = 1'd1;
+reg  main_litedramcore_steerer4 = 1'd1;
+reg  main_litedramcore_steerer5 = 1'd1;
+reg  main_litedramcore_steerer6 = 1'd1;
+reg  main_litedramcore_steerer7 = 1'd1;
 wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
-reg main_litedramcore_trrdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
+reg  main_litedramcore_trrdcon_count = 1'd0;
 wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
 wire [2:0] main_litedramcore_tfawcon_count;
-reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
 wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
-reg main_litedramcore_tccdcon_count = 1'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
+reg  main_litedramcore_tccdcon_count = 1'd0;
 wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
 wire main_litedramcore_read_available;
 wire main_litedramcore_write_available;
-reg main_litedramcore_en0 = 1'd0;
+reg  main_litedramcore_en0 = 1'd0;
 wire main_litedramcore_max_time0;
-reg [4:0] main_litedramcore_time0 = 5'd0;
-reg main_litedramcore_en1 = 1'd0;
+reg  [4:0] main_litedramcore_time0 = 5'd0;
+reg  main_litedramcore_en1 = 1'd0;
 wire main_litedramcore_max_time1;
-reg [3:0] main_litedramcore_time1 = 4'd0;
+reg  [3:0] main_litedramcore_time1 = 4'd0;
 wire main_litedramcore_go_to_refresh;
-reg main_init_done_storage = 1'd0;
-reg main_init_done_re = 1'd0;
-reg main_init_error_storage = 1'd0;
-reg main_init_error_re = 1'd0;
+reg  main_init_done_storage = 1'd0;
+reg  main_init_done_re = 1'd0;
+reg  main_init_error_storage = 1'd0;
+reg  main_init_error_re = 1'd0;
 wire [29:0] main_wb_bus_adr;
 wire [31:0] main_wb_bus_dat_w;
 wire [31:0] main_wb_bus_dat_r;
@@ -1570,6 +1592,7 @@ wire main_wb_bus_we;
 wire [2:0] main_wb_bus_cti;
 wire [1:0] main_wb_bus_bte;
 wire main_wb_bus_err;
+wire main_user_enable;
 wire main_user_port_cmd_valid;
 wire main_user_port_cmd_ready;
 wire main_user_port_cmd_payload_we;
@@ -1590,26 +1613,26 @@ wire builder_reset5;
 wire builder_reset6;
 wire builder_reset7;
 wire builder_pll_fb;
-reg [1:0] builder_refresher_state = 2'd0;
-reg [1:0] builder_refresher_next_state = 2'd0;
-reg [3:0] builder_bankmachine0_state = 4'd0;
-reg [3:0] builder_bankmachine0_next_state = 4'd0;
-reg [3:0] builder_bankmachine1_state = 4'd0;
-reg [3:0] builder_bankmachine1_next_state = 4'd0;
-reg [3:0] builder_bankmachine2_state = 4'd0;
-reg [3:0] builder_bankmachine2_next_state = 4'd0;
-reg [3:0] builder_bankmachine3_state = 4'd0;
-reg [3:0] builder_bankmachine3_next_state = 4'd0;
-reg [3:0] builder_bankmachine4_state = 4'd0;
-reg [3:0] builder_bankmachine4_next_state = 4'd0;
-reg [3:0] builder_bankmachine5_state = 4'd0;
-reg [3:0] builder_bankmachine5_next_state = 4'd0;
-reg [3:0] builder_bankmachine6_state = 4'd0;
-reg [3:0] builder_bankmachine6_next_state = 4'd0;
-reg [3:0] builder_bankmachine7_state = 4'd0;
-reg [3:0] builder_bankmachine7_next_state = 4'd0;
-reg [3:0] builder_multiplexer_state = 4'd0;
-reg [3:0] builder_multiplexer_next_state = 4'd0;
+reg  [1:0] builder_refresher_state = 2'd0;
+reg  [1:0] builder_refresher_next_state = 2'd0;
+reg  [3:0] builder_bankmachine0_state = 4'd0;
+reg  [3:0] builder_bankmachine0_next_state = 4'd0;
+reg  [3:0] builder_bankmachine1_state = 4'd0;
+reg  [3:0] builder_bankmachine1_next_state = 4'd0;
+reg  [3:0] builder_bankmachine2_state = 4'd0;
+reg  [3:0] builder_bankmachine2_next_state = 4'd0;
+reg  [3:0] builder_bankmachine3_state = 4'd0;
+reg  [3:0] builder_bankmachine3_next_state = 4'd0;
+reg  [3:0] builder_bankmachine4_state = 4'd0;
+reg  [3:0] builder_bankmachine4_next_state = 4'd0;
+reg  [3:0] builder_bankmachine5_state = 4'd0;
+reg  [3:0] builder_bankmachine5_next_state = 4'd0;
+reg  [3:0] builder_bankmachine6_state = 4'd0;
+reg  [3:0] builder_bankmachine6_next_state = 4'd0;
+reg  [3:0] builder_bankmachine7_state = 4'd0;
+reg  [3:0] builder_bankmachine7_next_state = 4'd0;
+reg  [3:0] builder_multiplexer_state = 4'd0;
+reg  [3:0] builder_multiplexer_next_state = 4'd0;
 wire builder_roundrobin0_request;
 wire builder_roundrobin0_grant;
 wire builder_roundrobin0_ce;
@@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce;
 wire builder_roundrobin7_request;
 wire builder_roundrobin7_grant;
 wire builder_roundrobin7_ce;
-reg builder_locked0 = 1'd0;
-reg builder_locked1 = 1'd0;
-reg builder_locked2 = 1'd0;
-reg builder_locked3 = 1'd0;
-reg builder_locked4 = 1'd0;
-reg builder_locked5 = 1'd0;
-reg builder_locked6 = 1'd0;
-reg builder_locked7 = 1'd0;
-reg builder_new_master_wdata_ready0 = 1'd0;
-reg builder_new_master_wdata_ready1 = 1'd0;
-reg builder_new_master_rdata_valid0 = 1'd0;
-reg builder_new_master_rdata_valid1 = 1'd0;
-reg builder_new_master_rdata_valid2 = 1'd0;
-reg builder_new_master_rdata_valid3 = 1'd0;
-reg builder_new_master_rdata_valid4 = 1'd0;
-reg builder_new_master_rdata_valid5 = 1'd0;
-reg builder_new_master_rdata_valid6 = 1'd0;
-reg builder_new_master_rdata_valid7 = 1'd0;
-reg builder_new_master_rdata_valid8 = 1'd0;
-reg [13:0] builder_litedramcore_adr = 14'd0;
-reg builder_litedramcore_we = 1'd0;
-reg [7:0] builder_litedramcore_dat_w = 8'd0;
-wire [7:0] builder_litedramcore_dat_r;
+reg  builder_locked0 = 1'd0;
+reg  builder_locked1 = 1'd0;
+reg  builder_locked2 = 1'd0;
+reg  builder_locked3 = 1'd0;
+reg  builder_locked4 = 1'd0;
+reg  builder_locked5 = 1'd0;
+reg  builder_locked6 = 1'd0;
+reg  builder_locked7 = 1'd0;
+reg  builder_new_master_wdata_ready0 = 1'd0;
+reg  builder_new_master_wdata_ready1 = 1'd0;
+reg  builder_new_master_rdata_valid0 = 1'd0;
+reg  builder_new_master_rdata_valid1 = 1'd0;
+reg  builder_new_master_rdata_valid2 = 1'd0;
+reg  builder_new_master_rdata_valid3 = 1'd0;
+reg  builder_new_master_rdata_valid4 = 1'd0;
+reg  builder_new_master_rdata_valid5 = 1'd0;
+reg  builder_new_master_rdata_valid6 = 1'd0;
+reg  builder_new_master_rdata_valid7 = 1'd0;
+reg  builder_new_master_rdata_valid8 = 1'd0;
+reg  [13:0] builder_litedramcore_adr = 14'd0;
+reg  builder_litedramcore_we = 1'd0;
+reg  [31:0] builder_litedramcore_dat_w = 32'd0;
+wire [31:0] builder_litedramcore_dat_r;
 wire [29:0] builder_litedramcore_wishbone_adr;
 wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
 wire [3:0] builder_litedramcore_wishbone_sel;
 wire builder_litedramcore_wishbone_cyc;
 wire builder_litedramcore_wishbone_stb;
-reg builder_litedramcore_wishbone_ack = 1'd0;
+reg  builder_litedramcore_wishbone_ack = 1'd0;
 wire builder_litedramcore_wishbone_we;
 wire [2:0] builder_litedramcore_wishbone_cti;
 wire [1:0] builder_litedramcore_wishbone_bte;
-reg builder_litedramcore_wishbone_err = 1'd0;
+reg  builder_litedramcore_wishbone_err = 1'd0;
 wire [13:0] builder_interface0_bank_bus_adr;
 wire builder_interface0_bank_bus_we;
-wire [7:0] builder_interface0_bank_bus_dat_w;
-reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
-reg builder_csrbank0_init_done0_re = 1'd0;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank0_init_done0_re = 1'd0;
 wire builder_csrbank0_init_done0_r;
-reg builder_csrbank0_init_done0_we = 1'd0;
+reg  builder_csrbank0_init_done0_we = 1'd0;
 wire builder_csrbank0_init_done0_w;
-reg builder_csrbank0_init_error0_re = 1'd0;
+reg  builder_csrbank0_init_error0_re = 1'd0;
 wire builder_csrbank0_init_error0_r;
-reg builder_csrbank0_init_error0_we = 1'd0;
+reg  builder_csrbank0_init_error0_we = 1'd0;
 wire builder_csrbank0_init_error0_w;
 wire builder_csrbank0_sel;
 wire [13:0] builder_interface1_bank_bus_adr;
 wire builder_interface1_bank_bus_we;
-wire [7:0] builder_interface1_bank_bus_dat_w;
-reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
-reg builder_csrbank1_rst0_re = 1'd0;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank1_rst0_re = 1'd0;
 wire builder_csrbank1_rst0_r;
-reg builder_csrbank1_rst0_we = 1'd0;
+reg  builder_csrbank1_rst0_we = 1'd0;
 wire builder_csrbank1_rst0_w;
-reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
 wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg builder_csrbank1_wlevel_en0_re = 1'd0;
+reg  builder_csrbank1_wlevel_en0_re = 1'd0;
 wire builder_csrbank1_wlevel_en0_r;
-reg builder_csrbank1_wlevel_en0_we = 1'd0;
+reg  builder_csrbank1_wlevel_en0_we = 1'd0;
 wire builder_csrbank1_wlevel_en0_w;
-reg builder_csrbank1_dly_sel0_re = 1'd0;
+reg  builder_csrbank1_dly_sel0_re = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_r;
-reg builder_csrbank1_dly_sel0_we = 1'd0;
+reg  builder_csrbank1_dly_sel0_we = 1'd0;
 wire [1:0] builder_csrbank1_dly_sel0_w;
-reg builder_csrbank1_rdphase0_re = 1'd0;
+reg  builder_csrbank1_rdphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_r;
-reg builder_csrbank1_rdphase0_we = 1'd0;
+reg  builder_csrbank1_rdphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_rdphase0_w;
-reg builder_csrbank1_wrphase0_re = 1'd0;
+reg  builder_csrbank1_wrphase0_re = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_r;
-reg builder_csrbank1_wrphase0_we = 1'd0;
+reg  builder_csrbank1_wrphase0_we = 1'd0;
 wire [1:0] builder_csrbank1_wrphase0_w;
 wire builder_csrbank1_sel;
 wire [13:0] builder_interface2_bank_bus_adr;
 wire builder_interface2_bank_bus_we;
-wire [7:0] builder_interface2_bank_bus_dat_w;
-reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
-reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg  builder_csrbank2_dfii_control0_re = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_r;
-reg builder_csrbank2_dfii_control0_we = 1'd0;
+reg  builder_csrbank2_dfii_control0_we = 1'd0;
 wire [3:0] builder_csrbank2_dfii_control0_w;
-reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_address1_r;
-reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_address1_w;
-reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
-reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
-reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi0_address0_r;
+reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi0_address0_w;
+reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
-reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
-reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
-reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
-reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
-reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
-reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
-reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
-reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_address1_r;
-reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_address1_w;
-reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
-reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
-reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi1_address0_r;
+reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi1_address0_w;
+reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
-reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
-reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
-reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
-reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
-reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
-reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
-reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
-reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_address1_r;
-reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_address1_w;
-reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
-reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
-reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi2_address0_r;
+reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi2_address0_w;
+reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
-reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
-reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
-reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
-reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
-reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
-reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
-reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
-reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
 wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_address1_r;
-reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_address1_w;
-reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
-reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
-reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi3_address0_r;
+reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] builder_csrbank2_dfii_pi3_address0_w;
+reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
 wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
-reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
-reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
-reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
-reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
-reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
-reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
-reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
-reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
 wire builder_csrbank2_sel;
 wire [13:0] builder_csr_interconnect_adr;
 wire builder_csr_interconnect_we;
-wire [7:0] builder_csr_interconnect_dat_w;
-wire [7:0] builder_csr_interconnect_dat_r;
-reg [1:0] builder_state = 2'd0;
-reg [1:0] builder_next_state = 2'd0;
-reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
-reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg builder_litedramcore_we_next_value2 = 1'd0;
-reg builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg builder_rhs_array_muxed0 = 1'd0;
-reg [13:0] builder_rhs_array_muxed1 = 14'd0;
-reg [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg builder_rhs_array_muxed3 = 1'd0;
-reg builder_rhs_array_muxed4 = 1'd0;
-reg builder_rhs_array_muxed5 = 1'd0;
-reg builder_t_array_muxed0 = 1'd0;
-reg builder_t_array_muxed1 = 1'd0;
-reg builder_t_array_muxed2 = 1'd0;
-reg builder_rhs_array_muxed6 = 1'd0;
-reg [13:0] builder_rhs_array_muxed7 = 14'd0;
-reg [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg builder_rhs_array_muxed9 = 1'd0;
-reg builder_rhs_array_muxed10 = 1'd0;
-reg builder_rhs_array_muxed11 = 1'd0;
-reg builder_t_array_muxed3 = 1'd0;
-reg builder_t_array_muxed4 = 1'd0;
-reg builder_t_array_muxed5 = 1'd0;
-reg [20:0] builder_rhs_array_muxed12 = 21'd0;
-reg builder_rhs_array_muxed13 = 1'd0;
-reg builder_rhs_array_muxed14 = 1'd0;
-reg [20:0] builder_rhs_array_muxed15 = 21'd0;
-reg builder_rhs_array_muxed16 = 1'd0;
-reg builder_rhs_array_muxed17 = 1'd0;
-reg [20:0] builder_rhs_array_muxed18 = 21'd0;
-reg builder_rhs_array_muxed19 = 1'd0;
-reg builder_rhs_array_muxed20 = 1'd0;
-reg [20:0] builder_rhs_array_muxed21 = 21'd0;
-reg builder_rhs_array_muxed22 = 1'd0;
-reg builder_rhs_array_muxed23 = 1'd0;
-reg [20:0] builder_rhs_array_muxed24 = 21'd0;
-reg builder_rhs_array_muxed25 = 1'd0;
-reg builder_rhs_array_muxed26 = 1'd0;
-reg [20:0] builder_rhs_array_muxed27 = 21'd0;
-reg builder_rhs_array_muxed28 = 1'd0;
-reg builder_rhs_array_muxed29 = 1'd0;
-reg [20:0] builder_rhs_array_muxed30 = 21'd0;
-reg builder_rhs_array_muxed31 = 1'd0;
-reg builder_rhs_array_muxed32 = 1'd0;
-reg [20:0] builder_rhs_array_muxed33 = 21'd0;
-reg builder_rhs_array_muxed34 = 1'd0;
-reg builder_rhs_array_muxed35 = 1'd0;
-reg [2:0] builder_array_muxed0 = 3'd0;
-reg [13:0] builder_array_muxed1 = 14'd0;
-reg builder_array_muxed2 = 1'd0;
-reg builder_array_muxed3 = 1'd0;
-reg builder_array_muxed4 = 1'd0;
-reg builder_array_muxed5 = 1'd0;
-reg builder_array_muxed6 = 1'd0;
-reg [2:0] builder_array_muxed7 = 3'd0;
-reg [13:0] builder_array_muxed8 = 14'd0;
-reg builder_array_muxed9 = 1'd0;
-reg builder_array_muxed10 = 1'd0;
-reg builder_array_muxed11 = 1'd0;
-reg builder_array_muxed12 = 1'd0;
-reg builder_array_muxed13 = 1'd0;
-reg [2:0] builder_array_muxed14 = 3'd0;
-reg [13:0] builder_array_muxed15 = 14'd0;
-reg builder_array_muxed16 = 1'd0;
-reg builder_array_muxed17 = 1'd0;
-reg builder_array_muxed18 = 1'd0;
-reg builder_array_muxed19 = 1'd0;
-reg builder_array_muxed20 = 1'd0;
-reg [2:0] builder_array_muxed21 = 3'd0;
-reg [13:0] builder_array_muxed22 = 14'd0;
-reg builder_array_muxed23 = 1'd0;
-reg builder_array_muxed24 = 1'd0;
-reg builder_array_muxed25 = 1'd0;
-reg builder_array_muxed26 = 1'd0;
-reg builder_array_muxed27 = 1'd0;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg  [1:0] builder_state = 2'd0;
+reg  [1:0] builder_next_state = 2'd0;
+reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
+reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg  builder_litedramcore_we_next_value2 = 1'd0;
+reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg  builder_rhs_array_muxed0 = 1'd0;
+reg  [13:0] builder_rhs_array_muxed1 = 14'd0;
+reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg  builder_rhs_array_muxed3 = 1'd0;
+reg  builder_rhs_array_muxed4 = 1'd0;
+reg  builder_rhs_array_muxed5 = 1'd0;
+reg  builder_t_array_muxed0 = 1'd0;
+reg  builder_t_array_muxed1 = 1'd0;
+reg  builder_t_array_muxed2 = 1'd0;
+reg  builder_rhs_array_muxed6 = 1'd0;
+reg  [13:0] builder_rhs_array_muxed7 = 14'd0;
+reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg  builder_rhs_array_muxed9 = 1'd0;
+reg  builder_rhs_array_muxed10 = 1'd0;
+reg  builder_rhs_array_muxed11 = 1'd0;
+reg  builder_t_array_muxed3 = 1'd0;
+reg  builder_t_array_muxed4 = 1'd0;
+reg  builder_t_array_muxed5 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed12 = 21'd0;
+reg  builder_rhs_array_muxed13 = 1'd0;
+reg  builder_rhs_array_muxed14 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed15 = 21'd0;
+reg  builder_rhs_array_muxed16 = 1'd0;
+reg  builder_rhs_array_muxed17 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed18 = 21'd0;
+reg  builder_rhs_array_muxed19 = 1'd0;
+reg  builder_rhs_array_muxed20 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed21 = 21'd0;
+reg  builder_rhs_array_muxed22 = 1'd0;
+reg  builder_rhs_array_muxed23 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed24 = 21'd0;
+reg  builder_rhs_array_muxed25 = 1'd0;
+reg  builder_rhs_array_muxed26 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed27 = 21'd0;
+reg  builder_rhs_array_muxed28 = 1'd0;
+reg  builder_rhs_array_muxed29 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed30 = 21'd0;
+reg  builder_rhs_array_muxed31 = 1'd0;
+reg  builder_rhs_array_muxed32 = 1'd0;
+reg  [20:0] builder_rhs_array_muxed33 = 21'd0;
+reg  builder_rhs_array_muxed34 = 1'd0;
+reg  builder_rhs_array_muxed35 = 1'd0;
+reg  [2:0] builder_array_muxed0 = 3'd0;
+reg  [13:0] builder_array_muxed1 = 14'd0;
+reg  builder_array_muxed2 = 1'd0;
+reg  builder_array_muxed3 = 1'd0;
+reg  builder_array_muxed4 = 1'd0;
+reg  builder_array_muxed5 = 1'd0;
+reg  builder_array_muxed6 = 1'd0;
+reg  [2:0] builder_array_muxed7 = 3'd0;
+reg  [13:0] builder_array_muxed8 = 14'd0;
+reg  builder_array_muxed9 = 1'd0;
+reg  builder_array_muxed10 = 1'd0;
+reg  builder_array_muxed11 = 1'd0;
+reg  builder_array_muxed12 = 1'd0;
+reg  builder_array_muxed13 = 1'd0;
+reg  [2:0] builder_array_muxed14 = 3'd0;
+reg  [13:0] builder_array_muxed15 = 14'd0;
+reg  builder_array_muxed16 = 1'd0;
+reg  builder_array_muxed17 = 1'd0;
+reg  builder_array_muxed18 = 1'd0;
+reg  builder_array_muxed19 = 1'd0;
+reg  builder_array_muxed20 = 1'd0;
+reg  [2:0] builder_array_muxed21 = 3'd0;
+reg  [13:0] builder_array_muxed22 = 14'd0;
+reg  builder_array_muxed23 = 1'd0;
+reg  builder_array_muxed24 = 1'd0;
+reg  builder_array_muxed25 = 1'd0;
+reg  builder_array_muxed26 = 1'd0;
+reg  builder_array_muxed27 = 1'd0;
 wire builder_xilinxasyncresetsynchronizerimpl0;
 wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl1;
@@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3;
 wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire builder_xilinxasyncresetsynchronizerimpl3_expr;
 
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
 assign init_done = main_init_done_storage;
 assign init_error = main_init_error_storage;
 assign main_wb_bus_adr = wb_ctrl_adr;
@@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte;
 assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
 assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
 assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
 assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
 assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
-assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
 assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = rst;
+assign main_reset = (rst | main_rst);
 assign pll_locked = main_locked;
 assign main_clkin = clk;
 assign iodelay_clk = main_clkout_buf0;
@@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2;
 assign sys4x_dqs_clk = main_clkout_buf3;
 assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
 assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-
-// synthesis translate_off
-reg dummy_d;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
@@ -2081,14 +1989,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
 	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
 	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-// synthesis translate_off
-	dummy_d = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_1;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
@@ -2123,14 +2024,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
 	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
 	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-// synthesis translate_off
-	dummy_d_1 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_2;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
@@ -2165,14 +2059,7 @@ always @(*) begin
 	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
 	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
 	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-// synthesis translate_off
-	dummy_d_2 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_3;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
 	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
@@ -2207,19 +2094,12 @@ always @(*) begin
 	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
 	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
 	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-// synthesis translate_off
-	dummy_d_3 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
 assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-
-// synthesis translate_off
-reg dummy_d_4;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqs_oe <= 1'd0;
 	if (main_a7ddrphy_wlevel_en_storage) begin
@@ -2227,16 +2107,9 @@ always @(*) begin
 	end else begin
 		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
 	end
-// synthesis translate_off
-	dummy_d_4 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
 assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_dqspattern_o0 <= 8'd0;
 	main_a7ddrphy_dqspattern_o0 <= 7'd85;
@@ -2252,14 +2125,7 @@ always @(*) begin
 			main_a7ddrphy_dqspattern_o0 <= 1'd1;
 		end
 	end
-// synthesis translate_off
-	dummy_d_5 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip00 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value0)
@@ -2288,14 +2154,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_6 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip10 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value0)
@@ -2324,14 +2183,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_7 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip01 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value1)
@@ -2360,14 +2212,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_8 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip11 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value1)
@@ -2396,14 +2241,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_9 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip02 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value2)
@@ -2432,14 +2270,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_10 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip04 <= 8'd0;
 	case (main_a7ddrphy_bitslip0_value3)
@@ -2468,14 +2299,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_11 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip12 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value2)
@@ -2504,14 +2328,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_12 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip14 <= 8'd0;
 	case (main_a7ddrphy_bitslip1_value3)
@@ -2540,14 +2357,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_13 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip20 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value0)
@@ -2576,14 +2386,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_14 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip22 <= 8'd0;
 	case (main_a7ddrphy_bitslip2_value1)
@@ -2612,14 +2415,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_15 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip30 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value0)
@@ -2648,14 +2444,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_16 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip32 <= 8'd0;
 	case (main_a7ddrphy_bitslip3_value1)
@@ -2684,14 +2473,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_17 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_18;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip40 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value0)
@@ -2720,14 +2502,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_18 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_19;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip42 <= 8'd0;
 	case (main_a7ddrphy_bitslip4_value1)
@@ -2756,14 +2531,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_19 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_20;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip50 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value0)
@@ -2792,14 +2560,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_20 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_21;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip52 <= 8'd0;
 	case (main_a7ddrphy_bitslip5_value1)
@@ -2828,14 +2589,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_21 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip60 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value0)
@@ -2864,14 +2618,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_22 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip62 <= 8'd0;
 	case (main_a7ddrphy_bitslip6_value1)
@@ -2900,14 +2647,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_23 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip70 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value0)
@@ -2936,14 +2676,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_24 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip72 <= 8'd0;
 	case (main_a7ddrphy_bitslip7_value1)
@@ -2972,14 +2705,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_25 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_26;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip80 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value0)
@@ -3008,14 +2734,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_26 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip82 <= 8'd0;
 	case (main_a7ddrphy_bitslip8_value1)
@@ -3044,14 +2763,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_27 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip90 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value0)
@@ -3080,14 +2792,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_28 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip92 <= 8'd0;
 	case (main_a7ddrphy_bitslip9_value1)
@@ -3116,14 +2821,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_29 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip100 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value0)
@@ -3152,14 +2850,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_30 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_31;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip102 <= 8'd0;
 	case (main_a7ddrphy_bitslip10_value1)
@@ -3188,14 +2879,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_31 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_32;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip110 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value0)
@@ -3224,14 +2908,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_32 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_33;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip112 <= 8'd0;
 	case (main_a7ddrphy_bitslip11_value1)
@@ -3260,14 +2937,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_33 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_34;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip120 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value0)
@@ -3296,14 +2966,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_34 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_35;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip122 <= 8'd0;
 	case (main_a7ddrphy_bitslip12_value1)
@@ -3332,14 +2995,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_35 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_36;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip130 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value0)
@@ -3368,14 +3024,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_36 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_37;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip132 <= 8'd0;
 	case (main_a7ddrphy_bitslip13_value1)
@@ -3404,14 +3053,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_37 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_38;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip140 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value0)
@@ -3440,14 +3082,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_38 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip142 <= 8'd0;
 	case (main_a7ddrphy_bitslip14_value1)
@@ -3476,14 +3111,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_39 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_40;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip150 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value0)
@@ -3512,14 +3140,7 @@ always @(*) begin
 			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_40 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_41;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_bitslip152 <= 8'd0;
 	case (main_a7ddrphy_bitslip15_value1)
@@ -3548,9 +3169,6 @@ always @(*) begin
 			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_41 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
 assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
@@ -3680,10 +3298,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-
-// synthesis translate_off
-reg dummy_d_42;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	end else begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p0_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -3691,14 +3313,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
-// synthesis translate_off
-	dummy_d_42 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_43;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3706,14 +3321,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
-// synthesis translate_off
-	dummy_d_43 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_44;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3721,14 +3329,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_44 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_45;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3736,14 +3337,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_45 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_46;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3751,28 +3345,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_46 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_47;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_47 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_48;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3780,28 +3360,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
-// synthesis translate_off
-	dummy_d_48 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_49;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_49 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_50;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3809,14 +3375,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
-// synthesis translate_off
-	dummy_d_50 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_51;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3824,14 +3383,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
-// synthesis translate_off
-	dummy_d_51 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_52;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3839,14 +3391,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_52 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_53;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3854,14 +3399,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
-// synthesis translate_off
-	dummy_d_53 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_54;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -3869,28 +3407,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_54 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_55;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
-// synthesis translate_off
-	dummy_d_55 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_56;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3898,28 +3422,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_56 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_57;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_57 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_58;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3927,14 +3437,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_58 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_59;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -3942,14 +3445,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_59 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_60;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -3957,14 +3453,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
-// synthesis translate_off
-	dummy_d_60 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_61;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -3972,14 +3461,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
-// synthesis translate_off
-	dummy_d_61 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_62;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -3987,14 +3469,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_62 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_63;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4002,14 +3477,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_63 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_64;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4017,28 +3485,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_64 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_65;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_65 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_66;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4046,28 +3500,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
-// synthesis translate_off
-	dummy_d_66 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_67;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_67 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_68;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4075,14 +3515,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
-// synthesis translate_off
-	dummy_d_68 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_69;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4090,14 +3523,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
-// synthesis translate_off
-	dummy_d_69 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_70;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4105,14 +3531,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_70 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_71;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4120,14 +3539,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
-// synthesis translate_off
-	dummy_d_71 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_72;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4135,28 +3547,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_72 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_73;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
-// synthesis translate_off
-	dummy_d_73 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_74;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4164,28 +3562,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_74 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_75 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_76;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4193,14 +3577,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_76 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_77;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4208,14 +3585,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_77 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_78;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -4223,14 +3593,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
-// synthesis translate_off
-	dummy_d_78 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_79;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4238,14 +3601,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_79 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_80;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4253,14 +3609,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_80 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_81;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4268,14 +3617,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_81 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_82;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4283,28 +3625,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_82 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_83;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_83 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_84;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4312,28 +3640,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
-// synthesis translate_off
-	dummy_d_84 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_85;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_85 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_86;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4341,28 +3655,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
-// synthesis translate_off
-	dummy_d_86 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_87;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
-	end
-// synthesis translate_off
-	dummy_d_87 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_88;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4370,14 +3663,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
-// synthesis translate_off
-	dummy_d_88 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_89;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4385,14 +3671,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4400,14 +3679,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_91;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4415,28 +3687,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_91 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_92;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
 		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
-// synthesis translate_off
-	dummy_d_92 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_93;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4444,28 +3702,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_93 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_94;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
-// synthesis translate_off
-	dummy_d_94 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_95;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4473,28 +3717,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_95 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_96;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p0_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
-// synthesis translate_off
-	dummy_d_96 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4502,14 +3732,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
-// synthesis translate_off
-	dummy_d_97 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_98;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 14'd0;
 	if (main_litedramcore_sel) begin
@@ -4517,14 +3740,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
-// synthesis translate_off
-	dummy_d_98 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_99;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
 	if (main_litedramcore_sel) begin
@@ -4532,14 +3748,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
-// synthesis translate_off
-	dummy_d_99 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_100;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	end
+end
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4547,14 +3763,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4562,14 +3771,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
-// synthesis translate_off
-	dummy_d_101 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_102;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4577,28 +3779,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
-// synthesis translate_off
-	dummy_d_102 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_103;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_103 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_104;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4606,28 +3794,14 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
-// synthesis translate_off
-	dummy_d_104 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_105;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
 		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end else begin
 	end
-// synthesis translate_off
-	dummy_d_105 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_106;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4635,14 +3809,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_106 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_107;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4650,14 +3817,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
-// synthesis translate_off
-	dummy_d_107 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_108;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4665,14 +3825,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
-// synthesis translate_off
-	dummy_d_108 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
@@ -4680,14 +3833,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
-// synthesis translate_off
-	dummy_d_109 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_110;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
@@ -4695,14 +3841,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
-// synthesis translate_off
-	dummy_d_110 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_111;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
@@ -4710,14 +3849,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
-// synthesis translate_off
-	dummy_d_111 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_112;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -4725,24 +3857,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_112 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_113;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
-	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
-	end
-// synthesis translate_off
-	dummy_d_113 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
 assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
@@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p0_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4767,14 +3885,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_114 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_115;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4782,14 +3893,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_115 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_116;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4797,24 +3901,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_116 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_117;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_117 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
@@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c
 assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
 assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_118;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p1_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4833,14 +3923,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_118 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_119;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4848,14 +3931,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_119 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4863,24 +3939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_120 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_121 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
@@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c
 assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
 assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p2_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4899,14 +3961,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4914,14 +3969,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_123 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4929,24 +3977,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_124 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_125 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
@@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c
 assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
 assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_126;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p3_we_n <= 1'd1;
+	end
+end
 always @(*) begin
 	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4965,14 +3999,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_126 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4980,14 +4007,7 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
-// synthesis translate_off
-	dummy_d_127 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4995,24 +4015,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_128 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
-	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
-	end
-// synthesis translate_off
-	dummy_d_129 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
@@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 &
 assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
 assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
 assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
 always @(*) begin
 	builder_refresher_next_state <= 2'd0;
 	builder_refresher_next_state <= builder_refresher_state;
@@ -5124,119 +4122,88 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_130 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_131;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
+	main_litedramcore_cmd_last <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+				end else begin
+					main_litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_131 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_132;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
+	main_litedramcore_sequencer_start0 <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
+			if (main_litedramcore_cmd_ready) begin
+				main_litedramcore_sequencer_start0 <= 1'd1;
 			end
 		end
+		2'd2: begin
+		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_132 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_133;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
+	main_litedramcore_cmd_valid <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_cmd_valid <= 1'd1;
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
+					main_litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_133 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_134;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
+	main_litedramcore_zqcs_executer_start <= 1'd0;
 	case (builder_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
 			if (main_litedramcore_sequencer_done0) begin
 				if (main_litedramcore_wants_zqcs) begin
+					main_litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_134 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
@@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_135;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
@@ -5263,17 +4226,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_135 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
 assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
 assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_136;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
@@ -5281,9 +4237,6 @@ always @(*) begin
 			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_136 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
@@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_137;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
@@ -5313,9 +4262,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_137 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
@@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_138;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine0_next_state <= 4'd0;
 	builder_bankmachine0_next_state <= builder_bankmachine0_state;
@@ -5389,14 +4331,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_138 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_139;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine0_row_open <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5422,14 +4398,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_139 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5455,14 +4424,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_140 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_141;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5497,14 +4459,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_141 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_142;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5533,14 +4488,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_142 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_143;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5581,14 +4529,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_143 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_144;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5614,14 +4555,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_144 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5651,14 +4585,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_145 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5696,16 +4623,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_146 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5730,8 +4650,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -5741,16 +4661,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_147 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5775,7 +4688,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5786,16 +4699,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5820,8 +4726,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -5831,14 +4737,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_149 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_150;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -5864,57 +4763,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_150 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_151;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_151 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
@@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_152;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
@@ -5941,17 +4785,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_152 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
 assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
 assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_153;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
@@ -5959,9 +4796,6 @@ always @(*) begin
 			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_153 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
@@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_154;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
@@ -5991,9 +4821,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_154 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
@@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_155;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine1_next_state <= 4'd0;
 	builder_bankmachine1_next_state <= builder_bankmachine1_state;
@@ -6067,14 +4890,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_155 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_156;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6100,14 +4957,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_156 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_157;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6133,14 +4983,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_157 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6175,14 +5018,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_158 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_159;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6211,14 +5047,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_159 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_160;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6259,14 +5088,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_160 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6292,14 +5114,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_161 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6329,47 +5144,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_162 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_163 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6407,14 +5182,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_164 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_165;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6452,14 +5220,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_165 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_166;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6497,14 +5258,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_166 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_167;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
@@ -6542,30 +5296,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_167 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_168;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6576,23 +5320,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_168 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
@@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_169;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
@@ -6619,17 +5344,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_169 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
 assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_170;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
@@ -6637,9 +5355,6 @@ always @(*) begin
 			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_170 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
@@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_171;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
@@ -6669,9 +5380,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_171 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
@@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_172;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine2_next_state <= 4'd0;
 	builder_bankmachine2_next_state <= builder_bankmachine2_state;
@@ -6745,22 +5449,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_172 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_173;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6778,10 +5481,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
+							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6790,14 +5490,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_173 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6823,14 +5516,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_174 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_175;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6856,14 +5542,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_175 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6898,14 +5577,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_176 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6934,14 +5606,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_177 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_178;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6982,14 +5647,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_178 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7015,14 +5673,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_179 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7052,14 +5703,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_180 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7097,14 +5741,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7142,14 +5779,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_182 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_183;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -7187,16 +5817,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_183 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_184;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -7205,9 +5828,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7218,32 +5838,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_184 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_185;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7254,23 +5879,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_185 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
@@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_186;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
@@ -7297,17 +5903,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
 assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
 assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
@@ -7315,9 +5914,6 @@ always @(*) begin
 			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
@@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_188;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
@@ -7347,9 +5939,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_188 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
@@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_189;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine3_next_state <= 4'd0;
 	builder_bankmachine3_next_state <= builder_bankmachine3_state;
@@ -7423,14 +6008,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_189 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_190;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7456,14 +6075,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_190 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_191;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7489,14 +6101,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_191 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7531,14 +6136,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_192 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_193;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7567,14 +6165,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_193 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_194;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7615,22 +6206,18 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_194 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_195;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7643,31 +6230,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_195 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7697,47 +6262,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_196 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_197 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7775,14 +6300,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_198 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_199;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7820,14 +6338,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_199 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_200;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
@@ -7865,16 +6376,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_200 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_201;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -7883,9 +6387,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7896,32 +6397,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_201 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_202;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7932,23 +6438,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_202 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
@@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_203;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
@@ -7975,17 +6462,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_203 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
 assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
 assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_204;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
@@ -7993,9 +6473,6 @@ always @(*) begin
 			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_204 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
@@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_205;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
@@ -8025,9 +6498,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_205 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
@@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_206;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine4_next_state <= 4'd0;
 	builder_bankmachine4_next_state <= builder_bankmachine4_state;
@@ -8101,24 +6567,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_206 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_207;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8132,29 +6594,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_207 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
+	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8167,24 +6634,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_208 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_209;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8195,7 +6658,30 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
 			end else begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
@@ -8209,14 +6695,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_209 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_210;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8245,14 +6724,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_210 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_211;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8293,14 +6765,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_211 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_212;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8326,14 +6791,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_212 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8363,14 +6821,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_213 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8408,14 +6859,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_214 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8453,14 +6897,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_215 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_216;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8498,14 +6935,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_216 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_217;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8543,14 +6973,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_217 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
@@ -8576,57 +6999,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_218 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_219;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_219 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
@@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_220;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
@@ -8653,17 +7021,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
 assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
 assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
@@ -8671,9 +7032,6 @@ always @(*) begin
 			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_221 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
@@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_222;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
@@ -8703,9 +7057,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_222 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
@@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_223;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine5_next_state <= 4'd0;
 	builder_bankmachine5_next_state <= builder_bankmachine5_state;
@@ -8779,22 +7126,21 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_223 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8812,10 +7158,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
+							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8824,14 +7167,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_224 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_225;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8857,14 +7193,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_225 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8890,14 +7219,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_226 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8932,14 +7254,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_227 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_228;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8968,14 +7283,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_228 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_229;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9016,14 +7324,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_229 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_230;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9049,14 +7350,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9086,14 +7380,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_231 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9131,14 +7418,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_232 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9176,14 +7456,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_233 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_234;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -9221,16 +7494,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_234 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_235;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -9239,9 +7505,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9252,32 +7515,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_235 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9288,23 +7556,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_236 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
@@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
@@ -9331,17 +7580,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_237 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
 assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
 assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_238;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
@@ -9349,9 +7591,6 @@ always @(*) begin
 			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_238 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
@@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_239;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
@@ -9381,9 +7616,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_239 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
@@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_240;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine6_next_state <= 4'd0;
 	builder_bankmachine6_next_state <= builder_bankmachine6_state;
@@ -9457,24 +7685,20 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_240 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_241;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9488,29 +7712,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_241 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
+	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9523,24 +7752,20 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_242 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_243;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9551,31 +7776,9 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_243 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_244;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9610,14 +7813,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_244 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_245;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9646,14 +7842,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_245 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9694,14 +7883,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_246 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9727,14 +7909,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_247 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9764,14 +7939,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_248 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9809,14 +7977,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_249 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_250;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9854,14 +8015,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_250 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_251;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
@@ -9899,16 +8053,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_251 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_252;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -9917,9 +8064,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9930,32 +8074,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_252 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9966,23 +8115,8 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_253 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
@@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco
 assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
 assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_254;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
 	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
@@ -10009,17 +8139,10 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
-// synthesis translate_off
-	dummy_d_254 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
 assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_255;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
 	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
@@ -10027,9 +8150,6 @@ always @(*) begin
 			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
-// synthesis translate_off
-	dummy_d_255 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
 assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
@@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_256;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
@@ -10059,9 +8175,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
-// synthesis translate_off
-	dummy_d_256 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
@@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_257;
-// synthesis translate_on
 always @(*) begin
 	builder_bankmachine7_next_state <= 4'd0;
 	builder_bankmachine7_next_state <= builder_bankmachine7_state;
@@ -10135,14 +8244,48 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_257 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_258;
-// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
 always @(*) begin
 	main_litedramcore_bankmachine7_row_open <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10168,14 +8311,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_258 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_259;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10201,14 +8337,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_259 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_260;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10243,14 +8372,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_260 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_261;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10279,14 +8401,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_261 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_262;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10327,14 +8442,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_262 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_263;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10360,14 +8468,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_263 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_264;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10397,16 +8498,9 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_264 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10432,7 +8526,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10442,16 +8536,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10476,8 +8563,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10487,16 +8574,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_266 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10521,7 +8601,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -10532,16 +8612,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_267 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10566,8 +8639,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -10577,14 +8650,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_268 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -10610,57 +8676,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_269 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_270 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
@@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_valids <= 8'd0;
 	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
@@ -10706,9 +8717,6 @@ always @(*) begin
 	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-// synthesis translate_off
-	dummy_d_271 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
 assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
@@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
 assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
 assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
 assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
 	end
-// synthesis translate_off
-	dummy_d_272 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
 	end
-// synthesis translate_off
-	dummy_d_273 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_cmd_cmd_valid) begin
 		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
 	end
-// synthesis translate_off
-	dummy_d_274 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
@@ -10768,14 +8751,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
 		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_275 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
@@ -10784,14 +8760,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
 		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_276 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
@@ -10800,14 +8769,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
 		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_277 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
@@ -10816,14 +8778,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
 		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_278 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
@@ -10832,14 +8787,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
 		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_279 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
@@ -10848,14 +8796,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
 		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_280 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
@@ -10864,14 +8805,7 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
 		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_281 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
 	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
@@ -10880,15 +8814,8 @@ always @(*) begin
 	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
 		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-// synthesis translate_off
-	dummy_d_282 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_valids <= 8'd0;
 	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
@@ -10899,9 +8826,6 @@ always @(*) begin
 	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-// synthesis translate_off
-	dummy_d_283 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
 assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
@@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
 assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
 assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
 assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
 	end
-// synthesis translate_off
-	dummy_d_284 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
 	end
-// synthesis translate_off
-	dummy_d_285 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
 	if (main_litedramcore_choose_req_cmd_valid) begin
 		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
 	end
-// synthesis translate_off
-	dummy_d_286 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
 assign main_litedramcore_dfi_p0_reset_n = 1'd1;
@@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1;
 assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
 assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
 assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
 always @(*) begin
 	builder_multiplexer_next_state <= 4'd0;
 	builder_multiplexer_next_state <= builder_multiplexer_state;
@@ -11023,18 +8922,15 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_287 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
+	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -11055,24 +8951,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_288 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -11094,22 +8989,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_289 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
+	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
 		end
@@ -11132,22 +9023,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_290 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -11168,25 +9055,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_291 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -11207,32 +9086,15 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_292 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
+			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11253,23 +9115,46 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+		end
+	endcase
+end
+always @(*) begin
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_293 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11297,14 +9182,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_294 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11346,14 +9224,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_295 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
@@ -11381,14 +9252,7 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11429,14 +9293,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11477,51 +9334,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_299 = dummy_s;
-// synthesis translate_on
 end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
@@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
 assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11580,14 +9388,7 @@ always @(*) begin
 			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_300 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
@@ -11598,9 +9399,6 @@ always @(*) begin
 			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_301 = dummy_s;
-// synthesis translate_on
 end
 assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
 assign builder_roundrobin0_grant = 1'd0;
@@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0;
 assign builder_roundrobin5_grant = 1'd0;
 assign builder_roundrobin6_grant = 1'd0;
 assign builder_roundrobin7_grant = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
 always @(*) begin
 	builder_next_state <= 2'd0;
 	builder_next_state <= builder_state;
@@ -11631,16 +9425,9 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_302 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	builder_litedramcore_dat_w_next_value0 <= 32'd0;
 	case (builder_state)
 		1'd1: begin
 		end
@@ -11650,14 +9437,7 @@ always @(*) begin
 			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_303 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (builder_state)
@@ -11669,14 +9449,19 @@ always @(*) begin
 			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_304 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_wishbone_ack <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	builder_litedramcore_adr_next_value1 <= 14'd0;
 	case (builder_state)
@@ -11691,14 +9476,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (builder_state)
@@ -11713,14 +9491,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_306 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value2 <= 1'd0;
 	case (builder_state)
@@ -11735,14 +9506,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_307 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_we_next_value_ce2 <= 1'd0;
 	case (builder_state)
@@ -11757,14 +9521,7 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_308 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
 always @(*) begin
 	builder_litedramcore_wishbone_dat_r <= 32'd0;
 	case (builder_state)
@@ -11776,28 +9533,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_309 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
-always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_310 = dummy_s;
-// synthesis translate_on
 end
 assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
 assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
@@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
+	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_311 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
+	builder_csrbank0_init_done0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_312 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
+	builder_csrbank0_init_error0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_313 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
+	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_314 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_315 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_316 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_317 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_318 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_319 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_320 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_321 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_322 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_323 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_324 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_325 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_326 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_327 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_328 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_329 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
 always @(*) begin
 	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_330 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_331 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_332 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_333 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_335 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_336 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_337 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_338;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_338 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
-
-// synthesis translate_off
-reg dummy_d_339;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_339 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_340;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_340 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
 assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
@@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
-
-// synthesis translate_off
-reg dummy_d_341;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
+	builder_csrbank2_dfii_control0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_341 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_342;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
+	builder_csrbank2_dfii_control0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_342 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_343;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_343 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_344;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_344 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_345;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_345 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_346;
-// synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_346 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_347;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_347 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_348;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_348 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_349;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_349 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_350;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_350 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_351;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_351 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_352;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_352 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_353;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_353 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_354;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_354 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_355;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_355 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_356;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_357 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_358;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_358 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_359;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_359 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_360;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_360 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_361;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_361 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_362;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_362 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_363;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_363 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_364;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_364 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_365;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_365 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_366;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_366 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_367;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_367 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_368;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_368 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_369;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_369 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_370;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_370 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_371;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_371 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_372;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
 		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_372 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_373;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_373 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_374;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_374 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_375;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_375 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_376;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_376 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_377;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_377 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_378;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
 		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_378 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_379;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_379 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_380;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_380 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_381;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_381 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_382;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_382 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_383;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_383 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_384;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_384 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_385;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_385 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_386;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
 		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_386 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_387;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_387 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_388;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_388 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_389;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_389 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_390;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_390 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_391;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_391 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_392;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_392 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_393;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_393 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_394;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_394 = dummy_s;
-// synthesis translate_on
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_395;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_395 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_396;
-// synthesis translate_on
 always @(*) begin
 	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
 		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_396 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_397;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_397 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_398;
-// synthesis translate_on
 always @(*) begin
 	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
 		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_398 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_399;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_399 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_400;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_400 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_401;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_401 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_402;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
 	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_402 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_403;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_403 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_404;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_404 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_405;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_405 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_406;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_406 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_407;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_407 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_408;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_408 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_409;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_409 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_410;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_410 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_411;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_411 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_412;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_412 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_413;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_413 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_414;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_414 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_415;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_416;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_416 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_417;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_417 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_418;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_418 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_419;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_419 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_420;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_420 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_421;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_421 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_422;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_422 = dummy_s;
-// synthesis translate_on
-end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
-
-// synthesis translate_off
-reg dummy_d_423;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_423 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_424;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_424 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0];
-
-// synthesis translate_off
-reg dummy_d_425;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
-	end
-// synthesis translate_off
-	dummy_d_425 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_426;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_426 = dummy_s;
-// synthesis translate_on
-end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_427;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
-	end
-// synthesis translate_off
-	dummy_d_427 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_428;
-// synthesis translate_on
-always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_428 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
-
-// synthesis translate_off
-reg dummy_d_429;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_429 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_430;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_430 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_431;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_431 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_432;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_432 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_433;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_433 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_434;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_434 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_435;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_435 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_436;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_436 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_437;
-// synthesis translate_on
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_437 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_438;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_438 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_439;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_439 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_440;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_440 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_441;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_441 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_442;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_442 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_443;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_443 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_444;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_444 = dummy_s;
-// synthesis translate_on
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
-
-// synthesis translate_off
-reg dummy_d_445;
-// synthesis translate_on
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
 	end
-// synthesis translate_off
-	dummy_d_445 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_446;
-// synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
 	end
-// synthesis translate_off
-	dummy_d_446 = dummy_s;
-// synthesis translate_on
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
@@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
 assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
 assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
 assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
 assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
 assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
 assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
-assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_csr_interconnect_adr = builder_litedramcore_adr;
 assign builder_csr_interconnect_we = builder_litedramcore_we;
 assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
@@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-
-// synthesis translate_off
-reg dummy_d_447;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13760,14 +10147,7 @@ always @(*) begin
 			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_447 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_448;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed1 <= 14'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13796,14 +10176,7 @@ always @(*) begin
 			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_448 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_449;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed2 <= 3'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13832,14 +10205,7 @@ always @(*) begin
 			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_449 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_450;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13868,14 +10234,7 @@ always @(*) begin
 			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_450 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_451;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13904,14 +10263,7 @@ always @(*) begin
 			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_451 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_452;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13940,14 +10292,7 @@ always @(*) begin
 			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_452 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_453;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed0 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -13976,14 +10321,7 @@ always @(*) begin
 			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_453 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_454;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed1 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14012,14 +10350,7 @@ always @(*) begin
 			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_454 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_455;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed2 <= 1'd0;
 	case (main_litedramcore_choose_cmd_grant)
@@ -14048,14 +10379,7 @@ always @(*) begin
 			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_455 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_456;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed6 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14084,14 +10408,7 @@ always @(*) begin
 			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_456 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_457;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed7 <= 14'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14120,14 +10437,7 @@ always @(*) begin
 			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_457 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_458;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed8 <= 3'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14156,14 +10466,7 @@ always @(*) begin
 			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_458 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_459;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed9 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14192,14 +10495,7 @@ always @(*) begin
 			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_459 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_460;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed10 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14228,14 +10524,7 @@ always @(*) begin
 			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_460 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_461;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed11 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14264,14 +10553,7 @@ always @(*) begin
 			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_461 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_462;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed3 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14300,14 +10582,7 @@ always @(*) begin
 			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_462 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_463;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed4 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14336,14 +10611,7 @@ always @(*) begin
 			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_463 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_464;
-// synthesis translate_on
 always @(*) begin
 	builder_t_array_muxed5 <= 1'd0;
 	case (main_litedramcore_choose_req_grant)
@@ -14372,14 +10640,7 @@ always @(*) begin
 			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_464 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_465;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed12 <= 21'd0;
 	case (builder_roundrobin0_grant)
@@ -14387,14 +10648,7 @@ always @(*) begin
 			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_465 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_466;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed13 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14402,14 +10656,7 @@ always @(*) begin
 			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_466 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_467;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed14 <= 1'd0;
 	case (builder_roundrobin0_grant)
@@ -14417,14 +10664,7 @@ always @(*) begin
 			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_467 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_468;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed15 <= 21'd0;
 	case (builder_roundrobin1_grant)
@@ -14432,14 +10672,7 @@ always @(*) begin
 			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_468 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_469;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed16 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14447,14 +10680,7 @@ always @(*) begin
 			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_469 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_470;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed17 <= 1'd0;
 	case (builder_roundrobin1_grant)
@@ -14462,14 +10688,7 @@ always @(*) begin
 			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_470 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_471;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed18 <= 21'd0;
 	case (builder_roundrobin2_grant)
@@ -14477,14 +10696,7 @@ always @(*) begin
 			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_471 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_472;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed19 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14492,14 +10704,7 @@ always @(*) begin
 			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_472 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_473;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed20 <= 1'd0;
 	case (builder_roundrobin2_grant)
@@ -14507,14 +10712,7 @@ always @(*) begin
 			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_473 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_474;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed21 <= 21'd0;
 	case (builder_roundrobin3_grant)
@@ -14522,14 +10720,7 @@ always @(*) begin
 			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_474 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_475;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed22 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14537,14 +10728,7 @@ always @(*) begin
 			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_475 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_476;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed23 <= 1'd0;
 	case (builder_roundrobin3_grant)
@@ -14552,14 +10736,7 @@ always @(*) begin
 			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_476 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_477;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed24 <= 21'd0;
 	case (builder_roundrobin4_grant)
@@ -14567,14 +10744,7 @@ always @(*) begin
 			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_477 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_478;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed25 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14582,14 +10752,7 @@ always @(*) begin
 			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_478 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_479;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed26 <= 1'd0;
 	case (builder_roundrobin4_grant)
@@ -14597,14 +10760,7 @@ always @(*) begin
 			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_479 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_480;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed27 <= 21'd0;
 	case (builder_roundrobin5_grant)
@@ -14612,14 +10768,7 @@ always @(*) begin
 			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_480 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_481;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed28 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14627,14 +10776,7 @@ always @(*) begin
 			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_481 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_482;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed29 <= 1'd0;
 	case (builder_roundrobin5_grant)
@@ -14642,14 +10784,7 @@ always @(*) begin
 			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_482 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_483;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed30 <= 21'd0;
 	case (builder_roundrobin6_grant)
@@ -14657,14 +10792,7 @@ always @(*) begin
 			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_483 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_484;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed31 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14672,14 +10800,7 @@ always @(*) begin
 			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_484 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_485;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed32 <= 1'd0;
 	case (builder_roundrobin6_grant)
@@ -14687,14 +10808,7 @@ always @(*) begin
 			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_485 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_486;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed33 <= 21'd0;
 	case (builder_roundrobin7_grant)
@@ -14702,14 +10816,7 @@ always @(*) begin
 			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_486 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_487;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed34 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14717,14 +10824,7 @@ always @(*) begin
 			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_487 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_488;
-// synthesis translate_on
 always @(*) begin
 	builder_rhs_array_muxed35 <= 1'd0;
 	case (builder_roundrobin7_grant)
@@ -14732,14 +10832,7 @@ always @(*) begin
 			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_488 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_489;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed0 <= 3'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14756,14 +10849,7 @@ always @(*) begin
 			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_489 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_490;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed1 <= 14'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14780,14 +10866,7 @@ always @(*) begin
 			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_490 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_491;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed2 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14804,14 +10883,7 @@ always @(*) begin
 			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_491 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_492;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed3 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14828,14 +10900,7 @@ always @(*) begin
 			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_492 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_493;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed4 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14852,14 +10917,7 @@ always @(*) begin
 			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_493 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_494;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed5 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14876,14 +10934,7 @@ always @(*) begin
 			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_494 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_495;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed6 <= 1'd0;
 	case (main_litedramcore_steerer_sel0)
@@ -14900,14 +10951,7 @@ always @(*) begin
 			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_495 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_496;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed7 <= 3'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14924,14 +10968,7 @@ always @(*) begin
 			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_496 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_497;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed8 <= 14'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14948,14 +10985,7 @@ always @(*) begin
 			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_497 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_498;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed9 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14972,14 +11002,7 @@ always @(*) begin
 			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_498 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_499;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed10 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -14996,14 +11019,7 @@ always @(*) begin
 			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_499 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_500;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed11 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15020,14 +11036,7 @@ always @(*) begin
 			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_500 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_501;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed12 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15044,14 +11053,7 @@ always @(*) begin
 			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_501 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_502;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed13 <= 1'd0;
 	case (main_litedramcore_steerer_sel1)
@@ -15068,14 +11070,7 @@ always @(*) begin
 			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_502 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_503;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed14 <= 3'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15092,14 +11087,7 @@ always @(*) begin
 			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_503 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_504;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed15 <= 14'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15116,14 +11104,7 @@ always @(*) begin
 			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_504 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_505;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed16 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15140,14 +11121,7 @@ always @(*) begin
 			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_505 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_506;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed17 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15164,14 +11138,7 @@ always @(*) begin
 			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_506 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_507;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed18 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15188,14 +11155,7 @@ always @(*) begin
 			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_507 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_508;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed19 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15212,14 +11172,7 @@ always @(*) begin
 			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_508 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_509;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed20 <= 1'd0;
 	case (main_litedramcore_steerer_sel2)
@@ -15236,14 +11189,7 @@ always @(*) begin
 			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_509 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_510;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed21 <= 3'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15260,14 +11206,7 @@ always @(*) begin
 			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_510 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_511;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed22 <= 14'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15284,14 +11223,7 @@ always @(*) begin
 			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_511 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_512;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed23 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15308,14 +11240,7 @@ always @(*) begin
 			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_512 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_513;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed24 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15332,14 +11257,7 @@ always @(*) begin
 			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_513 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_514;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed25 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15356,14 +11274,7 @@ always @(*) begin
 			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_514 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_515;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed26 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15380,14 +11291,7 @@ always @(*) begin
 			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_515 = dummy_s;
-// synthesis translate_on
 end
-
-// synthesis translate_off
-reg dummy_d_516;
-// synthesis translate_on
 always @(*) begin
 	builder_array_muxed27 <= 1'd0;
 	case (main_litedramcore_steerer_sel3)
@@ -15404,15 +11308,17 @@ always @(*) begin
 			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_516 = dummy_s;
-// synthesis translate_on
 end
 assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
 assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
 always @(posedge iodelay_clk) begin
 	if ((main_reset_counter != 1'd0)) begin
 		main_reset_counter <= (main_reset_counter - 1'd1);
@@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+			5'd24: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin
 		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
 	end
 	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address1_re) begin
-		main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+		main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
 	end
 	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
 	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
 		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
 	end
 	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
 	if (builder_csrbank2_dfii_pi1_command0_re) begin
 		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
 	end
 	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address1_re) begin
-		main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+		main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
 	end
 	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
 	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
 		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
 	end
 	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
 	if (builder_csrbank2_dfii_pi2_command0_re) begin
 		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
 	end
 	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address1_re) begin
-		main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+		main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
 	end
 	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
 	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
 		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
 	end
 	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
 	if (builder_csrbank2_dfii_pi3_command0_re) begin
 		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
 	end
 	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address1_re) begin
-		main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+		main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
 	end
 	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
 	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
 		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
 	end
 	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
-	end
-	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
-	end
 	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
 	end
 	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
 		main_a7ddrphy_rst_storage <= 1'd0;
 		main_a7ddrphy_rst_re <= 1'd0;
@@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin
 	end
 end
 
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
 BUFG BUFG(
 	.I(main_clkout0),
 	.O(main_clkout_buf0)
@@ -19581,118 +15360,150 @@ IOBUF IOBUF_15(
 	.O(main_a7ddrphy_dq_i_nodelay15)
 );
 
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage[0:15];
-reg [23:0] memdat;
+reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
 		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
 assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_1[0:15];
-reg [23:0] memdat_1;
+reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
 		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_2[0:15];
-reg [23:0] memdat_2;
+reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
 		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
 assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_3[0:15];
-reg [23:0] memdat_3;
+reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
 		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
 assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_4[0:15];
-reg [23:0] memdat_4;
+reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
 		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
 assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_5[0:15];
-reg [23:0] memdat_5;
+reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
 		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
 assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_6[0:15];
-reg [23:0] memdat_6;
+reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
 		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
 assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 24-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
+// Port 1 | Read: Async | Write: ---- | 
 reg [23:0] storage_7[0:15];
-reg [23:0] memdat_7;
+reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
 	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
 		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
-
 always @(posedge sys_clk) begin
 end
-
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
 assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
+
 FD FD(
 	.C(main_clkin),
 	.D(main_reset),
@@ -19849,3 +15660,7 @@ PLLE2_ADV #(
 );
 
 endmodule
+
+// -----------------------------------------------------------------------------
+//  Auto-Generated by LiteX on 2022-01-14 08:32:15.
+//------------------------------------------------------------------------------