diff --git a/simple_ram_behavioural.vhdl b/simple_ram_behavioural.vhdl
index 4279bb1..6d76d76 100644
--- a/simple_ram_behavioural.vhdl
+++ b/simple_ram_behavioural.vhdl
@@ -41,7 +41,7 @@ begin
 				state <= IDLE;
 				ret_ack <= '0';
 			else
-				ret_dat := x"XXXXXXXXXXXXXXXX";
+				ret_dat := x"FFFFFFFFFFFFFFFF";
 
 				-- Active
 				if wishbone_in.cyc = '1' then