From 6034a9e31ffdc287f3bddce13ea28b0e450b0547 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:24:38 +1000 Subject: [PATCH] litedram: simplify generate.py We can call litedram_gen instead of doing the work ourselves. Signed-off-by: Anton Blanchard --- litedram/gen-src/generate.py | 50 ++++-------------------------------- 1 file changed, 5 insertions(+), 45 deletions(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 2e13b0e..182c2d1 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -2,15 +2,9 @@ from litex.build.tools import write_to_file from litex.build.tools import replace_in_file -from litex.build.generic_platform import * -from litex.build.xilinx import XilinxPlatform -from litex.build.lattice import LatticePlatform -from litex.soc.integration.builder import * from litedram.gen import * import subprocess import os -import sys -import yaml import shutil def make_new_dir(base, added): @@ -27,9 +21,6 @@ gen_src_dir = os.path.join(base_dir, "gen-src") gen_dir = make_new_dir(base_dir, "generated") # Build the init code for microwatt-initialized DRAM -# -# XXX Not working yet -# def build_init_code(build_dir, is_sim): # More path fudging @@ -76,48 +67,17 @@ def generate_one(t): print("Generating target:", t) # Is it a simulation ? - is_sim = t is "sim" + is_sim = "sim" in t # Muck with directory path build_dir = make_new_dir(build_top_dir, t) t_dir = make_new_dir(gen_dir, t) - # Grab config file - cfile = os.path.join(gen_src_dir, t + ".yml") - core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader) - - ### TODO: Make most stuff below a function in litedram gen.py and - ### call it rather than duplicate it - ### - - # Convert YAML elements to Python/LiteX - for k, v in core_config.items(): - replaces = {"False": False, "True": True, "None": None} - for r in replaces.keys(): - if v == r: - core_config[k] = replaces[r] - if "clk_freq" in k: - core_config[k] = float(core_config[k]) - if k == "sdram_module": - core_config[k] = getattr(litedram_modules, core_config[k]) - if k == "sdram_phy": - core_config[k] = getattr(litedram_phys, core_config[k]) - - # Generate core + cmd = ["litedram_gen", "--output-dir=%s" % build_dir] if is_sim: - platform = SimPlatform("", io=[]) - elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: - platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") - elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: - platform = XilinxPlatform("", io=[], toolchain="vivado") - else: - raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - - soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000) - - # Build into build_dir - builder = Builder(soc, output_dir=build_dir, compile_gateware=False) - vns = builder.build(build_name="litedram_core", regular_comb=False) + cmd.append("--sim") + cmd.append("%s.yml" % t) + subprocess.check_call(cmd) # Grab generated gatewar dir gw_dir = os.path.join(build_dir, "gateware")