From 621a0f6b285f377fc5e8827918c8200d5ae80729 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 24 Sep 2021 14:24:37 +1000 Subject: [PATCH] fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz 50Mhz clkin, 100Mhz sys_clk, as needed for Wukon v2 Signed-off-by: Benjamin Herrenschmidt --- fpga/clk_gen_plle2.vhd | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/fpga/clk_gen_plle2.vhd b/fpga/clk_gen_plle2.vhd index b336d6f..6b86cb0 100644 --- a/fpga/clk_gen_plle2.vhd +++ b/fpga/clk_gen_plle2.vhd @@ -70,6 +70,18 @@ architecture rtl of clock_generator is report "Unsupported output frequency" severity failure; return bad_settings; end case; + when 50000000 => + case output_hz is + when 100000000 => + return (clkin_period => 20.0, + clkfbout_mult => 32, + clkout_divide => 16, + divclk_divide => 1, + force_rst => '0'); + when others => + report "Unsupported output frequency" severity failure; + return bad_settings; + end case; when others => report "Unsupported input frequency" severity failure; return bad_settings;