diff --git a/fpga/clk_gen_bypass.vhd b/fpga/clk_gen_bypass.vhd
index b204329..d583159 100644
--- a/fpga/clk_gen_bypass.vhd
+++ b/fpga/clk_gen_bypass.vhd
@@ -14,7 +14,7 @@ architecture bypass of clock_generator is
 
 begin
 
-  pll_locked_out <= pll_rst_in;
+  pll_locked_out <= not pll_rst_in;
   pll_clk_out <= ext_clk;
 
 end architecture bypass;