From 33c78f92828f13a6e1f60e6d4060757e840b699c Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Wed, 24 Mar 2021 21:40:26 +1100 Subject: [PATCH 1/2] Move verilator --trace flag into VERILATOR_FLAGS Signed-off-by: Anton Blanchard --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 9349d83..a395a83 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ GHDL ?= ghdl GHDLFLAGS=--std=08 CFLAGS=-O3 -Wall -VERILATOR_FLAGS=-O3 +VERILATOR_FLAGS=-O3 #--trace # It takes forever to build with optimisation, so disable by default #VERILATOR_CFLAGS=-O3 @@ -119,7 +119,7 @@ $(soc_dram_tbs): else verilated_dram: litedram/generated/sim/litedram_core.v - verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace + verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT) SIM_DRAM_CFLAGS = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd @@ -199,7 +199,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE) # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c - verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace + verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT make -C obj_dir -f Vmicrowatt.mk @cp -f obj_dir/microwatt-verilator microwatt-verilator From be11ebbf6df069138b28ff6b5596bf0a1cff8ee0 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 25 Mar 2021 14:05:00 +1100 Subject: [PATCH 2/2] Remove unused GHDL_TARGET_GENERICS Signed-off-by: Anton Blanchard --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index a395a83..2d34627 100644 --- a/Makefile +++ b/Makefile @@ -192,10 +192,10 @@ fpga_files = fpga/soc_reset.vhdl \ synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c