From 7c8bc85e44af03c31600ee434ff579d762076b4b Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 12 Dec 2020 13:19:52 +1100 Subject: [PATCH] Fix a few reset issues in flash controller Our flash controller fails when simulating with iverilog. Looking closer, both wb_stash and auto_last_addr are X state, and things fall apart after they get used. Initialise them both fixes the iverilog issue. Signed-off-by: Anton Blanchard --- spi_flash_ctrl.vhdl | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/spi_flash_ctrl.vhdl b/spi_flash_ctrl.vhdl index 095bc74..d2b4992 100644 --- a/spi_flash_ctrl.vhdl +++ b/spi_flash_ctrl.vhdl @@ -232,6 +232,10 @@ begin if rst = '1' then wb_out.ack <= '0'; wb_out.stall <= '0'; + wb_stash.cyc <= '0'; + wb_stash.stb <= '0'; + wb_stash.sel <= (others => '0'); + wb_stash.we <= '0'; else -- Latch wb responses as well for 1 cycle. Stall is updated -- below @@ -344,12 +348,16 @@ begin auto_sync: process(clk) begin if rising_edge(clk) then - auto_state <= auto_next; - auto_cnt <= auto_cnt_next; - auto_data <= auto_data_next; - if auto_latch_adr = '1' then - auto_last_addr <= auto_lad_next; - end if; + if rst = '1' then + auto_last_addr <= (others => '0'); + else + auto_state <= auto_next; + auto_cnt <= auto_cnt_next; + auto_data <= auto_data_next; + if auto_latch_adr = '1' then + auto_last_addr <= auto_lad_next; + end if; + end if; end if; end process;