diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 34c27c9..54e0675 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -4,7 +4,7 @@ set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }]; set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; @@ -26,6 +26,15 @@ set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b } set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; +################################################################################ +# Normal LEDs +################################################################################ + +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led4 }]; +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led5 }]; +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led6 }]; +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led7 }]; + ################################################################################ # SPI Flash ################################################################################ @@ -41,6 +50,85 @@ set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { spi_flas set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/*sck_1*}] set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_delay_1.dat_i_l*}] +################################################################################ +# Ethernet (generated by LiteX) +################################################################################ + +# eth_ref_clk:0 +set_property LOC G18 [get_ports {eth_ref_clk}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_ref_clk}] + +# eth_clocks:0.tx +set_property LOC H16 [get_ports {eth_clocks_tx}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}] + +# eth_clocks:0.rx +set_property LOC F15 [get_ports {eth_clocks_rx}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}] + +# eth:0.rst_n +set_property LOC C16 [get_ports {eth_rst_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}] + +# eth:0.mdio +set_property LOC K13 [get_ports {eth_mdio}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}] + +# eth:0.mdc +set_property LOC F16 [get_ports {eth_mdc}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}] + +# eth:0.rx_dv +set_property LOC G16 [get_ports {eth_rx_dv}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}] + +# eth:0.rx_er +set_property LOC C17 [get_ports {eth_rx_er}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}] + +# eth:0.rx_data +set_property LOC D18 [get_ports {eth_rx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}] + +# eth:0.rx_data +set_property LOC E17 [get_ports {eth_rx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}] + +# eth:0.rx_data +set_property LOC E18 [get_ports {eth_rx_data[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}] + +# eth:0.rx_data +set_property LOC G17 [get_ports {eth_rx_data[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}] + +# eth:0.tx_en +set_property LOC H15 [get_ports {eth_tx_en}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}] + +# eth:0.tx_data +set_property LOC H14 [get_ports {eth_tx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}] + +# eth:0.tx_data +set_property LOC J14 [get_ports {eth_tx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}] + +# eth:0.tx_data +set_property LOC J13 [get_ports {eth_tx_data[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}] + +# eth:0.tx_data +set_property LOC H17 [get_ports {eth_tx_data[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}] + +# eth:0.col +set_property LOC D17 [get_ports {eth_col}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}] + +# eth:0.crs +set_property LOC G14 [get_ports {eth_crs}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}] ################################################################################ # DRAM (generated by LiteX) @@ -326,10 +414,22 @@ set_property CONFIG_MODE SPIx4 [current_design] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; +create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }] + +create_clock -name eth_tx_clk -period 40.0 [get_ports { eth_clocks_tx }] + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous + ################################################################################ -# False path constraints (from LiteX as they relate to LiteDRAM) +# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth) ################################################################################ +set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] + set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index c8d560a..d38ed76 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -21,11 +21,12 @@ entity toplevel is SPI_FLASH_OFFSET : integer := 4194304; SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; - LOG_LENGTH : natural := 512 + LOG_LENGTH : natural := 512; + USE_LITEETH : boolean := false ); port( ext_clk : in std_ulogic; - ext_rst : in std_ulogic; + ext_rst_n : in std_ulogic; -- UART0 signals: uart_main_tx : out std_ulogic; @@ -35,6 +36,10 @@ entity toplevel is led0_b : out std_ulogic; led0_g : out std_ulogic; led0_r : out std_ulogic; + led4 : out std_ulogic; + led5 : out std_ulogic; + led6 : out std_ulogic; + led7 : out std_ulogic; -- SPI spi_flash_cs_n : out std_ulogic; @@ -44,6 +49,21 @@ entity toplevel is spi_flash_wp_n : inout std_ulogic; spi_flash_hold_n : inout std_ulogic; + -- Ethernet + eth_ref_clk : out std_ulogic; + eth_clocks_tx : in std_ulogic; + eth_clocks_rx : in std_ulogic; + eth_rst_n : out std_ulogic; + eth_mdio : inout std_ulogic; + eth_mdc : out std_ulogic; + eth_rx_dv : in std_ulogic; + eth_rx_er : in std_ulogic; + eth_rx_data : in std_ulogic_vector(3 downto 0); + eth_tx_en : out std_ulogic; + eth_tx_data : out std_ulogic_vector(3 downto 0); + eth_col : in std_ulogic; + eth_crs : in std_ulogic; + -- DRAM wires ddram_a : out std_ulogic_vector(13 downto 0); ddram_ba : out std_ulogic_vector(2 downto 0); @@ -70,20 +90,27 @@ architecture behaviour of toplevel is signal pll_rst : std_ulogic; -- Internal clock signals: - signal system_clk : std_ulogic; + signal system_clk : std_ulogic; signal system_clk_locked : std_ulogic; + signal eth_clk_locked : std_ulogic; - -- DRAM main data wishbone connection - signal wb_dram_in : wishbone_master_out; - signal wb_dram_out : wishbone_slave_out; - - -- DRAM control wishbone connection + -- External IOs from the SoC signal wb_ext_io_in : wb_io_master_out; signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_eth : std_ulogic; + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteEth connection + signal ext_irq_eth : std_ulogic; + signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; -- Control/status signal core_alt_reset : std_ulogic; @@ -142,7 +169,8 @@ begin SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, - LOG_LENGTH => LOG_LENGTH + LOG_LENGTH => LOG_LENGTH, + USE_LITEETH => USE_LITEETH ) port map ( -- System signals @@ -160,6 +188,9 @@ begin spi_flash_sdat_oe => spi_sdat_oe, spi_flash_sdat_i => spi_sdat_i, + -- External interrupts + ext_irq_eth => ext_irq_eth, + -- DRAM wishbone wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, @@ -167,6 +198,7 @@ begin wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_eth => wb_ext_is_eth, alt_reset => core_alt_reset ); @@ -217,8 +249,8 @@ begin port map( ext_clk => ext_clk, pll_clk => system_clk, - pll_locked_in => system_clk_locked, - ext_rst_in => ext_rst, + pll_locked_in => system_clk_locked and eth_clk_locked, + ext_rst_in => ext_rst_n, pll_rst_out => pll_rst, rst_out => soc_rst ); @@ -257,6 +289,7 @@ begin signal dram_init_done : std_ulogic; signal dram_init_error : std_ulogic; signal dram_sys_rst : std_ulogic; + signal rst_gen_rst : std_ulogic; begin -- Eventually dig out the frequency from the generator @@ -272,12 +305,22 @@ begin port map( ext_clk => ext_clk, pll_clk => system_clk, - pll_locked_in => '1', - ext_rst_in => ext_rst, + pll_locked_in => eth_clk_locked, + ext_rst_in => ext_rst_n, pll_rst_out => pll_rst, - rst_out => open + rst_out => rst_gen_rst ); + -- Generate SoC reset + soc_rst_gen: process(system_clk) + begin + if ext_rst_n = '0' then + soc_rst <= '1'; + elsif rising_edge(system_clk) then + soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked; + end if; + end process; + dram: entity work.litedram_wrapper generic map( DRAM_ABITS => 24, @@ -289,14 +332,14 @@ begin clk_in => ext_clk, rst => pll_rst, system_clk => system_clk, - system_reset => soc_rst, + system_reset => dram_sys_rst, core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, wb_out => wb_dram_out, wb_ctrl_in => wb_ext_io_in, - wb_ctrl_out => wb_ext_io_out, + wb_ctrl_out => wb_dram_ctrl_out, wb_ctrl_is_csr => wb_ext_is_dram_csr, wb_ctrl_is_init => wb_ext_is_dram_init, @@ -326,6 +369,141 @@ begin end generate; + has_liteeth : if USE_LITEETH generate + + component liteeth_core port ( + sys_clock : in std_ulogic; + sys_reset : in std_ulogic; + mii_eth_clocks_tx : in std_ulogic; + mii_eth_clocks_rx : in std_ulogic; + mii_eth_rst_n : out std_ulogic; + mii_eth_mdio : in std_ulogic; + mii_eth_mdc : out std_ulogic; + mii_eth_rx_dv : in std_ulogic; + mii_eth_rx_er : in std_ulogic; + mii_eth_rx_data : in std_ulogic_vector(3 downto 0); + mii_eth_tx_en : out std_ulogic; + mii_eth_tx_data : out std_ulogic_vector(3 downto 0); + mii_eth_col : in std_ulogic; + mii_eth_crs : in std_ulogic; + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic; + interrupt : out std_ulogic + ); + end component; + + signal wb_eth_cyc : std_ulogic; + signal wb_eth_adr : std_ulogic_vector(29 downto 0); + + -- Change this to use a PLL instead of a BUFR to generate the 25Mhz + -- reference clock to the PHY. + constant USE_PLL : boolean := false; + begin + eth_use_pll: if USE_PLL generate + signal eth_clk_25 : std_ulogic; + signal eth_clkfb : std_ulogic; + begin + pll_eth : PLLE2_BASE + generic map ( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT => 16, + CLKIN1_PERIOD => 10.0, + CLKOUT0_DIVIDE => 64, + DIVCLK_DIVIDE => 1, + STARTUP_WAIT => "FALSE") + port map ( + CLKOUT0 => eth_clk_25, + CLKOUT1 => open, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKFBOUT => eth_clkfb, + LOCKED => eth_clk_locked, + CLKIN1 => ext_clk, + PWRDWN => '0', + RST => pll_rst, + CLKFBIN => eth_clkfb); + + eth_clk_buf: BUFG + port map ( + I => eth_clk_25, + O => eth_ref_clk + ); + end generate; + + eth_use_bufr: if not USE_PLL generate + eth_clk_div: BUFR + generic map ( + BUFR_DIVIDE => "4" + ) + port map ( + I => system_clk, + O => eth_ref_clk, + CE => '1', + CLR => '0' + ); + eth_clk_locked <= '1'; + end generate; + + liteeth : liteeth_core + port map( + sys_clock => system_clk, + sys_reset => soc_rst, + mii_eth_clocks_tx => eth_clocks_tx, + mii_eth_clocks_rx => eth_clocks_rx, + mii_eth_rst_n => eth_rst_n, + mii_eth_mdio => eth_mdio, + mii_eth_mdc => eth_mdc, + mii_eth_rx_dv => eth_rx_dv, + mii_eth_rx_er => eth_rx_er, + mii_eth_rx_data => eth_rx_data, + mii_eth_tx_en => eth_tx_en, + mii_eth_tx_data => eth_tx_data, + mii_eth_col => eth_col, + mii_eth_crs => eth_crs, + wishbone_adr => wb_eth_adr, + wishbone_dat_w => wb_ext_io_in.dat, + wishbone_dat_r => wb_eth_out.dat, + wishbone_sel => wb_ext_io_in.sel, + wishbone_cyc => wb_eth_cyc, + wishbone_stb => wb_ext_io_in.stb, + wishbone_ack => wb_eth_out.ack, + wishbone_we => wb_ext_io_in.we, + wishbone_cti => "000", + wishbone_bte => "00", + wishbone_err => open, + interrupt => ext_irq_eth + ); + + -- Gate cyc with "chip select" from soc + wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; + + -- Remove top address bits as liteeth decoder doesn't know about them + wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(16 downto 2); + + -- LiteETH isn't pipelined + wb_eth_out.stall <= not wb_eth_out.ack; + + end generate; + + no_liteeth : if not USE_LITEETH generate + eth_clk_locked <= '1'; + ext_irq_eth <= '0'; + end generate; + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out; + leds_pwm : process(system_clk) begin if rising_edge(system_clk) then @@ -342,4 +520,9 @@ begin end if; end process; + led4 <= system_clk_locked; + led5 <= eth_clk_locked; + led6 <= not soc_rst; + led7 <= not spi_flash_cs_n; + end architecture behaviour; diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index fd83840..2d09f74 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -15,6 +15,8 @@ #define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */ #define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */ #define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */ +#define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */ +#define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */ #define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */ #define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */ @@ -22,6 +24,7 @@ * Interrupt numbers */ #define IRQ_UART0 0 +#define IRQ_ETHERNET 1 /* * Register definitions for the syscon registers @@ -33,6 +36,7 @@ #define SYS_REG_INFO_HAS_DRAM (1ull << 1) #define SYS_REG_INFO_HAS_BRAM (1ull << 2) #define SYS_REG_INFO_HAS_SPI_FLASH (1ull << 3) +#define SYS_REG_INFO_HAS_LITEETH (1ull << 4) #define SYS_REG_BRAMINFO 0x10 #define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull #define SYS_REG_DRAMINFO 0x18 diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index 386332c..dd3b507 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -260,6 +260,8 @@ uint64_t main(void) printf("BRAM "); if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) printf("SPIFLASH "); + if (ftr & SYS_REG_INFO_HAS_LITEETH) + printf("ETHERNET "); printf("\n"); if (ftr & SYS_REG_INFO_HAS_BRAM) { val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK; diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 84033c5..b75722c 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -527,11 +527,11 @@ f88100d83be10020 f8e100f038c100d8 f90100f87fe3fb78 f9410108f9210100 -6000000048001af9 +6000000048001b0d 7fe3fb787c7e1b78 -6000000048001611 +6000000048001625 7fc3f378382100b0 -00000000480020b8 +00000000480020cc 0000028001000000 000000004e800020 0000000000000000 @@ -540,555 +540,288 @@ f9410108f9210100 0000000000000000 3842a5203c4c0001 7d8000267c0802a6 -9181000848001ff5 -48001505f821fed1 +9181000848002009 +48001519f821fed1 3c62ffff60000000 -4bffff3938637b78 +4bffff3938637b88 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b98 +63ff000838637ba8 3c62ffff4bffff15 -38637bb87bff0020 +38637bc87bff0020 7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffee938637bd0 +4bfffee938637be0 4e00000073e90002 3c62ffff41820010 -4bfffed138637bd8 +4bfffed138637be8 4d80000073e90004 3c62ffff41820010 -4bfffeb938637be0 +4bfffeb938637bf0 4d00000073e90008 3c62ffff41820010 -4bfffea138637be8 -3b7b7f683f62ffff -4bfffe917f63db78 -3c80c000418e0028 -7884002060840010 -7c8026ea7c0004ac -7884b5823c62ffff -4bfffe6938637bf8 -3c80c0004192004c -7884002060840018 -7c8026ea7c0004ac -788460223c62ffff -4bfffe4138637c10 -608400303c80c000 +4bfffea138637bf8 +4182001073e90010 +38637c083c62ffff +3f62ffff4bfffe8d +7f63db783b7b7f88 +418e00284bfffe7d +608400103c80c000 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+faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1281,6 +1283,8 @@ e8010010ebc1fff0 000000204d415242 4853414c46495053 0000000000000020 +54454e5245485445 +0000000000000020 2020202020202020 203a4d4152422020 000a424b20646c25 diff --git a/liteeth/fusesoc-add-files.py b/liteeth/fusesoc-add-files.py new file mode 100644 index 0000000..2775d16 --- /dev/null +++ b/liteeth/fusesoc-add-files.py @@ -0,0 +1,27 @@ +#!/usr/bin/python3 +from fusesoc.capi2.generator import Generator +import os +import sys +import pathlib + +class LiteEthGenerator(Generator): + def run(self): + board = self.config.get('board') + + # Collect a bunch of directory path + script_dir = os.path.dirname(sys.argv[0]) + gen_dir = os.path.join(script_dir, "generated", board) + + print("Adding LiteEth for board... ", board) + + # Add files to fusesoc + files = [] + f = os.path.join(gen_dir, "liteeth_core.v") + files.append({f : {'file_type' : 'verilogSource'}}) + + self.add_files(files) + +g = LiteEthGenerator() +g.run() +g.write() + diff --git a/liteeth/gen-src/arty.yml b/liteeth/gen-src/arty.yml new file mode 100644 index 0000000..7200a70 --- /dev/null +++ b/liteeth/gen-src/arty.yml @@ -0,0 +1,15 @@ +# This file is Copyright (c) 2020 Florent Kermarrec +# License: BSD + +# PHY ---------------------------------------------------------------------- +phy: LiteEthPHYMII +vendor: xilinx +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: wishbone +endianness: little + +soc: + mem_map: + ethmac: 0x00010000 + csr_data_width: 32 diff --git a/liteeth/gen-src/generate.sh b/liteeth/gen-src/generate.sh new file mode 100755 index 0000000..805e0b8 --- /dev/null +++ b/liteeth/gen-src/generate.sh @@ -0,0 +1,30 @@ +#!/bin/bash + +TARGETS=arty + +ME=$(realpath $0) +echo ME=$ME +MY_PATH=$(dirname $ME) +echo MYPATH=$MY_PATH +PARENT_PATH=$(realpath $MY_PATH/..) +echo PARENT=$PARENT_PATH +BUILD_PATH=$PARENT_PATH/build +mkdir -p $BUILD_PATH +GEN_PATH=$PARENT_PATH/generated +mkdir -p $GEN_PATH + +for i in $TARGETS +do + TARGET_BUILD_PATH=$BUILD_PATH/$i + TARGET_GEN_PATH=$GEN_PATH/$i + rm -rf $TARGET_BUILD_PATH + rm -rf $TARGET_GEN_PATH + mkdir -p $TARGET_BUILD_PATH + mkdir -p $TARGET_GEN_PATH + + echo "Generating $i in $TARGET_BUILD_PATH" + liteeth_gen --output-dir=$TARGET_BUILD_PATH $MY_PATH/$i.yml + + cp $TARGET_BUILD_PATH/gateware/liteeth_core.v $TARGET_GEN_PATH/ +done + diff --git a/liteeth/generated/arty/liteeth_core.v b/liteeth/generated/arty/liteeth_core.v new file mode 100644 index 0000000..5157a8f --- /dev/null +++ b/liteeth/generated/arty/liteeth_core.v @@ -0,0 +1,3057 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-15 17:21:34 +//-------------------------------------------------------------------------------- +module liteeth_core( + input wire sys_clock, + input wire sys_reset, + input wire mii_eth_clocks_tx, + input wire mii_eth_clocks_rx, + output wire mii_eth_rst_n, + inout wire mii_eth_mdio, + output wire mii_eth_mdc, + input wire mii_eth_rx_dv, + input wire mii_eth_rx_er, + input wire [3:0] mii_eth_rx_data, + output reg mii_eth_tx_en, + output reg [3:0] mii_eth_tx_data, + input wire mii_eth_col, + input wire mii_eth_crs, + input wire [29:0] wishbone_adr, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + input wire [3:0] wishbone_sel, + input wire wishbone_cyc, + input wire wishbone_stb, + output wire wishbone_ack, + input wire wishbone_we, + input wire [2:0] wishbone_cti, + input wire [1:0] wishbone_bte, + output wire wishbone_err, + output wire interrupt +); + +reg main_maccore_maccore_reset_storage = 1'd0; +reg main_maccore_maccore_reset_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_scratch_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_reset; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg [13:0] main_maccore_maccore_adr = 14'd0; +reg main_maccore_maccore_we = 1'd0; +wire [31:0] main_maccore_maccore_dat_w; +wire [31:0] main_maccore_maccore_dat_r; +wire [29:0] main_maccore_maccore_wishbone_adr; +wire [31:0] main_maccore_maccore_wishbone_dat_w; +wire [31:0] main_maccore_maccore_wishbone_dat_r; +wire [3:0] main_maccore_maccore_wishbone_sel; +wire main_maccore_maccore_wishbone_cyc; +wire main_maccore_maccore_wishbone_stb; +reg main_maccore_maccore_wishbone_ack = 1'd0; +wire main_maccore_maccore_wishbone_we; +wire [2:0] main_maccore_maccore_wishbone_cti; +wire [1:0] main_maccore_maccore_wishbone_bte; +reg main_maccore_maccore_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire por_clk; +reg main_maccore_int_rst = 1'd1; +reg main_maccore_ethphy_reset_storage = 1'd0; +reg main_maccore_ethphy_reset_re = 1'd0; +wire eth_rx_clk; +wire eth_rx_rst; +wire eth_tx_clk; +wire eth_tx_rst; +wire main_maccore_ethphy_reset0; +wire main_maccore_ethphy_reset1; +reg [8:0] main_maccore_ethphy_counter = 9'd0; +wire main_maccore_ethphy_counter_done; +wire main_maccore_ethphy_counter_ce; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_valid; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_ready; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_first; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_last; +wire [7:0] main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be; +wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error; +wire main_maccore_ethphy_liteethphymiitx_converter_sink_valid; +wire main_maccore_ethphy_liteethphymiitx_converter_sink_ready; +reg main_maccore_ethphy_liteethphymiitx_converter_sink_first = 1'd0; +reg main_maccore_ethphy_liteethphymiitx_converter_sink_last = 1'd0; +wire [7:0] main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data; +wire main_maccore_ethphy_liteethphymiitx_converter_source_valid; +wire main_maccore_ethphy_liteethphymiitx_converter_source_ready; +wire main_maccore_ethphy_liteethphymiitx_converter_source_first; +wire main_maccore_ethphy_liteethphymiitx_converter_source_last; +wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last; +reg [7:0] main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data = 8'd0; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; +reg [3:0] main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data = 4'd0; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count; +reg main_maccore_ethphy_liteethphymiitx_converter_converter_mux = 1'd0; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_first; +wire main_maccore_ethphy_liteethphymiitx_converter_converter_last; +wire main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; +wire main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; +wire main_maccore_ethphy_liteethphymiitx_converter_source_source_first; +wire main_maccore_ethphy_liteethphymiitx_converter_source_source_last; +wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; +wire main_maccore_ethphy_liteethphymiirx_source_source_valid; +wire main_maccore_ethphy_liteethphymiirx_source_source_ready; +wire main_maccore_ethphy_liteethphymiirx_source_source_first; +wire main_maccore_ethphy_liteethphymiirx_source_source_last; +wire [7:0] main_maccore_ethphy_liteethphymiirx_source_source_payload_data; +reg main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be = 1'd0; +reg main_maccore_ethphy_liteethphymiirx_source_source_payload_error = 1'd0; +reg main_maccore_ethphy_liteethphymiirx_converter_sink_valid = 1'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_sink_ready; +reg main_maccore_ethphy_liteethphymiirx_converter_sink_first = 1'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_sink_last; +reg [3:0] main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data = 4'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_source_valid; +wire main_maccore_ethphy_liteethphymiirx_converter_source_ready; +wire main_maccore_ethphy_liteethphymiirx_converter_source_first; +wire main_maccore_ethphy_liteethphymiirx_converter_source_last; +reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_payload_data = 8'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; +wire [3:0] main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready; +reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_first = 1'd0; +reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data = 8'd0; +reg [1:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0; +reg main_maccore_ethphy_liteethphymiirx_converter_converter_demux = 1'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_converter_load_part; +reg main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all = 1'd0; +wire main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; +wire main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; +wire main_maccore_ethphy_liteethphymiirx_converter_source_source_first; +wire main_maccore_ethphy_liteethphymiirx_converter_source_source_last; +wire [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data; +reg main_maccore_ethphy_liteethphymiirx_converter_reset = 1'd0; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +wire main_maccore_ethphy_w; +reg [2:0] main_maccore_ethphy_storage = 3'd0; +reg main_maccore_ethphy_re = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy_status = 1'd0; +wire main_maccore_ethphy_we; +wire main_maccore_ethphy_data_w; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_tx_gap_inserter_sink_valid; +reg main_tx_gap_inserter_sink_ready = 1'd0; +wire main_tx_gap_inserter_sink_first; +wire main_tx_gap_inserter_sink_last; +wire [7:0] main_tx_gap_inserter_sink_payload_data; +wire main_tx_gap_inserter_sink_payload_last_be; +wire main_tx_gap_inserter_sink_payload_error; +reg main_tx_gap_inserter_source_valid = 1'd0; +wire main_tx_gap_inserter_source_ready; +reg main_tx_gap_inserter_source_first = 1'd0; +reg main_tx_gap_inserter_source_last = 1'd0; +reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; +reg main_tx_gap_inserter_source_payload_last_be = 1'd0; +reg main_tx_gap_inserter_source_payload_error = 1'd0; +reg [3:0] main_tx_gap_inserter_counter = 4'd0; +reg main_tx_gap_inserter_counter_reset = 1'd0; +reg main_tx_gap_inserter_counter_ce = 1'd0; +reg main_preamble_crc_status = 1'd1; +wire main_preamble_crc_we; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +wire main_preamble_inserter_sink_valid; +reg main_preamble_inserter_sink_ready = 1'd0; +wire main_preamble_inserter_sink_first; +wire main_preamble_inserter_sink_last; +wire [7:0] main_preamble_inserter_sink_payload_data; +wire main_preamble_inserter_sink_payload_last_be; +wire main_preamble_inserter_sink_payload_error; +reg main_preamble_inserter_source_valid = 1'd0; +wire main_preamble_inserter_source_ready; +reg main_preamble_inserter_source_first = 1'd0; +reg main_preamble_inserter_source_last = 1'd0; +reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; +wire main_preamble_inserter_source_payload_last_be; +reg main_preamble_inserter_source_payload_error = 1'd0; +reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; +reg [2:0] main_preamble_inserter_cnt = 3'd0; +reg main_preamble_inserter_clr_cnt = 1'd0; +reg main_preamble_inserter_inc_cnt = 1'd0; +wire main_preamble_checker_sink_valid; +reg main_preamble_checker_sink_ready = 1'd0; +wire main_preamble_checker_sink_first; +wire main_preamble_checker_sink_last; +wire [7:0] main_preamble_checker_sink_payload_data; +wire main_preamble_checker_sink_payload_last_be; +wire main_preamble_checker_sink_payload_error; +reg main_preamble_checker_source_valid = 1'd0; +wire main_preamble_checker_source_ready; +reg main_preamble_checker_source_first = 1'd0; +reg main_preamble_checker_source_last = 1'd0; +wire [7:0] main_preamble_checker_source_payload_data; +wire main_preamble_checker_source_payload_last_be; +reg main_preamble_checker_source_payload_error = 1'd0; +reg main_preamble_checker_error = 1'd0; +wire main_crc32_inserter_sink_valid; +reg main_crc32_inserter_sink_ready = 1'd0; +wire main_crc32_inserter_sink_first; +wire main_crc32_inserter_sink_last; +wire [7:0] main_crc32_inserter_sink_payload_data; +wire main_crc32_inserter_sink_payload_last_be; +wire main_crc32_inserter_sink_payload_error; +reg main_crc32_inserter_source_valid = 1'd0; +wire main_crc32_inserter_source_ready; +reg main_crc32_inserter_source_first = 1'd0; +reg main_crc32_inserter_source_last = 1'd0; +reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; +reg main_crc32_inserter_source_payload_last_be = 1'd0; +reg main_crc32_inserter_source_payload_error = 1'd0; +reg [7:0] main_crc32_inserter_data0 = 8'd0; +wire [31:0] main_crc32_inserter_value; +wire main_crc32_inserter_error; +wire [7:0] main_crc32_inserter_data1; +wire [31:0] main_crc32_inserter_last; +reg [31:0] main_crc32_inserter_next = 32'd0; +reg [31:0] main_crc32_inserter_reg = 32'd4294967295; +reg main_crc32_inserter_ce = 1'd0; +reg main_crc32_inserter_reset = 1'd0; +reg [1:0] main_crc32_inserter_cnt = 2'd3; +wire main_crc32_inserter_cnt_done; +reg main_crc32_inserter_is_ongoing0 = 1'd0; +reg main_crc32_inserter_is_ongoing1 = 1'd0; +wire main_crc32_checker_sink_sink_valid; +reg main_crc32_checker_sink_sink_ready = 1'd0; +wire main_crc32_checker_sink_sink_first; +wire main_crc32_checker_sink_sink_last; +wire [7:0] main_crc32_checker_sink_sink_payload_data; +wire main_crc32_checker_sink_sink_payload_last_be; +wire main_crc32_checker_sink_sink_payload_error; +wire main_crc32_checker_source_source_valid; +wire main_crc32_checker_source_source_ready; +reg main_crc32_checker_source_source_first = 1'd0; +wire main_crc32_checker_source_source_last; +wire [7:0] main_crc32_checker_source_source_payload_data; +wire main_crc32_checker_source_source_payload_last_be; +reg main_crc32_checker_source_source_payload_error = 1'd0; +wire main_crc32_checker_error; +wire [7:0] main_crc32_checker_crc_data0; +wire [31:0] main_crc32_checker_crc_value; +wire main_crc32_checker_crc_error; +wire [7:0] main_crc32_checker_crc_data1; +wire [31:0] main_crc32_checker_crc_last; +reg [31:0] main_crc32_checker_crc_next = 32'd0; +reg [31:0] main_crc32_checker_crc_reg = 32'd4294967295; +reg main_crc32_checker_crc_ce = 1'd0; +reg main_crc32_checker_crc_reset = 1'd0; +reg main_crc32_checker_syncfifo_sink_valid = 1'd0; +wire main_crc32_checker_syncfifo_sink_ready; +wire main_crc32_checker_syncfifo_sink_first; +wire main_crc32_checker_syncfifo_sink_last; +wire [7:0] main_crc32_checker_syncfifo_sink_payload_data; +wire main_crc32_checker_syncfifo_sink_payload_last_be; +wire main_crc32_checker_syncfifo_sink_payload_error; +wire main_crc32_checker_syncfifo_source_valid; +wire main_crc32_checker_syncfifo_source_ready; +wire main_crc32_checker_syncfifo_source_first; +wire main_crc32_checker_syncfifo_source_last; +wire [7:0] main_crc32_checker_syncfifo_source_payload_data; +wire main_crc32_checker_syncfifo_source_payload_last_be; +wire main_crc32_checker_syncfifo_source_payload_error; +wire main_crc32_checker_syncfifo_syncfifo_we; +wire main_crc32_checker_syncfifo_syncfifo_writable; +wire main_crc32_checker_syncfifo_syncfifo_re; +wire main_crc32_checker_syncfifo_syncfifo_readable; +wire [11:0] main_crc32_checker_syncfifo_syncfifo_din; +wire [11:0] main_crc32_checker_syncfifo_syncfifo_dout; +reg [2:0] main_crc32_checker_syncfifo_level = 3'd0; +reg main_crc32_checker_syncfifo_replace = 1'd0; +reg [2:0] main_crc32_checker_syncfifo_produce = 3'd0; +reg [2:0] main_crc32_checker_syncfifo_consume = 3'd0; +reg [2:0] main_crc32_checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_crc32_checker_syncfifo_wrport_dat_r; +wire main_crc32_checker_syncfifo_wrport_we; +wire [11:0] main_crc32_checker_syncfifo_wrport_dat_w; +wire main_crc32_checker_syncfifo_do_read; +wire [2:0] main_crc32_checker_syncfifo_rdport_adr; +wire [11:0] main_crc32_checker_syncfifo_rdport_dat_r; +wire [7:0] main_crc32_checker_syncfifo_fifo_in_payload_data; +wire main_crc32_checker_syncfifo_fifo_in_payload_last_be; +wire main_crc32_checker_syncfifo_fifo_in_payload_error; +wire main_crc32_checker_syncfifo_fifo_in_first; +wire main_crc32_checker_syncfifo_fifo_in_last; +wire [7:0] main_crc32_checker_syncfifo_fifo_out_payload_data; +wire main_crc32_checker_syncfifo_fifo_out_payload_last_be; +wire main_crc32_checker_syncfifo_fifo_out_payload_error; +wire main_crc32_checker_syncfifo_fifo_out_first; +wire main_crc32_checker_syncfifo_fifo_out_last; +reg main_crc32_checker_fifo_reset = 1'd0; +wire main_crc32_checker_fifo_in; +wire main_crc32_checker_fifo_out; +wire main_crc32_checker_fifo_full; +wire main_ps_preamble_error_i; +wire main_ps_preamble_error_o; +reg main_ps_preamble_error_toggle_i = 1'd0; +wire main_ps_preamble_error_toggle_o; +reg main_ps_preamble_error_toggle_o_r = 1'd0; +wire main_ps_crc_error_i; +wire main_ps_crc_error_o; +reg main_ps_crc_error_toggle_i = 1'd0; +wire main_ps_crc_error_toggle_o; +reg main_ps_crc_error_toggle_o_r = 1'd0; +wire main_padding_inserter_sink_valid; +reg main_padding_inserter_sink_ready = 1'd0; +wire main_padding_inserter_sink_first; +wire main_padding_inserter_sink_last; +wire [7:0] main_padding_inserter_sink_payload_data; +wire main_padding_inserter_sink_payload_last_be; +wire main_padding_inserter_sink_payload_error; +reg main_padding_inserter_source_valid = 1'd0; +wire main_padding_inserter_source_ready; +reg main_padding_inserter_source_first = 1'd0; +reg main_padding_inserter_source_last = 1'd0; +reg [7:0] main_padding_inserter_source_payload_data = 8'd0; +reg main_padding_inserter_source_payload_last_be = 1'd0; +reg main_padding_inserter_source_payload_error = 1'd0; +reg [15:0] main_padding_inserter_counter = 16'd1; +wire main_padding_inserter_counter_done; +reg main_padding_inserter_counter_reset = 1'd0; +reg main_padding_inserter_counter_ce = 1'd0; +wire main_padding_checker_sink_valid; +wire main_padding_checker_sink_ready; +wire main_padding_checker_sink_first; +wire main_padding_checker_sink_last; +wire [7:0] main_padding_checker_sink_payload_data; +wire main_padding_checker_sink_payload_last_be; +wire main_padding_checker_sink_payload_error; +wire main_padding_checker_source_valid; +wire main_padding_checker_source_ready; +wire main_padding_checker_source_first; +wire main_padding_checker_source_last; +wire [7:0] main_padding_checker_source_payload_data; +wire main_padding_checker_source_payload_last_be; +wire main_padding_checker_source_payload_error; +wire main_tx_last_be_sink_valid; +wire main_tx_last_be_sink_ready; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_last_be; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_source_valid; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_first = 1'd0; +wire main_tx_last_be_source_last; +wire [7:0] main_tx_last_be_source_payload_data; +reg main_tx_last_be_source_payload_last_be = 1'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_ongoing = 1'd1; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_source_valid; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_payload_error; +wire main_tx_converter_sink_valid; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire [3:0] main_tx_converter_sink_payload_error; +wire main_tx_converter_source_valid; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_rx_converter_sink_valid; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_source_valid; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +wire main_rx_converter_converter_sink_valid; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_source_valid; +wire main_rx_converter_converter_source_ready; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_tx_cdc_sink_valid; +wire main_tx_cdc_sink_ready; +wire main_tx_cdc_sink_first; +wire main_tx_cdc_sink_last; +wire [31:0] main_tx_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_sink_payload_last_be; +wire [3:0] main_tx_cdc_sink_payload_error; +wire main_tx_cdc_source_valid; +wire main_tx_cdc_source_ready; +wire main_tx_cdc_source_first; +wire main_tx_cdc_source_last; +wire [31:0] main_tx_cdc_source_payload_data; +wire [3:0] main_tx_cdc_source_payload_last_be; +wire [3:0] main_tx_cdc_source_payload_error; +wire main_tx_cdc_asyncfifo_we; +wire main_tx_cdc_asyncfifo_writable; +wire main_tx_cdc_asyncfifo_re; +wire main_tx_cdc_asyncfifo_readable; +wire [41:0] main_tx_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_asyncfifo_dout; +wire main_tx_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [6:0] main_tx_cdc_graycounter0_q = 7'd0; +wire [6:0] main_tx_cdc_graycounter0_q_next; +reg [6:0] main_tx_cdc_graycounter0_q_binary = 7'd0; +reg [6:0] main_tx_cdc_graycounter0_q_next_binary = 7'd0; +wire main_tx_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [6:0] main_tx_cdc_graycounter1_q = 7'd0; +wire [6:0] main_tx_cdc_graycounter1_q_next; +reg [6:0] main_tx_cdc_graycounter1_q_binary = 7'd0; +reg [6:0] main_tx_cdc_graycounter1_q_next_binary = 7'd0; +wire [6:0] main_tx_cdc_produce_rdomain; +wire [6:0] main_tx_cdc_consume_wdomain; +wire [5:0] main_tx_cdc_wrport_adr; +wire [41:0] main_tx_cdc_wrport_dat_r; +wire main_tx_cdc_wrport_we; +wire [41:0] main_tx_cdc_wrport_dat_w; +wire [5:0] main_tx_cdc_rdport_adr; +wire [41:0] main_tx_cdc_rdport_dat_r; +wire [31:0] main_tx_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_fifo_in_payload_last_be; +wire [3:0] main_tx_cdc_fifo_in_payload_error; +wire main_tx_cdc_fifo_in_first; +wire main_tx_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_fifo_out_payload_last_be; +wire [3:0] main_tx_cdc_fifo_out_payload_error; +wire main_tx_cdc_fifo_out_first; +wire main_tx_cdc_fifo_out_last; +wire main_rx_cdc_sink_valid; +wire main_rx_cdc_sink_ready; +wire main_rx_cdc_sink_first; +wire main_rx_cdc_sink_last; +wire [31:0] main_rx_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_sink_payload_last_be; +wire [3:0] main_rx_cdc_sink_payload_error; +wire main_rx_cdc_source_valid; +wire main_rx_cdc_source_ready; +wire main_rx_cdc_source_first; +wire main_rx_cdc_source_last; +wire [31:0] main_rx_cdc_source_payload_data; +wire [3:0] main_rx_cdc_source_payload_last_be; +wire [3:0] main_rx_cdc_source_payload_error; +wire main_rx_cdc_asyncfifo_we; +wire main_rx_cdc_asyncfifo_writable; +wire main_rx_cdc_asyncfifo_re; +wire main_rx_cdc_asyncfifo_readable; +wire [41:0] main_rx_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_asyncfifo_dout; +wire main_rx_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [6:0] main_rx_cdc_graycounter0_q = 7'd0; +wire [6:0] main_rx_cdc_graycounter0_q_next; +reg [6:0] main_rx_cdc_graycounter0_q_binary = 7'd0; +reg [6:0] main_rx_cdc_graycounter0_q_next_binary = 7'd0; +wire main_rx_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [6:0] main_rx_cdc_graycounter1_q = 7'd0; +wire [6:0] main_rx_cdc_graycounter1_q_next; +reg [6:0] main_rx_cdc_graycounter1_q_binary = 7'd0; +reg [6:0] main_rx_cdc_graycounter1_q_next_binary = 7'd0; +wire [6:0] main_rx_cdc_produce_rdomain; +wire [6:0] main_rx_cdc_consume_wdomain; +wire [5:0] main_rx_cdc_wrport_adr; +wire [41:0] main_rx_cdc_wrport_dat_r; +wire main_rx_cdc_wrport_we; +wire [41:0] main_rx_cdc_wrport_dat_w; +wire [5:0] main_rx_cdc_rdport_adr; +wire [41:0] main_rx_cdc_rdport_dat_r; +wire [31:0] main_rx_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_fifo_in_payload_last_be; +wire [3:0] main_rx_cdc_fifo_in_payload_error; +wire main_rx_cdc_fifo_in_first; +wire main_rx_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_fifo_out_payload_last_be; +wire [3:0] main_rx_cdc_fifo_out_payload_error; +wire main_rx_cdc_fifo_out_first; +wire main_rx_cdc_fifo_out_last; +wire main_sink_valid; +wire main_sink_ready; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_last_be; +wire [3:0] main_sink_payload_error; +wire main_source_valid; +wire main_source_ready; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_last_be; +wire [3:0] main_source_payload_error; +wire [29:0] main_bus_adr; +wire [31:0] main_bus_dat_w; +wire [31:0] main_bus_dat_r; +wire [3:0] main_bus_sel; +wire main_bus_cyc; +wire main_bus_stb; +wire main_bus_ack; +wire main_bus_we; +wire [2:0] main_bus_cti; +wire [1:0] main_bus_bte; +wire main_bus_err; +wire main_writer_sink_sink_valid; +reg main_writer_sink_sink_ready = 1'd1; +wire main_writer_sink_sink_first; +wire main_writer_sink_sink_last; +wire [31:0] main_writer_sink_sink_payload_data; +wire [3:0] main_writer_sink_sink_payload_last_be; +wire [3:0] main_writer_sink_sink_payload_error; +wire main_writer_slot_status; +wire main_writer_slot_we; +wire [31:0] main_writer_length_status; +wire main_writer_length_we; +reg [31:0] main_writer_errors_status = 32'd0; +wire main_writer_errors_we; +wire main_writer_irq; +wire main_writer_available_status; +wire main_writer_available_pending; +wire main_writer_available_trigger; +reg main_writer_available_clear = 1'd0; +wire main_writer_status_re; +wire main_writer_status_r; +wire main_writer_status_we; +wire main_writer_status_w; +wire main_writer_pending_re; +wire main_writer_pending_r; +wire main_writer_pending_we; +wire main_writer_pending_w; +reg main_writer_storage = 1'd0; +reg main_writer_re = 1'd0; +reg [2:0] main_writer_inc = 3'd0; +reg [31:0] main_writer_counter = 32'd0; +reg main_writer_slot = 1'd0; +reg main_writer_slot_ce = 1'd0; +reg main_writer_ongoing = 1'd0; +reg main_writer_fifo_sink_valid = 1'd0; +wire main_writer_fifo_sink_ready; +reg main_writer_fifo_sink_first = 1'd0; +reg main_writer_fifo_sink_last = 1'd0; +wire main_writer_fifo_sink_payload_slot; +wire [31:0] main_writer_fifo_sink_payload_length; +wire main_writer_fifo_source_valid; +wire main_writer_fifo_source_ready; +wire main_writer_fifo_source_first; +wire main_writer_fifo_source_last; +wire main_writer_fifo_source_payload_slot; +wire [31:0] main_writer_fifo_source_payload_length; +wire main_writer_fifo_syncfifo_we; +wire main_writer_fifo_syncfifo_writable; +wire main_writer_fifo_syncfifo_re; +wire main_writer_fifo_syncfifo_readable; +wire [34:0] main_writer_fifo_syncfifo_din; +wire [34:0] main_writer_fifo_syncfifo_dout; +reg [1:0] main_writer_fifo_level = 2'd0; +reg main_writer_fifo_replace = 1'd0; +reg main_writer_fifo_produce = 1'd0; +reg main_writer_fifo_consume = 1'd0; +reg main_writer_fifo_wrport_adr = 1'd0; +wire [34:0] main_writer_fifo_wrport_dat_r; +wire main_writer_fifo_wrport_we; +wire [34:0] main_writer_fifo_wrport_dat_w; +wire main_writer_fifo_do_read; +wire main_writer_fifo_rdport_adr; +wire [34:0] main_writer_fifo_rdport_dat_r; +wire main_writer_fifo_fifo_in_payload_slot; +wire [31:0] main_writer_fifo_fifo_in_payload_length; +wire main_writer_fifo_fifo_in_first; +wire main_writer_fifo_fifo_in_last; +wire main_writer_fifo_fifo_out_payload_slot; +wire [31:0] main_writer_fifo_fifo_out_payload_length; +wire main_writer_fifo_fifo_out_first; +wire main_writer_fifo_fifo_out_last; +reg [8:0] main_writer_memory0_adr = 9'd0; +wire [31:0] main_writer_memory0_dat_r; +reg main_writer_memory0_we = 1'd0; +reg [31:0] main_writer_memory0_dat_w = 32'd0; +reg [8:0] main_writer_memory1_adr = 9'd0; +wire [31:0] main_writer_memory1_dat_r; +reg main_writer_memory1_we = 1'd0; +reg [31:0] main_writer_memory1_dat_w = 32'd0; +reg main_reader_source_source_valid = 1'd0; +wire main_reader_source_source_ready; +reg main_reader_source_source_first = 1'd0; +reg main_reader_source_source_last = 1'd0; +reg [31:0] main_reader_source_source_payload_data = 32'd0; +reg [3:0] main_reader_source_source_payload_last_be = 4'd0; +reg [3:0] main_reader_source_source_payload_error = 4'd0; +wire main_reader_start_re; +wire main_reader_start_r; +wire main_reader_start_we; +reg main_reader_start_w = 1'd0; +wire main_reader_ready_status; +wire main_reader_ready_we; +wire [1:0] main_reader_level_status; +wire main_reader_level_we; +reg main_reader_slot_storage = 1'd0; +reg main_reader_slot_re = 1'd0; +reg [10:0] main_reader_length_storage = 11'd0; +reg main_reader_length_re = 1'd0; +wire main_reader_irq; +wire main_reader_done_status; +reg main_reader_done_pending = 1'd0; +reg main_reader_done_trigger = 1'd0; +reg main_reader_done_clear = 1'd0; +wire main_reader_eventmanager_status_re; +wire main_reader_eventmanager_status_r; +wire main_reader_eventmanager_status_we; +wire main_reader_eventmanager_status_w; +wire main_reader_eventmanager_pending_re; +wire main_reader_eventmanager_pending_r; +wire main_reader_eventmanager_pending_we; +wire main_reader_eventmanager_pending_w; +reg main_reader_eventmanager_storage = 1'd0; +reg main_reader_eventmanager_re = 1'd0; +wire main_reader_fifo_sink_valid; +wire main_reader_fifo_sink_ready; +reg main_reader_fifo_sink_first = 1'd0; +reg main_reader_fifo_sink_last = 1'd0; +wire main_reader_fifo_sink_payload_slot; +wire [10:0] main_reader_fifo_sink_payload_length; +wire main_reader_fifo_source_valid; +reg main_reader_fifo_source_ready = 1'd0; +wire main_reader_fifo_source_first; +wire main_reader_fifo_source_last; +wire main_reader_fifo_source_payload_slot; +wire [10:0] main_reader_fifo_source_payload_length; +wire main_reader_fifo_syncfifo_we; +wire main_reader_fifo_syncfifo_writable; +wire main_reader_fifo_syncfifo_re; +wire main_reader_fifo_syncfifo_readable; +wire [13:0] main_reader_fifo_syncfifo_din; +wire [13:0] main_reader_fifo_syncfifo_dout; +reg [1:0] main_reader_fifo_level = 2'd0; +reg main_reader_fifo_replace = 1'd0; +reg main_reader_fifo_produce = 1'd0; +reg main_reader_fifo_consume = 1'd0; +reg main_reader_fifo_wrport_adr = 1'd0; +wire [13:0] main_reader_fifo_wrport_dat_r; +wire main_reader_fifo_wrport_we; +wire [13:0] main_reader_fifo_wrport_dat_w; +wire main_reader_fifo_do_read; +wire main_reader_fifo_rdport_adr; +wire [13:0] main_reader_fifo_rdport_dat_r; +wire main_reader_fifo_fifo_in_payload_slot; +wire [10:0] main_reader_fifo_fifo_in_payload_length; +wire main_reader_fifo_fifo_in_first; +wire main_reader_fifo_fifo_in_last; +wire main_reader_fifo_fifo_out_payload_slot; +wire [10:0] main_reader_fifo_fifo_out_payload_length; +wire main_reader_fifo_fifo_out_first; +wire main_reader_fifo_fifo_out_last; +reg [10:0] main_reader_counter = 11'd0; +wire [8:0] main_reader_memory0_adr; +wire [31:0] main_reader_memory0_dat_r; +wire [8:0] main_reader_memory1_adr; +wire [31:0] main_reader_memory1_dat_r; +wire main_ev_irq; +wire [29:0] main_sram0_bus_adr0; +wire [31:0] main_sram0_bus_dat_w0; +wire [31:0] main_sram0_bus_dat_r0; +wire [3:0] main_sram0_bus_sel0; +wire main_sram0_bus_cyc0; +wire main_sram0_bus_stb0; +reg main_sram0_bus_ack0 = 1'd0; +wire main_sram0_bus_we0; +wire [2:0] main_sram0_bus_cti0; +wire [1:0] main_sram0_bus_bte0; +reg main_sram0_bus_err0 = 1'd0; +wire [8:0] main_sram0_adr0; +wire [31:0] main_sram0_dat_r0; +wire [29:0] main_sram1_bus_adr0; +wire [31:0] main_sram1_bus_dat_w0; +wire [31:0] main_sram1_bus_dat_r0; +wire [3:0] main_sram1_bus_sel0; +wire main_sram1_bus_cyc0; +wire main_sram1_bus_stb0; +reg main_sram1_bus_ack0 = 1'd0; +wire main_sram1_bus_we0; +wire [2:0] main_sram1_bus_cti0; +wire [1:0] main_sram1_bus_bte0; +reg main_sram1_bus_err0 = 1'd0; +wire [8:0] main_sram1_adr0; +wire [31:0] main_sram1_dat_r0; +wire [29:0] main_sram0_bus_adr1; +wire [31:0] main_sram0_bus_dat_w1; +wire [31:0] main_sram0_bus_dat_r1; +wire [3:0] main_sram0_bus_sel1; +wire main_sram0_bus_cyc1; +wire main_sram0_bus_stb1; +reg main_sram0_bus_ack1 = 1'd0; +wire main_sram0_bus_we1; +wire [2:0] main_sram0_bus_cti1; +wire [1:0] main_sram0_bus_bte1; +reg main_sram0_bus_err1 = 1'd0; +wire [8:0] main_sram0_adr1; +wire [31:0] main_sram0_dat_r1; +reg [3:0] main_sram0_we = 4'd0; +wire [31:0] main_sram0_dat_w; +wire [29:0] main_sram1_bus_adr1; +wire [31:0] main_sram1_bus_dat_w1; +wire [31:0] main_sram1_bus_dat_r1; +wire [3:0] main_sram1_bus_sel1; +wire main_sram1_bus_cyc1; +wire main_sram1_bus_stb1; +reg main_sram1_bus_ack1 = 1'd0; +wire main_sram1_bus_we1; +wire [2:0] main_sram1_bus_cti1; +wire [1:0] main_sram1_bus_bte1; +reg main_sram1_bus_err1 = 1'd0; +wire [8:0] main_sram1_adr1; +wire [31:0] main_sram1_dat_r1; +reg [3:0] main_sram1_we = 4'd0; +wire [31:0] main_sram1_dat_w; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg builder_state = 1'd0; +reg builder_next_state = 1'd0; +reg builder_liteethmacgap_state = 1'd0; +reg builder_liteethmacgap_next_state = 1'd0; +reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; +reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; +reg builder_liteethmacpreamblechecker_state = 1'd0; +reg builder_liteethmacpreamblechecker_next_state = 1'd0; +reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; +reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; +reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; +reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; +reg builder_liteethmacpaddinginserter_state = 1'd0; +reg builder_liteethmacpaddinginserter_next_state = 1'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [31:0] main_writer_counter_t_next_value = 32'd0; +reg main_writer_counter_t_next_value_ce = 1'd0; +reg [31:0] main_writer_errors_status_f_next_value = 32'd0; +reg main_writer_errors_status_f_next_value_ce = 1'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [10:0] main_reader_counter_next_value = 11'd0; +reg main_reader_counter_next_value_ce = 1'd0; +wire [29:0] builder_shared_adr; +wire [31:0] builder_shared_dat_w; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [3:0] builder_shared_sel; +wire builder_shared_cyc; +wire builder_shared_stb; +reg builder_shared_ack = 1'd0; +wire builder_shared_we; +wire [2:0] builder_shared_cti; +wire [1:0] builder_shared_bte; +wire builder_shared_err; +wire builder_request; +wire builder_grant; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_error = 1'd0; +wire builder_wait; +wire builder_done; +reg [19:0] builder_count = 20'd1000000; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire builder_csrbank0_reset0_re; +wire builder_csrbank0_reset0_r; +wire builder_csrbank0_reset0_we; +wire builder_csrbank0_reset0_w; +wire builder_csrbank0_scratch0_re; +wire [31:0] builder_csrbank0_scratch0_r; +wire builder_csrbank0_scratch0_we; +wire [31:0] builder_csrbank0_scratch0_w; +wire builder_csrbank0_bus_errors_re; +wire [31:0] builder_csrbank0_bus_errors_r; +wire builder_csrbank0_bus_errors_we; +wire [31:0] builder_csrbank0_bus_errors_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire builder_csrbank1_sram_writer_slot_re; +wire builder_csrbank1_sram_writer_slot_r; +wire builder_csrbank1_sram_writer_slot_we; +wire builder_csrbank1_sram_writer_slot_w; +wire builder_csrbank1_sram_writer_length_re; +wire [31:0] builder_csrbank1_sram_writer_length_r; +wire builder_csrbank1_sram_writer_length_we; +wire [31:0] builder_csrbank1_sram_writer_length_w; +wire builder_csrbank1_sram_writer_errors_re; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +wire builder_csrbank1_sram_writer_errors_we; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +wire builder_csrbank1_sram_writer_ev_enable0_re; +wire builder_csrbank1_sram_writer_ev_enable0_r; +wire builder_csrbank1_sram_writer_ev_enable0_we; +wire builder_csrbank1_sram_writer_ev_enable0_w; +wire builder_csrbank1_sram_reader_ready_re; +wire builder_csrbank1_sram_reader_ready_r; +wire builder_csrbank1_sram_reader_ready_we; +wire builder_csrbank1_sram_reader_ready_w; +wire builder_csrbank1_sram_reader_level_re; +wire [1:0] builder_csrbank1_sram_reader_level_r; +wire builder_csrbank1_sram_reader_level_we; +wire [1:0] builder_csrbank1_sram_reader_level_w; +wire builder_csrbank1_sram_reader_slot0_re; +wire builder_csrbank1_sram_reader_slot0_r; +wire builder_csrbank1_sram_reader_slot0_we; +wire builder_csrbank1_sram_reader_slot0_w; +wire builder_csrbank1_sram_reader_length0_re; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +wire builder_csrbank1_sram_reader_length0_we; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +wire builder_csrbank1_sram_reader_ev_enable0_re; +wire builder_csrbank1_sram_reader_ev_enable0_r; +wire builder_csrbank1_sram_reader_ev_enable0_we; +wire builder_csrbank1_sram_reader_ev_enable0_w; +wire builder_csrbank1_preamble_crc_re; +wire builder_csrbank1_preamble_crc_r; +wire builder_csrbank1_preamble_crc_we; +wire builder_csrbank1_preamble_crc_w; +wire builder_csrbank1_preamble_errors_re; +wire [31:0] builder_csrbank1_preamble_errors_r; +wire builder_csrbank1_preamble_errors_we; +wire [31:0] builder_csrbank1_preamble_errors_w; +wire builder_csrbank1_crc_errors_re; +wire [31:0] builder_csrbank1_crc_errors_r; +wire builder_csrbank1_crc_errors_we; +wire [31:0] builder_csrbank1_crc_errors_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire builder_csrbank2_crg_reset0_re; +wire builder_csrbank2_crg_reset0_r; +wire builder_csrbank2_crg_reset0_we; +wire builder_csrbank2_crg_reset0_w; +wire builder_csrbank2_mdio_w0_re; +wire [2:0] builder_csrbank2_mdio_w0_r; +wire builder_csrbank2_mdio_w0_we; +wire [2:0] builder_csrbank2_mdio_w0_w; +wire builder_csrbank2_mdio_r_re; +wire builder_csrbank2_mdio_r_r; +wire builder_csrbank2_mdio_r_we; +wire builder_csrbank2_mdio_r_w; +wire builder_csrbank2_sel; +wire [13:0] builder_adr; +wire builder_we; +wire [31:0] builder_dat_w; +wire [31:0] builder_dat_r; +reg [29:0] builder_array_muxed0 = 30'd0; +reg [31:0] builder_array_muxed1 = 32'd0; +reg [3:0] builder_array_muxed2 = 4'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg [2:0] builder_array_muxed6 = 3'd0; +reg [1:0] builder_array_muxed7 = 2'd0; +wire builder_rst_meta0; +wire builder_rst_meta1; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl3_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl3_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl4_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl4_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl5_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl5_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl6_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] builder_xilinxmultiregimpl6_regs1 = 7'd0; + +assign interrupt = main_ev_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign main_maccore_maccore_reset = main_maccore_maccore_reset_re; +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign main_maccore_maccore_dat_w = main_maccore_maccore_wishbone_dat_w; +assign main_maccore_maccore_wishbone_dat_r = main_maccore_maccore_dat_r; +always @(*) begin + main_maccore_maccore_we <= 1'd0; + main_maccore_maccore_wishbone_ack <= 1'd0; + builder_next_state <= 1'd0; + main_maccore_maccore_adr <= 14'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + main_maccore_maccore_wishbone_ack <= 1'd1; + builder_next_state <= 1'd0; + end + default: begin + if ((main_maccore_maccore_wishbone_cyc & main_maccore_maccore_wishbone_stb)) begin + main_maccore_maccore_adr <= main_maccore_maccore_wishbone_adr; + main_maccore_maccore_we <= (main_maccore_maccore_wishbone_we & (main_maccore_maccore_wishbone_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase +end +assign sys_clk = sys_clock; +assign por_clk = sys_clock; +assign sys_rst = main_maccore_int_rst; +assign eth_rx_clk = mii_eth_clocks_rx; +assign eth_tx_clk = mii_eth_clocks_tx; +assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); +assign mii_eth_rst_n = (~main_maccore_ethphy_reset0); +assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); +assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_liteethphymiitx_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_sink_sink_valid; +assign main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data = main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_sink_ready; +assign main_maccore_ethphy_liteethphymiitx_converter_source_ready = 1'd1; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_converter_sink_valid; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiitx_converter_sink_first; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiitx_converter_sink_last; +assign main_maccore_ethphy_liteethphymiitx_converter_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; +always @(*) begin + main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0; + main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[3:0]; + main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[7:4]; +end +assign main_maccore_ethphy_liteethphymiitx_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; +assign main_maccore_ethphy_liteethphymiitx_converter_source_first = main_maccore_ethphy_liteethphymiitx_converter_source_source_first; +assign main_maccore_ethphy_liteethphymiitx_converter_source_last = main_maccore_ethphy_liteethphymiitx_converter_source_source_last; +assign main_maccore_ethphy_liteethphymiitx_converter_source_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_ready; +assign {main_maccore_ethphy_liteethphymiitx_converter_source_payload_data} = main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; +assign main_maccore_ethphy_liteethphymiitx_converter_source_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; +assign main_maccore_ethphy_liteethphymiitx_converter_source_source_first = main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; +assign main_maccore_ethphy_liteethphymiitx_converter_source_source_last = main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; +assign main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd0); +assign main_maccore_ethphy_liteethphymiitx_converter_converter_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd1); +assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; +assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first & main_maccore_ethphy_liteethphymiitx_converter_converter_first); +assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last & main_maccore_ethphy_liteethphymiitx_converter_converter_last); +assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready = (main_maccore_ethphy_liteethphymiitx_converter_converter_last & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready); +always @(*) begin + main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= 4'd0; + case (main_maccore_ethphy_liteethphymiitx_converter_converter_mux) + 1'd0: begin + main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0]; + end + default: begin + main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4]; + end + endcase +end +assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count = main_maccore_ethphy_liteethphymiitx_converter_converter_last; +assign main_maccore_ethphy_liteethphymiirx_converter_sink_last = (~mii_eth_rx_dv); +assign main_maccore_ethphy_liteethphymiirx_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_valid; +assign main_maccore_ethphy_liteethphymiirx_converter_source_ready = main_maccore_ethphy_liteethphymiirx_source_source_ready; +assign main_maccore_ethphy_liteethphymiirx_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_first; +assign main_maccore_ethphy_liteethphymiirx_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_last; +assign main_maccore_ethphy_liteethphymiirx_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_source_payload_data; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiirx_converter_sink_valid; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiirx_converter_sink_first; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiirx_converter_sink_last; +assign main_maccore_ethphy_liteethphymiirx_converter_sink_ready = main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data = {main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data}; +assign main_maccore_ethphy_liteethphymiirx_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; +assign main_maccore_ethphy_liteethphymiirx_converter_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_source_first; +assign main_maccore_ethphy_liteethphymiirx_converter_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_source_last; +assign main_maccore_ethphy_liteethphymiirx_converter_source_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_ready; +always @(*) begin + main_maccore_ethphy_liteethphymiirx_converter_source_payload_data <= 8'd0; + main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[3:0]; + main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[7:4]; +end +assign main_maccore_ethphy_liteethphymiirx_converter_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; +assign main_maccore_ethphy_liteethphymiirx_converter_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_converter_source_first; +assign main_maccore_ethphy_liteethphymiirx_converter_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_converter_source_last; +assign main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready = ((~main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all) | main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready); +assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all; +assign main_maccore_ethphy_liteethphymiirx_converter_converter_load_part = (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready); +assign mii_eth_mdc = main_maccore_ethphy_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy_storage[2]; +assign main_tx_cdc_sink_valid = main_source_valid; +assign main_source_ready = main_tx_cdc_sink_ready; +assign main_tx_cdc_sink_first = main_source_first; +assign main_tx_cdc_sink_last = main_source_last; +assign main_tx_cdc_sink_payload_data = main_source_payload_data; +assign main_tx_cdc_sink_payload_last_be = main_source_payload_last_be; +assign main_tx_cdc_sink_payload_error = main_source_payload_error; +assign main_sink_valid = main_rx_cdc_source_valid; +assign main_rx_cdc_source_ready = main_sink_ready; +assign main_sink_first = main_rx_cdc_source_first; +assign main_sink_last = main_rx_cdc_source_last; +assign main_sink_payload_data = main_rx_cdc_source_payload_data; +assign main_sink_payload_last_be = main_rx_cdc_source_payload_last_be; +assign main_sink_payload_error = main_rx_cdc_source_payload_error; +assign main_ps_preamble_error_i = main_preamble_checker_error; +assign main_ps_crc_error_i = main_crc32_checker_error; +always @(*) begin + main_tx_gap_inserter_source_valid <= 1'd0; + main_tx_gap_inserter_source_first <= 1'd0; + main_tx_gap_inserter_source_last <= 1'd0; + main_tx_gap_inserter_source_payload_data <= 8'd0; + main_tx_gap_inserter_source_payload_last_be <= 1'd0; + main_tx_gap_inserter_source_payload_error <= 1'd0; + main_tx_gap_inserter_counter_reset <= 1'd0; + builder_liteethmacgap_next_state <= 1'd0; + main_tx_gap_inserter_counter_ce <= 1'd0; + main_tx_gap_inserter_sink_ready <= 1'd0; + builder_liteethmacgap_next_state <= builder_liteethmacgap_state; + case (builder_liteethmacgap_state) + 1'd1: begin + main_tx_gap_inserter_counter_ce <= 1'd1; + if ((main_tx_gap_inserter_counter == 4'd11)) begin + builder_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_inserter_counter_reset <= 1'd1; + main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; + main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; + main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; + main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; + main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; + main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; + main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; + if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin + builder_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; +always @(*) begin + builder_liteethmacpreambleinserter_next_state <= 2'd0; + main_preamble_inserter_source_last <= 1'd0; + main_preamble_inserter_source_payload_data <= 8'd0; + main_preamble_inserter_source_payload_error <= 1'd0; + main_preamble_inserter_clr_cnt <= 1'd0; + main_preamble_inserter_sink_ready <= 1'd0; + main_preamble_inserter_inc_cnt <= 1'd0; + main_preamble_inserter_source_valid <= 1'd0; + main_preamble_inserter_source_first <= 1'd0; + main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; + builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; + case (builder_liteethmacpreambleinserter_state) + 1'd1: begin + main_preamble_inserter_source_valid <= 1'd1; + case (main_preamble_inserter_cnt) + 1'd0: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; + end + 1'd1: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; + end + 2'd2: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; + end + 2'd3: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; + end + 3'd4: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; + end + 3'd5: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; + end + 3'd6: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; + end + default: begin + main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; + end + endcase + if ((main_preamble_inserter_cnt == 3'd7)) begin + if (main_preamble_inserter_source_ready) begin + builder_liteethmacpreambleinserter_next_state <= 2'd2; + end + end else begin + main_preamble_inserter_inc_cnt <= main_preamble_inserter_source_ready; + end + end + 2'd2: begin + main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; + main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; + main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; + main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; + main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; + if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin + builder_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_preamble_inserter_sink_ready <= 1'd1; + main_preamble_inserter_clr_cnt <= 1'd1; + if (main_preamble_inserter_sink_valid) begin + main_preamble_inserter_sink_ready <= 1'd0; + builder_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; +assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; +always @(*) begin + main_preamble_checker_source_last <= 1'd0; + main_preamble_checker_source_payload_error <= 1'd0; + main_preamble_checker_source_first <= 1'd0; + main_preamble_checker_error <= 1'd0; + builder_liteethmacpreamblechecker_next_state <= 1'd0; + main_preamble_checker_source_valid <= 1'd0; + main_preamble_checker_sink_ready <= 1'd0; + builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; + case (builder_liteethmacpreamblechecker_state) + 1'd1: begin + main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; + main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; + main_preamble_checker_source_first <= main_preamble_checker_sink_first; + main_preamble_checker_source_last <= main_preamble_checker_sink_last; + main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; + if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin + builder_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_preamble_checker_sink_ready <= 1'd1; + if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin + builder_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin + main_preamble_checker_error <= 1'd1; + end + end + endcase +end +assign main_crc32_inserter_cnt_done = (main_crc32_inserter_cnt == 1'd0); +assign main_crc32_inserter_data1 = main_crc32_inserter_data0; +assign main_crc32_inserter_last = main_crc32_inserter_reg; +assign main_crc32_inserter_value = (~{main_crc32_inserter_reg[0], main_crc32_inserter_reg[1], main_crc32_inserter_reg[2], main_crc32_inserter_reg[3], main_crc32_inserter_reg[4], main_crc32_inserter_reg[5], main_crc32_inserter_reg[6], main_crc32_inserter_reg[7], main_crc32_inserter_reg[8], main_crc32_inserter_reg[9], main_crc32_inserter_reg[10], main_crc32_inserter_reg[11], main_crc32_inserter_reg[12], main_crc32_inserter_reg[13], main_crc32_inserter_reg[14], main_crc32_inserter_reg[15], main_crc32_inserter_reg[16], main_crc32_inserter_reg[17], main_crc32_inserter_reg[18], main_crc32_inserter_reg[19], main_crc32_inserter_reg[20], main_crc32_inserter_reg[21], main_crc32_inserter_reg[22], main_crc32_inserter_reg[23], main_crc32_inserter_reg[24], main_crc32_inserter_reg[25], main_crc32_inserter_reg[26], main_crc32_inserter_reg[27], main_crc32_inserter_reg[28], main_crc32_inserter_reg[29], main_crc32_inserter_reg[30], main_crc32_inserter_reg[31]}); +assign main_crc32_inserter_error = (main_crc32_inserter_next != 32'd3338984827); +always @(*) begin + main_crc32_inserter_next <= 32'd0; + main_crc32_inserter_next[0] <= (((main_crc32_inserter_last[24] ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[1] <= (((((((main_crc32_inserter_last[25] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[2] <= (((((((((main_crc32_inserter_last[26] ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[3] <= (((((((main_crc32_inserter_last[27] ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[4] <= (((((((((main_crc32_inserter_last[28] ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[5] <= (((((((((((((main_crc32_inserter_last[29] ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[6] <= (((((((((((main_crc32_inserter_last[30] ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[7] <= (((((((((main_crc32_inserter_last[31] ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[8] <= ((((((((main_crc32_inserter_last[0] ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[9] <= ((((((((main_crc32_inserter_last[1] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[10] <= ((((((((main_crc32_inserter_last[2] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[11] <= ((((((((main_crc32_inserter_last[3] ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[12] <= ((((((((((((main_crc32_inserter_last[4] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[13] <= ((((((((((((main_crc32_inserter_last[5] ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[14] <= ((((((((((main_crc32_inserter_last[6] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]); + main_crc32_inserter_next[15] <= ((((((((main_crc32_inserter_last[7] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]); + main_crc32_inserter_next[16] <= ((((((main_crc32_inserter_last[8] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[17] <= ((((((main_crc32_inserter_last[9] ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[18] <= ((((((main_crc32_inserter_last[10] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]); + main_crc32_inserter_next[19] <= ((((main_crc32_inserter_last[11] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]); + main_crc32_inserter_next[20] <= ((main_crc32_inserter_last[12] ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]); + main_crc32_inserter_next[21] <= ((main_crc32_inserter_last[13] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]); + main_crc32_inserter_next[22] <= ((main_crc32_inserter_last[14] ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[23] <= ((((((main_crc32_inserter_last[15] ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_data1[6]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[24] <= ((((((main_crc32_inserter_last[16] ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[25] <= ((((main_crc32_inserter_last[17] ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]); + main_crc32_inserter_next[26] <= ((((((((main_crc32_inserter_last[18] ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]) ^ main_crc32_inserter_last[24]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_data1[7]); + main_crc32_inserter_next[27] <= ((((((((main_crc32_inserter_last[19] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]) ^ main_crc32_inserter_last[25]) ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_data1[6]); + main_crc32_inserter_next[28] <= ((((((main_crc32_inserter_last[20] ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]) ^ main_crc32_inserter_last[26]) ^ main_crc32_inserter_data1[5]); + main_crc32_inserter_next[29] <= ((((((main_crc32_inserter_last[21] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[30]) ^ main_crc32_inserter_data1[1]) ^ main_crc32_inserter_last[27]) ^ main_crc32_inserter_data1[4]); + main_crc32_inserter_next[30] <= ((((main_crc32_inserter_last[22] ^ main_crc32_inserter_last[31]) ^ main_crc32_inserter_data1[0]) ^ main_crc32_inserter_last[28]) ^ main_crc32_inserter_data1[3]); + main_crc32_inserter_next[31] <= ((main_crc32_inserter_last[23] ^ main_crc32_inserter_last[29]) ^ main_crc32_inserter_data1[2]); +end +always @(*) begin + main_crc32_inserter_source_valid <= 1'd0; + main_crc32_inserter_source_first <= 1'd0; + main_crc32_inserter_source_last <= 1'd0; + main_crc32_inserter_source_payload_data <= 8'd0; + builder_liteethmaccrc32inserter_next_state <= 2'd0; + main_crc32_inserter_source_payload_last_be <= 1'd0; + main_crc32_inserter_source_payload_error <= 1'd0; + main_crc32_inserter_data0 <= 8'd0; + main_crc32_inserter_is_ongoing0 <= 1'd0; + main_crc32_inserter_sink_ready <= 1'd0; + main_crc32_inserter_is_ongoing1 <= 1'd0; + main_crc32_inserter_ce <= 1'd0; + main_crc32_inserter_reset <= 1'd0; + builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; + case (builder_liteethmaccrc32inserter_state) + 1'd1: begin + main_crc32_inserter_ce <= (main_crc32_inserter_sink_valid & main_crc32_inserter_source_ready); + main_crc32_inserter_data0 <= main_crc32_inserter_sink_payload_data; + main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; + main_crc32_inserter_sink_ready <= main_crc32_inserter_source_ready; + main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; + main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; + main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; + main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; + main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; + main_crc32_inserter_source_last <= 1'd0; + if (((main_crc32_inserter_sink_valid & main_crc32_inserter_sink_last) & main_crc32_inserter_source_ready)) begin + builder_liteethmaccrc32inserter_next_state <= 2'd2; + end + end + 2'd2: begin + main_crc32_inserter_source_valid <= 1'd1; + case (main_crc32_inserter_cnt) + 1'd0: begin + main_crc32_inserter_source_payload_data <= main_crc32_inserter_value[31:24]; + end + 1'd1: begin + main_crc32_inserter_source_payload_data <= main_crc32_inserter_value[23:16]; + end + 2'd2: begin + main_crc32_inserter_source_payload_data <= main_crc32_inserter_value[15:8]; + end + default: begin + main_crc32_inserter_source_payload_data <= main_crc32_inserter_value[7:0]; + end + endcase + if (main_crc32_inserter_cnt_done) begin + main_crc32_inserter_source_last <= 1'd1; + if (main_crc32_inserter_source_ready) begin + builder_liteethmaccrc32inserter_next_state <= 1'd0; + end + end + main_crc32_inserter_is_ongoing1 <= 1'd1; + end + default: begin + main_crc32_inserter_reset <= 1'd1; + main_crc32_inserter_sink_ready <= 1'd1; + if (main_crc32_inserter_sink_valid) begin + main_crc32_inserter_sink_ready <= 1'd0; + builder_liteethmaccrc32inserter_next_state <= 1'd1; + end + main_crc32_inserter_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_crc32_checker_fifo_full = (main_crc32_checker_syncfifo_level == 3'd4); +assign main_crc32_checker_fifo_in = (main_crc32_checker_sink_sink_valid & ((~main_crc32_checker_fifo_full) | main_crc32_checker_fifo_out)); +assign main_crc32_checker_fifo_out = (main_crc32_checker_source_source_valid & main_crc32_checker_source_source_ready); +assign main_crc32_checker_syncfifo_sink_first = main_crc32_checker_sink_sink_first; +assign main_crc32_checker_syncfifo_sink_last = main_crc32_checker_sink_sink_last; +assign main_crc32_checker_syncfifo_sink_payload_data = main_crc32_checker_sink_sink_payload_data; +assign main_crc32_checker_syncfifo_sink_payload_last_be = main_crc32_checker_sink_sink_payload_last_be; +assign main_crc32_checker_syncfifo_sink_payload_error = main_crc32_checker_sink_sink_payload_error; +always @(*) begin + main_crc32_checker_syncfifo_sink_valid <= 1'd0; + main_crc32_checker_syncfifo_sink_valid <= main_crc32_checker_sink_sink_valid; + main_crc32_checker_syncfifo_sink_valid <= main_crc32_checker_fifo_in; +end +always @(*) begin + main_crc32_checker_sink_sink_ready <= 1'd0; + main_crc32_checker_sink_sink_ready <= main_crc32_checker_syncfifo_sink_ready; + main_crc32_checker_sink_sink_ready <= main_crc32_checker_fifo_in; +end +assign main_crc32_checker_source_source_valid = (main_crc32_checker_sink_sink_valid & main_crc32_checker_fifo_full); +assign main_crc32_checker_source_source_last = main_crc32_checker_sink_sink_last; +assign main_crc32_checker_syncfifo_source_ready = main_crc32_checker_fifo_out; +assign main_crc32_checker_source_source_payload_data = main_crc32_checker_syncfifo_source_payload_data; +assign main_crc32_checker_source_source_payload_last_be = main_crc32_checker_syncfifo_source_payload_last_be; +always @(*) begin + main_crc32_checker_source_source_payload_error <= 1'd0; + main_crc32_checker_source_source_payload_error <= main_crc32_checker_syncfifo_source_payload_error; + main_crc32_checker_source_source_payload_error <= (main_crc32_checker_sink_sink_payload_error | main_crc32_checker_crc_error); +end +assign main_crc32_checker_error = ((main_crc32_checker_source_source_valid & main_crc32_checker_source_source_last) & main_crc32_checker_crc_error); +assign main_crc32_checker_crc_data0 = main_crc32_checker_sink_sink_payload_data; +assign main_crc32_checker_crc_data1 = main_crc32_checker_crc_data0; +assign main_crc32_checker_crc_last = main_crc32_checker_crc_reg; +assign main_crc32_checker_crc_value = (~{main_crc32_checker_crc_reg[0], main_crc32_checker_crc_reg[1], main_crc32_checker_crc_reg[2], main_crc32_checker_crc_reg[3], main_crc32_checker_crc_reg[4], main_crc32_checker_crc_reg[5], main_crc32_checker_crc_reg[6], main_crc32_checker_crc_reg[7], main_crc32_checker_crc_reg[8], main_crc32_checker_crc_reg[9], main_crc32_checker_crc_reg[10], main_crc32_checker_crc_reg[11], main_crc32_checker_crc_reg[12], main_crc32_checker_crc_reg[13], main_crc32_checker_crc_reg[14], main_crc32_checker_crc_reg[15], main_crc32_checker_crc_reg[16], main_crc32_checker_crc_reg[17], main_crc32_checker_crc_reg[18], main_crc32_checker_crc_reg[19], main_crc32_checker_crc_reg[20], main_crc32_checker_crc_reg[21], main_crc32_checker_crc_reg[22], main_crc32_checker_crc_reg[23], main_crc32_checker_crc_reg[24], main_crc32_checker_crc_reg[25], main_crc32_checker_crc_reg[26], main_crc32_checker_crc_reg[27], main_crc32_checker_crc_reg[28], main_crc32_checker_crc_reg[29], main_crc32_checker_crc_reg[30], main_crc32_checker_crc_reg[31]}); +assign main_crc32_checker_crc_error = (main_crc32_checker_crc_next != 32'd3338984827); +always @(*) begin + main_crc32_checker_crc_next <= 32'd0; + main_crc32_checker_crc_next[0] <= (((main_crc32_checker_crc_last[24] ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[1] <= (((((((main_crc32_checker_crc_last[25] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[2] <= (((((((((main_crc32_checker_crc_last[26] ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[3] <= (((((((main_crc32_checker_crc_last[27] ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[4] <= (((((((((main_crc32_checker_crc_last[28] ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[5] <= (((((((((((((main_crc32_checker_crc_last[29] ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[6] <= (((((((((((main_crc32_checker_crc_last[30] ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[7] <= (((((((((main_crc32_checker_crc_last[31] ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[8] <= ((((((((main_crc32_checker_crc_last[0] ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[9] <= ((((((((main_crc32_checker_crc_last[1] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[10] <= ((((((((main_crc32_checker_crc_last[2] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[11] <= ((((((((main_crc32_checker_crc_last[3] ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[12] <= ((((((((((((main_crc32_checker_crc_last[4] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[13] <= ((((((((((((main_crc32_checker_crc_last[5] ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[14] <= ((((((((((main_crc32_checker_crc_last[6] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]); + main_crc32_checker_crc_next[15] <= ((((((((main_crc32_checker_crc_last[7] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]); + main_crc32_checker_crc_next[16] <= ((((((main_crc32_checker_crc_last[8] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[17] <= ((((((main_crc32_checker_crc_last[9] ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[18] <= ((((((main_crc32_checker_crc_last[10] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]); + main_crc32_checker_crc_next[19] <= ((((main_crc32_checker_crc_last[11] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]); + main_crc32_checker_crc_next[20] <= ((main_crc32_checker_crc_last[12] ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]); + main_crc32_checker_crc_next[21] <= ((main_crc32_checker_crc_last[13] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]); + main_crc32_checker_crc_next[22] <= ((main_crc32_checker_crc_last[14] ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[23] <= ((((((main_crc32_checker_crc_last[15] ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_data1[6]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[24] <= ((((((main_crc32_checker_crc_last[16] ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[25] <= ((((main_crc32_checker_crc_last[17] ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]); + main_crc32_checker_crc_next[26] <= ((((((((main_crc32_checker_crc_last[18] ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]) ^ main_crc32_checker_crc_last[24]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_data1[7]); + main_crc32_checker_crc_next[27] <= ((((((((main_crc32_checker_crc_last[19] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]) ^ main_crc32_checker_crc_last[25]) ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_data1[6]); + main_crc32_checker_crc_next[28] <= ((((((main_crc32_checker_crc_last[20] ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]) ^ main_crc32_checker_crc_last[26]) ^ main_crc32_checker_crc_data1[5]); + main_crc32_checker_crc_next[29] <= ((((((main_crc32_checker_crc_last[21] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[30]) ^ main_crc32_checker_crc_data1[1]) ^ main_crc32_checker_crc_last[27]) ^ main_crc32_checker_crc_data1[4]); + main_crc32_checker_crc_next[30] <= ((((main_crc32_checker_crc_last[22] ^ main_crc32_checker_crc_last[31]) ^ main_crc32_checker_crc_data1[0]) ^ main_crc32_checker_crc_last[28]) ^ main_crc32_checker_crc_data1[3]); + main_crc32_checker_crc_next[31] <= ((main_crc32_checker_crc_last[23] ^ main_crc32_checker_crc_last[29]) ^ main_crc32_checker_crc_data1[2]); +end +assign main_crc32_checker_syncfifo_syncfifo_din = {main_crc32_checker_syncfifo_fifo_in_last, main_crc32_checker_syncfifo_fifo_in_first, main_crc32_checker_syncfifo_fifo_in_payload_error, main_crc32_checker_syncfifo_fifo_in_payload_last_be, main_crc32_checker_syncfifo_fifo_in_payload_data}; +assign {main_crc32_checker_syncfifo_fifo_out_last, main_crc32_checker_syncfifo_fifo_out_first, main_crc32_checker_syncfifo_fifo_out_payload_error, main_crc32_checker_syncfifo_fifo_out_payload_last_be, main_crc32_checker_syncfifo_fifo_out_payload_data} = main_crc32_checker_syncfifo_syncfifo_dout; +assign main_crc32_checker_syncfifo_sink_ready = main_crc32_checker_syncfifo_syncfifo_writable; +assign main_crc32_checker_syncfifo_syncfifo_we = main_crc32_checker_syncfifo_sink_valid; +assign main_crc32_checker_syncfifo_fifo_in_first = main_crc32_checker_syncfifo_sink_first; +assign main_crc32_checker_syncfifo_fifo_in_last = main_crc32_checker_syncfifo_sink_last; +assign main_crc32_checker_syncfifo_fifo_in_payload_data = main_crc32_checker_syncfifo_sink_payload_data; +assign main_crc32_checker_syncfifo_fifo_in_payload_last_be = main_crc32_checker_syncfifo_sink_payload_last_be; +assign main_crc32_checker_syncfifo_fifo_in_payload_error = main_crc32_checker_syncfifo_sink_payload_error; +assign main_crc32_checker_syncfifo_source_valid = main_crc32_checker_syncfifo_syncfifo_readable; +assign main_crc32_checker_syncfifo_source_first = main_crc32_checker_syncfifo_fifo_out_first; +assign main_crc32_checker_syncfifo_source_last = main_crc32_checker_syncfifo_fifo_out_last; +assign main_crc32_checker_syncfifo_source_payload_data = main_crc32_checker_syncfifo_fifo_out_payload_data; +assign main_crc32_checker_syncfifo_source_payload_last_be = main_crc32_checker_syncfifo_fifo_out_payload_last_be; +assign main_crc32_checker_syncfifo_source_payload_error = main_crc32_checker_syncfifo_fifo_out_payload_error; +assign main_crc32_checker_syncfifo_syncfifo_re = main_crc32_checker_syncfifo_source_ready; +always @(*) begin + main_crc32_checker_syncfifo_wrport_adr <= 3'd0; + if (main_crc32_checker_syncfifo_replace) begin + main_crc32_checker_syncfifo_wrport_adr <= (main_crc32_checker_syncfifo_produce - 1'd1); + end else begin + main_crc32_checker_syncfifo_wrport_adr <= main_crc32_checker_syncfifo_produce; + end +end +assign main_crc32_checker_syncfifo_wrport_dat_w = main_crc32_checker_syncfifo_syncfifo_din; +assign main_crc32_checker_syncfifo_wrport_we = (main_crc32_checker_syncfifo_syncfifo_we & (main_crc32_checker_syncfifo_syncfifo_writable | main_crc32_checker_syncfifo_replace)); +assign main_crc32_checker_syncfifo_do_read = (main_crc32_checker_syncfifo_syncfifo_readable & main_crc32_checker_syncfifo_syncfifo_re); +assign main_crc32_checker_syncfifo_rdport_adr = main_crc32_checker_syncfifo_consume; +assign main_crc32_checker_syncfifo_syncfifo_dout = main_crc32_checker_syncfifo_rdport_dat_r; +assign main_crc32_checker_syncfifo_syncfifo_writable = (main_crc32_checker_syncfifo_level != 3'd5); +assign main_crc32_checker_syncfifo_syncfifo_readable = (main_crc32_checker_syncfifo_level != 1'd0); +always @(*) begin + main_crc32_checker_fifo_reset <= 1'd0; + main_crc32_checker_crc_ce <= 1'd0; + main_crc32_checker_crc_reset <= 1'd0; + builder_liteethmaccrc32checker_next_state <= 2'd0; + builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; + case (builder_liteethmaccrc32checker_state) + 1'd1: begin + if ((main_crc32_checker_sink_sink_valid & main_crc32_checker_sink_sink_ready)) begin + main_crc32_checker_crc_ce <= 1'd1; + builder_liteethmaccrc32checker_next_state <= 2'd2; + end + end + 2'd2: begin + if ((main_crc32_checker_sink_sink_valid & main_crc32_checker_sink_sink_ready)) begin + main_crc32_checker_crc_ce <= 1'd1; + if (main_crc32_checker_sink_sink_last) begin + builder_liteethmaccrc32checker_next_state <= 1'd0; + end + end + end + default: begin + main_crc32_checker_crc_reset <= 1'd1; + main_crc32_checker_fifo_reset <= 1'd1; + builder_liteethmaccrc32checker_next_state <= 1'd1; + end + endcase +end +assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); +assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); +assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); +always @(*) begin + main_padding_inserter_source_valid <= 1'd0; + main_padding_inserter_source_first <= 1'd0; + main_padding_inserter_source_last <= 1'd0; + main_padding_inserter_source_payload_data <= 8'd0; + builder_liteethmacpaddinginserter_next_state <= 1'd0; + main_padding_inserter_source_payload_last_be <= 1'd0; + main_padding_inserter_source_payload_error <= 1'd0; + main_padding_inserter_counter_reset <= 1'd0; + main_padding_inserter_sink_ready <= 1'd0; + main_padding_inserter_counter_ce <= 1'd0; + builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; + case (builder_liteethmacpaddinginserter_state) + 1'd1: begin + main_padding_inserter_source_valid <= 1'd1; + main_padding_inserter_source_last <= main_padding_inserter_counter_done; + main_padding_inserter_source_payload_data <= 1'd0; + if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin + main_padding_inserter_counter_ce <= 1'd1; + if (main_padding_inserter_counter_done) begin + main_padding_inserter_counter_reset <= 1'd1; + builder_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; + main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; + main_padding_inserter_source_first <= main_padding_inserter_sink_first; + main_padding_inserter_source_last <= main_padding_inserter_sink_last; + main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; + main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; + main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; + if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin + main_padding_inserter_counter_ce <= 1'd1; + if (main_padding_inserter_sink_last) begin + if ((~main_padding_inserter_counter_done)) begin + main_padding_inserter_source_last <= 1'd0; + builder_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + main_padding_inserter_counter_reset <= 1'd1; + end + end + end + end + endcase +end +assign main_padding_checker_source_valid = main_padding_checker_sink_valid; +assign main_padding_checker_sink_ready = main_padding_checker_source_ready; +assign main_padding_checker_source_first = main_padding_checker_sink_first; +assign main_padding_checker_source_last = main_padding_checker_sink_last; +assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; +assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; +assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; +assign main_tx_last_be_source_valid = (main_tx_last_be_sink_valid & main_tx_last_be_ongoing); +assign main_tx_last_be_source_last = main_tx_last_be_sink_payload_last_be; +assign main_tx_last_be_source_payload_data = main_tx_last_be_sink_payload_data; +assign main_tx_last_be_sink_ready = main_tx_last_be_source_ready; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; +end +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_tx_cdc_asyncfifo_din = {main_tx_cdc_fifo_in_last, main_tx_cdc_fifo_in_first, main_tx_cdc_fifo_in_payload_error, main_tx_cdc_fifo_in_payload_last_be, main_tx_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_fifo_out_last, main_tx_cdc_fifo_out_first, main_tx_cdc_fifo_out_payload_error, main_tx_cdc_fifo_out_payload_last_be, main_tx_cdc_fifo_out_payload_data} = main_tx_cdc_asyncfifo_dout; +assign main_tx_cdc_sink_ready = main_tx_cdc_asyncfifo_writable; +assign main_tx_cdc_asyncfifo_we = main_tx_cdc_sink_valid; +assign main_tx_cdc_fifo_in_first = main_tx_cdc_sink_first; +assign main_tx_cdc_fifo_in_last = main_tx_cdc_sink_last; +assign main_tx_cdc_fifo_in_payload_data = main_tx_cdc_sink_payload_data; +assign main_tx_cdc_fifo_in_payload_last_be = main_tx_cdc_sink_payload_last_be; +assign main_tx_cdc_fifo_in_payload_error = main_tx_cdc_sink_payload_error; +assign main_tx_cdc_source_valid = main_tx_cdc_asyncfifo_readable; +assign main_tx_cdc_source_first = main_tx_cdc_fifo_out_first; +assign main_tx_cdc_source_last = main_tx_cdc_fifo_out_last; +assign main_tx_cdc_source_payload_data = main_tx_cdc_fifo_out_payload_data; +assign main_tx_cdc_source_payload_last_be = main_tx_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_source_payload_error = main_tx_cdc_fifo_out_payload_error; +assign main_tx_cdc_asyncfifo_re = main_tx_cdc_source_ready; +assign main_tx_cdc_graycounter0_ce = (main_tx_cdc_asyncfifo_writable & main_tx_cdc_asyncfifo_we); +assign main_tx_cdc_graycounter1_ce = (main_tx_cdc_asyncfifo_readable & main_tx_cdc_asyncfifo_re); +assign main_tx_cdc_asyncfifo_writable = (((main_tx_cdc_graycounter0_q[6] == main_tx_cdc_consume_wdomain[6]) | (main_tx_cdc_graycounter0_q[5] == main_tx_cdc_consume_wdomain[5])) | (main_tx_cdc_graycounter0_q[4:0] != main_tx_cdc_consume_wdomain[4:0])); +assign main_tx_cdc_asyncfifo_readable = (main_tx_cdc_graycounter1_q != main_tx_cdc_produce_rdomain); +assign main_tx_cdc_wrport_adr = main_tx_cdc_graycounter0_q_binary[5:0]; +assign main_tx_cdc_wrport_dat_w = main_tx_cdc_asyncfifo_din; +assign main_tx_cdc_wrport_we = main_tx_cdc_graycounter0_ce; +assign main_tx_cdc_rdport_adr = main_tx_cdc_graycounter1_q_next_binary[5:0]; +assign main_tx_cdc_asyncfifo_dout = main_tx_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_graycounter0_q_next_binary <= 7'd0; + if (main_tx_cdc_graycounter0_ce) begin + main_tx_cdc_graycounter0_q_next_binary <= (main_tx_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_graycounter0_q_next_binary <= main_tx_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_graycounter0_q_next = (main_tx_cdc_graycounter0_q_next_binary ^ main_tx_cdc_graycounter0_q_next_binary[6:1]); +always @(*) begin + main_tx_cdc_graycounter1_q_next_binary <= 7'd0; + if (main_tx_cdc_graycounter1_ce) begin + main_tx_cdc_graycounter1_q_next_binary <= (main_tx_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_graycounter1_q_next_binary <= main_tx_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_graycounter1_q_next = (main_tx_cdc_graycounter1_q_next_binary ^ main_tx_cdc_graycounter1_q_next_binary[6:1]); +assign main_rx_cdc_asyncfifo_din = {main_rx_cdc_fifo_in_last, main_rx_cdc_fifo_in_first, main_rx_cdc_fifo_in_payload_error, main_rx_cdc_fifo_in_payload_last_be, main_rx_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_fifo_out_last, main_rx_cdc_fifo_out_first, main_rx_cdc_fifo_out_payload_error, main_rx_cdc_fifo_out_payload_last_be, main_rx_cdc_fifo_out_payload_data} = main_rx_cdc_asyncfifo_dout; +assign main_rx_cdc_sink_ready = main_rx_cdc_asyncfifo_writable; +assign main_rx_cdc_asyncfifo_we = main_rx_cdc_sink_valid; +assign main_rx_cdc_fifo_in_first = main_rx_cdc_sink_first; +assign main_rx_cdc_fifo_in_last = main_rx_cdc_sink_last; +assign main_rx_cdc_fifo_in_payload_data = main_rx_cdc_sink_payload_data; +assign main_rx_cdc_fifo_in_payload_last_be = main_rx_cdc_sink_payload_last_be; +assign main_rx_cdc_fifo_in_payload_error = main_rx_cdc_sink_payload_error; +assign main_rx_cdc_source_valid = main_rx_cdc_asyncfifo_readable; +assign main_rx_cdc_source_first = main_rx_cdc_fifo_out_first; +assign main_rx_cdc_source_last = main_rx_cdc_fifo_out_last; +assign main_rx_cdc_source_payload_data = main_rx_cdc_fifo_out_payload_data; +assign main_rx_cdc_source_payload_last_be = main_rx_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_source_payload_error = main_rx_cdc_fifo_out_payload_error; +assign main_rx_cdc_asyncfifo_re = main_rx_cdc_source_ready; +assign main_rx_cdc_graycounter0_ce = (main_rx_cdc_asyncfifo_writable & main_rx_cdc_asyncfifo_we); +assign main_rx_cdc_graycounter1_ce = (main_rx_cdc_asyncfifo_readable & main_rx_cdc_asyncfifo_re); +assign main_rx_cdc_asyncfifo_writable = (((main_rx_cdc_graycounter0_q[6] == main_rx_cdc_consume_wdomain[6]) | (main_rx_cdc_graycounter0_q[5] == main_rx_cdc_consume_wdomain[5])) | (main_rx_cdc_graycounter0_q[4:0] != main_rx_cdc_consume_wdomain[4:0])); +assign main_rx_cdc_asyncfifo_readable = (main_rx_cdc_graycounter1_q != main_rx_cdc_produce_rdomain); +assign main_rx_cdc_wrport_adr = main_rx_cdc_graycounter0_q_binary[5:0]; +assign main_rx_cdc_wrport_dat_w = main_rx_cdc_asyncfifo_din; +assign main_rx_cdc_wrport_we = main_rx_cdc_graycounter0_ce; +assign main_rx_cdc_rdport_adr = main_rx_cdc_graycounter1_q_next_binary[5:0]; +assign main_rx_cdc_asyncfifo_dout = main_rx_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_graycounter0_q_next_binary <= 7'd0; + if (main_rx_cdc_graycounter0_ce) begin + main_rx_cdc_graycounter0_q_next_binary <= (main_rx_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_graycounter0_q_next_binary <= main_rx_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_graycounter0_q_next = (main_rx_cdc_graycounter0_q_next_binary ^ main_rx_cdc_graycounter0_q_next_binary[6:1]); +always @(*) begin + main_rx_cdc_graycounter1_q_next_binary <= 7'd0; + if (main_rx_cdc_graycounter1_ce) begin + main_rx_cdc_graycounter1_q_next_binary <= (main_rx_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_graycounter1_q_next_binary <= main_rx_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_graycounter1_q_next = (main_rx_cdc_graycounter1_q_next_binary ^ main_rx_cdc_graycounter1_q_next_binary[6:1]); +assign main_tx_converter_sink_valid = main_tx_cdc_source_valid; +assign main_tx_cdc_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; +assign main_padding_inserter_sink_first = main_tx_last_be_source_first; +assign main_padding_inserter_sink_last = main_tx_last_be_source_last; +assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; +assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; +assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; +assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; +assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; +assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; +assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; +assign main_preamble_inserter_sink_valid = main_crc32_inserter_source_valid; +assign main_crc32_inserter_source_ready = main_preamble_inserter_sink_ready; +assign main_preamble_inserter_sink_first = main_crc32_inserter_source_first; +assign main_preamble_inserter_sink_last = main_crc32_inserter_source_last; +assign main_preamble_inserter_sink_payload_data = main_crc32_inserter_source_payload_data; +assign main_preamble_inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; +assign main_preamble_inserter_sink_payload_error = main_crc32_inserter_source_payload_error; +assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; +assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; +assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; +assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; +assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; +assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; +assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_valid = main_tx_gap_inserter_source_valid; +assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_liteethphymiitx_sink_sink_ready; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_first = main_tx_gap_inserter_source_first; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_last = main_tx_gap_inserter_source_last; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data = main_tx_gap_inserter_source_payload_data; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; +assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error = main_tx_gap_inserter_source_payload_error; +assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphymiirx_source_source_valid; +assign main_maccore_ethphy_liteethphymiirx_source_source_ready = main_preamble_checker_sink_ready; +assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphymiirx_source_source_first; +assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphymiirx_source_source_last; +assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphymiirx_source_source_payload_data; +assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be; +assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphymiirx_source_source_payload_error; +assign main_crc32_checker_sink_sink_valid = main_preamble_checker_source_valid; +assign main_preamble_checker_source_ready = main_crc32_checker_sink_sink_ready; +assign main_crc32_checker_sink_sink_first = main_preamble_checker_source_first; +assign main_crc32_checker_sink_sink_last = main_preamble_checker_source_last; +assign main_crc32_checker_sink_sink_payload_data = main_preamble_checker_source_payload_data; +assign main_crc32_checker_sink_sink_payload_last_be = main_preamble_checker_source_payload_last_be; +assign main_crc32_checker_sink_sink_payload_error = main_preamble_checker_source_payload_error; +assign main_padding_checker_sink_valid = main_crc32_checker_source_source_valid; +assign main_crc32_checker_source_source_ready = main_padding_checker_sink_ready; +assign main_padding_checker_sink_first = main_crc32_checker_source_source_first; +assign main_padding_checker_sink_last = main_crc32_checker_source_source_last; +assign main_padding_checker_sink_payload_data = main_crc32_checker_source_source_payload_data; +assign main_padding_checker_sink_payload_last_be = main_crc32_checker_source_source_payload_last_be; +assign main_padding_checker_sink_payload_error = main_crc32_checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; +assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_padding_checker_source_first; +assign main_rx_last_be_sink_last = main_padding_checker_source_last; +assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_ready; +assign main_rx_cdc_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_payload_error = main_rx_converter_source_payload_error; +assign main_writer_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_writer_sink_sink_ready; +assign main_writer_sink_sink_first = main_sink_first; +assign main_writer_sink_sink_last = main_sink_last; +assign main_writer_sink_sink_payload_data = main_sink_payload_data; +assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_writer_sink_sink_payload_error = main_sink_payload_error; +assign main_source_valid = main_reader_source_source_valid; +assign main_reader_source_source_ready = main_source_ready; +assign main_source_first = main_reader_source_source_first; +assign main_source_last = main_reader_source_source_last; +assign main_source_payload_data = main_reader_source_source_payload_data; +assign main_source_payload_last_be = main_reader_source_source_payload_last_be; +assign main_source_payload_error = main_reader_source_source_payload_error; +always @(*) begin + main_writer_inc <= 3'd0; + case (main_writer_sink_sink_payload_last_be) + 1'd1: begin + main_writer_inc <= 1'd1; + end + 2'd2: begin + main_writer_inc <= 2'd2; + end + 3'd4: begin + main_writer_inc <= 2'd3; + end + default: begin + main_writer_inc <= 3'd4; + end + endcase +end +assign main_writer_fifo_sink_payload_slot = main_writer_slot; +assign main_writer_fifo_sink_payload_length = main_writer_counter; +assign main_writer_fifo_source_ready = main_writer_available_clear; +assign main_writer_available_trigger = main_writer_fifo_source_valid; +assign main_writer_slot_status = main_writer_fifo_source_payload_slot; +assign main_writer_length_status = main_writer_fifo_source_payload_length; +always @(*) begin + main_writer_memory0_we <= 1'd0; + main_writer_memory0_dat_w <= 32'd0; + main_writer_memory1_adr <= 9'd0; + main_writer_memory1_we <= 1'd0; + main_writer_memory0_adr <= 9'd0; + main_writer_memory1_dat_w <= 32'd0; + case (main_writer_slot) + 1'd0: begin + main_writer_memory0_adr <= main_writer_counter[31:2]; + main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; + if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin + main_writer_memory0_we <= 4'd15; + end + end + 1'd1: begin + main_writer_memory1_adr <= main_writer_counter[31:2]; + main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; + if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin + main_writer_memory1_we <= 4'd15; + end + end + endcase +end +assign main_writer_status_w = main_writer_available_status; +always @(*) begin + main_writer_available_clear <= 1'd0; + if ((main_writer_pending_re & main_writer_pending_r)) begin + main_writer_available_clear <= 1'd1; + end +end +assign main_writer_pending_w = main_writer_available_pending; +assign main_writer_irq = (main_writer_pending_w & main_writer_storage); +assign main_writer_available_status = main_writer_available_trigger; +assign main_writer_available_pending = main_writer_available_trigger; +assign main_writer_fifo_syncfifo_din = {main_writer_fifo_fifo_in_last, main_writer_fifo_fifo_in_first, main_writer_fifo_fifo_in_payload_length, main_writer_fifo_fifo_in_payload_slot}; +assign {main_writer_fifo_fifo_out_last, main_writer_fifo_fifo_out_first, main_writer_fifo_fifo_out_payload_length, main_writer_fifo_fifo_out_payload_slot} = main_writer_fifo_syncfifo_dout; +assign main_writer_fifo_sink_ready = main_writer_fifo_syncfifo_writable; +assign main_writer_fifo_syncfifo_we = main_writer_fifo_sink_valid; +assign main_writer_fifo_fifo_in_first = main_writer_fifo_sink_first; +assign main_writer_fifo_fifo_in_last = main_writer_fifo_sink_last; +assign main_writer_fifo_fifo_in_payload_slot = main_writer_fifo_sink_payload_slot; +assign main_writer_fifo_fifo_in_payload_length = main_writer_fifo_sink_payload_length; +assign main_writer_fifo_source_valid = main_writer_fifo_syncfifo_readable; +assign main_writer_fifo_source_first = main_writer_fifo_fifo_out_first; +assign main_writer_fifo_source_last = main_writer_fifo_fifo_out_last; +assign main_writer_fifo_source_payload_slot = main_writer_fifo_fifo_out_payload_slot; +assign main_writer_fifo_source_payload_length = main_writer_fifo_fifo_out_payload_length; +assign main_writer_fifo_syncfifo_re = main_writer_fifo_source_ready; +always @(*) begin + main_writer_fifo_wrport_adr <= 1'd0; + if (main_writer_fifo_replace) begin + main_writer_fifo_wrport_adr <= (main_writer_fifo_produce - 1'd1); + end else begin + main_writer_fifo_wrport_adr <= main_writer_fifo_produce; + end +end +assign main_writer_fifo_wrport_dat_w = main_writer_fifo_syncfifo_din; +assign main_writer_fifo_wrport_we = (main_writer_fifo_syncfifo_we & (main_writer_fifo_syncfifo_writable | main_writer_fifo_replace)); +assign main_writer_fifo_do_read = (main_writer_fifo_syncfifo_readable & main_writer_fifo_syncfifo_re); +assign main_writer_fifo_rdport_adr = main_writer_fifo_consume; +assign main_writer_fifo_syncfifo_dout = main_writer_fifo_rdport_dat_r; +assign main_writer_fifo_syncfifo_writable = (main_writer_fifo_level != 2'd2); +assign main_writer_fifo_syncfifo_readable = (main_writer_fifo_level != 1'd0); +always @(*) begin + main_writer_counter_t_next_value_ce <= 1'd0; + main_writer_ongoing <= 1'd0; + main_writer_errors_status_f_next_value <= 32'd0; + main_writer_fifo_sink_valid <= 1'd0; + main_writer_errors_status_f_next_value_ce <= 1'd0; + main_writer_slot_ce <= 1'd0; + builder_liteethmacsramwriter_next_state <= 3'd0; + main_writer_counter_t_next_value <= 32'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if (main_writer_sink_sink_valid) begin + if ((main_writer_counter == 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); + main_writer_counter_t_next_value_ce <= 1'd1; + main_writer_ongoing <= 1'd1; + end + if (main_writer_sink_sink_last) begin + if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd2; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + end + 2'd2: begin + main_writer_counter_t_next_value <= 1'd0; + main_writer_counter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 2'd3: begin + if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + 3'd4: begin + main_writer_counter_t_next_value <= 1'd0; + main_writer_counter_t_next_value_ce <= 1'd1; + main_writer_slot_ce <= 1'd1; + main_writer_fifo_sink_valid <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_writer_sink_sink_valid) begin + if (main_writer_fifo_sink_ready) begin + main_writer_ongoing <= 1'd1; + main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); + main_writer_counter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd1; + end else begin + main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); + main_writer_errors_status_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd3; + end + end + end + endcase +end +assign main_reader_fifo_sink_valid = main_reader_start_re; +assign main_reader_fifo_sink_payload_slot = main_reader_slot_storage; +assign main_reader_fifo_sink_payload_length = main_reader_length_storage; +assign main_reader_ready_status = main_reader_fifo_sink_ready; +assign main_reader_level_status = main_reader_fifo_level; +always @(*) begin + main_reader_source_source_payload_last_be <= 4'd0; + if (main_reader_source_source_last) begin + case (main_reader_fifo_source_payload_length[1:0]) + 1'd0: begin + main_reader_source_source_payload_last_be <= 4'd8; + end + 1'd1: begin + main_reader_source_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_reader_source_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_reader_source_source_payload_last_be <= 3'd4; + end + endcase + end +end +assign main_reader_memory0_adr = main_reader_counter[10:2]; +assign main_reader_memory1_adr = main_reader_counter[10:2]; +always @(*) begin + main_reader_source_source_payload_data <= 32'd0; + case (main_reader_fifo_source_payload_slot) + 1'd0: begin + main_reader_source_source_payload_data <= main_reader_memory0_dat_r; + end + 1'd1: begin + main_reader_source_source_payload_data <= main_reader_memory1_dat_r; + end + endcase +end +assign main_reader_eventmanager_status_w = main_reader_done_status; +always @(*) begin + main_reader_done_clear <= 1'd0; + if ((main_reader_eventmanager_pending_re & main_reader_eventmanager_pending_r)) begin + main_reader_done_clear <= 1'd1; + end +end +assign main_reader_eventmanager_pending_w = main_reader_done_pending; +assign main_reader_irq = (main_reader_eventmanager_pending_w & main_reader_eventmanager_storage); +assign main_reader_done_status = 1'd0; +assign main_reader_fifo_syncfifo_din = {main_reader_fifo_fifo_in_last, main_reader_fifo_fifo_in_first, main_reader_fifo_fifo_in_payload_length, main_reader_fifo_fifo_in_payload_slot}; +assign {main_reader_fifo_fifo_out_last, main_reader_fifo_fifo_out_first, main_reader_fifo_fifo_out_payload_length, main_reader_fifo_fifo_out_payload_slot} = main_reader_fifo_syncfifo_dout; +assign main_reader_fifo_sink_ready = main_reader_fifo_syncfifo_writable; +assign main_reader_fifo_syncfifo_we = main_reader_fifo_sink_valid; +assign main_reader_fifo_fifo_in_first = main_reader_fifo_sink_first; +assign main_reader_fifo_fifo_in_last = main_reader_fifo_sink_last; +assign main_reader_fifo_fifo_in_payload_slot = main_reader_fifo_sink_payload_slot; +assign main_reader_fifo_fifo_in_payload_length = main_reader_fifo_sink_payload_length; +assign main_reader_fifo_source_valid = main_reader_fifo_syncfifo_readable; +assign main_reader_fifo_source_first = main_reader_fifo_fifo_out_first; +assign main_reader_fifo_source_last = main_reader_fifo_fifo_out_last; +assign main_reader_fifo_source_payload_slot = main_reader_fifo_fifo_out_payload_slot; +assign main_reader_fifo_source_payload_length = main_reader_fifo_fifo_out_payload_length; +assign main_reader_fifo_syncfifo_re = main_reader_fifo_source_ready; +always @(*) begin + main_reader_fifo_wrport_adr <= 1'd0; + if (main_reader_fifo_replace) begin + main_reader_fifo_wrport_adr <= (main_reader_fifo_produce - 1'd1); + end else begin + main_reader_fifo_wrport_adr <= main_reader_fifo_produce; + end +end +assign main_reader_fifo_wrport_dat_w = main_reader_fifo_syncfifo_din; +assign main_reader_fifo_wrport_we = (main_reader_fifo_syncfifo_we & (main_reader_fifo_syncfifo_writable | main_reader_fifo_replace)); +assign main_reader_fifo_do_read = (main_reader_fifo_syncfifo_readable & main_reader_fifo_syncfifo_re); +assign main_reader_fifo_rdport_adr = main_reader_fifo_consume; +assign main_reader_fifo_syncfifo_dout = main_reader_fifo_rdport_dat_r; +assign main_reader_fifo_syncfifo_writable = (main_reader_fifo_level != 2'd2); +assign main_reader_fifo_syncfifo_readable = (main_reader_fifo_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_reader_source_source_last <= 1'd0; + main_reader_counter_next_value <= 11'd0; + main_reader_counter_next_value_ce <= 1'd0; + main_reader_source_source_valid <= 1'd0; + main_reader_done_trigger <= 1'd0; + main_reader_fifo_source_ready <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_reader_source_source_valid <= 1'd1; + main_reader_source_source_last <= (main_reader_counter >= (main_reader_fifo_source_payload_length - 3'd4)); + if (main_reader_source_source_ready) begin + main_reader_counter_next_value <= (main_reader_counter + 3'd4); + main_reader_counter_next_value_ce <= 1'd1; + if (main_reader_source_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_reader_fifo_source_ready <= 1'd1; + main_reader_done_trigger <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + main_reader_counter_next_value <= 1'd0; + main_reader_counter_next_value_ce <= 1'd1; + if (main_reader_fifo_source_valid) begin + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_ev_irq = (main_writer_irq | main_reader_irq); +assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; +assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; +assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; +assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; +always @(*) begin + main_sram0_we <= 4'd0; + main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); + main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); + main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); + main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); +end +assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; +assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; +assign main_sram0_dat_w = main_sram0_bus_dat_w1; +always @(*) begin + main_sram1_we <= 4'd0; + main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); + main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); + main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); + main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); +end +assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; +assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; +assign main_sram1_dat_w = main_sram1_bus_dat_w1; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_sram0_bus_adr0 = main_bus_adr; +assign main_sram0_bus_dat_w0 = main_bus_dat_w; +assign main_sram0_bus_sel0 = main_bus_sel; +assign main_sram0_bus_stb0 = main_bus_stb; +assign main_sram0_bus_we0 = main_bus_we; +assign main_sram0_bus_cti0 = main_bus_cti; +assign main_sram0_bus_bte0 = main_bus_bte; +assign main_sram1_bus_adr0 = main_bus_adr; +assign main_sram1_bus_dat_w0 = main_bus_dat_w; +assign main_sram1_bus_sel0 = main_bus_sel; +assign main_sram1_bus_stb0 = main_bus_stb; +assign main_sram1_bus_we0 = main_bus_we; +assign main_sram1_bus_cti0 = main_bus_cti; +assign main_sram1_bus_bte0 = main_bus_bte; +assign main_sram0_bus_adr1 = main_bus_adr; +assign main_sram0_bus_dat_w1 = main_bus_dat_w; +assign main_sram0_bus_sel1 = main_bus_sel; +assign main_sram0_bus_stb1 = main_bus_stb; +assign main_sram0_bus_we1 = main_bus_we; +assign main_sram0_bus_cti1 = main_bus_cti; +assign main_sram0_bus_bte1 = main_bus_bte; +assign main_sram1_bus_adr1 = main_bus_adr; +assign main_sram1_bus_dat_w1 = main_bus_dat_w; +assign main_sram1_bus_sel1 = main_bus_sel; +assign main_sram1_bus_stb1 = main_bus_stb; +assign main_sram1_bus_we1 = main_bus_we; +assign main_sram1_bus_cti1 = main_bus_cti; +assign main_sram1_bus_bte1 = main_bus_bte; +assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); +assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); +assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); +assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); +assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); +assign builder_shared_adr = builder_array_muxed0; +assign builder_shared_dat_w = builder_array_muxed1; +assign builder_shared_sel = builder_array_muxed2; +assign builder_shared_cyc = builder_array_muxed3; +assign builder_shared_stb = builder_array_muxed4; +assign builder_shared_we = builder_array_muxed5; +assign builder_shared_cti = builder_array_muxed6; +assign builder_shared_bte = builder_array_muxed7; +assign wishbone_dat_r = builder_shared_dat_r; +assign wishbone_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign wishbone_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {wishbone_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:14] == 1'd0); + builder_slave_sel[1] <= (builder_shared_adr[29:11] == 4'd8); +end +assign main_maccore_maccore_wishbone_adr = builder_shared_adr; +assign main_maccore_maccore_wishbone_dat_w = builder_shared_dat_w; +assign main_maccore_maccore_wishbone_sel = builder_shared_sel; +assign main_maccore_maccore_wishbone_stb = builder_shared_stb; +assign main_maccore_maccore_wishbone_we = builder_shared_we; +assign main_maccore_maccore_wishbone_cti = builder_shared_cti; +assign main_maccore_maccore_wishbone_bte = builder_shared_bte; +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign main_maccore_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_maccore_maccore_wishbone_err | main_bus_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= 1'd0; + builder_shared_ack <= (main_maccore_maccore_wishbone_ack | main_bus_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_maccore_maccore_wishbone_dat_r) | ({32{builder_slave_sel_r[1]}} & main_bus_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_reset0_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[1:0] == 1'd0)); +assign builder_csrbank0_reset0_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[1:0] == 1'd0)); +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +assign builder_csrbank0_scratch0_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[1:0] == 1'd1)); +assign builder_csrbank0_scratch0_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[1:0] == 1'd1)); +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +assign builder_csrbank0_bus_errors_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[1:0] == 2'd2)); +assign builder_csrbank0_bus_errors_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[1:0] == 2'd2)); +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_sram_writer_slot_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 1'd0)); +assign builder_csrbank1_sram_writer_slot_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 1'd0)); +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_length_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 1'd1)); +assign builder_csrbank1_sram_writer_length_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 1'd1)); +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_errors_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 2'd2)); +assign builder_csrbank1_sram_writer_errors_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 2'd2)); +assign main_writer_status_r = builder_interface1_bank_bus_dat_w[0]; +assign main_writer_status_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 2'd3)); +assign main_writer_status_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 2'd3)); +assign main_writer_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign main_writer_pending_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 3'd4)); +assign main_writer_pending_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 3'd4)); +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_sram_writer_ev_enable0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 3'd5)); +assign builder_csrbank1_sram_writer_ev_enable0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 3'd5)); +assign main_reader_start_r = builder_interface1_bank_bus_dat_w[0]; +assign main_reader_start_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 3'd6)); +assign main_reader_start_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 3'd6)); +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_sram_reader_ready_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 3'd7)); +assign builder_csrbank1_sram_reader_ready_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 3'd7)); +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_sram_reader_level_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd8)); +assign builder_csrbank1_sram_reader_level_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd8)); +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_sram_reader_slot0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd9)); +assign builder_csrbank1_sram_reader_slot0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd9)); +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +assign builder_csrbank1_sram_reader_length0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd10)); +assign builder_csrbank1_sram_reader_length0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd10)); +assign main_reader_eventmanager_status_r = builder_interface1_bank_bus_dat_w[0]; +assign main_reader_eventmanager_status_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd11)); +assign main_reader_eventmanager_status_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd11)); +assign main_reader_eventmanager_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign main_reader_eventmanager_pending_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd12)); +assign main_reader_eventmanager_pending_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd12)); +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_sram_reader_ev_enable0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd13)); +assign builder_csrbank1_sram_reader_ev_enable0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd13)); +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_preamble_crc_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd14)); +assign builder_csrbank1_preamble_crc_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd14)); +assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_preamble_errors_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 4'd15)); +assign builder_csrbank1_preamble_errors_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 4'd15)); +assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_crc_errors_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[4:0] == 5'd16)); +assign builder_csrbank1_crc_errors_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[4:0] == 5'd16)); +assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; +assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; +assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; +assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_storage; +assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; +assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; +assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; +assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_eventmanager_storage; +assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; +assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; +assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +assign builder_csrbank2_crg_reset0_re = ((builder_csrbank2_sel & builder_interface2_bank_bus_we) & (builder_interface2_bank_bus_adr[1:0] == 1'd0)); +assign builder_csrbank2_crg_reset0_we = ((builder_csrbank2_sel & (~builder_interface2_bank_bus_we)) & (builder_interface2_bank_bus_adr[1:0] == 1'd0)); +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_mdio_w0_re = ((builder_csrbank2_sel & builder_interface2_bank_bus_we) & (builder_interface2_bank_bus_adr[1:0] == 1'd1)); +assign builder_csrbank2_mdio_w0_we = ((builder_csrbank2_sel & (~builder_interface2_bank_bus_we)) & (builder_interface2_bank_bus_adr[1:0] == 1'd1)); +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +assign builder_csrbank2_mdio_r_re = ((builder_csrbank2_sel & builder_interface2_bank_bus_we) & (builder_interface2_bank_bus_adr[1:0] == 2'd2)); +assign builder_csrbank2_mdio_r_we = ((builder_csrbank2_sel & (~builder_interface2_bank_bus_we)) & (builder_interface2_bank_bus_adr[1:0] == 2'd2)); +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +assign main_maccore_ethphy_mdc = main_maccore_ethphy_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy_status; +assign main_maccore_ethphy_we = builder_csrbank2_mdio_r_we; +assign builder_adr = main_maccore_maccore_adr; +assign builder_we = main_maccore_maccore_we; +assign builder_dat_w = main_maccore_maccore_dat_w; +assign main_maccore_maccore_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_array_muxed0 <= 30'd0; + case (builder_grant) + default: begin + builder_array_muxed0 <= wishbone_adr; + end + endcase +end +always @(*) begin + builder_array_muxed1 <= 32'd0; + case (builder_grant) + default: begin + builder_array_muxed1 <= wishbone_dat_w; + end + endcase +end +always @(*) begin + builder_array_muxed2 <= 4'd0; + case (builder_grant) + default: begin + builder_array_muxed2 <= wishbone_sel; + end + endcase +end +always @(*) begin + builder_array_muxed3 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed3 <= wishbone_cyc; + end + endcase +end +always @(*) begin + builder_array_muxed4 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed4 <= wishbone_stb; + end + endcase +end +always @(*) begin + builder_array_muxed5 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed5 <= wishbone_we; + end + endcase +end +always @(*) begin + builder_array_muxed6 <= 3'd0; + case (builder_grant) + default: begin + builder_array_muxed6 <= wishbone_cti; + end + endcase +end +always @(*) begin + builder_array_muxed7 <= 2'd0; + case (builder_grant) + default: begin + builder_array_muxed7 <= wishbone_bte; + end + endcase +end +always @(*) begin + main_maccore_ethphy_status <= 1'd0; + main_maccore_ethphy_status <= main_maccore_ethphy_r; + main_maccore_ethphy_status <= builder_xilinxmultiregimpl0_regs1; +end +assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; +assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; +assign main_tx_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; +assign main_tx_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; +assign main_rx_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; +assign main_rx_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; + +always @(posedge eth_rx_clk) begin + main_maccore_ethphy_liteethphymiirx_converter_reset <= (~mii_eth_rx_dv); + main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd1; + main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data <= mii_eth_rx_data; + if (main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; + end + if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin + if (((main_maccore_ethphy_liteethphymiirx_converter_converter_demux == 1'd1) | main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last)) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd1; + end else begin + main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); + end + end + if ((main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready)) begin + if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; + main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; + end else begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first | main_maccore_ethphy_liteethphymiirx_converter_converter_source_first); + main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last | main_maccore_ethphy_liteethphymiirx_converter_converter_source_last); + end + end + if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin + case (main_maccore_ethphy_liteethphymiirx_converter_converter_demux) + 1'd0: begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; + end + endcase + end + if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); + end + if (main_maccore_ethphy_liteethphymiirx_converter_reset) begin + main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; + end + builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; + if (main_crc32_checker_crc_ce) begin + main_crc32_checker_crc_reg <= main_crc32_checker_crc_next; + end + if (main_crc32_checker_crc_reset) begin + main_crc32_checker_crc_reg <= 32'd4294967295; + end + if (((main_crc32_checker_syncfifo_syncfifo_we & main_crc32_checker_syncfifo_syncfifo_writable) & (~main_crc32_checker_syncfifo_replace))) begin + if ((main_crc32_checker_syncfifo_produce == 3'd4)) begin + main_crc32_checker_syncfifo_produce <= 1'd0; + end else begin + main_crc32_checker_syncfifo_produce <= (main_crc32_checker_syncfifo_produce + 1'd1); + end + end + if (main_crc32_checker_syncfifo_do_read) begin + if ((main_crc32_checker_syncfifo_consume == 3'd4)) begin + main_crc32_checker_syncfifo_consume <= 1'd0; + end else begin + main_crc32_checker_syncfifo_consume <= (main_crc32_checker_syncfifo_consume + 1'd1); + end + end + if (((main_crc32_checker_syncfifo_syncfifo_we & main_crc32_checker_syncfifo_syncfifo_writable) & (~main_crc32_checker_syncfifo_replace))) begin + if ((~main_crc32_checker_syncfifo_do_read)) begin + main_crc32_checker_syncfifo_level <= (main_crc32_checker_syncfifo_level + 1'd1); + end + end else begin + if (main_crc32_checker_syncfifo_do_read) begin + main_crc32_checker_syncfifo_level <= (main_crc32_checker_syncfifo_level - 1'd1); + end + end + if (main_crc32_checker_fifo_reset) begin + main_crc32_checker_syncfifo_level <= 3'd0; + main_crc32_checker_syncfifo_produce <= 3'd0; + main_crc32_checker_syncfifo_consume <= 3'd0; + end + builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; + if (main_ps_preamble_error_i) begin + main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); + end + if (main_ps_crc_error_i) begin + main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_graycounter0_q_binary <= main_rx_cdc_graycounter0_q_next_binary; + main_rx_cdc_graycounter0_q <= main_rx_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; + main_maccore_ethphy_liteethphymiirx_converter_reset <= 1'd0; + main_crc32_checker_crc_reg <= 32'd4294967295; + main_crc32_checker_syncfifo_level <= 3'd0; + main_crc32_checker_syncfifo_produce <= 3'd0; + main_crc32_checker_syncfifo_consume <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_graycounter0_q <= 7'd0; + main_rx_cdc_graycounter0_q_binary <= 7'd0; + builder_liteethmacpreamblechecker_state <= 1'd0; + builder_liteethmaccrc32checker_state <= 2'd0; + end + builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_graycounter1_q; + builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; +end + +always @(posedge eth_tx_clk) begin + mii_eth_tx_en <= main_maccore_ethphy_liteethphymiitx_converter_source_valid; + mii_eth_tx_data <= main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; + if ((main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready)) begin + if (main_maccore_ethphy_liteethphymiitx_converter_converter_last) begin + main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; + end else begin + main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= (main_maccore_ethphy_liteethphymiitx_converter_converter_mux + 1'd1); + end + end + if (main_tx_gap_inserter_counter_reset) begin + main_tx_gap_inserter_counter <= 1'd0; + end else begin + if (main_tx_gap_inserter_counter_ce) begin + main_tx_gap_inserter_counter <= (main_tx_gap_inserter_counter + 1'd1); + end + end + builder_liteethmacgap_state <= builder_liteethmacgap_next_state; + if (main_preamble_inserter_clr_cnt) begin + main_preamble_inserter_cnt <= 1'd0; + end else begin + if (main_preamble_inserter_inc_cnt) begin + main_preamble_inserter_cnt <= (main_preamble_inserter_cnt + 1'd1); + end + end + builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; + if (main_crc32_inserter_is_ongoing0) begin + main_crc32_inserter_cnt <= 2'd3; + end else begin + if ((main_crc32_inserter_is_ongoing1 & (~main_crc32_inserter_cnt_done))) begin + main_crc32_inserter_cnt <= (main_crc32_inserter_cnt - main_crc32_inserter_source_ready); + end + end + if (main_crc32_inserter_ce) begin + main_crc32_inserter_reg <= main_crc32_inserter_next; + end + if (main_crc32_inserter_reset) begin + main_crc32_inserter_reg <= 32'd4294967295; + end + builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; + if (main_padding_inserter_counter_reset) begin + main_padding_inserter_counter <= 1'd0; + end else begin + if (main_padding_inserter_counter_ce) begin + main_padding_inserter_counter <= (main_padding_inserter_counter + 1'd1); + end + end + builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if (main_tx_last_be_sink_last) begin + main_tx_last_be_ongoing <= 1'd1; + end else begin + if (main_tx_last_be_sink_payload_last_be) begin + main_tx_last_be_ongoing <= 1'd0; + end + end + end + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + main_tx_cdc_graycounter1_q_binary <= main_tx_cdc_graycounter1_q_next_binary; + main_tx_cdc_graycounter1_q <= main_tx_cdc_graycounter1_q_next; + if (eth_tx_rst) begin + main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; + main_crc32_inserter_reg <= 32'd4294967295; + main_crc32_inserter_cnt <= 2'd3; + main_padding_inserter_counter <= 16'd1; + main_tx_last_be_ongoing <= 1'd1; + main_tx_converter_converter_mux <= 2'd0; + main_tx_cdc_graycounter1_q <= 7'd0; + main_tx_cdc_graycounter1_q_binary <= 7'd0; + builder_liteethmacgap_state <= 1'd0; + builder_liteethmacpreambleinserter_state <= 2'd0; + builder_liteethmaccrc32inserter_state <= 2'd0; + builder_liteethmacpaddinginserter_state <= 1'd0; + end + builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_graycounter0_q; + builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; +end + +always @(posedge por_clk) begin + main_maccore_int_rst <= sys_reset; +end + +always @(posedge sys_clk) begin + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + builder_state <= builder_next_state; + if (main_maccore_ethphy_counter_ce) begin + main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); + end + if (main_ps_preamble_error_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_ps_crc_error_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; + main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; + main_tx_cdc_graycounter0_q_binary <= main_tx_cdc_graycounter0_q_next_binary; + main_tx_cdc_graycounter0_q <= main_tx_cdc_graycounter0_q_next; + main_rx_cdc_graycounter1_q_binary <= main_rx_cdc_graycounter1_q_next_binary; + main_rx_cdc_graycounter1_q <= main_rx_cdc_graycounter1_q_next; + if (main_writer_slot_ce) begin + main_writer_slot <= (main_writer_slot + 1'd1); + end + if (((main_writer_fifo_syncfifo_we & main_writer_fifo_syncfifo_writable) & (~main_writer_fifo_replace))) begin + main_writer_fifo_produce <= (main_writer_fifo_produce + 1'd1); + end + if (main_writer_fifo_do_read) begin + main_writer_fifo_consume <= (main_writer_fifo_consume + 1'd1); + end + if (((main_writer_fifo_syncfifo_we & main_writer_fifo_syncfifo_writable) & (~main_writer_fifo_replace))) begin + if ((~main_writer_fifo_do_read)) begin + main_writer_fifo_level <= (main_writer_fifo_level + 1'd1); + end + end else begin + if (main_writer_fifo_do_read) begin + main_writer_fifo_level <= (main_writer_fifo_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_writer_counter_t_next_value_ce) begin + main_writer_counter <= main_writer_counter_t_next_value; + end + if (main_writer_errors_status_f_next_value_ce) begin + main_writer_errors_status <= main_writer_errors_status_f_next_value; + end + if (main_reader_done_clear) begin + main_reader_done_pending <= 1'd0; + end + if (main_reader_done_trigger) begin + main_reader_done_pending <= 1'd1; + end + if (((main_reader_fifo_syncfifo_we & main_reader_fifo_syncfifo_writable) & (~main_reader_fifo_replace))) begin + main_reader_fifo_produce <= (main_reader_fifo_produce + 1'd1); + end + if (main_reader_fifo_do_read) begin + main_reader_fifo_consume <= (main_reader_fifo_consume + 1'd1); + end + if (((main_reader_fifo_syncfifo_we & main_reader_fifo_syncfifo_writable) & (~main_reader_fifo_replace))) begin + if ((~main_reader_fifo_do_read)) begin + main_reader_fifo_level <= (main_reader_fifo_level + 1'd1); + end + end else begin + if (main_reader_fifo_do_read) begin + main_reader_fifo_level <= (main_reader_fifo_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_reader_counter_next_value_ce) begin + main_reader_counter <= main_reader_counter_next_value; + end + main_sram0_bus_ack0 <= 1'd0; + if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin + main_sram0_bus_ack0 <= 1'd1; + end + main_sram1_bus_ack0 <= 1'd0; + if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin + main_sram1_bus_ack0 <= 1'd1; + end + main_sram0_bus_ack1 <= 1'd0; + if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin + main_sram0_bus_ack1 <= 1'd1; + end + main_sram1_bus_ack1 <= 1'd0; + if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin + main_sram1_bus_ack1 <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[1:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[4:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= main_writer_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= main_writer_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_reader_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= main_reader_eventmanager_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= main_reader_eventmanager_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; + end + endcase + end + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_writer_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_writer_re <= builder_csrbank1_sram_writer_ev_enable0_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_reader_eventmanager_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_reader_eventmanager_re <= builder_csrbank1_sram_reader_ev_enable0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[1:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy_re <= builder_csrbank2_mdio_w0_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 1'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_counter <= 9'd0; + main_maccore_ethphy_storage <= 3'd0; + main_maccore_ethphy_re <= 1'd0; + main_preamble_errors_status <= 32'd0; + main_crc_errors_status <= 32'd0; + main_tx_cdc_graycounter0_q <= 7'd0; + main_tx_cdc_graycounter0_q_binary <= 7'd0; + main_rx_cdc_graycounter1_q <= 7'd0; + main_rx_cdc_graycounter1_q_binary <= 7'd0; + main_writer_errors_status <= 32'd0; + main_writer_storage <= 1'd0; + main_writer_re <= 1'd0; + main_writer_counter <= 32'd0; + main_writer_slot <= 1'd0; + main_writer_fifo_level <= 2'd0; + main_writer_fifo_produce <= 1'd0; + main_writer_fifo_consume <= 1'd0; + main_reader_slot_re <= 1'd0; + main_reader_length_re <= 1'd0; + main_reader_done_pending <= 1'd0; + main_reader_eventmanager_storage <= 1'd0; + main_reader_eventmanager_re <= 1'd0; + main_reader_fifo_level <= 2'd0; + main_reader_fifo_produce <= 1'd0; + main_reader_fifo_consume <= 1'd0; + main_reader_counter <= 11'd0; + main_sram0_bus_ack0 <= 1'd0; + main_sram1_bus_ack0 <= 1'd0; + main_sram0_bus_ack1 <= 1'd0; + main_sram1_bus_ack1 <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_state <= 1'd0; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + end + builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; + builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; + builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; + builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; + builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; + builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; + builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_graycounter1_q; + builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; + builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_graycounter0_q; + builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; +end + +assign mii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = mii_eth_mdio; + +reg [11:0] storage[0:4]; +reg [11:0] memdat; +always @(posedge eth_rx_clk) begin + if (main_crc32_checker_syncfifo_wrport_we) + storage[main_crc32_checker_syncfifo_wrport_adr] <= main_crc32_checker_syncfifo_wrport_dat_w; + memdat <= storage[main_crc32_checker_syncfifo_wrport_adr]; +end + +always @(posedge eth_rx_clk) begin +end + +assign main_crc32_checker_syncfifo_wrport_dat_r = memdat; +assign main_crc32_checker_syncfifo_rdport_dat_r = storage[main_crc32_checker_syncfifo_rdport_adr]; + +reg [41:0] storage_1[0:63]; +reg [5:0] memadr; +reg [5:0] memadr_1; +always @(posedge sys_clk) begin + if (main_tx_cdc_wrport_we) + storage_1[main_tx_cdc_wrport_adr] <= main_tx_cdc_wrport_dat_w; + memadr <= main_tx_cdc_wrport_adr; +end + +always @(posedge eth_tx_clk) begin + memadr_1 <= main_tx_cdc_rdport_adr; +end + +assign main_tx_cdc_wrport_dat_r = storage_1[memadr]; +assign main_tx_cdc_rdport_dat_r = storage_1[memadr_1]; + +reg [41:0] storage_2[0:63]; +reg [5:0] memadr_2; +reg [5:0] memadr_3; +always @(posedge eth_rx_clk) begin + if (main_rx_cdc_wrport_we) + storage_2[main_rx_cdc_wrport_adr] <= main_rx_cdc_wrport_dat_w; + memadr_2 <= main_rx_cdc_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_3 <= main_rx_cdc_rdport_adr; +end + +assign main_rx_cdc_wrport_dat_r = storage_2[memadr_2]; +assign main_rx_cdc_rdport_dat_r = storage_2[memadr_3]; + +reg [34:0] storage_3[0:1]; +reg [34:0] memdat_1; +always @(posedge sys_clk) begin + if (main_writer_fifo_wrport_we) + storage_3[main_writer_fifo_wrport_adr] <= main_writer_fifo_wrport_dat_w; + memdat_1 <= storage_3[main_writer_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_writer_fifo_wrport_dat_r = memdat_1; +assign main_writer_fifo_rdport_dat_r = storage_3[main_writer_fifo_rdport_adr]; + +reg [31:0] mem[0:381]; +reg [8:0] memadr_4; +reg [31:0] memdat_2; +always @(posedge sys_clk) begin + if (main_writer_memory0_we) + mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; + memadr_4 <= main_writer_memory0_adr; +end + +always @(posedge sys_clk) begin + memdat_2 <= mem[main_sram0_adr0]; +end + +assign main_writer_memory0_dat_r = mem[memadr_4]; +assign main_sram0_dat_r0 = memdat_2; + +reg [31:0] mem_1[0:381]; +reg [8:0] memadr_5; +reg [31:0] memdat_3; +always @(posedge sys_clk) begin + if (main_writer_memory1_we) + mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; + memadr_5 <= main_writer_memory1_adr; +end + +always @(posedge sys_clk) begin + memdat_3 <= mem_1[main_sram1_adr0]; +end + +assign main_writer_memory1_dat_r = mem_1[memadr_5]; +assign main_sram1_dat_r0 = memdat_3; + +reg [13:0] storage_4[0:1]; +reg [13:0] memdat_4; +always @(posedge sys_clk) begin + if (main_reader_fifo_wrport_we) + storage_4[main_reader_fifo_wrport_adr] <= main_reader_fifo_wrport_dat_w; + memdat_4 <= storage_4[main_reader_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_reader_fifo_wrport_dat_r = memdat_4; +assign main_reader_fifo_rdport_dat_r = storage_4[main_reader_fifo_rdport_adr]; + +reg [31:0] mem_2[0:381]; +reg [8:0] memadr_6; +always @(posedge sys_clk) begin +end + +always @(posedge sys_clk) begin + if (main_sram0_we[0]) + mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; + if (main_sram0_we[1]) + mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; + if (main_sram0_we[2]) + mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; + if (main_sram0_we[3]) + mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; + memadr_6 <= main_sram0_adr1; +end + +assign main_reader_memory0_dat_r = mem_2[main_reader_memory0_adr]; +assign main_sram0_dat_r1 = mem_2[memadr_6]; + +reg [31:0] mem_3[0:381]; +reg [8:0] memadr_7; +always @(posedge sys_clk) begin +end + +always @(posedge sys_clk) begin + if (main_sram1_we[0]) + mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; + if (main_sram1_we[1]) + mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; + if (main_sram1_we[2]) + mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; + if (main_sram1_we[3]) + mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; + memadr_7 <= main_sram1_adr1; +end + +assign main_reader_memory1_dat_r = mem_3[main_reader_memory1_adr]; +assign main_sram1_dat_r1 = mem_3[memadr_7]; + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(eth_tx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(main_maccore_ethphy_reset0), + .Q(builder_rst_meta0) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(eth_tx_clk), + .CE(1'd1), + .D(builder_rst_meta0), + .PRE(main_maccore_ethphy_reset0), + .Q(eth_tx_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(eth_rx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(main_maccore_ethphy_reset0), + .Q(builder_rst_meta1) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(eth_rx_clk), + .CE(1'd1), + .D(builder_rst_meta1), + .PRE(main_maccore_ethphy_reset0), + .Q(eth_rx_rst) +); + +endmodule diff --git a/liteeth/liteeth.core b/liteeth/liteeth.core new file mode 100644 index 0000000..6a5c719 --- /dev/null +++ b/liteeth/liteeth.core @@ -0,0 +1,15 @@ +CAPI=2: + +name : :microwatt:liteeth:0 + +generators: + liteeth_gen: + interpreter: python3 + command: fusesoc-add-files.py + description: Generate a liteeth ethernet controller + usage: | + liteeth_gen adds the pre-generated LiteX LiteEth memory controller + based on the board type. + + Parameters: + board: The board type (arty) diff --git a/microwatt.core b/microwatt.core index 83d7762..4f9820a 100644 --- a/microwatt.core +++ b/microwatt.core @@ -100,6 +100,9 @@ filesets: litedram: depend : [":microwatt:litedram"] + liteeth: + depend : [":microwatt:liteeth"] + targets: nexys_a7: default_tool: vivado @@ -141,7 +144,7 @@ targets: - no_bram - spi_flash_offset=10485760 - log_length=2048 - generate: [dram_nexys_video] + generate: [litedram_nexys_video] tools: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel @@ -163,16 +166,17 @@ targets: arty_a7-35: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific] parameters : - memory_size - ram_init_file - use_litedram=true + - use_liteeth=true - disable_flatten_core - no_bram - spi_flash_offset=3145728 - log_length=512 - generate: [dram_arty] + generate: [litedram_arty, liteeth_arty] tools: vivado: {part : xc7a35ticsg324-1L} toplevel : toplevel @@ -194,16 +198,17 @@ targets: arty_a7-100: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific] parameters: - memory_size - ram_init_file - use_litedram=true + - use_liteeth=true - disable_flatten_core - no_bram - spi_flash_offset=4194304 - log_length=2048 - generate: [dram_arty] + generate: [litedram_arty, liteeth_arty] tools: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel @@ -230,11 +235,15 @@ targets: toplevel: core generate: - dram_arty: + litedram_arty: generator: litedram_gen parameters: {board : arty} - dram_nexys_video: + liteeth_arty: + generator: liteeth_gen + parameters: {board : arty} + + litedram_nexys_video: generator: litedram_gen parameters: {board : nexys-video} @@ -279,6 +288,12 @@ parameters: paramtype : generic default : false + use_liteeth: + datatype : bool + description : Use liteEth + paramtype : generic + default : false + no_bram: datatype : bool description : No internal block RAM (only DRAM and init code carrying payload) diff --git a/soc.vhdl b/soc.vhdl index c3b47bc..04ac176 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -29,6 +29,12 @@ use work.wishbone_types.all; -- External IO bus: -- 0xc8000000: LiteDRAM control (CSRs) +-- 0xc8020000: LiteEth CSRs (*) +-- 0xc8030000: LiteEth MMIO (*) + +-- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs +-- are actually decoded as a single wishbone which LiteEth will +-- internally split based on bit 16. -- (**) DRAM init code is currently special and goes to the external -- IO bus, this will be fixed when it's moved out of litedram and @@ -37,6 +43,7 @@ use work.wishbone_types.all; -- Interrupt numbers: -- -- 0 : UART0 +-- 1 : Ethernet entity soc is generic ( @@ -53,7 +60,8 @@ entity soc is SPI_FLASH_OFFSET : integer := 0; SPI_FLASH_DEF_CKDV : natural := 2; SPI_FLASH_DEF_QUAD : boolean := false; - LOG_LENGTH : natural := 512 + LOG_LENGTH : natural := 512; + HAS_LITEETH : boolean := false ); port( rst : in std_ulogic; @@ -68,6 +76,10 @@ entity soc is wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init; wb_ext_is_dram_csr : out std_ulogic; wb_ext_is_dram_init : out std_ulogic; + wb_ext_is_eth : out std_ulogic; + + -- External interrupts + ext_irq_eth : in std_ulogic := '0'; -- UART0 signals: uart0_txd : out std_ulogic; @@ -181,6 +193,7 @@ architecture behaviour of soc is SLAVE_IO_EXTERNAL, SLAVE_IO_NONE); signal slave_io_dbg : slave_io_type; + begin resets: process(system_clk) @@ -298,6 +311,7 @@ begin wb_io_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_io_out; end case; + end process slave_top_intercon; -- IO wishbone slave 64->32 bits converter @@ -499,6 +513,7 @@ begin wb_ext_is_dram_csr <= '0'; wb_ext_is_dram_init <= '0'; + wb_ext_is_eth <= '0'; -- Default response, ack & return all 1's wb_sio_in.dat <= (others => '1'); @@ -520,6 +535,12 @@ begin elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then wb_ext_is_dram_csr <= '1'; ext_valid := true; + elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then + wb_ext_is_eth <= '1'; + ext_valid := true; + elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then + wb_ext_is_eth <= '1'; + ext_valid := true; end if; if ext_valid then wb_ext_io_in.cyc <= wb_sio_out.cyc; @@ -564,7 +585,8 @@ begin DRAM_INIT_SIZE => DRAM_INIT_SIZE, CLK_FREQ => CLK_FREQ, HAS_SPI_FLASH => HAS_SPI_FLASH, - SPI_FLASH_OFFSET => SPI_FLASH_OFFSET + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + HAS_LITEETH => HAS_LITEETH ) port map( clk => system_clk, @@ -657,6 +679,7 @@ begin begin int_level_in <= (others => '0'); int_level_in(0) <= uart0_irq; + int_level_in(1) <= ext_irq_eth; end process; -- BRAM Memory slave diff --git a/syscon.vhdl b/syscon.vhdl index 96053b5..86e53ba 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -16,7 +16,8 @@ entity syscon is DRAM_SIZE : integer; DRAM_INIT_SIZE : integer; HAS_SPI_FLASH : boolean; - SPI_FLASH_OFFSET : integer + SPI_FLASH_OFFSET : integer; + HAS_LITEETH : boolean ); port ( clk : in std_ulogic; @@ -56,6 +57,7 @@ architecture behaviour of syscon is constant SYS_REG_INFO_HAS_DRAM : integer := 1; constant SYS_REG_INFO_HAS_BRAM : integer := 2; constant SYS_REG_INFO_HAS_SPIF : integer := 3; + constant SYS_REG_INFO_HAS_LETH : integer := 4; -- BRAMINFO contains the BRAM size in the bottom 52 bits -- DRAMINFO contains the DRAM size if any in the bottom 52 bits @@ -89,6 +91,7 @@ architecture behaviour of syscon is signal info_has_bram : std_ulogic; signal info_has_uart : std_ulogic; signal info_has_spif : std_ulogic; + signal info_has_leth : std_ulogic; signal info_clk : std_ulogic_vector(39 downto 0); signal info_fl_off : std_ulogic_vector(31 downto 0); @@ -102,16 +105,19 @@ begin core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); -- Info register is hard wired - info_has_uart <= '1' when HAS_UART else '0'; - info_has_dram <= '1' when HAS_DRAM else '0'; + info_has_uart <= '1' when HAS_UART else '0'; + info_has_dram <= '1' when HAS_DRAM else '0'; info_has_bram <= '1' when BRAM_SIZE /= 0 else '0'; - info_has_spif <= '1' when HAS_SPI_FLASH else '0'; + info_has_spif <= '1' when HAS_SPI_FLASH else '0'; + info_has_leth <= '1' when HAS_LITEETH else '0'; info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart, SYS_REG_INFO_HAS_DRAM => info_has_dram, SYS_REG_INFO_HAS_BRAM => info_has_bram, SYS_REG_INFO_HAS_SPIF => info_has_spif, + SYS_REG_INFO_HAS_LETH => info_has_leth, others => '0'); + reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM else (others => '0');