From ad6c6790f96bb3b94025e1ec368d727ee17d8642 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 13 Oct 2019 12:52:39 +1100 Subject: [PATCH 1/2] fifo: Remove shared variable The shared variable used for FIFO memory is not VHDL 2008 compliant. I can't see why it needs to be a shared variable since reads and writes update top and bottom synchronously, meaning they don't need same cycle access to the FIFO memory. Signed-off-by: Anton Blanchard --- fpga/pp_fifo.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/pp_fifo.vhd b/fpga/pp_fifo.vhd index 909c969..7447782 100644 --- a/fpga/pp_fifo.vhd +++ b/fpga/pp_fifo.vhd @@ -30,7 +30,7 @@ end entity pp_fifo; architecture behaviour of pp_fifo is type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); - shared variable memory : memory_array := (others => (others => '0')); + signal memory : memory_array := (others => (others => '0')); subtype index_type is integer range 0 to DEPTH - 1; signal top, bottom : index_type; @@ -64,7 +64,7 @@ begin top <= 0; else if push = '1' then - memory(top) := data_in; + memory(top) <= data_in; top <= (top + 1) mod DEPTH; end if; end if; From 7aaed5abd512897fc47eef8d0624cc3d4de6cb93 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 13 Oct 2019 12:57:23 +1100 Subject: [PATCH 2/2] fifo: Reformat Signed-off-by: Anton Blanchard --- fpga/pp_fifo.vhd | 132 +++++++++++++++++++++++------------------------ 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/fpga/pp_fifo.vhd b/fpga/pp_fifo.vhd index 7447782..ee9b701 100644 --- a/fpga/pp_fifo.vhd +++ b/fpga/pp_fifo.vhd @@ -7,85 +7,85 @@ use ieee.std_logic_1164.all; --! @brief A generic FIFO module. --! Adopted from the FIFO module in . entity pp_fifo is - generic( - DEPTH : natural := 64; - WIDTH : natural := 32 - ); - port( - -- Control lines: - clk : in std_logic; - reset : in std_logic; + generic( + DEPTH : natural := 64; + WIDTH : natural := 32 + ); + port( + -- Control lines: + clk : in std_logic; + reset : in std_logic; - -- Status lines: - full : out std_logic; - empty : out std_logic; + -- Status lines: + full : out std_logic; + empty : out std_logic; - -- Data in: - data_in : in std_logic_vector(WIDTH - 1 downto 0); - data_out : out std_logic_vector(WIDTH - 1 downto 0); - push, pop : in std_logic - ); + -- Data in: + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0); + push, pop : in std_logic + ); end entity pp_fifo; architecture behaviour of pp_fifo is - type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); - signal memory : memory_array := (others => (others => '0')); + type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); + signal memory : memory_array := (others => (others => '0')); - subtype index_type is integer range 0 to DEPTH - 1; - signal top, bottom : index_type; + subtype index_type is integer range 0 to DEPTH - 1; + signal top, bottom : index_type; - type fifo_op is (FIFO_POP, FIFO_PUSH); - signal prev_op : fifo_op := FIFO_POP; + type fifo_op is (FIFO_POP, FIFO_PUSH); + signal prev_op : fifo_op := FIFO_POP; begin - empty <= '1' when top = bottom and prev_op = FIFO_POP else '0'; - full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0'; + empty <= '1' when top = bottom and prev_op = FIFO_POP else '0'; + full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0'; - read: process(clk) - begin - if rising_edge(clk) then - if reset = '1' then - bottom <= 0; - else - if pop = '1' then - data_out <= memory(bottom); - bottom <= (bottom + 1) mod DEPTH; - end if; - end if; - end if; - end process read; + read: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + bottom <= 0; + else + if pop = '1' then + data_out <= memory(bottom); + bottom <= (bottom + 1) mod DEPTH; + end if; + end if; + end if; + end process read; - write: process(clk) - begin - if rising_edge(clk) then - if reset = '1' then - top <= 0; - else - if push = '1' then - memory(top) <= data_in; - top <= (top + 1) mod DEPTH; - end if; - end if; - end if; - end process write; + write: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + top <= 0; + else + if push = '1' then + memory(top) <= data_in; + top <= (top + 1) mod DEPTH; + end if; + end if; + end if; + end process write; - set_prev_op: process(clk) - begin - if rising_edge(clk) then - if reset = '1' then - prev_op <= FIFO_POP; - else - if push = '1' and pop = '1' then - prev_op <= FIFO_POP; - elsif push = '1' then - prev_op <= FIFO_PUSH; - elsif pop = '1' then - prev_op <= FIFO_POP; - end if; - end if; - end if; - end process set_prev_op; + set_prev_op: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + prev_op <= FIFO_POP; + else + if push = '1' and pop = '1' then + prev_op <= FIFO_POP; + elsif push = '1' then + prev_op <= FIFO_PUSH; + elsif pop = '1' then + prev_op <= FIFO_POP; + end if; + end if; + end if; + end process set_prev_op; end architecture behaviour;