From 488c30fe91d5664890f72a7f4dee2ab5f100cb22 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 19 Jan 2020 21:18:05 +1100 Subject: [PATCH 1/2] Add log2ceil and use it in bram code We might want a non power of 2 amount of RAM in order to fit into an FPGA, so create log2ceil and use it when calculating the number of memory bits. Signed-off-by: Anton Blanchard --- utils.vhdl | 12 ++++++++++++ wishbone_bram_wrapper.vhdl | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/utils.vhdl b/utils.vhdl index 7238641..4ccc3b5 100644 --- a/utils.vhdl +++ b/utils.vhdl @@ -5,6 +5,7 @@ use ieee.numeric_std.all; package utils is function log2(i : natural) return integer; + function log2ceil(i : natural) return integer; function ispow2(i : integer) return boolean; end utils; @@ -22,6 +23,17 @@ package body utils is return ret; end function; + function log2ceil(i : natural) return integer is + variable tmp : integer := i; + variable ret : integer := 0; + begin + while tmp >= 1 loop + ret := ret + 1; + tmp := tmp / 2; + end loop; + return ret; + end function; + function ispow2(i : integer) return boolean is begin if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index 14520b5..2cf2a17 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is end entity wishbone_bram_wrapper; architecture behaviour of wishbone_bram_wrapper is - constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3; + constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3; -- RAM interface signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0); From f5424f8e717c59c5046105b4fc1cd6c4b92eaefc Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 19 Jan 2020 21:28:32 +1100 Subject: [PATCH 2/2] Reduce simulated and default FPGA RAM to 384kB Micropython has been able to fit into 384kB for ages, so lets reduce our simulated RAM. This is useful for testing if micropython will run on an ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB. Signed-off-by: Anton Blanchard --- core_tb.vhdl | 2 +- fpga/toplevel.vhdl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/core_tb.vhdl b/core_tb.vhdl index 90fc30c..8597e06 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -19,7 +19,7 @@ begin soc0: entity work.soc generic map( SIM => true, - MEMORY_SIZE => 524288, + MEMORY_SIZE => (384*1024), RAM_INIT_FILE => "main_ram.bin", RESET_LOW => false ) diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl index 38af730..a3b8282 100644 --- a/fpga/toplevel.vhdl +++ b/fpga/toplevel.vhdl @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 524288; + MEMORY_SIZE : positive := (384*1024); RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_INPUT : positive := 100000000;