From 8af2b004c389aeb65e12621eb59f5416706268f1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Sep 2019 12:17:42 +1000 Subject: [PATCH] Simplify fetch1 Do the +4 in a single place. This shouldn't cause any difference in behaviour as these are sequential variable assignments. Signed-off-by: Benjamin Herrenschmidt --- fetch1.vhdl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fetch1.vhdl b/fetch1.vhdl index 29ff71f..643e8c8 100644 --- a/fetch1.vhdl +++ b/fetch1.vhdl @@ -49,19 +49,18 @@ begin if stall_in = '0' then v.nia := r_int.nia_next; - v_int.nia_next := std_logic_vector(unsigned(r_int.nia_next) + 4); end if; if e_in.redirect = '1' then v.nia := e_in.redirect_nia; - v_int.nia_next := std_logic_vector(unsigned(e_in.redirect_nia) + 4); end if; if rst = '1' then v.nia := RESET_ADDRESS; - v_int.nia_next := std_logic_vector(unsigned(RESET_ADDRESS) + 4); end if; + v_int.nia_next := std_logic_vector(unsigned(v.nia) + 4); + -- Update registers rin <= v; rin_int <= v_int;