diff --git a/tests/mmu/head.S b/tests/mmu/head.S
index 083b1c5..824ad67 100644
--- a/tests/mmu/head.S
+++ b/tests/mmu/head.S
@@ -80,6 +80,20 @@ test_write:
 	mtmsrd	%r9,0
 	blr
 
+	/* Do a dcbz with translation on */
+	.globl	test_dcbz
+test_dcbz:
+	mfmsr	%r9
+	ori	%r8,%r9,0x10	/* set MSR_DR */
+	mtmsrd	%r8,0
+	mr	%r6,%r3
+	li	%r3,0
+	dcbz	0,%r6
+	li	%r3,1
+	/* land here if DSI occurred */
+	mtmsrd	%r9,0
+	blr
+
 	.globl	test_exec
 test_exec:
 	mtsrr0	%r4
diff --git a/tests/mmu/mmu.c b/tests/mmu/mmu.c
index a44c79d..994ffe3 100644
--- a/tests/mmu/mmu.c
+++ b/tests/mmu/mmu.c
@@ -9,6 +9,7 @@
 
 extern int test_read(long *addr, long *ret, long init);
 extern int test_write(long *addr, long val);
+extern int test_dcbz(long *addr);
 extern int test_exec(int testno, unsigned long pc, unsigned long msr);
 
 static inline void do_tlbie(unsigned long rb, unsigned long rs)
@@ -579,6 +580,25 @@ int mmu_test_17(void)
 	return 0;
 }
 
+int mmu_test_18(void)
+{
+	long *mem = (long *) 0x8000;
+	long *ptr = (long *) 0x124000;
+	long *ptr2 = (long *) 0x1124000;
+
+	/* create PTE */
+	map(ptr, mem, DFLT_PERM);
+	/* this should succeed and be a cache miss */
+	if (!test_dcbz(&ptr[129]))
+		return 1;
+	/* create a second PTE */
+	map(ptr2, mem, DFLT_PERM);
+	/* this should succeed and be a cache hit */
+	if (!test_dcbz(&ptr2[130]))
+		return 2;
+	return 0;
+}
+
 int fail = 0;
 
 void do_test(int num, int (*test)(void))
@@ -633,6 +653,7 @@ int main(void)
 	do_test(15, mmu_test_15);
 	do_test(16, mmu_test_16);
 	do_test(17, mmu_test_17);
+	do_test(18, mmu_test_18);
 
 	return fail;
 }
diff --git a/tests/test_mmu.bin b/tests/test_mmu.bin
index afae999..416ae70 100755
Binary files a/tests/test_mmu.bin and b/tests/test_mmu.bin differ
diff --git a/tests/test_mmu.console_out b/tests/test_mmu.console_out
index a8e2dcb..a5c08ea 100644
--- a/tests/test_mmu.console_out
+++ b/tests/test_mmu.console_out
@@ -15,3 +15,4 @@ test 14:PASS
 test 15:PASS
 test 16:PASS
 test 17:PASS
+test 18:PASS