From 907c83352179c911da9e2132bb264746ef12b145 Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@ozlabs.org>
Date: Wed, 23 Mar 2022 17:43:09 +1100
Subject: [PATCH] Move register stage back after the RAM

The 512x64 DFFRAM has quite big hold violations that we can hopefully
work around by removing the register stage before the RAM.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---
 asic/main_bram.vhdl | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/asic/main_bram.vhdl b/asic/main_bram.vhdl
index b4c0762..add4b29 100644
--- a/asic/main_bram.vhdl
+++ b/asic/main_bram.vhdl
@@ -34,39 +34,30 @@ architecture behaviour of main_bram is
 
     signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
 
-    signal addr_buf : std_logic_vector(HEIGHT_BITS-1 downto 0);
-    signal din_buf : std_logic_vector(WIDTH-1 downto 0);
-    signal sel_buf : std_logic_vector((WIDTH/8)-1 downto 0);
-    signal re_buf : std_ulogic;
-    signal we_buf : std_ulogic;
+    signal obuf : std_logic_vector(WIDTH-1 downto 0);
 begin
     assert (WIDTH = 64)         report "Must be 64 bit" severity FAILURE;
     -- Do we have a log2 round up issue here?
     assert (HEIGHT_BITS = 9)    report "HEIGHT_BITS must be 10" severity FAILURE;
     assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE;
 
-    sel_qual <= sel_buf when we_buf = '1' else (others => '0');
+    sel_qual <= sel when we = '1' else (others => '0');
 
     memory_0 : RAM512
         port map (
             CLK  => clk,
             WE0  => sel_qual(7 downto 0),
-            EN0  => re_buf or we_buf,
-            Di0  => din_buf(63 downto 0),
-            Do0  => dout(63 downto 0),
-            A0   => addr_buf(8 downto 0)
+            EN0  => re or we,
+            Di0  => din(63 downto 0),
+            Do0  => obuf(63 downto 0),
+            A0   => addr(8 downto 0)
             );
 
-    -- The wishbone BRAM wrapper assumes a 1 cycle delay.
-    -- Since the DFFRAM already registers outputs, place this on the input side.
+    -- The wishbone BRAM wrapper assumes a 1 cycle delay
     memory_read_buffer: process(clk)
     begin
         if rising_edge(clk) then
-            addr_buf <= addr;
-            din_buf <= din;
-            sel_buf <= sel;
-            re_buf <= re;
-            we_buf <= we;
+            dout <= obuf;
         end if;
     end process;
 end architecture behaviour;