From ad3db18dce46cfef0b1d0d1acba0071d891eac0c Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 13:24:14 +1100 Subject: [PATCH 1/8] Fix a ghdysynth inferred latch error in execute It should never happen in practise, but ghdlsynth is complaining about an inferred latch here. Fix it Signed-off-by: Anton Blanchard --- execute1.vhdl | 1 + 1 file changed, 1 insertion(+) diff --git a/execute1.vhdl b/execute1.vhdl index 4986c71..4714ec5 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -386,6 +386,7 @@ begin when "1110" => -- CROR crresult := (e_in.cr(banum) or e_in.cr(bbnum)); when others => + crresult := '0'; report "BAD CR?"; end case; v.e.write_cr_mask := num_to_fxm((31-btnum) / 4); From 25968951e4de5be37c53afec1da7ef10a3cbda49 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:20:35 +1100 Subject: [PATCH 2/8] Fix a ghdysynth inferred latch error in writeback Signed-off-by: Anton Blanchard --- writeback.vhdl | 1 + 1 file changed, 1 insertion(+) diff --git a/writeback.vhdl b/writeback.vhdl index b88277e..8582166 100644 --- a/writeback.vhdl +++ b/writeback.vhdl @@ -104,6 +104,7 @@ begin sign_extend <= '0'; second_word <= '0'; xe := e_in.xerc; + data_in <= (others => '0'); if e_in.write_enable = '1' then w_out.write_reg <= e_in.write_reg; From f37ef56d79bff577e90b080c7fdd8afb554e9393 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:28:20 +1100 Subject: [PATCH 3/8] Remove unused signal Signed-off-by: Anton Blanchard --- divider.vhdl | 1 - 1 file changed, 1 deletion(-) diff --git a/divider.vhdl b/divider.vhdl index 39893a8..affab85 100644 --- a/divider.vhdl +++ b/divider.vhdl @@ -22,7 +22,6 @@ architecture behaviour of divider is signal result : std_ulogic_vector(63 downto 0); signal sresult : std_ulogic_vector(64 downto 0); signal oresult : std_ulogic_vector(63 downto 0); - signal qbit : std_ulogic; signal running : std_ulogic; signal signcheck : std_ulogic; signal count : unsigned(6 downto 0); From b0212b0bf9e01ceab71b625430ef651099aa14ac Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:29:39 +1100 Subject: [PATCH 4/8] Fix ghdlsynth issue in register file We need to drive sim_dump_done to keep ghdlsynth happy. Signed-off-by: Anton Blanchard --- register_file.vhdl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/register_file.vhdl b/register_file.vhdl index 2caa4b5..6a4c989 100644 --- a/register_file.vhdl +++ b/register_file.vhdl @@ -92,4 +92,9 @@ begin end process; end generate; + -- Keep GHDL synthesis happy + sim_dump_test_synth: if not SIM generate + sim_dump_done <= '0'; + end generate; + end architecture behaviour; From 14c5cf3b8309f27d12199e296173b2169b19d1df Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:34:25 +1100 Subject: [PATCH 5/8] Fix some ghdlsynth issues with fpga_bram Use to_integer() instead of conv_integer(). Signed-off-by: Anton Blanchard --- fpga/main_bram.vhdl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fpga/main_bram.vhdl b/fpga/main_bram.vhdl index 810d60c..fcc3701 100644 --- a/fpga/main_bram.vhdl +++ b/fpga/main_bram.vhdl @@ -2,7 +2,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use std.textio.all; @@ -68,13 +67,13 @@ begin if we = '1' then for i in 0 to 7 loop if sel(i) = '1' then - memory(conv_integer(addr))((i + 1) * 8 - 1 downto i * 8) <= + memory(to_integer(unsigned(addr)))((i + 1) * 8 - 1 downto i * 8) <= di((i + 1) * 8 - 1 downto i * 8); end if; end loop; end if; if re = '1' then - obuf <= memory(conv_integer(addr)); + obuf <= memory(to_integer(unsigned(addr))); end if; do <= obuf; end if; From 3ad3e2abfd4b344af040657cfe511b050761b786 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:43:50 +1100 Subject: [PATCH 6/8] Removed unused core_terminated signal Right now it's unused. We can add it back when we add an LED to signify the core has terminated. Signed-off-by: Anton Blanchard --- soc.vhdl | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/soc.vhdl b/soc.vhdl index fb8a36d..9b45b5d 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -26,10 +26,7 @@ entity soc is -- UART0 signals: uart0_txd : out std_ulogic; - uart0_rxd : in std_ulogic; - - -- Misc (to use for things like LEDs) - core_terminated : out std_ulogic + uart0_rxd : in std_ulogic ); end entity soc; From dcee60a729be4a17bc618eb5ad621dce5ec9ee76 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 14:49:06 +1100 Subject: [PATCH 7/8] Fix a ghdlsynth issue in icache ghdlsynth doesn't like the debug statement, so wrap it in a generate. Signed-off-by: Anton Blanchard --- core.vhdl | 1 + icache.vhdl | 3 +++ 2 files changed, 4 insertions(+) diff --git a/core.vhdl b/core.vhdl index f4fe302..eb0b526 100644 --- a/core.vhdl +++ b/core.vhdl @@ -143,6 +143,7 @@ begin icache_0: entity work.icache generic map( + SIM => SIM, LINE_SIZE => 64, NUM_LINES => 32, NUM_WAYS => 2 diff --git a/icache.vhdl b/icache.vhdl index 20d5724..343c73a 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -29,6 +29,7 @@ use work.wishbone_types.all; entity icache is generic ( + SIM : boolean := false; -- Line size in bytes LINE_SIZE : positive := 64; -- Number of lines in a set @@ -264,6 +265,7 @@ begin assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS) report "geometry bits don't add up" severity FAILURE; + sim_debug: if SIM generate debug: process begin report "ROW_SIZE = " & natural'image(ROW_SIZE); @@ -280,6 +282,7 @@ begin report "WAY_BITS = " & natural'image(WAY_BITS); wait; end process; + end generate; -- Generate a cache RAM for each way rams: for i in 0 to NUM_WAYS-1 generate From f1d0382587d3771e2b9cd3caec381492e94e7ea1 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 11 Jan 2020 17:13:23 +1100 Subject: [PATCH 8/8] Fix a ghdlsynth issue in fast_spr_num I've submitted a bug report for this, but we can work around it easily for now. Signed-off-by: Anton Blanchard --- common.vhdl | 1 + 1 file changed, 1 insertion(+) diff --git a/common.vhdl b/common.vhdl index 8e24ab9..a27f4f2 100644 --- a/common.vhdl +++ b/common.vhdl @@ -346,6 +346,7 @@ package body common is when SPR_XER => n := 12; when others => + n := 0; return "000000"; end case; return "1" & std_ulogic_vector(to_unsigned(n, 5));