From 99dd4de54ec9839bf147402420b5be74a28d3455 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 19 Sep 2019 20:18:01 +1000 Subject: [PATCH] Don't use VHDL 2008 condition operator in multiply Signed-off-by: Anton Blanchard --- multiply.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/multiply.vhdl b/multiply.vhdl index 9aa4316..3e76b43 100644 --- a/multiply.vhdl +++ b/multiply.vhdl @@ -85,7 +85,7 @@ begin m_out.write_reg_data <= d2; m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg; - if v.multiply_pipeline(PIPELINE_DEPTH-1).valid then + if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then m_out.valid <= '1'; m_out.write_reg_enable <= '1';