From ac546a30243b7ffd7506daca7f05bd256000831b Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:26:35 +1000 Subject: [PATCH] litedram: Update yaml files Update the litedram yaml files based on latest upstream. Signed-off-by: Anton Blanchard --- litedram/gen-src/acorn-cle-215.yml | 8 +------- litedram/gen-src/arty.yml | 8 +------- litedram/gen-src/genesys2.yml | 15 +++++---------- litedram/gen-src/nexys-video.yml | 8 +------- litedram/gen-src/sim.yml | 9 +-------- 5 files changed, 9 insertions(+), 39 deletions(-) diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml index bce467b..0e3e9eb 100644 --- a/litedram/gen-src/acorn-cle-215.yml +++ b/litedram/gen-src/acorn-cle-215.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -2, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K512M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index 4472d56..22a0190 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml index 6cf8ac1..ac1deeb 100644 --- a/litedram/gen-src/genesys2.yml +++ b/litedram/gen-src/genesys2.yml @@ -3,8 +3,7 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -2, # FPGA speedgrade "memtype": "DDR3", # DRAM type @@ -13,12 +12,12 @@ "sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 4, # Number of byte groups "sdram_rank_nb": 1, # Number of ranks - "sdram_phy": K7DDRPHY, # Type of FPGA PHY + "sdram_phy": "K7DDRPHY", # Type of FPGA PHY # Electrical --------------------------------------------------------------- - "rtt_nom": "60ohm", # Nominal termination - "rtt_wr": "60ohm", # Write termination - "ron": "34ohm", # Output driver impedance + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance # Frequency ---------------------------------------------------------------- "input_clk_freq": 200e6, # Input clock frequency @@ -34,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 287f2f2..3752104 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml index 0160000..22a0190 100644 --- a/litedram/gen-src/sim.yml +++ b/litedram/gen-src/sim.yml @@ -3,14 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type - "sim" : "True", # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -36,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, }