From ace41e515363acc87ca91f3c3261a9c9a412b7ce Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 30 May 2022 14:34:21 +1000 Subject: [PATCH] ASIC: Reduce multiplier from 4 to 2 cycles Our sky130 gate level multiply/adder now makes timing with a single register stage. Signed-off-by: Anton Blanchard --- asic/behavioural/multiply_add_64x64.v | 8 +++----- asic/multiply.vhdl | 3 +-- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/asic/behavioural/multiply_add_64x64.v b/asic/behavioural/multiply_add_64x64.v index 303ed24..6bffb9a 100644 --- a/asic/behavioural/multiply_add_64x64.v +++ b/asic/behavioural/multiply_add_64x64.v @@ -12,13 +12,11 @@ module multiply_add_64x64 input [BITS*2-1:0] c, output [BITS*2-1:0] o ); - reg [BITS*2-1:0] o_tmp[2:0]; + reg [BITS*2-1:0] o_tmp; always @(posedge clk) begin - o_tmp[2] = o_tmp[1]; - o_tmp[1] = o_tmp[0]; - o_tmp[0] = (a * b) + c; + o_tmp = (a * b) + c; end - assign o = o_tmp[2]; + assign o = o_tmp; endmodule diff --git a/asic/multiply.vhdl b/asic/multiply.vhdl index a604554..c90aca8 100644 --- a/asic/multiply.vhdl +++ b/asic/multiply.vhdl @@ -5,10 +5,9 @@ use ieee.numeric_std.all; library work; use work.common.all; --- XXX We should be able to make timing with a 2 cycle multiplier entity multiply is generic ( - PIPELINE_DEPTH : natural := 4 + PIPELINE_DEPTH : natural := 2 ); port ( clk : in std_logic;