From ad6c6790f96bb3b94025e1ec368d727ee17d8642 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 13 Oct 2019 12:52:39 +1100 Subject: [PATCH] fifo: Remove shared variable The shared variable used for FIFO memory is not VHDL 2008 compliant. I can't see why it needs to be a shared variable since reads and writes update top and bottom synchronously, meaning they don't need same cycle access to the FIFO memory. Signed-off-by: Anton Blanchard --- fpga/pp_fifo.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/pp_fifo.vhd b/fpga/pp_fifo.vhd index 909c969..7447782 100644 --- a/fpga/pp_fifo.vhd +++ b/fpga/pp_fifo.vhd @@ -30,7 +30,7 @@ end entity pp_fifo; architecture behaviour of pp_fifo is type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); - shared variable memory : memory_array := (others => (others => '0')); + signal memory : memory_array := (others => (others => '0')); subtype index_type is integer range 0 to DEPTH - 1; signal top, bottom : index_type; @@ -64,7 +64,7 @@ begin top <= 0; else if push = '1' then - memory(top) := data_in; + memory(top) <= data_in; top <= (top + 1) mod DEPTH; end if; end if;