diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 5395ff6..15fa176 100644
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -20,6 +20,7 @@ entity toplevel is
         SPI_FLASH_OFFSET   : integer := 10485760;
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
+        LOG_LENGTH         : natural := 2048;
         UART_IS_16550      : boolean := true
 	);
     port(
@@ -128,6 +129,7 @@ begin
             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            LOG_LENGTH         => LOG_LENGTH,
             UART0_IS_16550     => UART_IS_16550
 	    )
 	port map (
diff --git a/microwatt.core b/microwatt.core
index 046020d..15786fe 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -118,7 +118,6 @@ targets:
       - disable_flatten_core
       - log_length=2048
       - uart_is_16550
-      - has_uart1
     tools:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : toplevel
@@ -135,7 +134,6 @@ targets:
       - spi_flash_offset=10485760
       - log_length=2048
       - uart_is_16550
-      - has_uart1
     tools:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
@@ -151,6 +149,7 @@ targets:
       - no_bram
       - spi_flash_offset=10485760
       - log_length=2048
+      - uart_is_16550
     generate: [litedram_nexys_video]
     tools:
       vivado: {part : xc7a200tsbg484-1}
@@ -240,7 +239,6 @@ targets:
       - disable_flatten_core
       - log_length=512
       - uart_is_16550
-      - has_uart1
     tools:
       vivado: {part : xc7a35tcpg236-1}
     toplevel : toplevel