From b5accb78b27c7cd8bfa4ec6dedf5d5c8069f8e5c Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 17 Mar 2022 18:03:29 +1100 Subject: [PATCH] wishbone_bram_wrapper ram_addr_bits is 1 bit off log2ceil() returns the number of bits required to store a value, so we need to pass in memory_size-1, not memory_size. Every other user of log2ceil() gets this right. Signed-off-by: Anton Blanchard --- wishbone_bram_wrapper.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index 182fd29..a45790f 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is end entity wishbone_bram_wrapper; architecture behaviour of wishbone_bram_wrapper is - constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3; + constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3; -- RAM interface signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);