From b5bccc4c13f5df5637011bc5d4f6f58fd9bee9b7 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Fri, 23 Aug 2019 13:17:35 +0200
Subject: [PATCH] Add dummy clock generator

---
 fpga/clk_gen_bypass.vhd | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 fpga/clk_gen_bypass.vhd

diff --git a/fpga/clk_gen_bypass.vhd b/fpga/clk_gen_bypass.vhd
new file mode 100644
index 0000000..2cc0226
--- /dev/null
+++ b/fpga/clk_gen_bypass.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clock_generator is
+  port (
+    clk        : in  std_logic;
+    resetn     : in  std_logic;
+    system_clk : out std_logic;
+    locked     : out std_logic);
+
+end entity clock_generator;
+
+architecture bypass of clock_generator is
+
+begin
+
+  locked <= not resetn;
+  system_clk <= clk;
+
+end architecture bypass;