From b47b71821e3142c71fc4550f6b22d3217ed1acfa Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 12 Jun 2022 22:15:11 +1000 Subject: [PATCH] loadstore1: reduce U state being output While these signals should only be read when valid is true, they are only a small number of bits and we want to reduce the amount of U/X state bouncing around the chip. Signed-off-by: Anton Blanchard --- loadstore1.vhdl | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/loadstore1.vhdl b/loadstore1.vhdl index 8fa39cf..6c4b0db 100644 --- a/loadstore1.vhdl +++ b/loadstore1.vhdl @@ -275,10 +275,27 @@ begin if rising_edge(clk) then if rst = '1' then r1.req.valid <= '0'; + r1.req.tlbie <= '0'; + r1.req.is_slbia <= '0'; + r1.req.instr_fault <= '0'; + r1.req.load <= '0'; + r1.req.priv_mode <= '0'; + r1.req.sprn <= (others => '0'); + r1.req.xerc <= xerc_init; + r2.req.valid <= '0'; + r2.req.tlbie <= '0'; + r2.req.is_slbia <= '0'; + r2.req.instr_fault <= '0'; + r2.req.load <= '0'; + r2.req.priv_mode <= '0'; + r2.req.sprn <= (others => '0'); + r2.req.xerc <= xerc_init; + r2.wait_dc <= '0'; r2.wait_mmu <= '0'; r2.one_cycle <= '0'; + r3.dar <= (others => '0'); r3.dsisr <= (others => '0'); r3.state <= IDLE;