From 3275304a7fde4201841b76ec970590fc0ba6f376 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 09:49:03 +1000 Subject: [PATCH 1/6] litedram: Remove variables.mak Instead of creating variables.mak, just pass the variables in on the make command line. Signed-off-by: Anton Blanchard --- litedram/gen-src/generate.py | 18 +++++++++--------- litedram/gen-src/sdram_init/Makefile | 1 - 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index eb677a8..2e13b0e 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -1,6 +1,5 @@ #!/usr/bin/python3 -from fusesoc.capi2.generator import Generator from litex.build.tools import write_to_file from litex.build.tools import replace_in_file from litex.build.generic_platform import * @@ -55,18 +54,19 @@ def build_init_code(build_dir, is_sim): def add_var(k, v): env_vars.append("{}={}\n".format(k, _makefile_escape(v))) - add_var("BUILD_DIR", sw_dir) - add_var("SRC_DIR", src_dir) - add_var("GENINC_DIR", sw_inc_dir) - add_var("LXSRC_DIR", lxbios_src_dir) + makefile = os.path.join(src_dir, "Makefile") + cmd = ["make", "-C", build_dir, "-f", makefile] + cmd.append("BUILD_DIR=%s" % sw_dir) + cmd.append("SRC_DIR=%s" % src_dir) + cmd.append("GENINC_DIR=%s" % sw_inc_dir) + cmd.append("LXSRC_DIR=%s" % lxbios_src_dir) + if is_sim: - add_var("EXTRA_CFLAGS", "-D__SIM__") - write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars)) + cmd.append("EXTRA_CFLAGS=%s" % "-D__SIM__") # Build init code print(" Generating init software...") - makefile = os.path.join(src_dir, "Makefile") - r = subprocess.check_call(["make", "-C", build_dir, "-I", gen_inc_dir, "-f", makefile]) + r = subprocess.check_call(cmd) print("Make result:", r) return os.path.join(sw_dir, "obj", "sdram_init.hex") diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 2e622d4..662cc26 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -1,6 +1,5 @@ #### Directories -include variables.mak OBJ = $(BUILD_DIR)/obj LXINC_DIR=$(LXSRC_DIR)/include From 6034a9e31ffdc287f3bddce13ea28b0e450b0547 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:24:38 +1000 Subject: [PATCH 2/6] litedram: simplify generate.py We can call litedram_gen instead of doing the work ourselves. Signed-off-by: Anton Blanchard --- litedram/gen-src/generate.py | 50 ++++-------------------------------- 1 file changed, 5 insertions(+), 45 deletions(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 2e13b0e..182c2d1 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -2,15 +2,9 @@ from litex.build.tools import write_to_file from litex.build.tools import replace_in_file -from litex.build.generic_platform import * -from litex.build.xilinx import XilinxPlatform -from litex.build.lattice import LatticePlatform -from litex.soc.integration.builder import * from litedram.gen import * import subprocess import os -import sys -import yaml import shutil def make_new_dir(base, added): @@ -27,9 +21,6 @@ gen_src_dir = os.path.join(base_dir, "gen-src") gen_dir = make_new_dir(base_dir, "generated") # Build the init code for microwatt-initialized DRAM -# -# XXX Not working yet -# def build_init_code(build_dir, is_sim): # More path fudging @@ -76,48 +67,17 @@ def generate_one(t): print("Generating target:", t) # Is it a simulation ? - is_sim = t is "sim" + is_sim = "sim" in t # Muck with directory path build_dir = make_new_dir(build_top_dir, t) t_dir = make_new_dir(gen_dir, t) - # Grab config file - cfile = os.path.join(gen_src_dir, t + ".yml") - core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader) - - ### TODO: Make most stuff below a function in litedram gen.py and - ### call it rather than duplicate it - ### - - # Convert YAML elements to Python/LiteX - for k, v in core_config.items(): - replaces = {"False": False, "True": True, "None": None} - for r in replaces.keys(): - if v == r: - core_config[k] = replaces[r] - if "clk_freq" in k: - core_config[k] = float(core_config[k]) - if k == "sdram_module": - core_config[k] = getattr(litedram_modules, core_config[k]) - if k == "sdram_phy": - core_config[k] = getattr(litedram_phys, core_config[k]) - - # Generate core + cmd = ["litedram_gen", "--output-dir=%s" % build_dir] if is_sim: - platform = SimPlatform("", io=[]) - elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: - platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") - elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: - platform = XilinxPlatform("", io=[], toolchain="vivado") - else: - raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - - soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000) - - # Build into build_dir - builder = Builder(soc, output_dir=build_dir, compile_gateware=False) - vns = builder.build(build_name="litedram_core", regular_comb=False) + cmd.append("--sim") + cmd.append("%s.yml" % t) + subprocess.check_call(cmd) # Grab generated gatewar dir gw_dir = os.path.join(build_dir, "gateware") From ac546a30243b7ffd7506daca7f05bd256000831b Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:26:35 +1000 Subject: [PATCH 3/6] litedram: Update yaml files Update the litedram yaml files based on latest upstream. Signed-off-by: Anton Blanchard --- litedram/gen-src/acorn-cle-215.yml | 8 +------- litedram/gen-src/arty.yml | 8 +------- litedram/gen-src/genesys2.yml | 15 +++++---------- litedram/gen-src/nexys-video.yml | 8 +------- litedram/gen-src/sim.yml | 9 +-------- 5 files changed, 9 insertions(+), 39 deletions(-) diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml index bce467b..0e3e9eb 100644 --- a/litedram/gen-src/acorn-cle-215.yml +++ b/litedram/gen-src/acorn-cle-215.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -2, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K512M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index 4472d56..22a0190 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml index 6cf8ac1..ac1deeb 100644 --- a/litedram/gen-src/genesys2.yml +++ b/litedram/gen-src/genesys2.yml @@ -3,8 +3,7 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -2, # FPGA speedgrade "memtype": "DDR3", # DRAM type @@ -13,12 +12,12 @@ "sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 4, # Number of byte groups "sdram_rank_nb": 1, # Number of ranks - "sdram_phy": K7DDRPHY, # Type of FPGA PHY + "sdram_phy": "K7DDRPHY", # Type of FPGA PHY # Electrical --------------------------------------------------------------- - "rtt_nom": "60ohm", # Nominal termination - "rtt_wr": "60ohm", # Write termination - "ron": "34ohm", # Output driver impedance + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance # Frequency ---------------------------------------------------------------- "input_clk_freq": 200e6, # Input clock frequency @@ -34,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 287f2f2..3752104 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -3,13 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -35,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml index 0160000..22a0190 100644 --- a/litedram/gen-src/sim.yml +++ b/litedram/gen-src/sim.yml @@ -3,14 +3,11 @@ { # General ------------------------------------------------------------------ - "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"standard", + "cpu": "None", # CPU type (ex vexriscv, serv, None) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type - "sim" : "True", # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) "cmd_latency": 0, # Command additional latency "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 2, # Number of byte groups @@ -36,8 +33,4 @@ "type": "native", }, }, - - # CSR Port ----------------------------------------------------------------- - "csr_alignment" : 32, - "csr_data_width" : 32, } From 346686feb8b094e1783aa105ce444d4e4cc6e0a1 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:29:48 +1000 Subject: [PATCH 4/6] litedram: Fix compiler warning define MAIN_RAM_BASE and MAIN_RAM_SIZE as unsigned long Signed-off-by: Anton Blanchard --- litedram/gen-src/generate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 182c2d1..a6018c6 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -35,7 +35,7 @@ def build_init_code(build_dir, is_sim): print(" lx src dir:", lxbios_src_dir) # Generate mem.h (hard wire size, it's not important) - mem_h = "#define MAIN_RAM_BASE 0x40000000\n#define MAIN_RAM_SIZE 0x10000000" + mem_h = "#define MAIN_RAM_BASE 0x40000000UL\n#define MAIN_RAM_SIZE 0x10000000UL\n" write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h) # Environment From 07f2edc4151f18f0496735b137ec8070606222ec Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:53:51 +1000 Subject: [PATCH 5/6] litedram: sdrinit() is now sdram_init() Signed-off-by: Anton Blanchard --- litedram/gen-src/sdram_init/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index 9ba4fd1..4917e30 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -286,7 +286,7 @@ uint64_t main(void) if (ftr & SYS_REG_INFO_HAS_DRAM) { printf("LiteDRAM built from Migen %s and LiteX %s\n", MIGEN_GIT_SHA1, LITEX_GIT_SHA1); - sdrinit(); + sdram_init(); } if (ftr & SYS_REG_INFO_HAS_BRAM) { printf("Booting from BRAM...\n"); From 780d6c754c8535de862b1e50dc23e1367116ef39 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 10:54:35 +1000 Subject: [PATCH 6/6] litedram: Regenerate from upstream litex Signed-off-by: Anton Blanchard --- .../acorn-cle-215/litedram_core.init | 2277 +- .../generated/acorn-cle-215/litedram_core.v | 19836 +++++++----- litedram/generated/arty/litedram_core.init | 2277 +- litedram/generated/arty/litedram_core.v | 20374 +++++++----- .../generated/genesys2/litedram_core.init | 2890 +- litedram/generated/genesys2/litedram_core.v | 26970 +++++++++------- .../generated/nexys-video/litedram_core.init | 2277 +- .../generated/nexys-video/litedram_core.v | 20364 +++++++----- litedram/generated/sim/litedram_core.init | 1585 +- litedram/generated/sim/litedram_core.v | 14706 +++++---- 10 files changed, 64321 insertions(+), 49235 deletions(-) diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init index 0f92f5b..af8cf09 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.init +++ b/litedram/generated/acorn-cle-215/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d8658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -518,79 +518,78 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842a9c4 -fbe1fff8fbc1fff0 -f821ff51f8010010 -f88100d83be10020 +7c0802a63842aec4 +f8010010fbe1fff8 +f88100d8f821ff51 38800080f8a100e0 -7c651b78f8c100e8 -f8e100f038c100d8 -f90100f87fe3fb78 +f8c100e87c651b78 +38c100d838610020 +f90100f8f8e100f0 f9410108f9210100 -6000000048001e99 -7fe3fb787c7e1b78 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a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v index 19b8d15..40d4f55 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.v +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:36:59 +// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:23 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -48,1806 +48,2039 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg [13:0] soc_litedramcore_adr = 14'd0; -reg soc_litedramcore_we = 1'd0; -wire [31:0] soc_litedramcore_dat_w; -wire [31:0] soc_litedramcore_dat_r; -wire [29:0] soc_litedramcore_wishbone_adr; -wire [31:0] soc_litedramcore_wishbone_dat_w; -wire [31:0] soc_litedramcore_wishbone_dat_r; -wire [3:0] soc_litedramcore_wishbone_sel; -wire soc_litedramcore_wishbone_cyc; -wire soc_litedramcore_wishbone_stb; -reg soc_litedramcore_wishbone_ack = 1'd0; -wire soc_litedramcore_wishbone_we; -wire [2:0] soc_litedramcore_wishbone_cti; -wire [1:0] soc_litedramcore_wishbone_bte; -reg soc_litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_reset; -wire soc_locked; -wire soc_clkin; -wire soc_clkout0; -wire soc_clkout_buf0; -wire soc_clkout1; -wire soc_clkout_buf1; -wire soc_clkout2; -wire soc_clkout_buf2; -wire soc_clkout3; -wire soc_clkout_buf3; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_a7ddrphy_wlevel_en_storage = 1'd0; -reg soc_a7ddrphy_wlevel_en_re = 1'd0; -wire soc_a7ddrphy_wlevel_strobe_re; -wire soc_a7ddrphy_wlevel_strobe_r; -wire soc_a7ddrphy_wlevel_strobe_we; -reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_a7ddrphy_cdly_rst_re; -wire soc_a7ddrphy_cdly_rst_r; -wire soc_a7ddrphy_cdly_rst_we; -reg soc_a7ddrphy_cdly_rst_w = 1'd0; -wire soc_a7ddrphy_cdly_inc_re; -wire soc_a7ddrphy_cdly_inc_r; -wire soc_a7ddrphy_cdly_inc_we; -reg soc_a7ddrphy_cdly_inc_w = 1'd0; -reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; -reg soc_a7ddrphy_dly_sel_re = 1'd0; -wire soc_a7ddrphy_rdly_dq_rst_re; -wire soc_a7ddrphy_rdly_dq_rst_r; -wire soc_a7ddrphy_rdly_dq_rst_we; -reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_inc_re; -wire soc_a7ddrphy_rdly_dq_inc_r; -wire soc_a7ddrphy_rdly_dq_inc_we; -reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_re; -wire soc_a7ddrphy_rdly_dq_bitslip_r; -wire soc_a7ddrphy_rdly_dq_bitslip_we; -reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire [15:0] soc_a7ddrphy_dfi_p0_address; -wire [2:0] soc_a7ddrphy_dfi_p0_bank; -wire soc_a7ddrphy_dfi_p0_cas_n; -wire soc_a7ddrphy_dfi_p0_cs_n; -wire soc_a7ddrphy_dfi_p0_ras_n; -wire soc_a7ddrphy_dfi_p0_we_n; -wire soc_a7ddrphy_dfi_p0_cke; -wire soc_a7ddrphy_dfi_p0_odt; -wire soc_a7ddrphy_dfi_p0_reset_n; -wire soc_a7ddrphy_dfi_p0_act_n; -wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; -wire soc_a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; -wire soc_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [15:0] soc_a7ddrphy_dfi_p1_address; -wire [2:0] soc_a7ddrphy_dfi_p1_bank; -wire soc_a7ddrphy_dfi_p1_cas_n; -wire soc_a7ddrphy_dfi_p1_cs_n; -wire soc_a7ddrphy_dfi_p1_ras_n; -wire soc_a7ddrphy_dfi_p1_we_n; -wire soc_a7ddrphy_dfi_p1_cke; -wire soc_a7ddrphy_dfi_p1_odt; -wire soc_a7ddrphy_dfi_p1_reset_n; -wire soc_a7ddrphy_dfi_p1_act_n; -wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; -wire soc_a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; -wire soc_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [15:0] soc_a7ddrphy_dfi_p2_address; -wire [2:0] soc_a7ddrphy_dfi_p2_bank; -wire soc_a7ddrphy_dfi_p2_cas_n; -wire soc_a7ddrphy_dfi_p2_cs_n; -wire soc_a7ddrphy_dfi_p2_ras_n; -wire soc_a7ddrphy_dfi_p2_we_n; -wire soc_a7ddrphy_dfi_p2_cke; -wire soc_a7ddrphy_dfi_p2_odt; -wire soc_a7ddrphy_dfi_p2_reset_n; -wire soc_a7ddrphy_dfi_p2_act_n; -wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; -wire soc_a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; -wire soc_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [15:0] soc_a7ddrphy_dfi_p3_address; -wire [2:0] soc_a7ddrphy_dfi_p3_bank; -wire soc_a7ddrphy_dfi_p3_cas_n; -wire soc_a7ddrphy_dfi_p3_cs_n; -wire soc_a7ddrphy_dfi_p3_ras_n; -wire soc_a7ddrphy_dfi_p3_we_n; -wire soc_a7ddrphy_dfi_p3_cke; -wire soc_a7ddrphy_dfi_p3_odt; -wire soc_a7ddrphy_dfi_p3_reset_n; -wire soc_a7ddrphy_dfi_p3_act_n; -wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; -wire soc_a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; -wire soc_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_a7ddrphy_sd_clk_se_nodelay; -reg soc_a7ddrphy_dqs_oe = 1'd0; -reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_a7ddrphy_dqspattern0; -wire soc_a7ddrphy_dqspattern1; -reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; -wire [1:0] soc_a7ddrphy_dqs_i; -wire [1:0] soc_a7ddrphy_dqs_i_delayed; -wire soc_a7ddrphy_dqs_o_no_delay0; -wire soc_a7ddrphy_dqs_t0; -wire soc_a7ddrphy0; -wire soc_a7ddrphy_dqs_o_no_delay1; -wire soc_a7ddrphy_dqs_t1; -wire soc_a7ddrphy1; -wire soc_a7ddrphy_dq_oe; -reg soc_a7ddrphy_dq_oe_delayed = 1'd0; -wire soc_a7ddrphy_dq_o_nodelay0; -wire soc_a7ddrphy_dq_i_nodelay0; -wire soc_a7ddrphy_dq_i_delayed0; -wire soc_a7ddrphy_dq_t0; -wire [7:0] soc_a7ddrphy_dq_i_data0; -wire [7:0] soc_a7ddrphy_bitslip0_i; -reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay1; -wire soc_a7ddrphy_dq_i_nodelay1; -wire soc_a7ddrphy_dq_i_delayed1; -wire soc_a7ddrphy_dq_t1; -wire [7:0] soc_a7ddrphy_dq_i_data1; -wire [7:0] soc_a7ddrphy_bitslip1_i; -reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay2; -wire soc_a7ddrphy_dq_i_nodelay2; -wire soc_a7ddrphy_dq_i_delayed2; -wire soc_a7ddrphy_dq_t2; -wire [7:0] soc_a7ddrphy_dq_i_data2; -wire [7:0] soc_a7ddrphy_bitslip2_i; -reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay3; -wire soc_a7ddrphy_dq_i_nodelay3; -wire soc_a7ddrphy_dq_i_delayed3; -wire soc_a7ddrphy_dq_t3; -wire [7:0] soc_a7ddrphy_dq_i_data3; -wire [7:0] soc_a7ddrphy_bitslip3_i; -reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay4; -wire soc_a7ddrphy_dq_i_nodelay4; -wire soc_a7ddrphy_dq_i_delayed4; -wire soc_a7ddrphy_dq_t4; -wire [7:0] soc_a7ddrphy_dq_i_data4; -wire [7:0] soc_a7ddrphy_bitslip4_i; -reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay5; -wire soc_a7ddrphy_dq_i_nodelay5; -wire soc_a7ddrphy_dq_i_delayed5; -wire soc_a7ddrphy_dq_t5; -wire [7:0] soc_a7ddrphy_dq_i_data5; -wire [7:0] soc_a7ddrphy_bitslip5_i; -reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay6; -wire soc_a7ddrphy_dq_i_nodelay6; -wire soc_a7ddrphy_dq_i_delayed6; -wire soc_a7ddrphy_dq_t6; -wire [7:0] soc_a7ddrphy_dq_i_data6; -wire [7:0] soc_a7ddrphy_bitslip6_i; -reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay7; -wire soc_a7ddrphy_dq_i_nodelay7; -wire soc_a7ddrphy_dq_i_delayed7; -wire soc_a7ddrphy_dq_t7; -wire [7:0] soc_a7ddrphy_dq_i_data7; -wire [7:0] soc_a7ddrphy_bitslip7_i; -reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay8; -wire soc_a7ddrphy_dq_i_nodelay8; -wire soc_a7ddrphy_dq_i_delayed8; -wire soc_a7ddrphy_dq_t8; -wire [7:0] soc_a7ddrphy_dq_i_data8; -wire [7:0] soc_a7ddrphy_bitslip8_i; -reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay9; -wire soc_a7ddrphy_dq_i_nodelay9; -wire soc_a7ddrphy_dq_i_delayed9; -wire soc_a7ddrphy_dq_t9; -wire [7:0] soc_a7ddrphy_dq_i_data9; -wire [7:0] soc_a7ddrphy_bitslip9_i; -reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay10; -wire soc_a7ddrphy_dq_i_nodelay10; -wire soc_a7ddrphy_dq_i_delayed10; -wire soc_a7ddrphy_dq_t10; -wire [7:0] soc_a7ddrphy_dq_i_data10; -wire [7:0] soc_a7ddrphy_bitslip10_i; -reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay11; -wire soc_a7ddrphy_dq_i_nodelay11; -wire soc_a7ddrphy_dq_i_delayed11; -wire soc_a7ddrphy_dq_t11; -wire [7:0] soc_a7ddrphy_dq_i_data11; -wire [7:0] soc_a7ddrphy_bitslip11_i; -reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay12; -wire soc_a7ddrphy_dq_i_nodelay12; -wire soc_a7ddrphy_dq_i_delayed12; -wire soc_a7ddrphy_dq_t12; -wire [7:0] soc_a7ddrphy_dq_i_data12; -wire [7:0] soc_a7ddrphy_bitslip12_i; -reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay13; -wire soc_a7ddrphy_dq_i_nodelay13; -wire soc_a7ddrphy_dq_i_delayed13; -wire soc_a7ddrphy_dq_t13; -wire [7:0] soc_a7ddrphy_dq_i_data13; -wire [7:0] soc_a7ddrphy_bitslip13_i; -reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay14; -wire soc_a7ddrphy_dq_i_nodelay14; -wire soc_a7ddrphy_dq_i_delayed14; -wire soc_a7ddrphy_dq_t14; -wire [7:0] soc_a7ddrphy_dq_i_data14; -wire [7:0] soc_a7ddrphy_bitslip14_i; -reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay15; -wire soc_a7ddrphy_dq_i_nodelay15; -wire soc_a7ddrphy_dq_i_delayed15; -wire soc_a7ddrphy_dq_t15; -wire [7:0] soc_a7ddrphy_dq_i_data15; -wire [7:0] soc_a7ddrphy_bitslip15_i; -reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0; -wire [7:0] soc_a7ddrphy_rddata_en; -reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_a7ddrphy_wrdata_en; -reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; -wire [15:0] soc_litedramcore_inti_p0_address; -wire [2:0] soc_litedramcore_inti_p0_bank; -reg soc_litedramcore_inti_p0_cas_n = 1'd1; -reg soc_litedramcore_inti_p0_cs_n = 1'd1; -reg soc_litedramcore_inti_p0_ras_n = 1'd1; -reg soc_litedramcore_inti_p0_we_n = 1'd1; -wire soc_litedramcore_inti_p0_cke; -wire soc_litedramcore_inti_p0_odt; -wire soc_litedramcore_inti_p0_reset_n; -reg soc_litedramcore_inti_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p0_wrdata; -wire soc_litedramcore_inti_p0_wrdata_en; -wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; -wire soc_litedramcore_inti_p0_rddata_en; -reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; -reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_inti_p1_address; -wire [2:0] soc_litedramcore_inti_p1_bank; -reg soc_litedramcore_inti_p1_cas_n = 1'd1; -reg soc_litedramcore_inti_p1_cs_n = 1'd1; -reg soc_litedramcore_inti_p1_ras_n = 1'd1; -reg soc_litedramcore_inti_p1_we_n = 1'd1; -wire soc_litedramcore_inti_p1_cke; -wire soc_litedramcore_inti_p1_odt; -wire soc_litedramcore_inti_p1_reset_n; -reg soc_litedramcore_inti_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p1_wrdata; -wire soc_litedramcore_inti_p1_wrdata_en; -wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; -wire soc_litedramcore_inti_p1_rddata_en; -reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; -reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_inti_p2_address; -wire [2:0] soc_litedramcore_inti_p2_bank; -reg soc_litedramcore_inti_p2_cas_n = 1'd1; -reg soc_litedramcore_inti_p2_cs_n = 1'd1; -reg soc_litedramcore_inti_p2_ras_n = 1'd1; -reg soc_litedramcore_inti_p2_we_n = 1'd1; -wire soc_litedramcore_inti_p2_cke; -wire soc_litedramcore_inti_p2_odt; -wire soc_litedramcore_inti_p2_reset_n; -reg soc_litedramcore_inti_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p2_wrdata; -wire soc_litedramcore_inti_p2_wrdata_en; -wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; -wire soc_litedramcore_inti_p2_rddata_en; -reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; -reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_inti_p3_address; -wire [2:0] soc_litedramcore_inti_p3_bank; -reg soc_litedramcore_inti_p3_cas_n = 1'd1; -reg soc_litedramcore_inti_p3_cs_n = 1'd1; -reg soc_litedramcore_inti_p3_ras_n = 1'd1; -reg soc_litedramcore_inti_p3_we_n = 1'd1; -wire soc_litedramcore_inti_p3_cke; -wire soc_litedramcore_inti_p3_odt; -wire soc_litedramcore_inti_p3_reset_n; -reg soc_litedramcore_inti_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p3_wrdata; -wire soc_litedramcore_inti_p3_wrdata_en; -wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; -wire soc_litedramcore_inti_p3_rddata_en; -reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; -reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [31:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [31:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [31:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [15:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [31:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [15:0] soc_litedramcore_master_p0_address = 16'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [15:0] soc_litedramcore_master_p1_address = 16'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [15:0] soc_litedramcore_master_p2_address = 16'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [15:0] soc_litedramcore_master_p3_address = 16'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_re; -wire soc_litedramcore_phaseinjector0_command_issue_r; -wire soc_litedramcore_phaseinjector0_command_issue_we; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [15:0] soc_litedramcore_phaseinjector0_address_storage = 16'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0; -wire soc_litedramcore_phaseinjector0_we; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_re; -wire soc_litedramcore_phaseinjector1_command_issue_r; -wire soc_litedramcore_phaseinjector1_command_issue_we; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [15:0] soc_litedramcore_phaseinjector1_address_storage = 16'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0; -wire soc_litedramcore_phaseinjector1_we; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_re; -wire soc_litedramcore_phaseinjector2_command_issue_r; -wire soc_litedramcore_phaseinjector2_command_issue_we; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [15:0] soc_litedramcore_phaseinjector2_address_storage = 16'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0; -wire soc_litedramcore_phaseinjector2_we; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_re; -wire soc_litedramcore_phaseinjector3_command_issue_r; -wire soc_litedramcore_phaseinjector3_command_issue_we; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [15:0] soc_litedramcore_phaseinjector3_address_storage = 16'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0; -wire soc_litedramcore_phaseinjector3_we; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [22:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [22:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [22:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [22:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [22:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [22:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [22:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [22:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; -wire [127:0] soc_litedramcore_interface_rdata; -reg [15:0] soc_litedramcore_dfi_p0_address = 16'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [15:0] soc_litedramcore_dfi_p1_address = 16'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [15:0] soc_litedramcore_dfi_p2_address = 16'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [15:0] soc_litedramcore_dfi_p3_address = 16'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [15:0] soc_litedramcore_cmd_payload_a = 16'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [6:0] soc_litedramcore_sequencer_counter = 7'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [22:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine0_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine0_row = 16'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [22:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine1_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine1_row = 16'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [22:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine2_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine2_row = 16'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [22:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine3_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine3_row = 16'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [22:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine4_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine4_row = 16'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [22:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine5_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine5_row = 16'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [22:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine6_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine6_row = 16'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [22:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [15:0] soc_litedramcore_bankmachine7_cmd_payload_a = 16'd0; -wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] soc_litedramcore_bankmachine7_row = 16'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; -wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [15:0] soc_litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; -wire soc_litedramcore_choose_cmd_cmd_payload_is_read; -wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; -wire [15:0] soc_litedramcore_choose_req_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_req_cmd_payload_is_cmd; -wire soc_litedramcore_choose_req_cmd_payload_is_read; -wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; -reg [15:0] soc_litedramcore_nop_a = 16'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; -wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; -wire [31:0] soc_wb_bus_dat_r; -wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; -wire soc_wb_bus_stb; -wire soc_wb_bus_ack; -wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [25:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [127:0] soc_user_port_wdata_payload_data; -wire [15:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [127:0] soc_user_port_rdata_payload_data; -reg vns_state = 1'd0; -reg vns_next_state = 1'd0; -wire vns_pll_fb; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire vns_roundrobin0_request; -wire vns_roundrobin0_grant; -wire vns_roundrobin0_ce; -wire vns_roundrobin1_request; -wire vns_roundrobin1_grant; -wire vns_roundrobin1_ce; -wire vns_roundrobin2_request; -wire vns_roundrobin2_grant; -wire vns_roundrobin2_ce; -wire vns_roundrobin3_request; -wire vns_roundrobin3_grant; -wire vns_roundrobin3_ce; -wire vns_roundrobin4_request; -wire vns_roundrobin4_grant; -wire vns_roundrobin4_ce; -wire vns_roundrobin5_request; -wire vns_roundrobin5_grant; -wire vns_roundrobin5_ce; -wire vns_roundrobin6_request; -wire vns_roundrobin6_grant; -wire vns_roundrobin6_ce; -wire vns_roundrobin7_request; -wire vns_roundrobin7_grant; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [31:0] vns_interface0_bank_bus_dat_w; -reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; -wire vns_csrbank0_init_done0_re; -wire vns_csrbank0_init_done0_r; -wire vns_csrbank0_init_done0_we; -wire vns_csrbank0_init_done0_w; -wire vns_csrbank0_init_error0_re; -wire vns_csrbank0_init_error0_r; -wire vns_csrbank0_init_error0_we; -wire vns_csrbank0_init_error0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [31:0] vns_interface1_bank_bus_dat_w; -reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; -wire vns_csrbank1_half_sys8x_taps0_re; -wire [4:0] vns_csrbank1_half_sys8x_taps0_r; -wire vns_csrbank1_half_sys8x_taps0_we; -wire [4:0] vns_csrbank1_half_sys8x_taps0_w; -wire vns_csrbank1_wlevel_en0_re; -wire vns_csrbank1_wlevel_en0_r; -wire vns_csrbank1_wlevel_en0_we; -wire vns_csrbank1_wlevel_en0_w; -wire vns_csrbank1_dly_sel0_re; -wire [1:0] vns_csrbank1_dly_sel0_r; -wire vns_csrbank1_dly_sel0_we; -wire [1:0] vns_csrbank1_dly_sel0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [31:0] vns_interface2_bank_bus_dat_w; -reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; -wire vns_csrbank2_dfii_control0_re; -wire [3:0] vns_csrbank2_dfii_control0_r; -wire vns_csrbank2_dfii_control0_we; -wire [3:0] vns_csrbank2_dfii_control0_w; -wire vns_csrbank2_dfii_pi0_command0_re; -wire [5:0] vns_csrbank2_dfii_pi0_command0_r; -wire vns_csrbank2_dfii_pi0_command0_we; -wire [5:0] vns_csrbank2_dfii_pi0_command0_w; -wire vns_csrbank2_dfii_pi0_address0_re; -wire [15:0] vns_csrbank2_dfii_pi0_address0_r; -wire vns_csrbank2_dfii_pi0_address0_we; -wire [15:0] vns_csrbank2_dfii_pi0_address0_w; -wire vns_csrbank2_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; -wire vns_csrbank2_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; -wire vns_csrbank2_dfii_pi0_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; -wire vns_csrbank2_dfii_pi0_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; -wire vns_csrbank2_dfii_pi0_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_r; -wire vns_csrbank2_dfii_pi0_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_w; -wire vns_csrbank2_dfii_pi1_command0_re; -wire [5:0] vns_csrbank2_dfii_pi1_command0_r; -wire vns_csrbank2_dfii_pi1_command0_we; -wire [5:0] vns_csrbank2_dfii_pi1_command0_w; -wire vns_csrbank2_dfii_pi1_address0_re; -wire [15:0] vns_csrbank2_dfii_pi1_address0_r; -wire vns_csrbank2_dfii_pi1_address0_we; -wire [15:0] vns_csrbank2_dfii_pi1_address0_w; -wire vns_csrbank2_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; -wire vns_csrbank2_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; -wire vns_csrbank2_dfii_pi1_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; -wire vns_csrbank2_dfii_pi1_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; -wire vns_csrbank2_dfii_pi1_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_r; -wire vns_csrbank2_dfii_pi1_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_w; -wire vns_csrbank2_dfii_pi2_command0_re; -wire [5:0] vns_csrbank2_dfii_pi2_command0_r; -wire vns_csrbank2_dfii_pi2_command0_we; -wire [5:0] vns_csrbank2_dfii_pi2_command0_w; -wire vns_csrbank2_dfii_pi2_address0_re; -wire [15:0] vns_csrbank2_dfii_pi2_address0_r; -wire vns_csrbank2_dfii_pi2_address0_we; -wire [15:0] vns_csrbank2_dfii_pi2_address0_w; -wire vns_csrbank2_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; -wire vns_csrbank2_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; -wire vns_csrbank2_dfii_pi2_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; -wire vns_csrbank2_dfii_pi2_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; -wire vns_csrbank2_dfii_pi2_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_r; -wire vns_csrbank2_dfii_pi2_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_w; -wire vns_csrbank2_dfii_pi3_command0_re; -wire [5:0] vns_csrbank2_dfii_pi3_command0_r; -wire vns_csrbank2_dfii_pi3_command0_we; -wire [5:0] vns_csrbank2_dfii_pi3_command0_w; -wire vns_csrbank2_dfii_pi3_address0_re; -wire [15:0] vns_csrbank2_dfii_pi3_address0_r; -wire vns_csrbank2_dfii_pi3_address0_we; -wire [15:0] vns_csrbank2_dfii_pi3_address0_w; -wire vns_csrbank2_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; -wire vns_csrbank2_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; -wire vns_csrbank2_dfii_pi3_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; -wire vns_csrbank2_dfii_pi3_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; -wire vns_csrbank2_dfii_pi3_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_r; -wire vns_csrbank2_dfii_pi3_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_w; -wire vns_csrbank2_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [31:0] vns_dat_w; -wire [31:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [15:0] vns_rhs_array_muxed1 = 16'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [15:0] vns_rhs_array_muxed7 = 16'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [22:0] vns_rhs_array_muxed12 = 23'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [22:0] vns_rhs_array_muxed15 = 23'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [22:0] vns_rhs_array_muxed18 = 23'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [22:0] vns_rhs_array_muxed21 = 23'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [22:0] vns_rhs_array_muxed24 = 23'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [22:0] vns_rhs_array_muxed27 = 23'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [22:0] vns_rhs_array_muxed30 = 23'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [22:0] vns_rhs_array_muxed33 = 23'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [15:0] vns_array_muxed1 = 16'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [15:0] vns_array_muxed8 = 16'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [15:0] vns_array_muxed15 = 16'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [15:0] vns_array_muxed22 = 16'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl3_expr; +wire main_reset; +reg main_power_down = 1'd0; +wire main_locked; +wire main_clkin; +wire main_clkout0; +wire main_clkout_buf0; +wire main_clkout1; +wire main_clkout_buf1; +wire main_clkout2; +wire main_clkout_buf2; +wire main_clkout3; +wire main_clkout_buf3; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; +wire [15:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_ras_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_act_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire [15:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_ras_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_act_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire [15:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_ras_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_act_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire [15:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_ras_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_act_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +wire main_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_sd_clk_se_nodelay; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_t0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +wire main_a7ddrphy0; +wire main_a7ddrphy_dqs_o_no_delay1; +wire main_a7ddrphy_dqs_t1; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_t0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_t1; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_t2; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_t3; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_t4; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_t5; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_t6; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_t7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_t8; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_t9; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_t10; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_t11; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_t12; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_t13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_t14; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_t15; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [15:0] main_litedramcore_inti_p0_address; +wire [2:0] main_litedramcore_inti_p0_bank; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; +wire main_litedramcore_inti_p0_cke; +wire main_litedramcore_inti_p0_odt; +wire main_litedramcore_inti_p0_reset_n; +reg main_litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p0_wrdata; +wire main_litedramcore_inti_p0_wrdata_en; +wire [3:0] main_litedramcore_inti_p0_wrdata_mask; +wire main_litedramcore_inti_p0_rddata_en; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_inti_p1_address; +wire [2:0] main_litedramcore_inti_p1_bank; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; +wire main_litedramcore_inti_p1_cke; +wire main_litedramcore_inti_p1_odt; +wire main_litedramcore_inti_p1_reset_n; +reg main_litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p1_wrdata; +wire main_litedramcore_inti_p1_wrdata_en; +wire [3:0] main_litedramcore_inti_p1_wrdata_mask; +wire main_litedramcore_inti_p1_rddata_en; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_inti_p2_address; +wire [2:0] main_litedramcore_inti_p2_bank; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; +wire main_litedramcore_inti_p2_cke; +wire main_litedramcore_inti_p2_odt; +wire main_litedramcore_inti_p2_reset_n; +reg main_litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p2_wrdata; +wire main_litedramcore_inti_p2_wrdata_en; +wire [3:0] main_litedramcore_inti_p2_wrdata_mask; +wire main_litedramcore_inti_p2_rddata_en; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_inti_p3_address; +wire [2:0] main_litedramcore_inti_p3_bank; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; +wire main_litedramcore_inti_p3_cke; +wire main_litedramcore_inti_p3_odt; +wire main_litedramcore_inti_p3_reset_n; +reg main_litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p3_wrdata; +wire main_litedramcore_inti_p3_wrdata_en; +wire [3:0] main_litedramcore_inti_p3_wrdata_mask; +wire main_litedramcore_inti_p3_rddata_en; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_ras_n; +wire main_litedramcore_slave_p0_we_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_act_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p0_rddata_en; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_ras_n; +wire main_litedramcore_slave_p1_we_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_act_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p1_rddata_en; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_ras_n; +wire main_litedramcore_slave_p2_we_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_act_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p2_rddata_en; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [15:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_ras_n; +wire main_litedramcore_slave_p3_we_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_act_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +wire main_litedramcore_slave_p3_rddata_en; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [15:0] main_litedramcore_master_p0_address = 16'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p0_rddata; +wire main_litedramcore_master_p0_rddata_valid; +reg [15:0] main_litedramcore_master_p1_address = 16'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p1_rddata; +wire main_litedramcore_master_p1_rddata_valid; +reg [15:0] main_litedramcore_master_p2_address = 16'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p2_rddata; +wire main_litedramcore_master_p2_rddata_valid; +reg [15:0] main_litedramcore_master_p3_address = 16'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p3_rddata; +wire main_litedramcore_master_p3_rddata_valid; +wire main_litedramcore_sel; +wire main_litedramcore_cke; +wire main_litedramcore_odt; +wire main_litedramcore_reset_n; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_we; +wire [22:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_we; +wire [22:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_we; +wire [22:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_we; +wire [22:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_we; +wire [22:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_we; +wire [22:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_we; +wire [22:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_we; +wire [22:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_rdata_valid; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] main_litedramcore_interface_rdata; +reg [15:0] main_litedramcore_dfi_p0_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +wire main_litedramcore_dfi_p0_odt; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p0_rddata; +wire main_litedramcore_dfi_p0_rddata_valid; +reg [15:0] main_litedramcore_dfi_p1_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +wire main_litedramcore_dfi_p1_odt; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p1_rddata; +wire main_litedramcore_dfi_p1_rddata_valid; +reg [15:0] main_litedramcore_dfi_p2_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +wire main_litedramcore_dfi_p2_odt; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p2_rddata; +wire main_litedramcore_dfi_p2_rddata_valid; +reg [15:0] main_litedramcore_dfi_p3_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +wire main_litedramcore_dfi_p3_odt; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p3_rddata; +wire main_litedramcore_dfi_p3_rddata_valid; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [15:0] main_litedramcore_cmd_payload_a = 16'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_timer_wait; +wire main_litedramcore_timer_done0; +wire [9:0] main_litedramcore_timer_count0; +wire main_litedramcore_timer_done1; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_done0; +wire main_litedramcore_sequencer_start1; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [6:0] main_litedramcore_sequencer_counter = 7'd0; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_zqcs_timer_wait; +wire main_litedramcore_zqcs_timer_done0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +wire main_litedramcore_zqcs_timer_done1; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +wire main_litedramcore_bankmachine0_req_valid; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_we; +wire [22:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine0_row = 16'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +wire main_litedramcore_bankmachine1_req_valid; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_we; +wire [22:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine1_row = 16'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +wire main_litedramcore_bankmachine2_req_valid; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_we; +wire [22:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine2_row = 16'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +wire main_litedramcore_bankmachine3_req_valid; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_we; +wire [22:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine3_row = 16'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +wire main_litedramcore_bankmachine4_req_valid; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_we; +wire [22:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine4_row = 16'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +wire main_litedramcore_bankmachine5_req_valid; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_we; +wire [22:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine5_row = 16'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +wire main_litedramcore_bankmachine6_req_valid; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_we; +wire [22:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine6_row = 16'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +wire main_litedramcore_bankmachine7_req_valid; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_we; +wire [22:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine7_row = 16'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +wire main_litedramcore_ras_allowed; +wire main_litedramcore_cas_allowed; +wire [1:0] main_litedramcore_rdcmdphase; +wire [1:0] main_litedramcore_wrcmdphase; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [15:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire main_litedramcore_choose_cmd_ce; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire [15:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire main_litedramcore_choose_req_ce; +reg [15:0] main_litedramcore_nop_a = 16'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +wire main_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; +wire main_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] main_litedramcore_tfawcon_count; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +wire main_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; +wire main_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_write_available; +reg main_litedramcore_en0 = 1'd0; +wire main_litedramcore_max_time0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; +wire main_litedramcore_max_time1; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire main_litedramcore_go_to_refresh; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; +wire [29:0] main_wb_bus_adr; +wire [31:0] main_wb_bus_dat_w; +wire [31:0] main_wb_bus_dat_r; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_cyc; +wire main_wb_bus_stb; +wire main_wb_bus_ack; +wire main_wb_bus_we; +wire [2:0] main_wb_bus_cti; +wire [1:0] main_wb_bus_bte; +wire main_wb_bus_err; +wire main_user_port_cmd_valid; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_payload_we; +wire [25:0] main_user_port_cmd_payload_addr; +wire main_user_port_wdata_valid; +wire main_user_port_wdata_ready; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_rdata_valid; +wire main_user_port_rdata_ready; +wire [127:0] main_user_port_rdata_payload_data; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +wire builder_pll_fb; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +wire builder_roundrobin0_request; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_ce; +wire builder_roundrobin1_request; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_ce; +wire builder_roundrobin2_request; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_ce; +wire builder_roundrobin3_request; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_ce; +wire builder_roundrobin4_request; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_ce; +wire builder_roundrobin5_request; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_ce; +wire builder_roundrobin6_request; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_ce; +wire builder_roundrobin7_request; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_ce; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [7:0] builder_litedramcore_dat_w = 8'd0; +wire [7:0] builder_litedramcore_dat_r; +wire [29:0] builder_litedramcore_wishbone_adr; +wire [31:0] builder_litedramcore_wishbone_dat_w; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] builder_litedramcore_wishbone_sel; +wire builder_litedramcore_wishbone_cyc; +wire builder_litedramcore_wishbone_stb; +reg builder_litedramcore_wishbone_ack = 1'd0; +wire builder_litedramcore_wishbone_we; +wire [2:0] builder_litedramcore_wishbone_cti; +wire [1:0] builder_litedramcore_wishbone_bte; +reg builder_litedramcore_wishbone_err = 1'd0; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [7:0] builder_interface0_bank_bus_dat_w; +reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_init_error0_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [7:0] builder_interface1_bank_bus_dat_w; +reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [7:0] builder_interface2_bank_bus_dat_w; +reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address1_r; +reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address1_w; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; +reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; +reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; +reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; +reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; +reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; +reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address1_r; +reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address1_w; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; +reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; +reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; +reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; +reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; +reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; +reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address1_r; +reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address1_w; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; +reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; +reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; +reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; +reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; +reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; +reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address1_r; +reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address1_w; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; +reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; +reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; +reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; +reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; +reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; +reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +wire builder_csrbank2_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [7:0] builder_csr_interconnect_dat_w; +wire [7:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [15:0] builder_rhs_array_muxed1 = 16'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [15:0] builder_rhs_array_muxed7 = 16'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [22:0] builder_rhs_array_muxed12 = 23'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [22:0] builder_rhs_array_muxed15 = 23'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [22:0] builder_rhs_array_muxed18 = 23'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [22:0] builder_rhs_array_muxed21 = 23'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [22:0] builder_rhs_array_muxed24 = 23'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [22:0] builder_rhs_array_muxed27 = 23'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [22:0] builder_rhs_array_muxed30 = 23'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [22:0] builder_rhs_array_muxed33 = 23'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [15:0] builder_array_muxed1 = 16'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [15:0] builder_array_muxed8 = 16'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [15:0] builder_array_muxed15 = 16'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [15:0] builder_array_muxed22 = 16'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl3; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; -assign soc_wb_bus_adr = wb_ctrl_adr; -assign soc_wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = soc_wb_bus_dat_r; -assign soc_wb_bus_sel = wb_ctrl_sel; -assign soc_wb_bus_cyc = wb_ctrl_cyc; -assign soc_wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = soc_wb_bus_ack; -assign soc_wb_bus_we = wb_ctrl_we; -assign soc_wb_bus_cti = wb_ctrl_cti; -assign soc_wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = soc_wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; -assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; -assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; -assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; -assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; -assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; +assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; +assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign main_reset = rst; +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - vns_next_state <= 1'd0; - vns_next_state <= vns_state; - case (vns_state) - 1'd1: begin - vns_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - vns_next_state <= 1'd1; - end - end - endcase + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on @@ -1857,16 +2090,39 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_adr <= 14'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; - end - end - endcase + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on @@ -1876,14 +2132,39 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_wishbone_ack <= 1'd0; - case (vns_state) - 1'd1: begin - soc_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -1893,108 +2174,84 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_we <= 1'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); - end - end - endcase + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end -assign soc_reset = rst; -assign pll_locked = soc_locked; -assign soc_clkin = clk; -assign iodelay_clk = soc_clkout_buf0; -assign sys_clk = soc_clkout_buf1; -assign sys4x_clk = soc_clkout_buf2; -assign sys4x_dqs_clk = soc_clkout_buf3; -assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p0_rddata <= 32'd0; - soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; - soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; - soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; - soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; - soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; - soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; - soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; - soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; - soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; - soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; - soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; - soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; - soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; - soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; - soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; - soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; - soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; - soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; - soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; - soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; - soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; - soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; - soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; - soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; - soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; - soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; - soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; - soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; - soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; - soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; - soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; - soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end // synthesis translate_off dummy_d_4 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); // synthesis translate_off reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p1_rddata <= 32'd0; - soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; - soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; - soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; - soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; - soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; - soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; - soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; - soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; - soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; - soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; - soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; - soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; - soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; - soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; - soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; - soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; - soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; - soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; - soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; - soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; - soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; - soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; - soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; - soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; - soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; - soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; - soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; - soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; - soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; - soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; - soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; - soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end // synthesis translate_off dummy_d_5 = dummy_s; // synthesis translate_on @@ -2004,39 +2261,33 @@ end reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p2_rddata <= 32'd0; - soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; - soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; - soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; - soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; - soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; - soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; - soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; - soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; - soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; - soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; - soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; - soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; - soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; - soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; - soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; - soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; - soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; - soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; - soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; - soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; - soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; - soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; - soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; - soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; - soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; - soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; - soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; - soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; - soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; - soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; - soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; - soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) + 1'd0: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_6 = dummy_s; // synthesis translate_on @@ -2046,97 +2297,105 @@ end reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p3_rddata <= 32'd0; - soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; - soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; - soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; - soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; - soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; - soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; - soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; - soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; - soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; - soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; - soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; - soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; - soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; - soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; - soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; - soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; - soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; - soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; - soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; - soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; - soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; - soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; - soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; - soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; - soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; - soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; - soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; - soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; - soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; - soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; - soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; - soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) + 1'd0: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_7 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; -assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; -assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; -assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; -assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; -assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; -assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; -assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; -assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; -assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; -assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; -assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; -assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; -assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; -assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; -assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; -assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; -assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqs_oe <= 1'd0; - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqs_oe <= 1'd1; - end else begin - soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; - end + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) + 1'd0: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_8 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); -assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); // synthesis translate_off reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqspattern_o0 <= 8'd0; - soc_a7ddrphy_dqspattern_o0 <= 7'd85; - if (soc_a7ddrphy_dqspattern0) begin - soc_a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (soc_a7ddrphy_dqspattern1) begin - soc_a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd0; - if (soc_a7ddrphy_wlevel_strobe_re) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd1; + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) + 1'd0: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end - end + 1'd1: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_9 = dummy_s; // synthesis translate_on @@ -2146,55 +2405,31 @@ end reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip0_o <= 8'd0; - case (soc_a7ddrphy_bitslip0_value) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase // synthesis translate_off @@ -2206,55 +2441,31 @@ end reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip1_o <= 8'd0; - case (soc_a7ddrphy_bitslip1_value) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase // synthesis translate_off @@ -2266,55 +2477,31 @@ end reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip2_o <= 8'd0; - case (soc_a7ddrphy_bitslip2_value) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase // synthesis translate_off @@ -2326,55 +2513,31 @@ end reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip3_o <= 8'd0; - case (soc_a7ddrphy_bitslip3_value) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase // synthesis translate_off @@ -2386,55 +2549,31 @@ end reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip4_o <= 8'd0; - case (soc_a7ddrphy_bitslip4_value) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase // synthesis translate_off @@ -2446,55 +2585,31 @@ end reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip5_o <= 8'd0; - case (soc_a7ddrphy_bitslip5_value) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase // synthesis translate_off @@ -2506,55 +2621,31 @@ end reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip6_o <= 8'd0; - case (soc_a7ddrphy_bitslip6_value) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase // synthesis translate_off @@ -2566,55 +2657,31 @@ end reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip7_o <= 8'd0; - case (soc_a7ddrphy_bitslip7_value) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase // synthesis translate_off @@ -2626,55 +2693,31 @@ end reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip8_o <= 8'd0; - case (soc_a7ddrphy_bitslip8_value) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase // synthesis translate_off @@ -2686,55 +2729,31 @@ end reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip9_o <= 8'd0; - case (soc_a7ddrphy_bitslip9_value) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase // synthesis translate_off @@ -2746,55 +2765,31 @@ end reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip10_o <= 8'd0; - case (soc_a7ddrphy_bitslip10_value) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase // synthesis translate_off @@ -2806,55 +2801,31 @@ end reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip11_o <= 8'd0; - case (soc_a7ddrphy_bitslip11_value) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase // synthesis translate_off @@ -2866,55 +2837,31 @@ end reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip12_o <= 8'd0; - case (soc_a7ddrphy_bitslip12_value) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase // synthesis translate_off @@ -2926,55 +2873,31 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip13_o <= 8'd0; - case (soc_a7ddrphy_bitslip13_value) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase // synthesis translate_off @@ -2986,55 +2909,31 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip14_o <= 8'd0; - case (soc_a7ddrphy_bitslip14_value) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase // synthesis translate_off @@ -3046,200 +2945,69 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip15_o <= 8'd0; - case (soc_a7ddrphy_bitslip15_value) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase // synthesis translate_off dummy_d_25 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; -assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; -assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; -assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; -assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; -assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; -assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; -assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; -assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; -assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; -assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; -assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; -assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; -assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; -assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; -assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; -assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; -assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; -assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; -assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; -assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; -assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; -assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; -assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; -assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; -assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; -assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; -assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; -assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; -assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; -assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; -assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; -assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; -assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; -assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; -assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; -assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; -assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; -assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; -assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; -assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; -assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; -assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; -assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; -assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; -assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; -assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; -assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; -assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; -assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; -assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; -assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; -assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; -assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; -assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; -assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; -assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; -assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; -assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; -assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; -assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; -assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; -assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; -assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; -assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; -assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; -assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; -assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; -assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; -assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; -assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; -assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; -assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; -assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; -assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; -assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; -assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; -assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; -assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; -assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; -assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; -assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; -assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; -assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; -assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; -assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; -assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; -assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; -assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; -assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; -assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; -assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; -assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; -assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; -assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; -assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; -assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; -assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; -assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; -assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; -assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; -assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; -assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; -assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; -assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; -assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; -assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; -assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; -assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; -assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; -assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; -assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; -assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; -assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; -assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; -assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; -assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; -assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; -assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; -assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; -assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; -assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; -assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; -assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; -assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; -assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; -assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; -assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; - end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; - end + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) + 1'd0: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_26 = dummy_s; // synthesis translate_on @@ -3249,12 +3017,33 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; - end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; - end + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) + 1'd0: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_27 = dummy_s; // synthesis translate_on @@ -3264,12 +3053,33 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; - end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; - end + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) + 1'd0: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_28 = dummy_s; // synthesis translate_on @@ -3279,12 +3089,33 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; - end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; - end + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) + 1'd0: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_29 = dummy_s; // synthesis translate_on @@ -3294,12 +3125,33 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; - end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; - end + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) + 1'd0: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_30 = dummy_s; // synthesis translate_on @@ -3309,11 +3161,33 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; - end + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) + 1'd0: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_31 = dummy_s; // synthesis translate_on @@ -3323,12 +3197,33 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; - end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; - end + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) + 1'd0: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_32 = dummy_s; // synthesis translate_on @@ -3338,11 +3233,33 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; - end + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) + 1'd0: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_33 = dummy_s; // synthesis translate_on @@ -3352,12 +3269,33 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; - end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; - end + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) + 1'd0: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_34 = dummy_s; // synthesis translate_on @@ -3367,12 +3305,33 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; - end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; - end + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) + 1'd0: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_35 = dummy_s; // synthesis translate_on @@ -3382,12 +3341,33 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_address <= 16'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; - end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; - end + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) + 1'd0: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_36 = dummy_s; // synthesis translate_on @@ -3397,12 +3377,33 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; - end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; - end + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) + 1'd0: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_37 = dummy_s; // synthesis translate_on @@ -3412,27 +3413,69 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; - end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; - end -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on -end - + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) + 1'd0: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; + end + endcase +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + // synthesis translate_off reg dummy_d_39; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; - end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; - end + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) + 1'd0: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_39 = dummy_s; // synthesis translate_on @@ -3442,12 +3485,33 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; - end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; - end + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) + 1'd0: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_40 = dummy_s; // synthesis translate_on @@ -3457,25 +3521,175 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; - end else begin - end + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) + 1'd0: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_41 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_42; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3486,10 +3700,11 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end else begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3500,11 +3715,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + main_litedramcore_master_p3_address <= 16'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3515,11 +3730,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3530,11 +3745,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3545,11 +3760,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3560,11 +3775,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; + main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3575,10 +3790,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin - soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3589,11 +3804,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3604,10 +3819,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3618,11 +3833,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3633,11 +3848,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3648,11 +3863,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_address <= 16'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3663,11 +3878,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3678,11 +3893,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; + main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3693,11 +3908,10 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + main_litedramcore_inti_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3708,11 +3922,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3723,10 +3937,10 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3737,11 +3951,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3752,10 +3966,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3766,11 +3981,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + main_litedramcore_master_p0_address <= 16'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3781,11 +3996,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3796,11 +4011,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3811,11 +4026,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3826,11 +4041,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3841,10 +4056,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin - soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3855,11 +4070,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3870,10 +4085,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin - soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3884,11 +4099,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3899,11 +4114,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3914,11 +4129,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_address <= 16'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; + main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3929,11 +4144,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; + main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3944,11 +4159,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; + main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3959,10 +4174,10 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + main_litedramcore_inti_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3973,11 +4188,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3988,10 +4203,10 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + main_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -4002,11 +4217,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -4017,10 +4232,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end else begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -4031,11 +4247,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + main_litedramcore_master_p1_address <= 16'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -4046,11 +4262,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -4061,11 +4277,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -4076,10 +4292,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; end else begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -4090,11 +4307,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -4105,11 +4322,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -4120,11 +4336,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -4135,10 +4351,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin - soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -4149,11 +4365,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -4164,10 +4380,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end else begin - soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -4178,11 +4395,10 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -4193,11 +4409,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -4208,11 +4424,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_address <= 16'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -4223,11 +4439,11 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; + main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4238,11 +4454,10 @@ end reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + main_litedramcore_inti_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -4253,11 +4468,11 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -4268,11 +4483,10 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + main_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; + main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -4283,38 +4497,26 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; // synthesis translate_off reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end else begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4325,11 +4527,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + main_litedramcore_master_p2_address <= 16'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end else begin - soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4340,11 +4542,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end else begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4355,32 +4557,25 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_101 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; -assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; -assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); -assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); -assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; -assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + main_litedramcore_inti_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4391,11 +4586,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; end else begin - soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4406,11 +4601,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; + main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4421,32 +4616,25 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin - soc_litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; -assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; -assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); -assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); -assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; -assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4457,11 +4645,10 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4472,11 +4659,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; + main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4487,32 +4674,26 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end else begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_109 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; -assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; -assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); -assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); -assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; -assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4523,11 +4704,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4538,11 +4719,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4553,126 +4734,39 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; -assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; -assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); -assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); -assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; -assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; -assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; -assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; -assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; -assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; -assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; -assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; -assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; -assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; -assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; -assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; -assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; -assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; -assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; -assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; -assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; -assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; -assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; -assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; -assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; -assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; -assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; -assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; -assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; -assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; -assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; -assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; -assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; -assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; -assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; -assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; -assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; -assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; -assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; -assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; -assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; -assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; -assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; -assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; -assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; -assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; -assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; -assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; -assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; -assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; -assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; -assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; -assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; -assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; -assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; -assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; -assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; -assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; -assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; -assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; -assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; -assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; -assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); -assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; -assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; -assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; -assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); -assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); -assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; -assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; -assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); -assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); -assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); -assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; -assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; +assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p2_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p3_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p0_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p1_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p2_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p3_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; // synthesis translate_off reg dummy_d_114; // synthesis translate_on always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (soc_litedramcore_wants_refresh) begin - vns_refresher_next_state <= 1'd1; - end - end - end - endcase + main_litedramcore_inti_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); + end else begin + main_litedramcore_inti_p0_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_114 = dummy_s; // synthesis translate_on @@ -4682,29 +4776,12 @@ end reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; + end // synthesis translate_off dummy_d_115 = dummy_s; // synthesis translate_on @@ -4714,23 +4791,12 @@ end reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + end else begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_116 = dummy_s; // synthesis translate_on @@ -4740,204 +4806,99 @@ end reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase + main_litedramcore_inti_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]); +assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); +assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); + end else begin + main_litedramcore_inti_p1_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_118 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; -assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); -assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); end else begin - soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_119 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); -assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); -assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); - end + main_litedramcore_inti_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); + end else begin + main_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_120 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_inti_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_121 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); +assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]); +assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); +assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_122; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end - end else begin - vns_bankmachine0_next_state <= 1'd1; - end - end else begin - vns_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_122 = dummy_s; // synthesis translate_on @@ -4947,42 +4908,12 @@ end reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end // synthesis translate_off dummy_d_123 = dummy_s; // synthesis translate_on @@ -4992,30 +4923,12 @@ end reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); + end else begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_124 = dummy_s; // synthesis translate_on @@ -5025,177 +4938,478 @@ end reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin + main_litedramcore_inti_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]); +assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); +assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + end else begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + end else begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]); +assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]); +assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end end - 3'd7: begin + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; + end else begin + builder_refresher_next_state <= 1'd0; + end + end end - 4'd8: begin + 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; + end end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end + if (1'd1) begin + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end end end - 3'd4: begin + 2'd3: begin end - 3'd5: begin + default: begin end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) + 1'd1: begin end - 3'd7: begin + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end - 4'd8: begin + 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_133; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin + default: begin end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) + 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end - 3'd7: begin + 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end - 4'd8: begin + 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_128; +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_138; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; + end end else begin + builder_bankmachine0_next_state <= 1'd1; end end else begin + builder_bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5209,24 +5423,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5239,15 +5456,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -5257,30 +5471,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5294,16 +5504,49 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_142; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_142 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5321,14 +5564,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5339,16 +5582,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5366,15 +5609,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5384,23 +5624,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5417,17 +5660,20 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5444,13 +5690,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5462,171 +5708,131 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; -assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); -assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_136; +reg dummy_d_147; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; - end else begin - soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); -assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); -assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin end - end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_138; +reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_139; +reg dummy_d_149; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5644,14 +5850,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5662,16 +5868,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5679,9 +5885,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5692,74 +5895,232 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_142; +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_155; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; + end end else begin + builder_bankmachine1_next_state <= 1'd1; end end else begin + builder_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_156; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_156 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5773,26 +6134,38 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5809,26 +6182,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5842,16 +6215,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5869,12 +6242,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5884,26 +6257,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5920,19 +6293,19 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -5950,13 +6323,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5968,30 +6341,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6005,23 +6374,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6032,34 +6408,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6077,14 +6438,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -6095,16 +6456,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_166; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6122,14 +6483,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6140,171 +6501,61 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; - end else begin - soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); -assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_156; +reg dummy_d_167; // synthesis translate_on always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin end end else begin - vns_bankmachine2_next_state <= 1'd1; end end else begin - vns_bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6322,14 +6573,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6340,62 +6591,181 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_158; +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end + end end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; + end + end else begin + builder_bankmachine2_next_state <= 1'd1; + end + end else begin + builder_bankmachine2_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6406,38 +6776,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6451,29 +6812,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6487,26 +6860,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6520,16 +6893,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6547,12 +6920,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6562,26 +6935,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6598,19 +6971,19 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6628,13 +7001,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6646,30 +7019,63 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_180; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_180 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6683,16 +7089,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6710,14 +7116,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6728,16 +7134,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6755,13 +7161,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6773,16 +7179,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6800,13 +7206,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6818,171 +7224,216 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; -assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); -assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_170; +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; + +// synthesis translate_off +reg dummy_d_186; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; end else begin - soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); -assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); -assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_171; +reg dummy_d_187; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_172; +reg dummy_d_188; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_173; +reg dummy_d_189; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; + builder_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; end end else begin - vns_bankmachine3_next_state <= 1'd1; + builder_bankmachine3_next_state <= 1'd1; end end else begin - vns_bankmachine3_next_state <= 2'd3; + builder_bankmachine3_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6990,6 +7441,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7000,44 +7454,32 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7048,30 +7490,36 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7084,12 +7532,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end end else begin end end else begin @@ -7099,23 +7550,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7132,26 +7583,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7165,26 +7616,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7195,24 +7643,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7225,42 +7691,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7273,27 +7724,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7306,48 +7772,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7361,16 +7812,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7388,14 +7839,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7406,16 +7857,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7433,13 +7884,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7451,16 +7902,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7478,13 +7929,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -7496,171 +7947,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_187; +reg dummy_d_203; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; end else begin - soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); -assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); -assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_188; +reg dummy_d_204; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_189; +reg dummy_d_205; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_190; +reg dummy_d_206; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; end end else begin - vns_bankmachine4_next_state <= 1'd1; + builder_bankmachine4_next_state <= 1'd1; end end else begin - vns_bankmachine4_next_state <= 2'd3; + builder_bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7668,6 +8119,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7678,41 +8132,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7726,29 +8168,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7762,29 +8216,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7795,39 +8246,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; - end end 3'd4: begin end @@ -7840,29 +8276,38 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7873,24 +8318,45 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7903,42 +8369,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_214; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7951,27 +8402,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7984,48 +8450,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8039,16 +8490,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8066,14 +8517,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8084,16 +8535,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8111,13 +8562,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8129,16 +8580,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8156,13 +8607,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; end else begin end end else begin @@ -8174,171 +8625,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; -assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); -assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_204; +reg dummy_d_220; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; end else begin - soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); -assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); -assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_205; +reg dummy_d_221; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_206; +reg dummy_d_222; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_207; +reg dummy_d_223; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin - vns_bankmachine5_next_state <= 1'd1; + builder_bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; + builder_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8346,6 +8797,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8356,44 +8810,32 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8404,29 +8846,38 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -8440,41 +8891,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8488,24 +8927,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin end @@ -8518,29 +8954,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8554,17 +9005,20 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8581,12 +9035,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8596,26 +9053,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8632,26 +9086,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8662,48 +9120,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8714,19 +9150,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8744,14 +9195,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8762,16 +9213,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8789,14 +9240,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8807,16 +9258,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8834,13 +9285,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -8852,171 +9303,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_221; +reg dummy_d_237; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; end else begin - soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); -assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); -assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_222; +reg dummy_d_238; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_223; +reg dummy_d_239; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_224; +reg dummy_d_240; // synthesis translate_on always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; + builder_bankmachine6_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; end end else begin - vns_bankmachine6_next_state <= 1'd1; + builder_bankmachine6_next_state <= 1'd1; end end else begin - vns_bankmachine6_next_state <= 2'd3; + builder_bankmachine6_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9024,6 +9475,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9034,44 +9488,32 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9082,30 +9524,36 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9118,12 +9566,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -9133,23 +9584,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -9166,26 +9617,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9199,16 +9650,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9226,12 +9677,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9241,23 +9692,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9274,27 +9728,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9307,27 +9758,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9340,48 +9806,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9395,16 +9846,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9422,14 +9873,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9440,16 +9891,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9467,13 +9918,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9485,16 +9936,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9512,13 +9963,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -9530,181 +9981,181 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; -assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); -assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]); -assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_238; +reg dummy_d_254; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= 16'd0; - if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; + main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; end else begin - soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); -assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); -assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_239; +reg dummy_d_255; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin - soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_240; +reg dummy_d_256; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_241; +reg dummy_d_257; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; + builder_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; end end else begin - vns_bankmachine7_next_state <= 1'd1; + builder_bankmachine7_next_state <= 1'd1; end end else begin - vns_bankmachine7_next_state <= 2'd3; + builder_bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9718,21 +10169,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_259; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9745,15 +10202,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9763,26 +10217,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_260; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9796,27 +10250,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_261; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9829,12 +10277,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; + end end else begin end end else begin @@ -9844,26 +10295,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9877,26 +10328,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9907,24 +10355,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -9937,42 +10403,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9985,27 +10436,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -10018,48 +10484,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_267; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10073,16 +10524,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10100,14 +10551,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10118,16 +10569,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_269; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10145,13 +10596,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10163,16 +10614,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_270; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10190,13 +10641,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -10208,380 +10659,389 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); -assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); -assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; -assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); -assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); -assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); -assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); -assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); -assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); -assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_255; +reg dummy_d_271; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_valids <= 8'd0; - soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; -assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; // synthesis translate_off -reg dummy_d_256; +reg dummy_d_272; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_273; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_274; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_275; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_276; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_277; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_278; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_279; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_264; +reg dummy_d_280; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_281; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_282; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_283; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_valids <= 8'd0; - soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; -assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; // synthesis translate_off -reg dummy_d_268; +reg dummy_d_284; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_285; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_286; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); -assign soc_litedramcore_dfi_p0_reset_n = 1'd1; -assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; -assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; -assign soc_litedramcore_dfi_p1_reset_n = 1'd1; -assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; -assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; -assign soc_litedramcore_dfi_p2_reset_n = 1'd1; -assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; -assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; -assign soc_litedramcore_dfi_p3_reset_n = 1'd1; -assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; -assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; -assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_271; +reg dummy_d_287; // synthesis translate_on always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (soc_litedramcore_read_available) begin - if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (soc_litedramcore_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (soc_litedramcore_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - vns_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - vns_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - vns_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - vns_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - vns_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - vns_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - vns_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (soc_litedramcore_write_available) begin - if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_288; // synthesis translate_on always @(*) begin - soc_litedramcore_en0 <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end 2'd2: begin end @@ -10602,22 +11062,31 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_en0 <= 1'd1; + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_289; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 <= 2'd2; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -10638,24 +11107,30 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_290; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end 2'd2: begin @@ -10677,23 +11152,26 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_291; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -10715,22 +11193,25 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_292; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10751,23 +11232,26 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_293; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10786,24 +11270,60 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_295; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin @@ -10826,25 +11346,25 @@ always @(*) begin end default: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_296; // synthesis translate_on always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_en1 <= 1'd1; + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10868,2999 +11388,5070 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_280; +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel0 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + main_litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel1 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12; +assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15; +assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18; +assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21; +assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24; +assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27; +assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30; +assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33; +assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + end + default: begin + main_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + end + default: begin + main_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_next_state <= 2'd2; + end + 2'd2: begin + builder_next_state <= 1'd0; + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value0 <= 8'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value1 <= 14'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_dat_r <= 32'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end +assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; +assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r; +assign builder_litedramcore_wishbone_sel = main_wb_bus_sel; +assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc; +assign builder_litedramcore_wishbone_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_litedramcore_wishbone_ack; +assign builder_litedramcore_wishbone_we = main_wb_bus_we; +assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; +assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_litedramcore_wishbone_err; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_416; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_416 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_417; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_417 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_418; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_418 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_419; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_419 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_420; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_420 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_421; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_421 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_422; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_422 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_423; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_423 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_424; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_424 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_425; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_425 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_426; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_426 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_427; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_427 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_428; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_428 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_429; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_429 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_430; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_430 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_431; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_431 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_432; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_432 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_433; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_433 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_434; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_434 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_435; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_435 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_436; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_436 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_437; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_437 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_438; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_438 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_439; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_439 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_440; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_440 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_281; +reg dummy_d_441; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_441 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_282; +reg dummy_d_442; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_442 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_443; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - endcase + builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_443 = dummy_s; // synthesis translate_on end -assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); -assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); -assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); -assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); -assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); -assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); -assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); -assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); -assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); -assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_444; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; - end - default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_444 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_285; +reg dummy_d_445; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; - end - default: begin - soc_litedramcore_interface_wdata <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_445 = dummy_s; // synthesis translate_on end -assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; -assign vns_roundrobin0_grant = 1'd0; -assign vns_roundrobin1_grant = 1'd0; -assign vns_roundrobin2_grant = 1'd0; -assign vns_roundrobin3_grant = 1'd0; -assign vns_roundrobin4_grant = 1'd0; -assign vns_roundrobin5_grant = 1'd0; -assign vns_roundrobin6_grant = 1'd0; -assign vns_roundrobin7_grant = 1'd0; -assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; -assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; -assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; -assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; -assign soc_litedramcore_wishbone_we = soc_wb_bus_we; -assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; -assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = soc_litedramcore_wishbone_err; -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_done0_w = soc_init_done_storage; -assign vns_csrbank0_init_error0_w = soc_init_error_storage; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; -assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0]; -assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; -assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); -assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; -assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[15:0]; -assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[15:0]; -assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[15:0]; -assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[15:0]; -assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign soc_litedramcore_sel = soc_litedramcore_storage[0]; -assign soc_litedramcore_cke = soc_litedramcore_storage[1]; -assign soc_litedramcore_odt = soc_litedramcore_storage[2]; -assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; -assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; -assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; -assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[15:0]; -assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0]; -assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we; -assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; -assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[15:0]; -assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0]; -assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we; -assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; -assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[15:0]; -assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0]; -assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we; -assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; -assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[15:0]; -assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0]; -assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we; -assign vns_adr = soc_litedramcore_adr; -assign vns_we = soc_litedramcore_we; -assign vns_dat_w = soc_litedramcore_dat_w; -assign soc_litedramcore_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_286; +reg dummy_d_446; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_446 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; +assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[15:8]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; +assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[15:8]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; +assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[15:8]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; +assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[15:8]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csr_interconnect_adr = builder_litedramcore_adr; +assign builder_csr_interconnect_we = builder_litedramcore_we; +assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; +assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r; +assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_447; +// synthesis translate_on +always @(*) begin + builder_rhs_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_447 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_448; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 16'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed1 <= 16'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_448 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_449; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_449 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_450; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_450 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_451; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_451 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_452; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_452 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_453; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_453 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_454; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_454 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_455; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_455 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_456; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6]; end default: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_456 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_457; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 16'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed7 <= 16'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_457 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_458; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_458 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_459; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_459 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_460; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_460 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_461; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_461 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_462; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_462 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_463; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_463 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_464; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_464 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_465; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 23'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed12 <= 23'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_465 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_466; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_466 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_467; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_467 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_468; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 23'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed15 <= 23'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_468 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_469; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_469 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_470; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_470 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_471; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 23'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed18 <= 23'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_471 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_472; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_472 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_473; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_473 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_474; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 23'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed21 <= 23'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_474 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_475; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_475 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_476; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_476 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_477; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 23'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed24 <= 23'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_477 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_478; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_478 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_479; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_479 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_480; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 23'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed27 <= 23'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_480 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_481; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_481 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_482; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_482 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_483; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 23'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed30 <= 23'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_483 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_484; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_484 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_485; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_485 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_486; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 23'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed33 <= 23'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_486 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_487; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_487 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_488; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_488 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_489; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed0 <= 3'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_489 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_490; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 16'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed1 <= 16'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_litedramcore_nop_a; + builder_array_muxed1 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_490 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_491; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed2 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + builder_array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_491 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_492; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed3 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + builder_array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_492 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_493; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed4 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + builder_array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_493 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_494; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed5 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + builder_array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_494 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_495; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed6 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + builder_array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_495 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_496; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed7 <= 3'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_496 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_497; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 16'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed8 <= 16'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_litedramcore_nop_a; + builder_array_muxed8 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_497 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_498; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed9 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + builder_array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_498 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_499; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed10 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + builder_array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_499 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_500; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed11 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + builder_array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_500 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_501; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed12 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + builder_array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_501 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_502; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed13 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + builder_array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_502 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_503; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed14 <= 3'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_503 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_504; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 16'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed15 <= 16'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_litedramcore_nop_a; + builder_array_muxed15 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_504 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_505; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed16 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + builder_array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_505 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_506; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed17 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + builder_array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_506 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_507; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed18 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + builder_array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_507 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_508; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed19 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + builder_array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_508 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_509; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed20 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + builder_array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_509 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_510; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed21 <= 3'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_510 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_511; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 16'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed22 <= 16'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_litedramcore_nop_a; + builder_array_muxed22 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_511 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_512; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed23 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + builder_array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_512 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_513; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed24 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + builder_array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_513 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_514; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed25 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + builder_array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_514 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_515; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed26 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + builder_array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_515 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_516; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed27 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + builder_array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_516 = dummy_s; // synthesis translate_on end -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - soc_ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - vns_state <= vns_next_state; - soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; - soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; - soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; + end + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; + end + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; + end + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; + end + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; + end + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; + end + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; + end + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; + end + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; + end + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip0_value <= 1'd0; + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip1_value <= 1'd0; + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip2_value <= 1'd0; + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip3_value <= 1'd0; + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip4_value <= 1'd0; + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip5_value <= 1'd0; + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip6_value <= 1'd0; + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip7_value <= 1'd0; + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip8_value <= 1'd0; + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip9_value <= 1'd0; + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip10_value <= 1'd0; + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip11_value <= 1'd0; + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip12_value <= 1'd0; + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip13_value <= 1'd0; + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip14_value <= 1'd0; + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip15_value <= 1'd0; + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]}; - if (soc_litedramcore_inti_p0_rddata_valid) begin - soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - if (soc_litedramcore_inti_p1_rddata_valid) begin - soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if (soc_litedramcore_inti_p2_rddata_valid) begin - soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; end - if (soc_litedramcore_inti_p3_rddata_valid) begin - soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); end - if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin - soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; + end + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; + end + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; + end + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; + end + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; + end + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; + end + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; + end + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; + end + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; + end + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_inti_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata; + end + if (main_litedramcore_inti_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata; + end + if (main_litedramcore_inti_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata; + end + if (main_litedramcore_inti_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - soc_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - soc_litedramcore_postponer_req_o <= 1'd0; - if (soc_litedramcore_postponer_req_i) begin - soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); - if ((soc_litedramcore_postponer_count == 1'd0)) begin - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (soc_litedramcore_sequencer_start0) begin - soc_litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_litedramcore_sequencer_done1) begin - if ((soc_litedramcore_sequencer_count != 1'd0)) begin - soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); - end - end - end - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd1; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd0; - end - if ((soc_litedramcore_sequencer_counter == 7'd73)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 7'd73)) begin - soc_litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_counter == 7'd73)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 7'd73)) begin + main_litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_counter != 1'd0)) begin + main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin - soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_zqcs_executer_done <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin + main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_litedramcore_bankmachine0_row_close) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine0_row_open) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd1; - soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; - soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid; + main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first; + main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine0_twtpcon_valid) begin - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin - soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trccon_valid) begin - soc_litedramcore_bankmachine0_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin - soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trascon_valid) begin - soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_litedramcore_bankmachine1_row_close) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine1_row_open) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd1; - soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; - soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid; + main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first; + main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine1_twtpcon_valid) begin - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin - soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trccon_valid) begin - soc_litedramcore_bankmachine1_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin - soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trascon_valid) begin - soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_litedramcore_bankmachine2_row_close) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine2_row_open) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd1; - soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; - soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid; + main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first; + main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine2_twtpcon_valid) begin - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin - soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trccon_valid) begin - soc_litedramcore_bankmachine2_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin - soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trascon_valid) begin - soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_litedramcore_bankmachine3_row_close) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine3_row_open) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd1; - soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; - soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid; + main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first; + main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine3_twtpcon_valid) begin - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin - soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trccon_valid) begin - soc_litedramcore_bankmachine3_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin - soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trascon_valid) begin - soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_litedramcore_bankmachine4_row_close) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine4_row_open) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd1; - soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; - soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid; + main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first; + main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine4_twtpcon_valid) begin - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin - soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trccon_valid) begin - soc_litedramcore_bankmachine4_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin - soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trascon_valid) begin - soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_litedramcore_bankmachine5_row_close) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine5_row_open) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd1; - soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; - soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid; + main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first; + main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine5_twtpcon_valid) begin - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin - soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trccon_valid) begin - soc_litedramcore_bankmachine5_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin - soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trascon_valid) begin - soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_litedramcore_bankmachine6_row_close) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine6_row_open) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd1; - soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; - soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid; + main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first; + main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine6_twtpcon_valid) begin - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin - soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trccon_valid) begin - soc_litedramcore_bankmachine6_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin - soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trascon_valid) begin - soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_litedramcore_bankmachine7_row_close) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine7_row_open) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd1; - soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; end end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; - soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid; + main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first; + main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine7_twtpcon_valid) begin - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin - soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trccon_valid) begin - soc_litedramcore_bankmachine7_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd6; if (1'd0) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin - soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trascon_valid) begin - soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_litedramcore_en0)) begin - soc_litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~soc_litedramcore_max_time0)) begin - soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~soc_litedramcore_en1)) begin - soc_litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~soc_litedramcore_max_time1)) begin - soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (soc_litedramcore_choose_cmd_ce) begin - case (soc_litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13870,26 +16461,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13899,26 +16490,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13928,26 +16519,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13957,26 +16548,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13986,26 +16577,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -14015,26 +16606,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -14044,26 +16635,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -14074,29 +16665,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_litedramcore_choose_req_ce) begin - case (soc_litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -14106,26 +16697,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -14135,26 +16726,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -14164,26 +16755,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -14193,26 +16784,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -14222,26 +16813,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -14251,26 +16842,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -14280,26 +16871,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -14310,578 +16901,802 @@ always @(posedge sys_clk) begin end endcase end - soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; - soc_litedramcore_dfi_p0_address <= vns_array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; - soc_litedramcore_dfi_p1_address <= vns_array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; - soc_litedramcore_dfi_p2_address <= vns_array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; - soc_litedramcore_dfi_p3_address <= vns_array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_litedramcore_trrdcon_valid) begin - soc_litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_array_muxed0; + main_litedramcore_dfi_p0_address <= builder_array_muxed1; + main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2); + main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3); + main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4); + main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5; + main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_array_muxed7; + main_litedramcore_dfi_p1_address <= builder_array_muxed8; + main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9); + main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10); + main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11); + main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12; + main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_array_muxed14; + main_litedramcore_dfi_p2_address <= builder_array_muxed15; + main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16); + main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17); + main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18); + main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19; + main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_array_muxed21; + main_litedramcore_dfi_p3_address <= builder_array_muxed22; + main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23); + main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24); + main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25); + main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26; + main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_trrdcon_ready)) begin - soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); - if ((soc_litedramcore_trrdcon_count == 1'd1)) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; - if ((soc_litedramcore_tfawcon_count < 3'd4)) begin - if ((soc_litedramcore_tfawcon_count == 2'd3)) begin - soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - soc_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_litedramcore_tccdcon_valid) begin - soc_litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_tccdcon_ready)) begin - soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); - if ((soc_litedramcore_tccdcon_count == 1'd1)) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_litedramcore_twtrcon_valid) begin - soc_litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_twtrcon_ready)) begin - soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); - if ((soc_litedramcore_twtrcon_count == 1'd1)) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_litedramcore_dat_w_next_value_ce0) begin + builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0; + end + if (builder_litedramcore_adr_next_value_ce1) begin + builder_litedramcore_adr <= builder_litedramcore_adr_next_value1; + end + if (builder_litedramcore_we_next_value_ce2) begin + builder_litedramcore_we <= builder_litedramcore_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (vns_csrbank0_init_done0_re) begin - soc_init_done_storage <= vns_csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank0_init_done0_re; - if (vns_csrbank0_init_error0_re) begin - soc_init_error_storage <= vns_csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank0_init_error0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[3:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd2: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 2'd3: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd4: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 3'd5: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (vns_csrbank1_half_sys8x_taps0_re) begin - soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; + end + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; - if (vns_csrbank1_wlevel_en0_re) begin - soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; - if (vns_csrbank1_dly_sel0_re) begin - soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[4:0]) + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + end + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + end + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 4'd10: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; end 4'd11: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; end 4'd12: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end 4'd13: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end 4'd14: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd15: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; end 5'd17: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 5'd18: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 5'd19: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; end 5'd20: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; end 5'd21: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; end 5'd22: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 5'd23: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; end 5'd24: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; + end + 5'd25: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; + end + 5'd26: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; + end + 5'd27: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; + end + 5'd28: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; + end + 5'd29: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; + end + 5'd30: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; + end + 5'd31: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; + end + 6'd32: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; + end + 6'd33: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; + end + 6'd34: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; + end + 6'd35: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; + end + 6'd36: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; + end + 6'd37: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; + end + 6'd38: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; + end + 6'd39: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; + end + 6'd40: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; + end + 6'd41: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; + end + 6'd42: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; + end + 6'd43: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; + end + 6'd44: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; + end + 6'd45: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; + end + 6'd46: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; + end + 6'd47: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; + end + 6'd48: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; + end + 6'd49: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; + end + 6'd50: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; + end + 6'd51: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; + end + 6'd52: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank2_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + end + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; + end + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address1_re) begin + main_litedramcore_phaseinjector0_address_storage[15:8] <= builder_csrbank2_dfii_pi0_address1_r; + end + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + end + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + end + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata3_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; + end + if (builder_csrbank2_dfii_pi0_wrdata2_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; end - soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; - if (vns_csrbank2_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + if (builder_csrbank2_dfii_pi0_wrdata1_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; end - soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; - if (vns_csrbank2_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[15:0] <= vns_csrbank2_dfii_pi0_address0_r; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; - if (vns_csrbank2_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end - soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; - if (vns_csrbank2_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address1_re) begin + main_litedramcore_phaseinjector1_address_storage[15:8] <= builder_csrbank2_dfii_pi1_address1_r; end - soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; - if (vns_csrbank2_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; end - soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; - if (vns_csrbank2_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[15:0] <= vns_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; - if (vns_csrbank2_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata3_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; end - soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; - if (vns_csrbank2_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + if (builder_csrbank2_dfii_pi1_wrdata2_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; end - soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; - if (vns_csrbank2_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + if (builder_csrbank2_dfii_pi1_wrdata1_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; end - soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; - if (vns_csrbank2_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[15:0] <= vns_csrbank2_dfii_pi2_address0_r; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; - if (vns_csrbank2_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end - soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; - if (vns_csrbank2_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address1_re) begin + main_litedramcore_phaseinjector2_address_storage[15:8] <= builder_csrbank2_dfii_pi2_address1_r; end - soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; - if (vns_csrbank2_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; end - soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; - if (vns_csrbank2_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[15:0] <= vns_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; - if (vns_csrbank2_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata3_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; end - soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; - if (vns_csrbank2_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + if (builder_csrbank2_dfii_pi2_wrdata2_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; end - soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + if (builder_csrbank2_dfii_pi2_wrdata1_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; + end + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + end + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; + end + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address1_re) begin + main_litedramcore_phaseinjector3_address_storage[15:8] <= builder_csrbank2_dfii_pi3_address1_r; + end + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + end + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + end + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata3_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; + end + if (builder_csrbank2_dfii_pi3_wrdata2_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; + end + if (builder_csrbank2_dfii_pi3_wrdata1_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; + end + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + end + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; if (sys_rst) begin - soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_a7ddrphy_wlevel_en_storage <= 1'd0; - soc_a7ddrphy_wlevel_en_re <= 1'd0; - soc_a7ddrphy_dly_sel_storage <= 2'd0; - soc_a7ddrphy_dly_sel_re <= 1'd0; - soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_a7ddrphy_dqs_oe_delayed <= 1'd0; - soc_a7ddrphy_dqspattern_o1 <= 8'd0; - soc_a7ddrphy_dq_oe_delayed <= 1'd0; - soc_a7ddrphy_bitslip0_value <= 4'd0; - soc_a7ddrphy_bitslip1_value <= 4'd0; - soc_a7ddrphy_bitslip2_value <= 4'd0; - soc_a7ddrphy_bitslip3_value <= 4'd0; - soc_a7ddrphy_bitslip4_value <= 4'd0; - soc_a7ddrphy_bitslip5_value <= 4'd0; - soc_a7ddrphy_bitslip6_value <= 4'd0; - soc_a7ddrphy_bitslip7_value <= 4'd0; - soc_a7ddrphy_bitslip8_value <= 4'd0; - soc_a7ddrphy_bitslip9_value <= 4'd0; - soc_a7ddrphy_bitslip10_value <= 4'd0; - soc_a7ddrphy_bitslip11_value <= 4'd0; - soc_a7ddrphy_bitslip12_value <= 4'd0; - soc_a7ddrphy_bitslip13_value <= 4'd0; - soc_a7ddrphy_bitslip14_value <= 4'd0; - soc_a7ddrphy_bitslip15_value <= 4'd0; - soc_a7ddrphy_rddata_en_last <= 8'd0; - soc_a7ddrphy_wrdata_en_last <= 4'd0; - soc_litedramcore_storage <= 4'd1; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; - soc_litedramcore_phaseinjector0_command_re <= 1'd0; - soc_litedramcore_phaseinjector0_address_re <= 1'd0; - soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector0_status <= 32'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; - soc_litedramcore_phaseinjector1_command_re <= 1'd0; - soc_litedramcore_phaseinjector1_address_re <= 1'd0; - soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector1_status <= 32'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; - soc_litedramcore_phaseinjector2_command_re <= 1'd0; - soc_litedramcore_phaseinjector2_address_re <= 1'd0; - soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector2_status <= 32'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; - soc_litedramcore_phaseinjector3_command_re <= 1'd0; - soc_litedramcore_phaseinjector3_address_re <= 1'd0; - soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector3_status <= 32'd0; - soc_litedramcore_dfi_p0_address <= 16'd0; - soc_litedramcore_dfi_p0_bank <= 3'd0; - soc_litedramcore_dfi_p0_cas_n <= 1'd1; - soc_litedramcore_dfi_p0_cs_n <= 1'd1; - soc_litedramcore_dfi_p0_ras_n <= 1'd1; - soc_litedramcore_dfi_p0_we_n <= 1'd1; - soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p0_rddata_en <= 1'd0; - soc_litedramcore_dfi_p1_address <= 16'd0; - soc_litedramcore_dfi_p1_bank <= 3'd0; - soc_litedramcore_dfi_p1_cas_n <= 1'd1; - soc_litedramcore_dfi_p1_cs_n <= 1'd1; - soc_litedramcore_dfi_p1_ras_n <= 1'd1; - soc_litedramcore_dfi_p1_we_n <= 1'd1; - soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p1_rddata_en <= 1'd0; - soc_litedramcore_dfi_p2_address <= 16'd0; - soc_litedramcore_dfi_p2_bank <= 3'd0; - soc_litedramcore_dfi_p2_cas_n <= 1'd1; - soc_litedramcore_dfi_p2_cs_n <= 1'd1; - soc_litedramcore_dfi_p2_ras_n <= 1'd1; - soc_litedramcore_dfi_p2_we_n <= 1'd1; - soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p2_rddata_en <= 1'd0; - soc_litedramcore_dfi_p3_address <= 16'd0; - soc_litedramcore_dfi_p3_bank <= 3'd0; - soc_litedramcore_dfi_p3_cas_n <= 1'd1; - soc_litedramcore_dfi_p3_cs_n <= 1'd1; - soc_litedramcore_dfi_p3_ras_n <= 1'd1; - soc_litedramcore_dfi_p3_we_n <= 1'd1; - soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p3_rddata_en <= 1'd0; - soc_litedramcore_timer_count1 <= 10'd781; - soc_litedramcore_postponer_req_o <= 1'd0; - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 7'd0; - soc_litedramcore_sequencer_count <= 1'd0; - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine0_row <= 16'd0; - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trccon_count <= 3'd0; - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trascon_count <= 3'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine1_row <= 16'd0; - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trccon_count <= 3'd0; - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trascon_count <= 3'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine2_row <= 16'd0; - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trccon_count <= 3'd0; - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trascon_count <= 3'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine3_row <= 16'd0; - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trccon_count <= 3'd0; - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trascon_count <= 3'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine4_row <= 16'd0; - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trccon_count <= 3'd0; - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trascon_count <= 3'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine5_row <= 16'd0; - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trccon_count <= 3'd0; - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trascon_count <= 3'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine6_row <= 16'd0; - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trccon_count <= 3'd0; - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trascon_count <= 3'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine7_row <= 16'd0; - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trccon_count <= 3'd0; - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trascon_count <= 3'd0; - soc_litedramcore_choose_cmd_grant <= 3'd0; - soc_litedramcore_choose_req_grant <= 3'd0; - soc_litedramcore_trrdcon_ready <= 1'd0; - soc_litedramcore_trrdcon_count <= 1'd0; - soc_litedramcore_tfawcon_ready <= 1'd1; - soc_litedramcore_tfawcon_window <= 5'd0; - soc_litedramcore_tccdcon_ready <= 1'd0; - soc_litedramcore_tccdcon_count <= 1'd0; - soc_litedramcore_twtrcon_ready <= 1'd0; - soc_litedramcore_twtrcon_count <= 3'd0; - soc_litedramcore_time0 <= 5'd0; - soc_litedramcore_time1 <= 4'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 6'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 6'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 6'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 6'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 16'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 16'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 16'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 16'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 16'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_counter <= 7'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_counter <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine0_row <= 16'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine1_row <= 16'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine2_row <= 16'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine3_row <= 16'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine4_row <= 16'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine5_row <= 16'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine6_row <= 16'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine7_row <= 16'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_litedramcore_we <= 1'd0; + builder_state <= 2'd0; end end BUFG BUFG( - .I(soc_clkout0), - .O(soc_clkout_buf0) + .I(main_clkout0), + .O(main_clkout_buf0) ); BUFG BUFG_1( - .I(soc_clkout1), - .O(soc_clkout_buf1) + .I(main_clkout1), + .O(main_clkout_buf1) ); BUFG BUFG_2( - .I(soc_clkout2), - .O(soc_clkout_buf2) + .I(main_clkout2), + .O(main_clkout_buf2) ); BUFG BUFG_3( - .I(soc_clkout3), - .O(soc_clkout_buf3) + .I(main_clkout3), + .O(main_clkout_buf3) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(main_ic_reset) ); OSERDESE2 #( @@ -14902,12 +17717,12 @@ OSERDESE2 #( .D7(1'd0), .D8(1'd1), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_a7ddrphy_sd_clk_se_nodelay) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(main_a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_a7ddrphy_sd_clk_se_nodelay), + .I(main_a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -14921,17 +17736,17 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[0]), - .D2(soc_a7ddrphy_dfi_p0_address[0]), - .D3(soc_a7ddrphy_dfi_p1_address[0]), - .D4(soc_a7ddrphy_dfi_p1_address[0]), - .D5(soc_a7ddrphy_dfi_p2_address[0]), - .D6(soc_a7ddrphy_dfi_p2_address[0]), - .D7(soc_a7ddrphy_dfi_p3_address[0]), - .D8(soc_a7ddrphy_dfi_p3_address[0]), + .D1(main_a7ddrphy_dfi_p0_reset_n), + .D2(main_a7ddrphy_dfi_p0_reset_n), + .D3(main_a7ddrphy_dfi_p1_reset_n), + .D4(main_a7ddrphy_dfi_p1_reset_n), + .D5(main_a7ddrphy_dfi_p2_reset_n), + .D6(main_a7ddrphy_dfi_p2_reset_n), + .D7(main_a7ddrphy_dfi_p3_reset_n), + .D8(main_a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_reset_n) ); OSERDESE2 #( @@ -14943,17 +17758,17 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[1]), - .D2(soc_a7ddrphy_dfi_p0_address[1]), - .D3(soc_a7ddrphy_dfi_p1_address[1]), - .D4(soc_a7ddrphy_dfi_p1_address[1]), - .D5(soc_a7ddrphy_dfi_p2_address[1]), - .D6(soc_a7ddrphy_dfi_p2_address[1]), - .D7(soc_a7ddrphy_dfi_p3_address[1]), - .D8(soc_a7ddrphy_dfi_p3_address[1]), + .D1(main_a7ddrphy_dfi_p0_cs_n), + .D2(main_a7ddrphy_dfi_p0_cs_n), + .D3(main_a7ddrphy_dfi_p1_cs_n), + .D4(main_a7ddrphy_dfi_p1_cs_n), + .D5(main_a7ddrphy_dfi_p2_cs_n), + .D6(main_a7ddrphy_dfi_p2_cs_n), + .D7(main_a7ddrphy_dfi_p3_cs_n), + .D8(main_a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cs_n) ); OSERDESE2 #( @@ -14965,17 +17780,17 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[2]), - .D2(soc_a7ddrphy_dfi_p0_address[2]), - .D3(soc_a7ddrphy_dfi_p1_address[2]), - .D4(soc_a7ddrphy_dfi_p1_address[2]), - .D5(soc_a7ddrphy_dfi_p2_address[2]), - .D6(soc_a7ddrphy_dfi_p2_address[2]), - .D7(soc_a7ddrphy_dfi_p3_address[2]), - .D8(soc_a7ddrphy_dfi_p3_address[2]), + .D1(main_a7ddrphy_dfi_p0_address[0]), + .D2(main_a7ddrphy_dfi_p0_address[0]), + .D3(main_a7ddrphy_dfi_p1_address[0]), + .D4(main_a7ddrphy_dfi_p1_address[0]), + .D5(main_a7ddrphy_dfi_p2_address[0]), + .D6(main_a7ddrphy_dfi_p2_address[0]), + .D7(main_a7ddrphy_dfi_p3_address[0]), + .D8(main_a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[0]) ); OSERDESE2 #( @@ -14987,17 +17802,17 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[3]), - .D2(soc_a7ddrphy_dfi_p0_address[3]), - .D3(soc_a7ddrphy_dfi_p1_address[3]), - .D4(soc_a7ddrphy_dfi_p1_address[3]), - .D5(soc_a7ddrphy_dfi_p2_address[3]), - .D6(soc_a7ddrphy_dfi_p2_address[3]), - .D7(soc_a7ddrphy_dfi_p3_address[3]), - .D8(soc_a7ddrphy_dfi_p3_address[3]), + .D1(main_a7ddrphy_dfi_p0_address[1]), + .D2(main_a7ddrphy_dfi_p0_address[1]), + .D3(main_a7ddrphy_dfi_p1_address[1]), + .D4(main_a7ddrphy_dfi_p1_address[1]), + .D5(main_a7ddrphy_dfi_p2_address[1]), + .D6(main_a7ddrphy_dfi_p2_address[1]), + .D7(main_a7ddrphy_dfi_p3_address[1]), + .D8(main_a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[3]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[1]) ); OSERDESE2 #( @@ -15009,17 +17824,17 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[4]), - .D2(soc_a7ddrphy_dfi_p0_address[4]), - .D3(soc_a7ddrphy_dfi_p1_address[4]), - .D4(soc_a7ddrphy_dfi_p1_address[4]), - .D5(soc_a7ddrphy_dfi_p2_address[4]), - .D6(soc_a7ddrphy_dfi_p2_address[4]), - .D7(soc_a7ddrphy_dfi_p3_address[4]), - .D8(soc_a7ddrphy_dfi_p3_address[4]), + .D1(main_a7ddrphy_dfi_p0_address[2]), + .D2(main_a7ddrphy_dfi_p0_address[2]), + .D3(main_a7ddrphy_dfi_p1_address[2]), + .D4(main_a7ddrphy_dfi_p1_address[2]), + .D5(main_a7ddrphy_dfi_p2_address[2]), + .D6(main_a7ddrphy_dfi_p2_address[2]), + .D7(main_a7ddrphy_dfi_p3_address[2]), + .D8(main_a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[4]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[2]) ); OSERDESE2 #( @@ -15031,17 +17846,17 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[5]), - .D2(soc_a7ddrphy_dfi_p0_address[5]), - .D3(soc_a7ddrphy_dfi_p1_address[5]), - .D4(soc_a7ddrphy_dfi_p1_address[5]), - .D5(soc_a7ddrphy_dfi_p2_address[5]), - .D6(soc_a7ddrphy_dfi_p2_address[5]), - .D7(soc_a7ddrphy_dfi_p3_address[5]), - .D8(soc_a7ddrphy_dfi_p3_address[5]), + .D1(main_a7ddrphy_dfi_p0_address[3]), + .D2(main_a7ddrphy_dfi_p0_address[3]), + .D3(main_a7ddrphy_dfi_p1_address[3]), + .D4(main_a7ddrphy_dfi_p1_address[3]), + .D5(main_a7ddrphy_dfi_p2_address[3]), + .D6(main_a7ddrphy_dfi_p2_address[3]), + .D7(main_a7ddrphy_dfi_p3_address[3]), + .D8(main_a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[5]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[3]) ); OSERDESE2 #( @@ -15053,17 +17868,17 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[6]), - .D2(soc_a7ddrphy_dfi_p0_address[6]), - .D3(soc_a7ddrphy_dfi_p1_address[6]), - .D4(soc_a7ddrphy_dfi_p1_address[6]), - .D5(soc_a7ddrphy_dfi_p2_address[6]), - .D6(soc_a7ddrphy_dfi_p2_address[6]), - .D7(soc_a7ddrphy_dfi_p3_address[6]), - .D8(soc_a7ddrphy_dfi_p3_address[6]), + .D1(main_a7ddrphy_dfi_p0_address[4]), + .D2(main_a7ddrphy_dfi_p0_address[4]), + .D3(main_a7ddrphy_dfi_p1_address[4]), + .D4(main_a7ddrphy_dfi_p1_address[4]), + .D5(main_a7ddrphy_dfi_p2_address[4]), + .D6(main_a7ddrphy_dfi_p2_address[4]), + .D7(main_a7ddrphy_dfi_p3_address[4]), + .D8(main_a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[6]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[4]) ); OSERDESE2 #( @@ -15075,17 +17890,17 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[7]), - .D2(soc_a7ddrphy_dfi_p0_address[7]), - .D3(soc_a7ddrphy_dfi_p1_address[7]), - .D4(soc_a7ddrphy_dfi_p1_address[7]), - .D5(soc_a7ddrphy_dfi_p2_address[7]), - .D6(soc_a7ddrphy_dfi_p2_address[7]), - .D7(soc_a7ddrphy_dfi_p3_address[7]), - .D8(soc_a7ddrphy_dfi_p3_address[7]), + .D1(main_a7ddrphy_dfi_p0_address[5]), + .D2(main_a7ddrphy_dfi_p0_address[5]), + .D3(main_a7ddrphy_dfi_p1_address[5]), + .D4(main_a7ddrphy_dfi_p1_address[5]), + .D5(main_a7ddrphy_dfi_p2_address[5]), + .D6(main_a7ddrphy_dfi_p2_address[5]), + .D7(main_a7ddrphy_dfi_p3_address[5]), + .D8(main_a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[7]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[5]) ); OSERDESE2 #( @@ -15097,17 +17912,17 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[8]), - .D2(soc_a7ddrphy_dfi_p0_address[8]), - .D3(soc_a7ddrphy_dfi_p1_address[8]), - .D4(soc_a7ddrphy_dfi_p1_address[8]), - .D5(soc_a7ddrphy_dfi_p2_address[8]), - .D6(soc_a7ddrphy_dfi_p2_address[8]), - .D7(soc_a7ddrphy_dfi_p3_address[8]), - .D8(soc_a7ddrphy_dfi_p3_address[8]), + .D1(main_a7ddrphy_dfi_p0_address[6]), + .D2(main_a7ddrphy_dfi_p0_address[6]), + .D3(main_a7ddrphy_dfi_p1_address[6]), + .D4(main_a7ddrphy_dfi_p1_address[6]), + .D5(main_a7ddrphy_dfi_p2_address[6]), + .D6(main_a7ddrphy_dfi_p2_address[6]), + .D7(main_a7ddrphy_dfi_p3_address[6]), + .D8(main_a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[8]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[6]) ); OSERDESE2 #( @@ -15119,17 +17934,17 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[9]), - .D2(soc_a7ddrphy_dfi_p0_address[9]), - .D3(soc_a7ddrphy_dfi_p1_address[9]), - .D4(soc_a7ddrphy_dfi_p1_address[9]), - .D5(soc_a7ddrphy_dfi_p2_address[9]), - .D6(soc_a7ddrphy_dfi_p2_address[9]), - .D7(soc_a7ddrphy_dfi_p3_address[9]), - .D8(soc_a7ddrphy_dfi_p3_address[9]), + .D1(main_a7ddrphy_dfi_p0_address[7]), + .D2(main_a7ddrphy_dfi_p0_address[7]), + .D3(main_a7ddrphy_dfi_p1_address[7]), + .D4(main_a7ddrphy_dfi_p1_address[7]), + .D5(main_a7ddrphy_dfi_p2_address[7]), + .D6(main_a7ddrphy_dfi_p2_address[7]), + .D7(main_a7ddrphy_dfi_p3_address[7]), + .D8(main_a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[9]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[7]) ); OSERDESE2 #( @@ -15141,17 +17956,17 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[10]), - .D2(soc_a7ddrphy_dfi_p0_address[10]), - .D3(soc_a7ddrphy_dfi_p1_address[10]), - .D4(soc_a7ddrphy_dfi_p1_address[10]), - .D5(soc_a7ddrphy_dfi_p2_address[10]), - .D6(soc_a7ddrphy_dfi_p2_address[10]), - .D7(soc_a7ddrphy_dfi_p3_address[10]), - .D8(soc_a7ddrphy_dfi_p3_address[10]), + .D1(main_a7ddrphy_dfi_p0_address[8]), + .D2(main_a7ddrphy_dfi_p0_address[8]), + .D3(main_a7ddrphy_dfi_p1_address[8]), + .D4(main_a7ddrphy_dfi_p1_address[8]), + .D5(main_a7ddrphy_dfi_p2_address[8]), + .D6(main_a7ddrphy_dfi_p2_address[8]), + .D7(main_a7ddrphy_dfi_p3_address[8]), + .D8(main_a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[10]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[8]) ); OSERDESE2 #( @@ -15163,17 +17978,17 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[11]), - .D2(soc_a7ddrphy_dfi_p0_address[11]), - .D3(soc_a7ddrphy_dfi_p1_address[11]), - .D4(soc_a7ddrphy_dfi_p1_address[11]), - .D5(soc_a7ddrphy_dfi_p2_address[11]), - .D6(soc_a7ddrphy_dfi_p2_address[11]), - .D7(soc_a7ddrphy_dfi_p3_address[11]), - .D8(soc_a7ddrphy_dfi_p3_address[11]), + .D1(main_a7ddrphy_dfi_p0_address[9]), + .D2(main_a7ddrphy_dfi_p0_address[9]), + .D3(main_a7ddrphy_dfi_p1_address[9]), + .D4(main_a7ddrphy_dfi_p1_address[9]), + .D5(main_a7ddrphy_dfi_p2_address[9]), + .D6(main_a7ddrphy_dfi_p2_address[9]), + .D7(main_a7ddrphy_dfi_p3_address[9]), + .D8(main_a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[11]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[9]) ); OSERDESE2 #( @@ -15185,17 +18000,17 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[12]), - .D2(soc_a7ddrphy_dfi_p0_address[12]), - .D3(soc_a7ddrphy_dfi_p1_address[12]), - .D4(soc_a7ddrphy_dfi_p1_address[12]), - .D5(soc_a7ddrphy_dfi_p2_address[12]), - .D6(soc_a7ddrphy_dfi_p2_address[12]), - .D7(soc_a7ddrphy_dfi_p3_address[12]), - .D8(soc_a7ddrphy_dfi_p3_address[12]), + .D1(main_a7ddrphy_dfi_p0_address[10]), + .D2(main_a7ddrphy_dfi_p0_address[10]), + .D3(main_a7ddrphy_dfi_p1_address[10]), + .D4(main_a7ddrphy_dfi_p1_address[10]), + .D5(main_a7ddrphy_dfi_p2_address[10]), + .D6(main_a7ddrphy_dfi_p2_address[10]), + .D7(main_a7ddrphy_dfi_p3_address[10]), + .D8(main_a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[12]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[10]) ); OSERDESE2 #( @@ -15207,17 +18022,17 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[13]), - .D2(soc_a7ddrphy_dfi_p0_address[13]), - .D3(soc_a7ddrphy_dfi_p1_address[13]), - .D4(soc_a7ddrphy_dfi_p1_address[13]), - .D5(soc_a7ddrphy_dfi_p2_address[13]), - .D6(soc_a7ddrphy_dfi_p2_address[13]), - .D7(soc_a7ddrphy_dfi_p3_address[13]), - .D8(soc_a7ddrphy_dfi_p3_address[13]), + .D1(main_a7ddrphy_dfi_p0_address[11]), + .D2(main_a7ddrphy_dfi_p0_address[11]), + .D3(main_a7ddrphy_dfi_p1_address[11]), + .D4(main_a7ddrphy_dfi_p1_address[11]), + .D5(main_a7ddrphy_dfi_p2_address[11]), + .D6(main_a7ddrphy_dfi_p2_address[11]), + .D7(main_a7ddrphy_dfi_p3_address[11]), + .D8(main_a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[13]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[11]) ); OSERDESE2 #( @@ -15229,17 +18044,17 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[14]), - .D2(soc_a7ddrphy_dfi_p0_address[14]), - .D3(soc_a7ddrphy_dfi_p1_address[14]), - .D4(soc_a7ddrphy_dfi_p1_address[14]), - .D5(soc_a7ddrphy_dfi_p2_address[14]), - .D6(soc_a7ddrphy_dfi_p2_address[14]), - .D7(soc_a7ddrphy_dfi_p3_address[14]), - .D8(soc_a7ddrphy_dfi_p3_address[14]), + .D1(main_a7ddrphy_dfi_p0_address[12]), + .D2(main_a7ddrphy_dfi_p0_address[12]), + .D3(main_a7ddrphy_dfi_p1_address[12]), + .D4(main_a7ddrphy_dfi_p1_address[12]), + .D5(main_a7ddrphy_dfi_p2_address[12]), + .D6(main_a7ddrphy_dfi_p2_address[12]), + .D7(main_a7ddrphy_dfi_p3_address[12]), + .D8(main_a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[14]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[12]) ); OSERDESE2 #( @@ -15251,17 +18066,17 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[15]), - .D2(soc_a7ddrphy_dfi_p0_address[15]), - .D3(soc_a7ddrphy_dfi_p1_address[15]), - .D4(soc_a7ddrphy_dfi_p1_address[15]), - .D5(soc_a7ddrphy_dfi_p2_address[15]), - .D6(soc_a7ddrphy_dfi_p2_address[15]), - .D7(soc_a7ddrphy_dfi_p3_address[15]), - .D8(soc_a7ddrphy_dfi_p3_address[15]), + .D1(main_a7ddrphy_dfi_p0_address[13]), + .D2(main_a7ddrphy_dfi_p0_address[13]), + .D3(main_a7ddrphy_dfi_p1_address[13]), + .D4(main_a7ddrphy_dfi_p1_address[13]), + .D5(main_a7ddrphy_dfi_p2_address[13]), + .D6(main_a7ddrphy_dfi_p2_address[13]), + .D7(main_a7ddrphy_dfi_p3_address[13]), + .D8(main_a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[15]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[13]) ); OSERDESE2 #( @@ -15273,17 +18088,17 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[0]), - .D2(soc_a7ddrphy_dfi_p0_bank[0]), - .D3(soc_a7ddrphy_dfi_p1_bank[0]), - .D4(soc_a7ddrphy_dfi_p1_bank[0]), - .D5(soc_a7ddrphy_dfi_p2_bank[0]), - .D6(soc_a7ddrphy_dfi_p2_bank[0]), - .D7(soc_a7ddrphy_dfi_p3_bank[0]), - .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .D1(main_a7ddrphy_dfi_p0_address[14]), + .D2(main_a7ddrphy_dfi_p0_address[14]), + .D3(main_a7ddrphy_dfi_p1_address[14]), + .D4(main_a7ddrphy_dfi_p1_address[14]), + .D5(main_a7ddrphy_dfi_p2_address[14]), + .D6(main_a7ddrphy_dfi_p2_address[14]), + .D7(main_a7ddrphy_dfi_p3_address[14]), + .D8(main_a7ddrphy_dfi_p3_address[14]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[14]) ); OSERDESE2 #( @@ -15295,17 +18110,17 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[1]), - .D2(soc_a7ddrphy_dfi_p0_bank[1]), - .D3(soc_a7ddrphy_dfi_p1_bank[1]), - .D4(soc_a7ddrphy_dfi_p1_bank[1]), - .D5(soc_a7ddrphy_dfi_p2_bank[1]), - .D6(soc_a7ddrphy_dfi_p2_bank[1]), - .D7(soc_a7ddrphy_dfi_p3_bank[1]), - .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .D1(main_a7ddrphy_dfi_p0_address[15]), + .D2(main_a7ddrphy_dfi_p0_address[15]), + .D3(main_a7ddrphy_dfi_p1_address[15]), + .D4(main_a7ddrphy_dfi_p1_address[15]), + .D5(main_a7ddrphy_dfi_p2_address[15]), + .D6(main_a7ddrphy_dfi_p2_address[15]), + .D7(main_a7ddrphy_dfi_p3_address[15]), + .D8(main_a7ddrphy_dfi_p3_address[15]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[15]) ); OSERDESE2 #( @@ -15317,17 +18132,17 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[2]), - .D2(soc_a7ddrphy_dfi_p0_bank[2]), - .D3(soc_a7ddrphy_dfi_p1_bank[2]), - .D4(soc_a7ddrphy_dfi_p1_bank[2]), - .D5(soc_a7ddrphy_dfi_p2_bank[2]), - .D6(soc_a7ddrphy_dfi_p2_bank[2]), - .D7(soc_a7ddrphy_dfi_p3_bank[2]), - .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .D1(main_a7ddrphy_dfi_p0_bank[0]), + .D2(main_a7ddrphy_dfi_p0_bank[0]), + .D3(main_a7ddrphy_dfi_p1_bank[0]), + .D4(main_a7ddrphy_dfi_p1_bank[0]), + .D5(main_a7ddrphy_dfi_p2_bank[0]), + .D6(main_a7ddrphy_dfi_p2_bank[0]), + .D7(main_a7ddrphy_dfi_p3_bank[0]), + .D8(main_a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[0]) ); OSERDESE2 #( @@ -15339,17 +18154,17 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_ras_n), - .D2(soc_a7ddrphy_dfi_p0_ras_n), - .D3(soc_a7ddrphy_dfi_p1_ras_n), - .D4(soc_a7ddrphy_dfi_p1_ras_n), - .D5(soc_a7ddrphy_dfi_p2_ras_n), - .D6(soc_a7ddrphy_dfi_p2_ras_n), - .D7(soc_a7ddrphy_dfi_p3_ras_n), - .D8(soc_a7ddrphy_dfi_p3_ras_n), + .D1(main_a7ddrphy_dfi_p0_bank[1]), + .D2(main_a7ddrphy_dfi_p0_bank[1]), + .D3(main_a7ddrphy_dfi_p1_bank[1]), + .D4(main_a7ddrphy_dfi_p1_bank[1]), + .D5(main_a7ddrphy_dfi_p2_bank[1]), + .D6(main_a7ddrphy_dfi_p2_bank[1]), + .D7(main_a7ddrphy_dfi_p3_bank[1]), + .D8(main_a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ras_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[1]) ); OSERDESE2 #( @@ -15361,17 +18176,17 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cas_n), - .D2(soc_a7ddrphy_dfi_p0_cas_n), - .D3(soc_a7ddrphy_dfi_p1_cas_n), - .D4(soc_a7ddrphy_dfi_p1_cas_n), - .D5(soc_a7ddrphy_dfi_p2_cas_n), - .D6(soc_a7ddrphy_dfi_p2_cas_n), - .D7(soc_a7ddrphy_dfi_p3_cas_n), - .D8(soc_a7ddrphy_dfi_p3_cas_n), + .D1(main_a7ddrphy_dfi_p0_bank[2]), + .D2(main_a7ddrphy_dfi_p0_bank[2]), + .D3(main_a7ddrphy_dfi_p1_bank[2]), + .D4(main_a7ddrphy_dfi_p1_bank[2]), + .D5(main_a7ddrphy_dfi_p2_bank[2]), + .D6(main_a7ddrphy_dfi_p2_bank[2]), + .D7(main_a7ddrphy_dfi_p3_bank[2]), + .D8(main_a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cas_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[2]) ); OSERDESE2 #( @@ -15383,17 +18198,17 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_we_n), - .D2(soc_a7ddrphy_dfi_p0_we_n), - .D3(soc_a7ddrphy_dfi_p1_we_n), - .D4(soc_a7ddrphy_dfi_p1_we_n), - .D5(soc_a7ddrphy_dfi_p2_we_n), - .D6(soc_a7ddrphy_dfi_p2_we_n), - .D7(soc_a7ddrphy_dfi_p3_we_n), - .D8(soc_a7ddrphy_dfi_p3_we_n), + .D1(main_a7ddrphy_dfi_p0_ras_n), + .D2(main_a7ddrphy_dfi_p0_ras_n), + .D3(main_a7ddrphy_dfi_p1_ras_n), + .D4(main_a7ddrphy_dfi_p1_ras_n), + .D5(main_a7ddrphy_dfi_p2_ras_n), + .D6(main_a7ddrphy_dfi_p2_ras_n), + .D7(main_a7ddrphy_dfi_p3_ras_n), + .D8(main_a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_we_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ras_n) ); OSERDESE2 #( @@ -15405,17 +18220,17 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cke), - .D2(soc_a7ddrphy_dfi_p0_cke), - .D3(soc_a7ddrphy_dfi_p1_cke), - .D4(soc_a7ddrphy_dfi_p1_cke), - .D5(soc_a7ddrphy_dfi_p2_cke), - .D6(soc_a7ddrphy_dfi_p2_cke), - .D7(soc_a7ddrphy_dfi_p3_cke), - .D8(soc_a7ddrphy_dfi_p3_cke), + .D1(main_a7ddrphy_dfi_p0_cas_n), + .D2(main_a7ddrphy_dfi_p0_cas_n), + .D3(main_a7ddrphy_dfi_p1_cas_n), + .D4(main_a7ddrphy_dfi_p1_cas_n), + .D5(main_a7ddrphy_dfi_p2_cas_n), + .D6(main_a7ddrphy_dfi_p2_cas_n), + .D7(main_a7ddrphy_dfi_p3_cas_n), + .D8(main_a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cke) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cas_n) ); OSERDESE2 #( @@ -15427,17 +18242,17 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_odt), - .D2(soc_a7ddrphy_dfi_p0_odt), - .D3(soc_a7ddrphy_dfi_p1_odt), - .D4(soc_a7ddrphy_dfi_p1_odt), - .D5(soc_a7ddrphy_dfi_p2_odt), - .D6(soc_a7ddrphy_dfi_p2_odt), - .D7(soc_a7ddrphy_dfi_p3_odt), - .D8(soc_a7ddrphy_dfi_p3_odt), + .D1(main_a7ddrphy_dfi_p0_we_n), + .D2(main_a7ddrphy_dfi_p0_we_n), + .D3(main_a7ddrphy_dfi_p1_we_n), + .D4(main_a7ddrphy_dfi_p1_we_n), + .D5(main_a7ddrphy_dfi_p2_we_n), + .D6(main_a7ddrphy_dfi_p2_we_n), + .D7(main_a7ddrphy_dfi_p3_we_n), + .D8(main_a7ddrphy_dfi_p3_we_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_odt) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_we_n) ); OSERDESE2 #( @@ -15449,17 +18264,17 @@ OSERDESE2 #( ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_reset_n), - .D2(soc_a7ddrphy_dfi_p0_reset_n), - .D3(soc_a7ddrphy_dfi_p1_reset_n), - .D4(soc_a7ddrphy_dfi_p1_reset_n), - .D5(soc_a7ddrphy_dfi_p2_reset_n), - .D6(soc_a7ddrphy_dfi_p2_reset_n), - .D7(soc_a7ddrphy_dfi_p3_reset_n), - .D8(soc_a7ddrphy_dfi_p3_reset_n), + .D1(main_a7ddrphy_dfi_p0_cke), + .D2(main_a7ddrphy_dfi_p0_cke), + .D3(main_a7ddrphy_dfi_p1_cke), + .D4(main_a7ddrphy_dfi_p1_cke), + .D5(main_a7ddrphy_dfi_p2_cke), + .D6(main_a7ddrphy_dfi_p2_cke), + .D7(main_a7ddrphy_dfi_p3_cke), + .D8(main_a7ddrphy_dfi_p3_cke), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_reset_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cke) ); OSERDESE2 #( @@ -15471,17 +18286,17 @@ OSERDESE2 #( ) OSERDESE2_26 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cs_n), - .D2(soc_a7ddrphy_dfi_p0_cs_n), - .D3(soc_a7ddrphy_dfi_p1_cs_n), - .D4(soc_a7ddrphy_dfi_p1_cs_n), - .D5(soc_a7ddrphy_dfi_p2_cs_n), - .D6(soc_a7ddrphy_dfi_p2_cs_n), - .D7(soc_a7ddrphy_dfi_p3_cs_n), - .D8(soc_a7ddrphy_dfi_p3_cs_n), + .D1(main_a7ddrphy_dfi_p0_odt), + .D2(main_a7ddrphy_dfi_p0_odt), + .D3(main_a7ddrphy_dfi_p1_odt), + .D4(main_a7ddrphy_dfi_p1_odt), + .D5(main_a7ddrphy_dfi_p2_odt), + .D6(main_a7ddrphy_dfi_p2_odt), + .D7(main_a7ddrphy_dfi_p3_odt), + .D8(main_a7ddrphy_dfi_p3_odt), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cs_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_odt) ); OSERDESE2 #( @@ -15491,19 +18306,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .D1(main_a7ddrphy_bitslip00[0]), + .D2(main_a7ddrphy_bitslip00[1]), + .D3(main_a7ddrphy_bitslip00[2]), + .D4(main_a7ddrphy_bitslip00[3]), + .D5(main_a7ddrphy_bitslip00[4]), + .D6(main_a7ddrphy_bitslip00[5]), + .D7(main_a7ddrphy_bitslip00[6]), + .D8(main_a7ddrphy_bitslip00[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy0), + .OQ(main_a7ddrphy_dqs_o_no_delay0), + .TQ(main_a7ddrphy_dqs_t0) +); + +IOBUFDS IOBUFDS( + .I(main_a7ddrphy_dqs_o_no_delay0), + .T(main_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( @@ -15513,19 +18339,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .D1(main_a7ddrphy_bitslip10[0]), + .D2(main_a7ddrphy_bitslip10[1]), + .D3(main_a7ddrphy_bitslip10[2]), + .D4(main_a7ddrphy_bitslip10[3]), + .D5(main_a7ddrphy_bitslip10[4]), + .D6(main_a7ddrphy_bitslip10[5]), + .D7(main_a7ddrphy_bitslip10[6]), + .D8(main_a7ddrphy_bitslip10[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy1), + .OQ(main_a7ddrphy_dqs_o_no_delay1), + .TQ(main_a7ddrphy_dqs_t1) +); + +IOBUFDS IOBUFDS_1( + .I(main_a7ddrphy_dqs_o_no_delay1), + .T(main_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( @@ -15535,45 +18372,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip01[0]), + .D2(main_a7ddrphy_bitslip01[1]), + .D3(main_a7ddrphy_bitslip01[2]), + .D4(main_a7ddrphy_bitslip01[3]), + .D5(main_a7ddrphy_bitslip01[4]), + .D6(main_a7ddrphy_bitslip01[5]), + .D7(main_a7ddrphy_bitslip01[6]), + .D8(main_a7ddrphy_bitslip01[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy0), - .OQ(soc_a7ddrphy_dqs_o_no_delay0), - .TQ(soc_a7ddrphy_dqs_t0) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2 ( - .IDATAIN(soc_a7ddrphy_dqs_i[0]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) -); - -IOBUFDS IOBUFDS( - .I(soc_a7ddrphy_dqs_o_no_delay0), - .T(soc_a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]), - .O(soc_a7ddrphy_dqs_i[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[0]) ); OSERDESE2 #( @@ -15583,45 +18394,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip11[0]), + .D2(main_a7ddrphy_bitslip11[1]), + .D3(main_a7ddrphy_bitslip11[2]), + .D4(main_a7ddrphy_bitslip11[3]), + .D5(main_a7ddrphy_bitslip11[4]), + .D6(main_a7ddrphy_bitslip11[5]), + .D7(main_a7ddrphy_bitslip11[6]), + .D8(main_a7ddrphy_bitslip11[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy1), - .OQ(soc_a7ddrphy_dqs_o_no_delay1), - .TQ(soc_a7ddrphy_dqs_t1) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_1 ( - .IDATAIN(soc_a7ddrphy_dqs_i[1]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) -); - -IOBUFDS IOBUFDS_1( - .I(soc_a7ddrphy_dqs_o_no_delay1), - .T(soc_a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]), - .O(soc_a7ddrphy_dqs_i[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[1]) ); OSERDESE2 #( @@ -15633,20 +18418,20 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .D1(main_a7ddrphy_bitslip02[0]), + .D2(main_a7ddrphy_bitslip02[1]), + .D3(main_a7ddrphy_bitslip02[2]), + .D4(main_a7ddrphy_bitslip02[3]), + .D5(main_a7ddrphy_bitslip02[4]), + .D6(main_a7ddrphy_bitslip02[5]), + .D7(main_a7ddrphy_bitslip02[6]), + .D8(main_a7ddrphy_bitslip02[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay0), - .TQ(soc_a7ddrphy_dq_t0) + .OQ(main_a7ddrphy_dq_o_nodelay0), + .TQ(main_a7ddrphy_dq_t0) ); ISERDESE2 #( @@ -15662,16 +18447,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed0), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data0[7]), - .Q2(soc_a7ddrphy_dq_i_data0[6]), - .Q3(soc_a7ddrphy_dq_i_data0[5]), - .Q4(soc_a7ddrphy_dq_i_data0[4]), - .Q5(soc_a7ddrphy_dq_i_data0[3]), - .Q6(soc_a7ddrphy_dq_i_data0[2]), - .Q7(soc_a7ddrphy_dq_i_data0[1]), - .Q8(soc_a7ddrphy_dq_i_data0[0]) + .DDLY(main_a7ddrphy_dq_i_delayed0), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip03[7]), + .Q2(main_a7ddrphy_bitslip03[6]), + .Q3(main_a7ddrphy_bitslip03[5]), + .Q4(main_a7ddrphy_bitslip03[4]), + .Q5(main_a7ddrphy_bitslip03[3]), + .Q6(main_a7ddrphy_bitslip03[2]), + .Q7(main_a7ddrphy_bitslip03[1]), + .Q8(main_a7ddrphy_bitslip03[0]) ); IDELAYE2 #( @@ -15683,21 +18468,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_2 ( +) IDELAYE2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed0) + .DATAOUT(main_a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_a7ddrphy_dq_o_nodelay0), - .T(soc_a7ddrphy_dq_t0), + .I(main_a7ddrphy_dq_o_nodelay0), + .T(main_a7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_a7ddrphy_dq_i_nodelay0) + .O(main_a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -15709,20 +18494,20 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .D1(main_a7ddrphy_bitslip12[0]), + .D2(main_a7ddrphy_bitslip12[1]), + .D3(main_a7ddrphy_bitslip12[2]), + .D4(main_a7ddrphy_bitslip12[3]), + .D5(main_a7ddrphy_bitslip12[4]), + .D6(main_a7ddrphy_bitslip12[5]), + .D7(main_a7ddrphy_bitslip12[6]), + .D8(main_a7ddrphy_bitslip12[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay1), - .TQ(soc_a7ddrphy_dq_t1) + .OQ(main_a7ddrphy_dq_o_nodelay1), + .TQ(main_a7ddrphy_dq_t1) ); ISERDESE2 #( @@ -15738,16 +18523,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed1), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data1[7]), - .Q2(soc_a7ddrphy_dq_i_data1[6]), - .Q3(soc_a7ddrphy_dq_i_data1[5]), - .Q4(soc_a7ddrphy_dq_i_data1[4]), - .Q5(soc_a7ddrphy_dq_i_data1[3]), - .Q6(soc_a7ddrphy_dq_i_data1[2]), - .Q7(soc_a7ddrphy_dq_i_data1[1]), - .Q8(soc_a7ddrphy_dq_i_data1[0]) + .DDLY(main_a7ddrphy_dq_i_delayed1), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip13[7]), + .Q2(main_a7ddrphy_bitslip13[6]), + .Q3(main_a7ddrphy_bitslip13[5]), + .Q4(main_a7ddrphy_bitslip13[4]), + .Q5(main_a7ddrphy_bitslip13[3]), + .Q6(main_a7ddrphy_bitslip13[2]), + .Q7(main_a7ddrphy_bitslip13[1]), + .Q8(main_a7ddrphy_bitslip13[0]) ); IDELAYE2 #( @@ -15759,21 +18544,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_3 ( +) IDELAYE2_1 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed1) + .DATAOUT(main_a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_a7ddrphy_dq_o_nodelay1), - .T(soc_a7ddrphy_dq_t1), + .I(main_a7ddrphy_dq_o_nodelay1), + .T(main_a7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_a7ddrphy_dq_i_nodelay1) + .O(main_a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -15785,20 +18570,20 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .D1(main_a7ddrphy_bitslip20[0]), + .D2(main_a7ddrphy_bitslip20[1]), + .D3(main_a7ddrphy_bitslip20[2]), + .D4(main_a7ddrphy_bitslip20[3]), + .D5(main_a7ddrphy_bitslip20[4]), + .D6(main_a7ddrphy_bitslip20[5]), + .D7(main_a7ddrphy_bitslip20[6]), + .D8(main_a7ddrphy_bitslip20[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay2), - .TQ(soc_a7ddrphy_dq_t2) + .OQ(main_a7ddrphy_dq_o_nodelay2), + .TQ(main_a7ddrphy_dq_t2) ); ISERDESE2 #( @@ -15814,16 +18599,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed2), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data2[7]), - .Q2(soc_a7ddrphy_dq_i_data2[6]), - .Q3(soc_a7ddrphy_dq_i_data2[5]), - .Q4(soc_a7ddrphy_dq_i_data2[4]), - .Q5(soc_a7ddrphy_dq_i_data2[3]), - .Q6(soc_a7ddrphy_dq_i_data2[2]), - .Q7(soc_a7ddrphy_dq_i_data2[1]), - .Q8(soc_a7ddrphy_dq_i_data2[0]) + .DDLY(main_a7ddrphy_dq_i_delayed2), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip21[7]), + .Q2(main_a7ddrphy_bitslip21[6]), + .Q3(main_a7ddrphy_bitslip21[5]), + .Q4(main_a7ddrphy_bitslip21[4]), + .Q5(main_a7ddrphy_bitslip21[3]), + .Q6(main_a7ddrphy_bitslip21[2]), + .Q7(main_a7ddrphy_bitslip21[1]), + .Q8(main_a7ddrphy_bitslip21[0]) ); IDELAYE2 #( @@ -15835,21 +18620,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_4 ( +) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed2) + .DATAOUT(main_a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_a7ddrphy_dq_o_nodelay2), - .T(soc_a7ddrphy_dq_t2), + .I(main_a7ddrphy_dq_o_nodelay2), + .T(main_a7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_a7ddrphy_dq_i_nodelay2) + .O(main_a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -15861,20 +18646,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .D1(main_a7ddrphy_bitslip30[0]), + .D2(main_a7ddrphy_bitslip30[1]), + .D3(main_a7ddrphy_bitslip30[2]), + .D4(main_a7ddrphy_bitslip30[3]), + .D5(main_a7ddrphy_bitslip30[4]), + .D6(main_a7ddrphy_bitslip30[5]), + .D7(main_a7ddrphy_bitslip30[6]), + .D8(main_a7ddrphy_bitslip30[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay3), - .TQ(soc_a7ddrphy_dq_t3) + .OQ(main_a7ddrphy_dq_o_nodelay3), + .TQ(main_a7ddrphy_dq_t3) ); ISERDESE2 #( @@ -15890,16 +18675,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed3), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data3[7]), - .Q2(soc_a7ddrphy_dq_i_data3[6]), - .Q3(soc_a7ddrphy_dq_i_data3[5]), - .Q4(soc_a7ddrphy_dq_i_data3[4]), - .Q5(soc_a7ddrphy_dq_i_data3[3]), - .Q6(soc_a7ddrphy_dq_i_data3[2]), - .Q7(soc_a7ddrphy_dq_i_data3[1]), - .Q8(soc_a7ddrphy_dq_i_data3[0]) + .DDLY(main_a7ddrphy_dq_i_delayed3), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip31[7]), + .Q2(main_a7ddrphy_bitslip31[6]), + .Q3(main_a7ddrphy_bitslip31[5]), + .Q4(main_a7ddrphy_bitslip31[4]), + .Q5(main_a7ddrphy_bitslip31[3]), + .Q6(main_a7ddrphy_bitslip31[2]), + .Q7(main_a7ddrphy_bitslip31[1]), + .Q8(main_a7ddrphy_bitslip31[0]) ); IDELAYE2 #( @@ -15911,21 +18696,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_5 ( +) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed3) + .DATAOUT(main_a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_a7ddrphy_dq_o_nodelay3), - .T(soc_a7ddrphy_dq_t3), + .I(main_a7ddrphy_dq_o_nodelay3), + .T(main_a7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_a7ddrphy_dq_i_nodelay3) + .O(main_a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -15937,20 +18722,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .D1(main_a7ddrphy_bitslip40[0]), + .D2(main_a7ddrphy_bitslip40[1]), + .D3(main_a7ddrphy_bitslip40[2]), + .D4(main_a7ddrphy_bitslip40[3]), + .D5(main_a7ddrphy_bitslip40[4]), + .D6(main_a7ddrphy_bitslip40[5]), + .D7(main_a7ddrphy_bitslip40[6]), + .D8(main_a7ddrphy_bitslip40[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay4), - .TQ(soc_a7ddrphy_dq_t4) + .OQ(main_a7ddrphy_dq_o_nodelay4), + .TQ(main_a7ddrphy_dq_t4) ); ISERDESE2 #( @@ -15966,16 +18751,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed4), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data4[7]), - .Q2(soc_a7ddrphy_dq_i_data4[6]), - .Q3(soc_a7ddrphy_dq_i_data4[5]), - .Q4(soc_a7ddrphy_dq_i_data4[4]), - .Q5(soc_a7ddrphy_dq_i_data4[3]), - .Q6(soc_a7ddrphy_dq_i_data4[2]), - .Q7(soc_a7ddrphy_dq_i_data4[1]), - .Q8(soc_a7ddrphy_dq_i_data4[0]) + .DDLY(main_a7ddrphy_dq_i_delayed4), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip41[7]), + .Q2(main_a7ddrphy_bitslip41[6]), + .Q3(main_a7ddrphy_bitslip41[5]), + .Q4(main_a7ddrphy_bitslip41[4]), + .Q5(main_a7ddrphy_bitslip41[3]), + .Q6(main_a7ddrphy_bitslip41[2]), + .Q7(main_a7ddrphy_bitslip41[1]), + .Q8(main_a7ddrphy_bitslip41[0]) ); IDELAYE2 #( @@ -15987,21 +18772,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_6 ( +) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed4) + .DATAOUT(main_a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_a7ddrphy_dq_o_nodelay4), - .T(soc_a7ddrphy_dq_t4), + .I(main_a7ddrphy_dq_o_nodelay4), + .T(main_a7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_a7ddrphy_dq_i_nodelay4) + .O(main_a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -16013,20 +18798,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .D1(main_a7ddrphy_bitslip50[0]), + .D2(main_a7ddrphy_bitslip50[1]), + .D3(main_a7ddrphy_bitslip50[2]), + .D4(main_a7ddrphy_bitslip50[3]), + .D5(main_a7ddrphy_bitslip50[4]), + .D6(main_a7ddrphy_bitslip50[5]), + .D7(main_a7ddrphy_bitslip50[6]), + .D8(main_a7ddrphy_bitslip50[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay5), - .TQ(soc_a7ddrphy_dq_t5) + .OQ(main_a7ddrphy_dq_o_nodelay5), + .TQ(main_a7ddrphy_dq_t5) ); ISERDESE2 #( @@ -16042,16 +18827,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed5), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data5[7]), - .Q2(soc_a7ddrphy_dq_i_data5[6]), - .Q3(soc_a7ddrphy_dq_i_data5[5]), - .Q4(soc_a7ddrphy_dq_i_data5[4]), - .Q5(soc_a7ddrphy_dq_i_data5[3]), - .Q6(soc_a7ddrphy_dq_i_data5[2]), - .Q7(soc_a7ddrphy_dq_i_data5[1]), - .Q8(soc_a7ddrphy_dq_i_data5[0]) + .DDLY(main_a7ddrphy_dq_i_delayed5), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip51[7]), + .Q2(main_a7ddrphy_bitslip51[6]), + .Q3(main_a7ddrphy_bitslip51[5]), + .Q4(main_a7ddrphy_bitslip51[4]), + .Q5(main_a7ddrphy_bitslip51[3]), + .Q6(main_a7ddrphy_bitslip51[2]), + .Q7(main_a7ddrphy_bitslip51[1]), + .Q8(main_a7ddrphy_bitslip51[0]) ); IDELAYE2 #( @@ -16063,21 +18848,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_7 ( +) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed5) + .DATAOUT(main_a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_a7ddrphy_dq_o_nodelay5), - .T(soc_a7ddrphy_dq_t5), + .I(main_a7ddrphy_dq_o_nodelay5), + .T(main_a7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_a7ddrphy_dq_i_nodelay5) + .O(main_a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -16089,20 +18874,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .D1(main_a7ddrphy_bitslip60[0]), + .D2(main_a7ddrphy_bitslip60[1]), + .D3(main_a7ddrphy_bitslip60[2]), + .D4(main_a7ddrphy_bitslip60[3]), + .D5(main_a7ddrphy_bitslip60[4]), + .D6(main_a7ddrphy_bitslip60[5]), + .D7(main_a7ddrphy_bitslip60[6]), + .D8(main_a7ddrphy_bitslip60[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay6), - .TQ(soc_a7ddrphy_dq_t6) + .OQ(main_a7ddrphy_dq_o_nodelay6), + .TQ(main_a7ddrphy_dq_t6) ); ISERDESE2 #( @@ -16118,16 +18903,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed6), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data6[7]), - .Q2(soc_a7ddrphy_dq_i_data6[6]), - .Q3(soc_a7ddrphy_dq_i_data6[5]), - .Q4(soc_a7ddrphy_dq_i_data6[4]), - .Q5(soc_a7ddrphy_dq_i_data6[3]), - .Q6(soc_a7ddrphy_dq_i_data6[2]), - .Q7(soc_a7ddrphy_dq_i_data6[1]), - .Q8(soc_a7ddrphy_dq_i_data6[0]) + .DDLY(main_a7ddrphy_dq_i_delayed6), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip61[7]), + .Q2(main_a7ddrphy_bitslip61[6]), + .Q3(main_a7ddrphy_bitslip61[5]), + .Q4(main_a7ddrphy_bitslip61[4]), + .Q5(main_a7ddrphy_bitslip61[3]), + .Q6(main_a7ddrphy_bitslip61[2]), + .Q7(main_a7ddrphy_bitslip61[1]), + .Q8(main_a7ddrphy_bitslip61[0]) ); IDELAYE2 #( @@ -16139,21 +18924,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_8 ( +) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed6) + .DATAOUT(main_a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_a7ddrphy_dq_o_nodelay6), - .T(soc_a7ddrphy_dq_t6), + .I(main_a7ddrphy_dq_o_nodelay6), + .T(main_a7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_a7ddrphy_dq_i_nodelay6) + .O(main_a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -16165,20 +18950,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .D1(main_a7ddrphy_bitslip70[0]), + .D2(main_a7ddrphy_bitslip70[1]), + .D3(main_a7ddrphy_bitslip70[2]), + .D4(main_a7ddrphy_bitslip70[3]), + .D5(main_a7ddrphy_bitslip70[4]), + .D6(main_a7ddrphy_bitslip70[5]), + .D7(main_a7ddrphy_bitslip70[6]), + .D8(main_a7ddrphy_bitslip70[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay7), - .TQ(soc_a7ddrphy_dq_t7) + .OQ(main_a7ddrphy_dq_o_nodelay7), + .TQ(main_a7ddrphy_dq_t7) ); ISERDESE2 #( @@ -16194,16 +18979,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed7), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data7[7]), - .Q2(soc_a7ddrphy_dq_i_data7[6]), - .Q3(soc_a7ddrphy_dq_i_data7[5]), - .Q4(soc_a7ddrphy_dq_i_data7[4]), - .Q5(soc_a7ddrphy_dq_i_data7[3]), - .Q6(soc_a7ddrphy_dq_i_data7[2]), - .Q7(soc_a7ddrphy_dq_i_data7[1]), - .Q8(soc_a7ddrphy_dq_i_data7[0]) + .DDLY(main_a7ddrphy_dq_i_delayed7), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip71[7]), + .Q2(main_a7ddrphy_bitslip71[6]), + .Q3(main_a7ddrphy_bitslip71[5]), + .Q4(main_a7ddrphy_bitslip71[4]), + .Q5(main_a7ddrphy_bitslip71[3]), + .Q6(main_a7ddrphy_bitslip71[2]), + .Q7(main_a7ddrphy_bitslip71[1]), + .Q8(main_a7ddrphy_bitslip71[0]) ); IDELAYE2 #( @@ -16215,21 +19000,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_9 ( +) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed7) + .DATAOUT(main_a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_a7ddrphy_dq_o_nodelay7), - .T(soc_a7ddrphy_dq_t7), + .I(main_a7ddrphy_dq_o_nodelay7), + .T(main_a7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_a7ddrphy_dq_i_nodelay7) + .O(main_a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -16241,20 +19026,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .D1(main_a7ddrphy_bitslip80[0]), + .D2(main_a7ddrphy_bitslip80[1]), + .D3(main_a7ddrphy_bitslip80[2]), + .D4(main_a7ddrphy_bitslip80[3]), + .D5(main_a7ddrphy_bitslip80[4]), + .D6(main_a7ddrphy_bitslip80[5]), + .D7(main_a7ddrphy_bitslip80[6]), + .D8(main_a7ddrphy_bitslip80[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay8), - .TQ(soc_a7ddrphy_dq_t8) + .OQ(main_a7ddrphy_dq_o_nodelay8), + .TQ(main_a7ddrphy_dq_t8) ); ISERDESE2 #( @@ -16270,16 +19055,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed8), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data8[7]), - .Q2(soc_a7ddrphy_dq_i_data8[6]), - .Q3(soc_a7ddrphy_dq_i_data8[5]), - .Q4(soc_a7ddrphy_dq_i_data8[4]), - .Q5(soc_a7ddrphy_dq_i_data8[3]), - .Q6(soc_a7ddrphy_dq_i_data8[2]), - .Q7(soc_a7ddrphy_dq_i_data8[1]), - .Q8(soc_a7ddrphy_dq_i_data8[0]) + .DDLY(main_a7ddrphy_dq_i_delayed8), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip81[7]), + .Q2(main_a7ddrphy_bitslip81[6]), + .Q3(main_a7ddrphy_bitslip81[5]), + .Q4(main_a7ddrphy_bitslip81[4]), + .Q5(main_a7ddrphy_bitslip81[3]), + .Q6(main_a7ddrphy_bitslip81[2]), + .Q7(main_a7ddrphy_bitslip81[1]), + .Q8(main_a7ddrphy_bitslip81[0]) ); IDELAYE2 #( @@ -16291,21 +19076,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_10 ( +) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed8) + .DATAOUT(main_a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_a7ddrphy_dq_o_nodelay8), - .T(soc_a7ddrphy_dq_t8), + .I(main_a7ddrphy_dq_o_nodelay8), + .T(main_a7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_a7ddrphy_dq_i_nodelay8) + .O(main_a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -16317,20 +19102,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .D1(main_a7ddrphy_bitslip90[0]), + .D2(main_a7ddrphy_bitslip90[1]), + .D3(main_a7ddrphy_bitslip90[2]), + .D4(main_a7ddrphy_bitslip90[3]), + .D5(main_a7ddrphy_bitslip90[4]), + .D6(main_a7ddrphy_bitslip90[5]), + .D7(main_a7ddrphy_bitslip90[6]), + .D8(main_a7ddrphy_bitslip90[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay9), - .TQ(soc_a7ddrphy_dq_t9) + .OQ(main_a7ddrphy_dq_o_nodelay9), + .TQ(main_a7ddrphy_dq_t9) ); ISERDESE2 #( @@ -16346,16 +19131,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed9), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data9[7]), - .Q2(soc_a7ddrphy_dq_i_data9[6]), - .Q3(soc_a7ddrphy_dq_i_data9[5]), - .Q4(soc_a7ddrphy_dq_i_data9[4]), - .Q5(soc_a7ddrphy_dq_i_data9[3]), - .Q6(soc_a7ddrphy_dq_i_data9[2]), - .Q7(soc_a7ddrphy_dq_i_data9[1]), - .Q8(soc_a7ddrphy_dq_i_data9[0]) + .DDLY(main_a7ddrphy_dq_i_delayed9), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip91[7]), + .Q2(main_a7ddrphy_bitslip91[6]), + .Q3(main_a7ddrphy_bitslip91[5]), + .Q4(main_a7ddrphy_bitslip91[4]), + .Q5(main_a7ddrphy_bitslip91[3]), + .Q6(main_a7ddrphy_bitslip91[2]), + .Q7(main_a7ddrphy_bitslip91[1]), + .Q8(main_a7ddrphy_bitslip91[0]) ); IDELAYE2 #( @@ -16367,21 +19152,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_11 ( +) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed9) + .DATAOUT(main_a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_a7ddrphy_dq_o_nodelay9), - .T(soc_a7ddrphy_dq_t9), + .I(main_a7ddrphy_dq_o_nodelay9), + .T(main_a7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_a7ddrphy_dq_i_nodelay9) + .O(main_a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -16393,20 +19178,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .D1(main_a7ddrphy_bitslip100[0]), + .D2(main_a7ddrphy_bitslip100[1]), + .D3(main_a7ddrphy_bitslip100[2]), + .D4(main_a7ddrphy_bitslip100[3]), + .D5(main_a7ddrphy_bitslip100[4]), + .D6(main_a7ddrphy_bitslip100[5]), + .D7(main_a7ddrphy_bitslip100[6]), + .D8(main_a7ddrphy_bitslip100[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay10), - .TQ(soc_a7ddrphy_dq_t10) + .OQ(main_a7ddrphy_dq_o_nodelay10), + .TQ(main_a7ddrphy_dq_t10) ); ISERDESE2 #( @@ -16422,16 +19207,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed10), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data10[7]), - .Q2(soc_a7ddrphy_dq_i_data10[6]), - .Q3(soc_a7ddrphy_dq_i_data10[5]), - .Q4(soc_a7ddrphy_dq_i_data10[4]), - .Q5(soc_a7ddrphy_dq_i_data10[3]), - .Q6(soc_a7ddrphy_dq_i_data10[2]), - .Q7(soc_a7ddrphy_dq_i_data10[1]), - .Q8(soc_a7ddrphy_dq_i_data10[0]) + .DDLY(main_a7ddrphy_dq_i_delayed10), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip101[7]), + .Q2(main_a7ddrphy_bitslip101[6]), + .Q3(main_a7ddrphy_bitslip101[5]), + .Q4(main_a7ddrphy_bitslip101[4]), + .Q5(main_a7ddrphy_bitslip101[3]), + .Q6(main_a7ddrphy_bitslip101[2]), + .Q7(main_a7ddrphy_bitslip101[1]), + .Q8(main_a7ddrphy_bitslip101[0]) ); IDELAYE2 #( @@ -16443,21 +19228,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_12 ( +) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed10) + .DATAOUT(main_a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_a7ddrphy_dq_o_nodelay10), - .T(soc_a7ddrphy_dq_t10), + .I(main_a7ddrphy_dq_o_nodelay10), + .T(main_a7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_a7ddrphy_dq_i_nodelay10) + .O(main_a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -16469,20 +19254,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .D1(main_a7ddrphy_bitslip110[0]), + .D2(main_a7ddrphy_bitslip110[1]), + .D3(main_a7ddrphy_bitslip110[2]), + .D4(main_a7ddrphy_bitslip110[3]), + .D5(main_a7ddrphy_bitslip110[4]), + .D6(main_a7ddrphy_bitslip110[5]), + .D7(main_a7ddrphy_bitslip110[6]), + .D8(main_a7ddrphy_bitslip110[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay11), - .TQ(soc_a7ddrphy_dq_t11) + .OQ(main_a7ddrphy_dq_o_nodelay11), + .TQ(main_a7ddrphy_dq_t11) ); ISERDESE2 #( @@ -16498,16 +19283,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed11), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data11[7]), - .Q2(soc_a7ddrphy_dq_i_data11[6]), - .Q3(soc_a7ddrphy_dq_i_data11[5]), - .Q4(soc_a7ddrphy_dq_i_data11[4]), - .Q5(soc_a7ddrphy_dq_i_data11[3]), - .Q6(soc_a7ddrphy_dq_i_data11[2]), - .Q7(soc_a7ddrphy_dq_i_data11[1]), - .Q8(soc_a7ddrphy_dq_i_data11[0]) + .DDLY(main_a7ddrphy_dq_i_delayed11), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip111[7]), + .Q2(main_a7ddrphy_bitslip111[6]), + .Q3(main_a7ddrphy_bitslip111[5]), + .Q4(main_a7ddrphy_bitslip111[4]), + .Q5(main_a7ddrphy_bitslip111[3]), + .Q6(main_a7ddrphy_bitslip111[2]), + .Q7(main_a7ddrphy_bitslip111[1]), + .Q8(main_a7ddrphy_bitslip111[0]) ); IDELAYE2 #( @@ -16519,21 +19304,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_13 ( +) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed11) + .DATAOUT(main_a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_a7ddrphy_dq_o_nodelay11), - .T(soc_a7ddrphy_dq_t11), + .I(main_a7ddrphy_dq_o_nodelay11), + .T(main_a7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_a7ddrphy_dq_i_nodelay11) + .O(main_a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -16545,20 +19330,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .D1(main_a7ddrphy_bitslip120[0]), + .D2(main_a7ddrphy_bitslip120[1]), + .D3(main_a7ddrphy_bitslip120[2]), + .D4(main_a7ddrphy_bitslip120[3]), + .D5(main_a7ddrphy_bitslip120[4]), + .D6(main_a7ddrphy_bitslip120[5]), + .D7(main_a7ddrphy_bitslip120[6]), + .D8(main_a7ddrphy_bitslip120[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay12), - .TQ(soc_a7ddrphy_dq_t12) + .OQ(main_a7ddrphy_dq_o_nodelay12), + .TQ(main_a7ddrphy_dq_t12) ); ISERDESE2 #( @@ -16574,16 +19359,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed12), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data12[7]), - .Q2(soc_a7ddrphy_dq_i_data12[6]), - .Q3(soc_a7ddrphy_dq_i_data12[5]), - .Q4(soc_a7ddrphy_dq_i_data12[4]), - .Q5(soc_a7ddrphy_dq_i_data12[3]), - .Q6(soc_a7ddrphy_dq_i_data12[2]), - .Q7(soc_a7ddrphy_dq_i_data12[1]), - .Q8(soc_a7ddrphy_dq_i_data12[0]) + .DDLY(main_a7ddrphy_dq_i_delayed12), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip121[7]), + .Q2(main_a7ddrphy_bitslip121[6]), + .Q3(main_a7ddrphy_bitslip121[5]), + .Q4(main_a7ddrphy_bitslip121[4]), + .Q5(main_a7ddrphy_bitslip121[3]), + .Q6(main_a7ddrphy_bitslip121[2]), + .Q7(main_a7ddrphy_bitslip121[1]), + .Q8(main_a7ddrphy_bitslip121[0]) ); IDELAYE2 #( @@ -16595,21 +19380,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_14 ( +) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed12) + .DATAOUT(main_a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_a7ddrphy_dq_o_nodelay12), - .T(soc_a7ddrphy_dq_t12), + .I(main_a7ddrphy_dq_o_nodelay12), + .T(main_a7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_a7ddrphy_dq_i_nodelay12) + .O(main_a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -16621,20 +19406,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .D1(main_a7ddrphy_bitslip130[0]), + .D2(main_a7ddrphy_bitslip130[1]), + .D3(main_a7ddrphy_bitslip130[2]), + .D4(main_a7ddrphy_bitslip130[3]), + .D5(main_a7ddrphy_bitslip130[4]), + .D6(main_a7ddrphy_bitslip130[5]), + .D7(main_a7ddrphy_bitslip130[6]), + .D8(main_a7ddrphy_bitslip130[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay13), - .TQ(soc_a7ddrphy_dq_t13) + .OQ(main_a7ddrphy_dq_o_nodelay13), + .TQ(main_a7ddrphy_dq_t13) ); ISERDESE2 #( @@ -16650,16 +19435,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed13), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data13[7]), - .Q2(soc_a7ddrphy_dq_i_data13[6]), - .Q3(soc_a7ddrphy_dq_i_data13[5]), - .Q4(soc_a7ddrphy_dq_i_data13[4]), - .Q5(soc_a7ddrphy_dq_i_data13[3]), - .Q6(soc_a7ddrphy_dq_i_data13[2]), - .Q7(soc_a7ddrphy_dq_i_data13[1]), - .Q8(soc_a7ddrphy_dq_i_data13[0]) + .DDLY(main_a7ddrphy_dq_i_delayed13), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip131[7]), + .Q2(main_a7ddrphy_bitslip131[6]), + .Q3(main_a7ddrphy_bitslip131[5]), + .Q4(main_a7ddrphy_bitslip131[4]), + .Q5(main_a7ddrphy_bitslip131[3]), + .Q6(main_a7ddrphy_bitslip131[2]), + .Q7(main_a7ddrphy_bitslip131[1]), + .Q8(main_a7ddrphy_bitslip131[0]) ); IDELAYE2 #( @@ -16671,21 +19456,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_15 ( +) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed13) + .DATAOUT(main_a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_a7ddrphy_dq_o_nodelay13), - .T(soc_a7ddrphy_dq_t13), + .I(main_a7ddrphy_dq_o_nodelay13), + .T(main_a7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_a7ddrphy_dq_i_nodelay13) + .O(main_a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -16697,20 +19482,20 @@ OSERDESE2 #( ) OSERDESE2_45 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .D1(main_a7ddrphy_bitslip140[0]), + .D2(main_a7ddrphy_bitslip140[1]), + .D3(main_a7ddrphy_bitslip140[2]), + .D4(main_a7ddrphy_bitslip140[3]), + .D5(main_a7ddrphy_bitslip140[4]), + .D6(main_a7ddrphy_bitslip140[5]), + .D7(main_a7ddrphy_bitslip140[6]), + .D8(main_a7ddrphy_bitslip140[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay14), - .TQ(soc_a7ddrphy_dq_t14) + .OQ(main_a7ddrphy_dq_o_nodelay14), + .TQ(main_a7ddrphy_dq_t14) ); ISERDESE2 #( @@ -16726,16 +19511,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed14), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data14[7]), - .Q2(soc_a7ddrphy_dq_i_data14[6]), - .Q3(soc_a7ddrphy_dq_i_data14[5]), - .Q4(soc_a7ddrphy_dq_i_data14[4]), - .Q5(soc_a7ddrphy_dq_i_data14[3]), - .Q6(soc_a7ddrphy_dq_i_data14[2]), - .Q7(soc_a7ddrphy_dq_i_data14[1]), - .Q8(soc_a7ddrphy_dq_i_data14[0]) + .DDLY(main_a7ddrphy_dq_i_delayed14), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip141[7]), + .Q2(main_a7ddrphy_bitslip141[6]), + .Q3(main_a7ddrphy_bitslip141[5]), + .Q4(main_a7ddrphy_bitslip141[4]), + .Q5(main_a7ddrphy_bitslip141[3]), + .Q6(main_a7ddrphy_bitslip141[2]), + .Q7(main_a7ddrphy_bitslip141[1]), + .Q8(main_a7ddrphy_bitslip141[0]) ); IDELAYE2 #( @@ -16747,21 +19532,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_16 ( +) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed14) + .DATAOUT(main_a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_a7ddrphy_dq_o_nodelay14), - .T(soc_a7ddrphy_dq_t14), + .I(main_a7ddrphy_dq_o_nodelay14), + .T(main_a7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_a7ddrphy_dq_i_nodelay14) + .O(main_a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -16773,20 +19558,20 @@ OSERDESE2 #( ) OSERDESE2_46 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .D1(main_a7ddrphy_bitslip150[0]), + .D2(main_a7ddrphy_bitslip150[1]), + .D3(main_a7ddrphy_bitslip150[2]), + .D4(main_a7ddrphy_bitslip150[3]), + .D5(main_a7ddrphy_bitslip150[4]), + .D6(main_a7ddrphy_bitslip150[5]), + .D7(main_a7ddrphy_bitslip150[6]), + .D8(main_a7ddrphy_bitslip150[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay15), - .TQ(soc_a7ddrphy_dq_t15) + .OQ(main_a7ddrphy_dq_o_nodelay15), + .TQ(main_a7ddrphy_dq_t15) ); ISERDESE2 #( @@ -16802,16 +19587,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed15), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data15[7]), - .Q2(soc_a7ddrphy_dq_i_data15[6]), - .Q3(soc_a7ddrphy_dq_i_data15[5]), - .Q4(soc_a7ddrphy_dq_i_data15[4]), - .Q5(soc_a7ddrphy_dq_i_data15[3]), - .Q6(soc_a7ddrphy_dq_i_data15[2]), - .Q7(soc_a7ddrphy_dq_i_data15[1]), - .Q8(soc_a7ddrphy_dq_i_data15[0]) + .DDLY(main_a7ddrphy_dq_i_delayed15), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip151[7]), + .Q2(main_a7ddrphy_bitslip151[6]), + .Q3(main_a7ddrphy_bitslip151[5]), + .Q4(main_a7ddrphy_bitslip151[4]), + .Q5(main_a7ddrphy_bitslip151[3]), + .Q6(main_a7ddrphy_bitslip151[2]), + .Q7(main_a7ddrphy_bitslip151[1]), + .Q8(main_a7ddrphy_bitslip151[0]) ); IDELAYE2 #( @@ -16823,134 +19608,182 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_17 ( +) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed15) + .DATAOUT(main_a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_a7ddrphy_dq_o_nodelay15), - .T(soc_a7ddrphy_dq_t15), + .I(main_a7ddrphy_dq_o_nodelay15), + .T(main_a7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_a7ddrphy_dq_i_nodelay15) + .O(main_a7ddrphy_dq_i_nodelay15) ); reg [25:0] storage[0:15]; reg [25:0] memdat; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_1[0:15]; reg [25:0] memdat_1; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_2[0:15]; reg [25:0] memdat_2; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_3[0:15]; reg [25:0] memdat_3; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_4[0:15]; reg [25:0] memdat_4; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_5[0:15]; reg [25:0] memdat_5; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_6[0:15]; reg [25:0] memdat_6; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [25:0] storage_7[0:15]; reg [25:0] memdat_7; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +FD FD( + .C(main_clkin), + .D(main_reset), + .Q(builder_reset0) +); + +FD FD_1( + .C(main_clkin), + .D(builder_reset0), + .Q(builder_reset1) +); + +FD FD_2( + .C(main_clkin), + .D(builder_reset1), + .Q(builder_reset2) +); + +FD FD_3( + .C(main_clkin), + .D(builder_reset2), + .Q(builder_reset3) +); + +FD FD_4( + .C(main_clkin), + .D(builder_reset3), + .Q(builder_reset4) +); + +FD FD_5( + .C(main_clkin), + .D(builder_reset4), + .Q(builder_reset5) +); + +FD FD_6( + .C(main_clkin), + .D(builder_reset5), + .Q(builder_reset6) +); + +FD FD_7( + .C(main_clkin), + .D(builder_reset6), + .Q(builder_reset7) +); PLLE2_ADV #( .CLKFBOUT_MULT(4'd8), @@ -16967,15 +19800,16 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb), - .CLKIN1(soc_clkin), - .RST(soc_reset), - .CLKFBOUT(vns_pll_fb), - .CLKOUT0(soc_clkout0), - .CLKOUT1(soc_clkout1), - .CLKOUT2(soc_clkout2), - .CLKOUT3(soc_clkout3), - .LOCKED(soc_locked) + .CLKFBIN(builder_pll_fb), + .CLKIN1(main_clkin), + .PWRDWN(main_power_down), + .RST(builder_reset7), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout0), + .CLKOUT1(main_clkout1), + .CLKOUT2(main_clkout2), + .CLKOUT3(main_clkout3), + .LOCKED(main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -16984,8 +19818,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16993,8 +19827,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(iodelay_rst) ); @@ -17004,8 +19838,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17013,8 +19847,8 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), .Q(sys_rst) ); @@ -17024,8 +19858,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17033,9 +19867,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -17044,8 +19878,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17053,9 +19887,9 @@ PLLE2_ADV #( ) FDPE_7 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) + .D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 0f92f5b..af8cf09 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d8658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -518,79 +518,78 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842a9c4 -fbe1fff8fbc1fff0 -f821ff51f8010010 -f88100d83be10020 +7c0802a63842aec4 +f8010010fbe1fff8 +f88100d8f821ff51 38800080f8a100e0 -7c651b78f8c100e8 -f8e100f038c100d8 -f90100f87fe3fb78 +f8c100e87c651b78 +38c100d838610020 +f90100f8f8e100f0 f9410108f9210100 -6000000048001e99 -7fe3fb787c7e1b78 -6000000048001881 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+0000000000000000 64656570736d654d -7025783020746120 -000000000a2e2e2e -203a736574697257 -7370624d20646c25 -000000000000000a -20203a7364616552 -7370624d20646c25 -000000000000000a +2820702520746120 +0000000000000000 +0000000a2e2e2e29 +2065746972572020 +00203a6465657073 +000000000000732f +2064616552202020 +00203a6465657073 20747365746d654d -2e70257830207461 -00000000000a2e2e -726520737562202d +0028207025207461 +7265207375622020 2520203a73726f72 00000a646c252f64 -652072646461202d +6520726464612020 25203a73726f7272 00000a646c252f64 -652061746164202d +6520617461642020 25203a73726f7272 00000a646c252f64 20747365746d654d 00000000000a4f4b 20747365746d654d -00000000000a4b4f +60000000000a4b4f +3736353433323130 +6665646362613938 +0000000000000000 +0000000000007830 0000000000000000 00000000000000ff 000000000000ffff @@ -1855,4 +2043,3 @@ e8010010ebc1fff0 0000ffffffffffff 00ffffffffffffff ffffffffffffffff -0000000000007830 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 0f99197..83d3225 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:20 +// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:20 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -48,1806 +48,2039 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg [13:0] soc_litedramcore_adr = 14'd0; -reg soc_litedramcore_we = 1'd0; -wire [31:0] soc_litedramcore_dat_w; -wire [31:0] soc_litedramcore_dat_r; -wire [29:0] soc_litedramcore_wishbone_adr; -wire [31:0] soc_litedramcore_wishbone_dat_w; -wire [31:0] soc_litedramcore_wishbone_dat_r; -wire [3:0] soc_litedramcore_wishbone_sel; -wire soc_litedramcore_wishbone_cyc; -wire soc_litedramcore_wishbone_stb; -reg soc_litedramcore_wishbone_ack = 1'd0; -wire soc_litedramcore_wishbone_we; -wire [2:0] soc_litedramcore_wishbone_cti; -wire [1:0] soc_litedramcore_wishbone_bte; -reg soc_litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_reset; -wire soc_locked; -wire soc_clkin; -wire soc_clkout0; -wire soc_clkout_buf0; -wire soc_clkout1; -wire soc_clkout_buf1; -wire soc_clkout2; -wire soc_clkout_buf2; -wire soc_clkout3; -wire soc_clkout_buf3; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_a7ddrphy_wlevel_en_storage = 1'd0; -reg soc_a7ddrphy_wlevel_en_re = 1'd0; -wire soc_a7ddrphy_wlevel_strobe_re; -wire soc_a7ddrphy_wlevel_strobe_r; -wire soc_a7ddrphy_wlevel_strobe_we; -reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_a7ddrphy_cdly_rst_re; -wire soc_a7ddrphy_cdly_rst_r; -wire soc_a7ddrphy_cdly_rst_we; -reg soc_a7ddrphy_cdly_rst_w = 1'd0; -wire soc_a7ddrphy_cdly_inc_re; -wire soc_a7ddrphy_cdly_inc_r; -wire soc_a7ddrphy_cdly_inc_we; -reg soc_a7ddrphy_cdly_inc_w = 1'd0; -reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; -reg soc_a7ddrphy_dly_sel_re = 1'd0; -wire soc_a7ddrphy_rdly_dq_rst_re; -wire soc_a7ddrphy_rdly_dq_rst_r; -wire soc_a7ddrphy_rdly_dq_rst_we; -reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_inc_re; -wire soc_a7ddrphy_rdly_dq_inc_r; -wire soc_a7ddrphy_rdly_dq_inc_we; -reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_re; -wire soc_a7ddrphy_rdly_dq_bitslip_r; -wire soc_a7ddrphy_rdly_dq_bitslip_we; -reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p0_address; -wire [2:0] soc_a7ddrphy_dfi_p0_bank; -wire soc_a7ddrphy_dfi_p0_cas_n; -wire soc_a7ddrphy_dfi_p0_cs_n; -wire soc_a7ddrphy_dfi_p0_ras_n; -wire soc_a7ddrphy_dfi_p0_we_n; -wire soc_a7ddrphy_dfi_p0_cke; -wire soc_a7ddrphy_dfi_p0_odt; -wire soc_a7ddrphy_dfi_p0_reset_n; -wire soc_a7ddrphy_dfi_p0_act_n; -wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; -wire soc_a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; -wire soc_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p1_address; -wire [2:0] soc_a7ddrphy_dfi_p1_bank; -wire soc_a7ddrphy_dfi_p1_cas_n; -wire soc_a7ddrphy_dfi_p1_cs_n; -wire soc_a7ddrphy_dfi_p1_ras_n; -wire soc_a7ddrphy_dfi_p1_we_n; -wire soc_a7ddrphy_dfi_p1_cke; -wire soc_a7ddrphy_dfi_p1_odt; -wire soc_a7ddrphy_dfi_p1_reset_n; -wire soc_a7ddrphy_dfi_p1_act_n; -wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; -wire soc_a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; -wire soc_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p2_address; -wire [2:0] soc_a7ddrphy_dfi_p2_bank; -wire soc_a7ddrphy_dfi_p2_cas_n; -wire soc_a7ddrphy_dfi_p2_cs_n; -wire soc_a7ddrphy_dfi_p2_ras_n; -wire soc_a7ddrphy_dfi_p2_we_n; -wire soc_a7ddrphy_dfi_p2_cke; -wire soc_a7ddrphy_dfi_p2_odt; -wire soc_a7ddrphy_dfi_p2_reset_n; -wire soc_a7ddrphy_dfi_p2_act_n; -wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; -wire soc_a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; -wire soc_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p3_address; -wire [2:0] soc_a7ddrphy_dfi_p3_bank; -wire soc_a7ddrphy_dfi_p3_cas_n; -wire soc_a7ddrphy_dfi_p3_cs_n; -wire soc_a7ddrphy_dfi_p3_ras_n; -wire soc_a7ddrphy_dfi_p3_we_n; -wire soc_a7ddrphy_dfi_p3_cke; -wire soc_a7ddrphy_dfi_p3_odt; -wire soc_a7ddrphy_dfi_p3_reset_n; -wire soc_a7ddrphy_dfi_p3_act_n; -wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; -wire soc_a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; -wire soc_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_a7ddrphy_sd_clk_se_nodelay; -reg soc_a7ddrphy_dqs_oe = 1'd0; -reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_a7ddrphy_dqspattern0; -wire soc_a7ddrphy_dqspattern1; -reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; -wire [1:0] soc_a7ddrphy_dqs_i; -wire [1:0] soc_a7ddrphy_dqs_i_delayed; -wire soc_a7ddrphy_dqs_o_no_delay0; -wire soc_a7ddrphy_dqs_t0; -wire soc_a7ddrphy0; -wire soc_a7ddrphy_dqs_o_no_delay1; -wire soc_a7ddrphy_dqs_t1; -wire soc_a7ddrphy1; -wire soc_a7ddrphy_dq_oe; -reg soc_a7ddrphy_dq_oe_delayed = 1'd0; -wire soc_a7ddrphy_dq_o_nodelay0; -wire soc_a7ddrphy_dq_i_nodelay0; -wire soc_a7ddrphy_dq_i_delayed0; -wire soc_a7ddrphy_dq_t0; -wire [7:0] soc_a7ddrphy_dq_i_data0; -wire [7:0] soc_a7ddrphy_bitslip0_i; -reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay1; -wire soc_a7ddrphy_dq_i_nodelay1; -wire soc_a7ddrphy_dq_i_delayed1; -wire soc_a7ddrphy_dq_t1; -wire [7:0] soc_a7ddrphy_dq_i_data1; -wire [7:0] soc_a7ddrphy_bitslip1_i; -reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay2; -wire soc_a7ddrphy_dq_i_nodelay2; -wire soc_a7ddrphy_dq_i_delayed2; -wire soc_a7ddrphy_dq_t2; -wire [7:0] soc_a7ddrphy_dq_i_data2; -wire [7:0] soc_a7ddrphy_bitslip2_i; -reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay3; -wire soc_a7ddrphy_dq_i_nodelay3; -wire soc_a7ddrphy_dq_i_delayed3; -wire soc_a7ddrphy_dq_t3; -wire [7:0] soc_a7ddrphy_dq_i_data3; -wire [7:0] soc_a7ddrphy_bitslip3_i; -reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay4; -wire soc_a7ddrphy_dq_i_nodelay4; -wire soc_a7ddrphy_dq_i_delayed4; -wire soc_a7ddrphy_dq_t4; -wire [7:0] soc_a7ddrphy_dq_i_data4; -wire [7:0] soc_a7ddrphy_bitslip4_i; -reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay5; -wire soc_a7ddrphy_dq_i_nodelay5; -wire soc_a7ddrphy_dq_i_delayed5; -wire soc_a7ddrphy_dq_t5; -wire [7:0] soc_a7ddrphy_dq_i_data5; -wire [7:0] soc_a7ddrphy_bitslip5_i; -reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay6; -wire soc_a7ddrphy_dq_i_nodelay6; -wire soc_a7ddrphy_dq_i_delayed6; -wire soc_a7ddrphy_dq_t6; -wire [7:0] soc_a7ddrphy_dq_i_data6; -wire [7:0] soc_a7ddrphy_bitslip6_i; -reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay7; -wire soc_a7ddrphy_dq_i_nodelay7; -wire soc_a7ddrphy_dq_i_delayed7; -wire soc_a7ddrphy_dq_t7; -wire [7:0] soc_a7ddrphy_dq_i_data7; -wire [7:0] soc_a7ddrphy_bitslip7_i; -reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay8; -wire soc_a7ddrphy_dq_i_nodelay8; -wire soc_a7ddrphy_dq_i_delayed8; -wire soc_a7ddrphy_dq_t8; -wire [7:0] soc_a7ddrphy_dq_i_data8; -wire [7:0] soc_a7ddrphy_bitslip8_i; -reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay9; -wire soc_a7ddrphy_dq_i_nodelay9; -wire soc_a7ddrphy_dq_i_delayed9; -wire soc_a7ddrphy_dq_t9; -wire [7:0] soc_a7ddrphy_dq_i_data9; -wire [7:0] soc_a7ddrphy_bitslip9_i; -reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay10; -wire soc_a7ddrphy_dq_i_nodelay10; -wire soc_a7ddrphy_dq_i_delayed10; -wire soc_a7ddrphy_dq_t10; -wire [7:0] soc_a7ddrphy_dq_i_data10; -wire [7:0] soc_a7ddrphy_bitslip10_i; -reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay11; -wire soc_a7ddrphy_dq_i_nodelay11; -wire soc_a7ddrphy_dq_i_delayed11; -wire soc_a7ddrphy_dq_t11; -wire [7:0] soc_a7ddrphy_dq_i_data11; -wire [7:0] soc_a7ddrphy_bitslip11_i; -reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay12; -wire soc_a7ddrphy_dq_i_nodelay12; -wire soc_a7ddrphy_dq_i_delayed12; -wire soc_a7ddrphy_dq_t12; -wire [7:0] soc_a7ddrphy_dq_i_data12; -wire [7:0] soc_a7ddrphy_bitslip12_i; -reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay13; -wire soc_a7ddrphy_dq_i_nodelay13; -wire soc_a7ddrphy_dq_i_delayed13; -wire soc_a7ddrphy_dq_t13; -wire [7:0] soc_a7ddrphy_dq_i_data13; -wire [7:0] soc_a7ddrphy_bitslip13_i; -reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay14; -wire soc_a7ddrphy_dq_i_nodelay14; -wire soc_a7ddrphy_dq_i_delayed14; -wire soc_a7ddrphy_dq_t14; -wire [7:0] soc_a7ddrphy_dq_i_data14; -wire [7:0] soc_a7ddrphy_bitslip14_i; -reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay15; -wire soc_a7ddrphy_dq_i_nodelay15; -wire soc_a7ddrphy_dq_i_delayed15; -wire soc_a7ddrphy_dq_t15; -wire [7:0] soc_a7ddrphy_dq_i_data15; -wire [7:0] soc_a7ddrphy_bitslip15_i; -reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0; -wire [7:0] soc_a7ddrphy_rddata_en; -reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_a7ddrphy_wrdata_en; -reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; -wire [13:0] soc_litedramcore_inti_p0_address; -wire [2:0] soc_litedramcore_inti_p0_bank; -reg soc_litedramcore_inti_p0_cas_n = 1'd1; -reg soc_litedramcore_inti_p0_cs_n = 1'd1; -reg soc_litedramcore_inti_p0_ras_n = 1'd1; -reg soc_litedramcore_inti_p0_we_n = 1'd1; -wire soc_litedramcore_inti_p0_cke; -wire soc_litedramcore_inti_p0_odt; -wire soc_litedramcore_inti_p0_reset_n; -reg soc_litedramcore_inti_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p0_wrdata; -wire soc_litedramcore_inti_p0_wrdata_en; -wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; -wire soc_litedramcore_inti_p0_rddata_en; -reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; -reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_inti_p1_address; -wire [2:0] soc_litedramcore_inti_p1_bank; -reg soc_litedramcore_inti_p1_cas_n = 1'd1; -reg soc_litedramcore_inti_p1_cs_n = 1'd1; -reg soc_litedramcore_inti_p1_ras_n = 1'd1; -reg soc_litedramcore_inti_p1_we_n = 1'd1; -wire soc_litedramcore_inti_p1_cke; -wire soc_litedramcore_inti_p1_odt; -wire soc_litedramcore_inti_p1_reset_n; -reg soc_litedramcore_inti_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p1_wrdata; -wire soc_litedramcore_inti_p1_wrdata_en; -wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; -wire soc_litedramcore_inti_p1_rddata_en; -reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; -reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_inti_p2_address; -wire [2:0] soc_litedramcore_inti_p2_bank; -reg soc_litedramcore_inti_p2_cas_n = 1'd1; -reg soc_litedramcore_inti_p2_cs_n = 1'd1; -reg soc_litedramcore_inti_p2_ras_n = 1'd1; -reg soc_litedramcore_inti_p2_we_n = 1'd1; -wire soc_litedramcore_inti_p2_cke; -wire soc_litedramcore_inti_p2_odt; -wire soc_litedramcore_inti_p2_reset_n; -reg soc_litedramcore_inti_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p2_wrdata; -wire soc_litedramcore_inti_p2_wrdata_en; -wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; -wire soc_litedramcore_inti_p2_rddata_en; -reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; -reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_inti_p3_address; -wire [2:0] soc_litedramcore_inti_p3_bank; -reg soc_litedramcore_inti_p3_cas_n = 1'd1; -reg soc_litedramcore_inti_p3_cs_n = 1'd1; -reg soc_litedramcore_inti_p3_ras_n = 1'd1; -reg soc_litedramcore_inti_p3_we_n = 1'd1; -wire soc_litedramcore_inti_p3_cke; -wire soc_litedramcore_inti_p3_odt; -wire soc_litedramcore_inti_p3_reset_n; -reg soc_litedramcore_inti_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p3_wrdata; -wire soc_litedramcore_inti_p3_wrdata_en; -wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; -wire soc_litedramcore_inti_p3_rddata_en; -reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; -reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [31:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [31:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [31:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [31:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_master_p0_address = 14'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [13:0] soc_litedramcore_master_p1_address = 14'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [13:0] soc_litedramcore_master_p2_address = 14'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [13:0] soc_litedramcore_master_p3_address = 14'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_re; -wire soc_litedramcore_phaseinjector0_command_issue_r; -wire soc_litedramcore_phaseinjector0_command_issue_we; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0; -wire soc_litedramcore_phaseinjector0_we; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_re; -wire soc_litedramcore_phaseinjector1_command_issue_r; -wire soc_litedramcore_phaseinjector1_command_issue_we; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0; -wire soc_litedramcore_phaseinjector1_we; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_re; -wire soc_litedramcore_phaseinjector2_command_issue_r; -wire soc_litedramcore_phaseinjector2_command_issue_we; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0; -wire soc_litedramcore_phaseinjector2_we; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_re; -wire soc_litedramcore_phaseinjector3_command_issue_r; -wire soc_litedramcore_phaseinjector3_command_issue_we; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0; -wire soc_litedramcore_phaseinjector3_we; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [20:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [20:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [20:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [20:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [20:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [20:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [20:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [20:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; -wire [127:0] soc_litedramcore_interface_rdata; -reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [20:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [20:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [20:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [20:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [20:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [20:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [20:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [20:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; -wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; -wire soc_litedramcore_choose_cmd_cmd_payload_is_read; -wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_req_cmd_payload_is_cmd; -wire soc_litedramcore_choose_req_cmd_payload_is_read; -wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; -reg [13:0] soc_litedramcore_nop_a = 14'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; -wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; -wire [31:0] soc_wb_bus_dat_r; -wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; -wire soc_wb_bus_stb; -wire soc_wb_bus_ack; -wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [23:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [127:0] soc_user_port_wdata_payload_data; -wire [15:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [127:0] soc_user_port_rdata_payload_data; -reg vns_state = 1'd0; -reg vns_next_state = 1'd0; -wire vns_pll_fb; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire vns_roundrobin0_request; -wire vns_roundrobin0_grant; -wire vns_roundrobin0_ce; -wire vns_roundrobin1_request; -wire vns_roundrobin1_grant; -wire vns_roundrobin1_ce; -wire vns_roundrobin2_request; -wire vns_roundrobin2_grant; -wire vns_roundrobin2_ce; -wire vns_roundrobin3_request; -wire vns_roundrobin3_grant; -wire vns_roundrobin3_ce; -wire vns_roundrobin4_request; -wire vns_roundrobin4_grant; -wire vns_roundrobin4_ce; -wire vns_roundrobin5_request; -wire vns_roundrobin5_grant; -wire vns_roundrobin5_ce; -wire vns_roundrobin6_request; -wire vns_roundrobin6_grant; -wire vns_roundrobin6_ce; -wire vns_roundrobin7_request; -wire vns_roundrobin7_grant; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [31:0] vns_interface0_bank_bus_dat_w; -reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; -wire vns_csrbank0_init_done0_re; -wire vns_csrbank0_init_done0_r; -wire vns_csrbank0_init_done0_we; -wire vns_csrbank0_init_done0_w; -wire vns_csrbank0_init_error0_re; -wire vns_csrbank0_init_error0_r; -wire vns_csrbank0_init_error0_we; -wire vns_csrbank0_init_error0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [31:0] vns_interface1_bank_bus_dat_w; -reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; -wire vns_csrbank1_half_sys8x_taps0_re; -wire [4:0] vns_csrbank1_half_sys8x_taps0_r; -wire vns_csrbank1_half_sys8x_taps0_we; -wire [4:0] vns_csrbank1_half_sys8x_taps0_w; -wire vns_csrbank1_wlevel_en0_re; -wire vns_csrbank1_wlevel_en0_r; -wire vns_csrbank1_wlevel_en0_we; -wire vns_csrbank1_wlevel_en0_w; -wire vns_csrbank1_dly_sel0_re; -wire [1:0] vns_csrbank1_dly_sel0_r; -wire vns_csrbank1_dly_sel0_we; -wire [1:0] vns_csrbank1_dly_sel0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [31:0] vns_interface2_bank_bus_dat_w; -reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; -wire vns_csrbank2_dfii_control0_re; -wire [3:0] vns_csrbank2_dfii_control0_r; -wire vns_csrbank2_dfii_control0_we; -wire [3:0] vns_csrbank2_dfii_control0_w; -wire vns_csrbank2_dfii_pi0_command0_re; -wire [5:0] vns_csrbank2_dfii_pi0_command0_r; -wire vns_csrbank2_dfii_pi0_command0_we; -wire [5:0] vns_csrbank2_dfii_pi0_command0_w; -wire vns_csrbank2_dfii_pi0_address0_re; -wire [13:0] vns_csrbank2_dfii_pi0_address0_r; -wire vns_csrbank2_dfii_pi0_address0_we; -wire [13:0] vns_csrbank2_dfii_pi0_address0_w; -wire vns_csrbank2_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; -wire vns_csrbank2_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; -wire vns_csrbank2_dfii_pi0_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; -wire vns_csrbank2_dfii_pi0_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; -wire vns_csrbank2_dfii_pi0_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_r; -wire vns_csrbank2_dfii_pi0_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_w; -wire vns_csrbank2_dfii_pi1_command0_re; -wire [5:0] vns_csrbank2_dfii_pi1_command0_r; -wire vns_csrbank2_dfii_pi1_command0_we; -wire [5:0] vns_csrbank2_dfii_pi1_command0_w; -wire vns_csrbank2_dfii_pi1_address0_re; -wire [13:0] vns_csrbank2_dfii_pi1_address0_r; -wire vns_csrbank2_dfii_pi1_address0_we; -wire [13:0] vns_csrbank2_dfii_pi1_address0_w; -wire vns_csrbank2_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; -wire vns_csrbank2_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; -wire vns_csrbank2_dfii_pi1_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; -wire vns_csrbank2_dfii_pi1_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; -wire vns_csrbank2_dfii_pi1_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_r; -wire vns_csrbank2_dfii_pi1_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_w; -wire vns_csrbank2_dfii_pi2_command0_re; -wire [5:0] vns_csrbank2_dfii_pi2_command0_r; -wire vns_csrbank2_dfii_pi2_command0_we; -wire [5:0] vns_csrbank2_dfii_pi2_command0_w; -wire vns_csrbank2_dfii_pi2_address0_re; -wire [13:0] vns_csrbank2_dfii_pi2_address0_r; -wire vns_csrbank2_dfii_pi2_address0_we; -wire [13:0] vns_csrbank2_dfii_pi2_address0_w; -wire vns_csrbank2_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; -wire vns_csrbank2_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; -wire vns_csrbank2_dfii_pi2_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; -wire vns_csrbank2_dfii_pi2_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; -wire vns_csrbank2_dfii_pi2_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_r; -wire vns_csrbank2_dfii_pi2_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_w; -wire vns_csrbank2_dfii_pi3_command0_re; -wire [5:0] vns_csrbank2_dfii_pi3_command0_r; -wire vns_csrbank2_dfii_pi3_command0_we; -wire [5:0] vns_csrbank2_dfii_pi3_command0_w; -wire vns_csrbank2_dfii_pi3_address0_re; -wire [13:0] vns_csrbank2_dfii_pi3_address0_r; -wire vns_csrbank2_dfii_pi3_address0_we; -wire [13:0] vns_csrbank2_dfii_pi3_address0_w; -wire vns_csrbank2_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; -wire vns_csrbank2_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; -wire vns_csrbank2_dfii_pi3_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; -wire vns_csrbank2_dfii_pi3_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; -wire vns_csrbank2_dfii_pi3_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_r; -wire vns_csrbank2_dfii_pi3_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_w; -wire vns_csrbank2_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [31:0] vns_dat_w; -wire [31:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [13:0] vns_rhs_array_muxed1 = 14'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [13:0] vns_rhs_array_muxed7 = 14'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [20:0] vns_rhs_array_muxed12 = 21'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [20:0] vns_rhs_array_muxed15 = 21'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [20:0] vns_rhs_array_muxed18 = 21'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [20:0] vns_rhs_array_muxed21 = 21'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [20:0] vns_rhs_array_muxed24 = 21'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [20:0] vns_rhs_array_muxed27 = 21'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [20:0] vns_rhs_array_muxed30 = 21'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [20:0] vns_rhs_array_muxed33 = 21'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [13:0] vns_array_muxed1 = 14'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [13:0] vns_array_muxed8 = 14'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [13:0] vns_array_muxed15 = 14'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [13:0] vns_array_muxed22 = 14'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl3_expr; +wire main_reset; +reg main_power_down = 1'd0; +wire main_locked; +wire main_clkin; +wire main_clkout0; +wire main_clkout_buf0; +wire main_clkout1; +wire main_clkout_buf1; +wire main_clkout2; +wire main_clkout_buf2; +wire main_clkout3; +wire main_clkout_buf3; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; +wire [13:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_ras_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_act_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire [13:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_ras_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_act_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire [13:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_ras_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_act_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire [13:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_ras_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_act_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +wire main_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_sd_clk_se_nodelay; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_t0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +wire main_a7ddrphy0; +wire main_a7ddrphy_dqs_o_no_delay1; +wire main_a7ddrphy_dqs_t1; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_t0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_t1; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_t2; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_t3; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_t4; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_t5; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_t6; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_t7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_t8; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_t9; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_t10; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_t11; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_t12; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_t13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_t14; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_t15; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [13:0] main_litedramcore_inti_p0_address; +wire [2:0] main_litedramcore_inti_p0_bank; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; +wire main_litedramcore_inti_p0_cke; +wire main_litedramcore_inti_p0_odt; +wire main_litedramcore_inti_p0_reset_n; +reg main_litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p0_wrdata; +wire main_litedramcore_inti_p0_wrdata_en; +wire [3:0] main_litedramcore_inti_p0_wrdata_mask; +wire main_litedramcore_inti_p0_rddata_en; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_inti_p1_address; +wire [2:0] main_litedramcore_inti_p1_bank; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; +wire main_litedramcore_inti_p1_cke; +wire main_litedramcore_inti_p1_odt; +wire main_litedramcore_inti_p1_reset_n; +reg main_litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p1_wrdata; +wire main_litedramcore_inti_p1_wrdata_en; +wire [3:0] main_litedramcore_inti_p1_wrdata_mask; +wire main_litedramcore_inti_p1_rddata_en; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_inti_p2_address; +wire [2:0] main_litedramcore_inti_p2_bank; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; +wire main_litedramcore_inti_p2_cke; +wire main_litedramcore_inti_p2_odt; +wire main_litedramcore_inti_p2_reset_n; +reg main_litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p2_wrdata; +wire main_litedramcore_inti_p2_wrdata_en; +wire [3:0] main_litedramcore_inti_p2_wrdata_mask; +wire main_litedramcore_inti_p2_rddata_en; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_inti_p3_address; +wire [2:0] main_litedramcore_inti_p3_bank; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; +wire main_litedramcore_inti_p3_cke; +wire main_litedramcore_inti_p3_odt; +wire main_litedramcore_inti_p3_reset_n; +reg main_litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p3_wrdata; +wire main_litedramcore_inti_p3_wrdata_en; +wire [3:0] main_litedramcore_inti_p3_wrdata_mask; +wire main_litedramcore_inti_p3_rddata_en; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_ras_n; +wire main_litedramcore_slave_p0_we_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_act_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p0_rddata_en; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_ras_n; +wire main_litedramcore_slave_p1_we_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_act_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p1_rddata_en; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_ras_n; +wire main_litedramcore_slave_p2_we_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_act_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p2_rddata_en; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_ras_n; +wire main_litedramcore_slave_p3_we_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_act_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +wire main_litedramcore_slave_p3_rddata_en; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] main_litedramcore_master_p0_address = 14'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p0_rddata; +wire main_litedramcore_master_p0_rddata_valid; +reg [13:0] main_litedramcore_master_p1_address = 14'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p1_rddata; +wire main_litedramcore_master_p1_rddata_valid; +reg [13:0] main_litedramcore_master_p2_address = 14'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p2_rddata; +wire main_litedramcore_master_p2_rddata_valid; +reg [13:0] main_litedramcore_master_p3_address = 14'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p3_rddata; +wire main_litedramcore_master_p3_rddata_valid; +wire main_litedramcore_sel; +wire main_litedramcore_cke; +wire main_litedramcore_odt; +wire main_litedramcore_reset_n; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_we; +wire [20:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_we; +wire [20:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_we; +wire [20:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_we; +wire [20:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_we; +wire [20:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_we; +wire [20:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_we; +wire [20:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_we; +wire [20:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_rdata_valid; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] main_litedramcore_interface_rdata; +reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +wire main_litedramcore_dfi_p0_odt; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p0_rddata; +wire main_litedramcore_dfi_p0_rddata_valid; +reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +wire main_litedramcore_dfi_p1_odt; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p1_rddata; +wire main_litedramcore_dfi_p1_rddata_valid; +reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +wire main_litedramcore_dfi_p2_odt; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p2_rddata; +wire main_litedramcore_dfi_p2_rddata_valid; +reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +wire main_litedramcore_dfi_p3_odt; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p3_rddata; +wire main_litedramcore_dfi_p3_rddata_valid; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_timer_wait; +wire main_litedramcore_timer_done0; +wire [9:0] main_litedramcore_timer_count0; +wire main_litedramcore_timer_done1; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_done0; +wire main_litedramcore_sequencer_start1; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_zqcs_timer_wait; +wire main_litedramcore_zqcs_timer_done0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +wire main_litedramcore_zqcs_timer_done1; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +wire main_litedramcore_bankmachine0_req_valid; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_we; +wire [20:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +wire main_litedramcore_bankmachine1_req_valid; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_we; +wire [20:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +wire main_litedramcore_bankmachine2_req_valid; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_we; +wire [20:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +wire main_litedramcore_bankmachine3_req_valid; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_we; +wire [20:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +wire main_litedramcore_bankmachine4_req_valid; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_we; +wire [20:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +wire main_litedramcore_bankmachine5_req_valid; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_we; +wire [20:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +wire main_litedramcore_bankmachine6_req_valid; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_we; +wire [20:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +wire main_litedramcore_bankmachine7_req_valid; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_we; +wire [20:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +wire main_litedramcore_ras_allowed; +wire main_litedramcore_cas_allowed; +wire [1:0] main_litedramcore_rdcmdphase; +wire [1:0] main_litedramcore_wrcmdphase; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire main_litedramcore_choose_cmd_ce; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire main_litedramcore_choose_req_ce; +reg [13:0] main_litedramcore_nop_a = 14'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +wire main_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; +wire main_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] main_litedramcore_tfawcon_count; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +wire main_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; +wire main_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_write_available; +reg main_litedramcore_en0 = 1'd0; +wire main_litedramcore_max_time0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; +wire main_litedramcore_max_time1; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire main_litedramcore_go_to_refresh; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; +wire [29:0] main_wb_bus_adr; +wire [31:0] main_wb_bus_dat_w; +wire [31:0] main_wb_bus_dat_r; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_cyc; +wire main_wb_bus_stb; +wire main_wb_bus_ack; +wire main_wb_bus_we; +wire [2:0] main_wb_bus_cti; +wire [1:0] main_wb_bus_bte; +wire main_wb_bus_err; +wire main_user_port_cmd_valid; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_payload_we; +wire [23:0] main_user_port_cmd_payload_addr; +wire main_user_port_wdata_valid; +wire main_user_port_wdata_ready; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_rdata_valid; +wire main_user_port_rdata_ready; +wire [127:0] main_user_port_rdata_payload_data; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +wire builder_pll_fb; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +wire builder_roundrobin0_request; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_ce; +wire builder_roundrobin1_request; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_ce; +wire builder_roundrobin2_request; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_ce; +wire builder_roundrobin3_request; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_ce; +wire builder_roundrobin4_request; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_ce; +wire builder_roundrobin5_request; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_ce; +wire builder_roundrobin6_request; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_ce; +wire builder_roundrobin7_request; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_ce; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [7:0] builder_litedramcore_dat_w = 8'd0; +wire [7:0] builder_litedramcore_dat_r; +wire [29:0] builder_litedramcore_wishbone_adr; +wire [31:0] builder_litedramcore_wishbone_dat_w; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] builder_litedramcore_wishbone_sel; +wire builder_litedramcore_wishbone_cyc; +wire builder_litedramcore_wishbone_stb; +reg builder_litedramcore_wishbone_ack = 1'd0; +wire builder_litedramcore_wishbone_we; +wire [2:0] builder_litedramcore_wishbone_cti; +wire [1:0] builder_litedramcore_wishbone_bte; +reg builder_litedramcore_wishbone_err = 1'd0; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [7:0] builder_interface0_bank_bus_dat_w; +reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_init_error0_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [7:0] builder_interface1_bank_bus_dat_w; +reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [7:0] builder_interface2_bank_bus_dat_w; +reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_address1_r; +reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_address1_w; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; +reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; +reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; +reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; +reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; +reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; +reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_address1_r; +reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_address1_w; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; +reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; +reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; +reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; +reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; +reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; +reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_address1_r; +reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_address1_w; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; +reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; +reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; +reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; +reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; +reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; +reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_address1_r; +reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_address1_w; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; +reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; +reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; +reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; +reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; +reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; +reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +wire builder_csrbank2_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [7:0] builder_csr_interconnect_dat_w; +wire [7:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [13:0] builder_rhs_array_muxed1 = 14'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [13:0] builder_rhs_array_muxed7 = 14'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [20:0] builder_rhs_array_muxed12 = 21'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [20:0] builder_rhs_array_muxed15 = 21'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [20:0] builder_rhs_array_muxed18 = 21'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [20:0] builder_rhs_array_muxed21 = 21'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [20:0] builder_rhs_array_muxed24 = 21'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [20:0] builder_rhs_array_muxed27 = 21'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [20:0] builder_rhs_array_muxed30 = 21'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [20:0] builder_rhs_array_muxed33 = 21'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [13:0] builder_array_muxed1 = 14'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [13:0] builder_array_muxed8 = 14'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [13:0] builder_array_muxed15 = 14'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [13:0] builder_array_muxed22 = 14'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl3; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; -assign soc_wb_bus_adr = wb_ctrl_adr; -assign soc_wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = soc_wb_bus_dat_r; -assign soc_wb_bus_sel = wb_ctrl_sel; -assign soc_wb_bus_cyc = wb_ctrl_cyc; -assign soc_wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = soc_wb_bus_ack; -assign soc_wb_bus_we = wb_ctrl_we; -assign soc_wb_bus_cti = wb_ctrl_cti; -assign soc_wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = soc_wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; -assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; -assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; -assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; -assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; -assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; +assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; +assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign main_reset = rst; +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - vns_next_state <= 1'd0; - vns_next_state <= vns_state; - case (vns_state) - 1'd1: begin - vns_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - vns_next_state <= 1'd1; - end - end - endcase + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on @@ -1857,14 +2090,39 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_wishbone_ack <= 1'd0; - case (vns_state) - 1'd1: begin - soc_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on @@ -1874,16 +2132,39 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_adr <= 14'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; - end - end - endcase + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -1893,108 +2174,84 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_we <= 1'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); - end - end - endcase + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end -assign soc_reset = rst; -assign pll_locked = soc_locked; -assign soc_clkin = clk; -assign iodelay_clk = soc_clkout_buf0; -assign sys_clk = soc_clkout_buf1; -assign sys4x_clk = soc_clkout_buf2; -assign sys4x_dqs_clk = soc_clkout_buf3; -assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p0_rddata <= 32'd0; - soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; - soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; - soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; - soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; - soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; - soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; - soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; - soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; - soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; - soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; - soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; - soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; - soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; - soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; - soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; - soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; - soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; - soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; - soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; - soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; - soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; - soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; - soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; - soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; - soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; - soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; - soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; - soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; - soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; - soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; - soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; - soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end // synthesis translate_off dummy_d_4 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); // synthesis translate_off reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p1_rddata <= 32'd0; - soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; - soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; - soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; - soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; - soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; - soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; - soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; - soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; - soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; - soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; - soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; - soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; - soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; - soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; - soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; - soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; - soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; - soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; - soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; - soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; - soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; - soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; - soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; - soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; - soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; - soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; - soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; - soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; - soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; - soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; - soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; - soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end // synthesis translate_off dummy_d_5 = dummy_s; // synthesis translate_on @@ -2004,39 +2261,33 @@ end reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p2_rddata <= 32'd0; - soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; - soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; - soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; - soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; - soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; - soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; - soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; - soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; - soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; - soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; - soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; - soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; - soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; - soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; - soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; - soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; - soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; - soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; - soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; - soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; - soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; - soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; - soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; - soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; - soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; - soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; - soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; - soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; - soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; - soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; - soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; - soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) + 1'd0: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_6 = dummy_s; // synthesis translate_on @@ -2046,97 +2297,105 @@ end reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p3_rddata <= 32'd0; - soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; - soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; - soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; - soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; - soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; - soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; - soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; - soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; - soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; - soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; - soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; - soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; - soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; - soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; - soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; - soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; - soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; - soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; - soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; - soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; - soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; - soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; - soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; - soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; - soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; - soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; - soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; - soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; - soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; - soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; - soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; - soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) + 1'd0: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_7 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; -assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; -assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; -assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; -assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; -assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; -assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; -assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; -assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; -assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; -assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; -assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; -assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; -assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; -assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; -assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; -assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; -assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqs_oe <= 1'd0; - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqs_oe <= 1'd1; - end else begin - soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; - end + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) + 1'd0: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_8 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); -assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); // synthesis translate_off reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqspattern_o0 <= 8'd0; - soc_a7ddrphy_dqspattern_o0 <= 7'd85; - if (soc_a7ddrphy_dqspattern0) begin - soc_a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (soc_a7ddrphy_dqspattern1) begin - soc_a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd0; - if (soc_a7ddrphy_wlevel_strobe_re) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd1; + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) + 1'd0: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end - end + 1'd1: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_9 = dummy_s; // synthesis translate_on @@ -2146,55 +2405,31 @@ end reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip0_o <= 8'd0; - case (soc_a7ddrphy_bitslip0_value) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase // synthesis translate_off @@ -2206,55 +2441,31 @@ end reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip1_o <= 8'd0; - case (soc_a7ddrphy_bitslip1_value) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase // synthesis translate_off @@ -2266,55 +2477,31 @@ end reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip2_o <= 8'd0; - case (soc_a7ddrphy_bitslip2_value) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase // synthesis translate_off @@ -2326,55 +2513,31 @@ end reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip3_o <= 8'd0; - case (soc_a7ddrphy_bitslip3_value) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase // synthesis translate_off @@ -2386,55 +2549,31 @@ end reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip4_o <= 8'd0; - case (soc_a7ddrphy_bitslip4_value) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase // synthesis translate_off @@ -2446,55 +2585,31 @@ end reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip5_o <= 8'd0; - case (soc_a7ddrphy_bitslip5_value) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase // synthesis translate_off @@ -2506,55 +2621,31 @@ end reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip6_o <= 8'd0; - case (soc_a7ddrphy_bitslip6_value) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase // synthesis translate_off @@ -2566,55 +2657,31 @@ end reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip7_o <= 8'd0; - case (soc_a7ddrphy_bitslip7_value) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase // synthesis translate_off @@ -2626,55 +2693,31 @@ end reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip8_o <= 8'd0; - case (soc_a7ddrphy_bitslip8_value) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase // synthesis translate_off @@ -2686,55 +2729,31 @@ end reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip9_o <= 8'd0; - case (soc_a7ddrphy_bitslip9_value) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase // synthesis translate_off @@ -2746,55 +2765,31 @@ end reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip10_o <= 8'd0; - case (soc_a7ddrphy_bitslip10_value) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase // synthesis translate_off @@ -2806,55 +2801,31 @@ end reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip11_o <= 8'd0; - case (soc_a7ddrphy_bitslip11_value) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase // synthesis translate_off @@ -2866,55 +2837,31 @@ end reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip12_o <= 8'd0; - case (soc_a7ddrphy_bitslip12_value) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase // synthesis translate_off @@ -2926,55 +2873,31 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip13_o <= 8'd0; - case (soc_a7ddrphy_bitslip13_value) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase // synthesis translate_off @@ -2986,55 +2909,31 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip14_o <= 8'd0; - case (soc_a7ddrphy_bitslip14_value) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase // synthesis translate_off @@ -3046,200 +2945,69 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip15_o <= 8'd0; - case (soc_a7ddrphy_bitslip15_value) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase // synthesis translate_off dummy_d_25 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; -assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; -assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; -assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; -assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; -assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; -assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; -assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; -assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; -assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; -assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; -assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; -assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; -assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; -assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; -assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; -assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; -assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; -assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; -assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; -assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; -assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; -assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; -assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; -assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; -assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; -assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; -assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; -assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; -assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; -assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; -assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; -assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; -assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; -assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; -assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; -assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; -assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; -assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; -assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; -assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; -assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; -assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; -assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; -assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; -assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; -assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; -assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; -assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; -assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; -assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; -assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; -assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; -assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; -assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; -assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; -assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; -assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; -assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; -assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; -assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; -assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; -assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; -assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; -assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; -assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; -assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; -assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; -assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; -assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; -assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; -assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; -assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; -assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; -assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; -assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; -assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; -assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; -assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; -assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; -assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; -assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; -assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; -assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; -assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; -assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; -assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; -assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; -assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; -assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; -assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; -assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; -assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; -assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; -assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; -assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; -assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; -assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; -assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; -assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; -assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; -assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; -assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; -assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; -assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; -assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; -assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; -assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; -assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; -assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; -assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; -assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; -assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; -assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; -assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; -assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; -assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; -assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; -assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; -assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; -assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; -assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; -assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; -assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; -assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; -assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; -assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; -assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; - end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; - end + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) + 1'd0: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_26 = dummy_s; // synthesis translate_on @@ -3249,12 +3017,33 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; - end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; - end + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) + 1'd0: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_27 = dummy_s; // synthesis translate_on @@ -3264,12 +3053,33 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; - end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; - end + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) + 1'd0: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_28 = dummy_s; // synthesis translate_on @@ -3279,11 +3089,33 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; - end + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) + 1'd0: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_29 = dummy_s; // synthesis translate_on @@ -3293,12 +3125,33 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; - end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; - end + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) + 1'd0: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_30 = dummy_s; // synthesis translate_on @@ -3308,11 +3161,33 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) + 1'd0: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_31 = dummy_s; // synthesis translate_on @@ -3322,12 +3197,33 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; - end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; - end + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) + 1'd0: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_32 = dummy_s; // synthesis translate_on @@ -3337,12 +3233,33 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; - end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; - end + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) + 1'd0: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_33 = dummy_s; // synthesis translate_on @@ -3352,12 +3269,33 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_address <= 14'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; - end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; - end + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) + 1'd0: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_34 = dummy_s; // synthesis translate_on @@ -3367,12 +3305,33 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; - end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; - end + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) + 1'd0: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_35 = dummy_s; // synthesis translate_on @@ -3382,12 +3341,33 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; - end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; - end + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) + 1'd0: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_36 = dummy_s; // synthesis translate_on @@ -3397,12 +3377,33 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; - end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; - end + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) + 1'd0: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_37 = dummy_s; // synthesis translate_on @@ -3412,26 +3413,69 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; - end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; - end -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on -end - + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) + 1'd0: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; + end + endcase +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + // synthesis translate_off reg dummy_d_39; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; - end else begin - end + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) + 1'd0: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_39 = dummy_s; // synthesis translate_on @@ -3441,12 +3485,33 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; - end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; - end + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) + 1'd0: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_40 = dummy_s; // synthesis translate_on @@ -3456,25 +3521,175 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end else begin - end + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) + 1'd0: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_41 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_42; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + main_litedramcore_master_p0_address <= 14'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3485,11 +3700,11 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3500,11 +3715,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3515,11 +3730,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3530,11 +3745,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3545,10 +3760,10 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin - soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3559,11 +3774,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3574,10 +3789,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin - soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3588,11 +3803,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3603,11 +3818,11 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3618,11 +3833,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_address <= 14'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; + main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3633,11 +3848,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; + main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3648,11 +3863,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; + main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3663,11 +3878,10 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + main_litedramcore_inti_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3678,10 +3892,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end else begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3692,11 +3907,10 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + main_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3707,10 +3921,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end else begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3721,11 +3936,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3736,11 +3951,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + main_litedramcore_master_p1_address <= 14'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3751,11 +3966,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3766,11 +3981,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3781,11 +3996,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3796,11 +4011,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3811,10 +4026,10 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3825,11 +4040,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3840,10 +4055,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin - soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3854,11 +4069,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3869,10 +4084,11 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end else begin + main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3883,11 +4099,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3898,11 +4114,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_address <= 14'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3913,11 +4129,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; + main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3928,10 +4144,10 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_inti_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3942,11 +4158,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3957,11 +4173,10 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + main_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3972,11 +4187,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3987,10 +4202,11 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end else begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -4001,11 +4217,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + main_litedramcore_master_p2_address <= 14'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -4016,10 +4232,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end else begin + main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -4030,11 +4247,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; + main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -4045,11 +4262,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; + main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -4060,11 +4277,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -4075,11 +4292,10 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -4090,11 +4306,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; + main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -4105,10 +4321,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -4119,11 +4335,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; + main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -4134,10 +4350,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_inti_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -4148,11 +4364,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -4163,11 +4379,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -4178,11 +4394,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_address <= 14'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -4193,11 +4409,10 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -4208,11 +4423,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; + main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -4223,11 +4438,10 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + main_litedramcore_inti_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4238,11 +4452,11 @@ end reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -4253,11 +4467,10 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -4268,11 +4481,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -4283,38 +4496,26 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; // synthesis translate_off reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + main_litedramcore_master_p3_address <= 14'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end else begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4325,11 +4526,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4340,11 +4541,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4355,32 +4556,26 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_101 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; -assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; -assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); -assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); -assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; -assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; + main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4391,11 +4586,10 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin - soc_litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4406,11 +4600,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; + main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4421,32 +4615,25 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_105 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; -assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; -assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); -assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); -assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; -assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; + main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4457,11 +4644,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4472,11 +4659,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end else begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4487,32 +4674,26 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_109 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; -assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; -assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); -assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); -assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; -assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4523,11 +4704,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4538,11 +4719,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end else begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4553,126 +4734,39 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; end else begin - soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; -assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; -assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); -assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); -assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; -assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; -assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; -assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; -assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; -assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; -assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; -assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; -assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; -assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; -assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; -assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; -assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; -assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; -assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; -assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; -assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; -assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; -assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; -assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; -assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; -assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; -assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; -assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; -assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; -assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; -assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; -assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; -assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; -assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; -assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; -assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; -assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; -assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; -assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; -assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; -assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; -assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; -assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; -assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; -assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; -assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; -assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; -assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; -assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; -assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; -assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; -assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; -assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; -assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; -assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; -assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; -assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; -assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; -assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; -assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; -assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; -assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; -assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); -assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; -assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; -assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; -assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); -assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); -assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; -assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; -assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); -assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); -assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); -assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; -assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; +assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p2_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p3_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p0_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p1_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p2_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p3_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; // synthesis translate_off reg dummy_d_114; // synthesis translate_on always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (soc_litedramcore_wants_refresh) begin - vns_refresher_next_state <= 1'd1; - end - end - end - endcase + main_litedramcore_inti_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_114 = dummy_s; // synthesis translate_on @@ -4682,23 +4776,12 @@ end reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); + end else begin + main_litedramcore_inti_p0_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_115 = dummy_s; // synthesis translate_on @@ -4708,26 +4791,12 @@ end reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; + end // synthesis translate_off dummy_d_116 = dummy_s; // synthesis translate_on @@ -4737,207 +4806,99 @@ end reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + end else begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]); +assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); +assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase + main_litedramcore_inti_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_118 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; -assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); -assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + main_litedramcore_inti_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_119 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); -assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); -assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); - end + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + end else begin + main_litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_120 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_inti_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + main_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_121 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); +assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]); +assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); +assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_122; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end - end else begin - vns_bankmachine0_next_state <= 1'd1; - end - end else begin - vns_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase + main_litedramcore_inti_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_122 = dummy_s; // synthesis translate_on @@ -4947,30 +4908,12 @@ end reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_123 = dummy_s; // synthesis translate_on @@ -4980,45 +4923,12 @@ end reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end // synthesis translate_off dummy_d_124 = dummy_s; // synthesis translate_on @@ -5028,207 +4938,475 @@ end reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); + end else begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_125 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]); +assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); +assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_126; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_inti_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + end else begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + end else begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]); +assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]); +assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end end 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; + end else begin + builder_refresher_next_state <= 1'd0; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; + end end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin + default: begin + if (1'd1) begin + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; + end + end end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_130 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_131; +// synthesis translate_on +always @(*) begin + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end - 3'd7: begin + 2'd2: begin end - 4'd8: begin + 2'd3: begin end default: begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_132; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end - 3'd4: begin - end - 3'd5: begin + default: begin end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) + 1'd1: begin end - 3'd7: begin + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end end - 4'd8: begin + 2'd3: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_134; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end default: begin end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_129; +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_138; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin + builder_bankmachine0_next_state <= 1'd1; end end else begin + builder_bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin @@ -5245,30 +5423,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5282,16 +5456,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5309,15 +5483,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5327,21 +5498,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5354,35 +5531,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5399,13 +5564,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5417,16 +5582,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5444,14 +5609,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5462,171 +5627,131 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; -assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); -assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_136; +reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); -assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); -assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_137; +reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin end - end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_139; +reg dummy_d_147; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5634,9 +5759,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5647,30 +5769,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_149; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5683,12 +5814,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end end else begin end end else begin @@ -5698,26 +5832,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5731,26 +5865,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5761,71 +5898,193 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_144; +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_155; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; + end end else begin + builder_bankmachine1_next_state <= 1'd1; end end else begin + builder_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5842,26 +6101,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5872,42 +6131,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5920,33 +6161,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5960,17 +6212,20 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5987,14 +6242,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6005,21 +6260,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6032,41 +6290,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6077,34 +6327,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6122,14 +6357,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6140,171 +6375,61 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); -assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_156; +reg dummy_d_164; // synthesis translate_on always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin end end else begin - vns_bankmachine2_next_state <= 1'd1; end end else begin - vns_bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6312,9 +6437,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6325,30 +6447,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_166; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6361,12 +6492,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -6376,26 +6510,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_167; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6409,26 +6543,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6439,101 +6576,187 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_161; +reg dummy_d_169; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end + main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end - endcase + end // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_162; +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; + end + end else begin + builder_bankmachine2_next_state <= 1'd1; + end + end else begin + builder_bankmachine2_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6550,14 +6773,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6568,23 +6791,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6601,30 +6824,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6638,16 +6857,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6665,15 +6884,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6683,21 +6899,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -6710,35 +6932,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6755,13 +6965,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6773,21 +6983,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6800,189 +7013,56 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; -assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); -assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); -assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); -assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_173; +reg dummy_d_180; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; - end + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; - end - end else begin - vns_bankmachine3_next_state <= 1'd1; - end - end else begin - vns_bankmachine3_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6990,9 +7070,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7003,30 +7080,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7039,12 +7125,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -7054,24 +7143,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin end @@ -7084,29 +7170,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7120,21 +7221,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_185; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7147,12 +7254,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -7162,107 +7269,178 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_179; +reg dummy_d_186; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_186 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_187; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end - endcase + end // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_180; +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_189; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; end end else begin + builder_bankmachine3_next_state <= 1'd1; end end else begin + builder_bankmachine3_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7279,30 +7457,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7316,16 +7490,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7343,14 +7517,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7361,16 +7535,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7388,15 +7562,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7406,21 +7577,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7433,35 +7610,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -7478,14 +7643,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7496,181 +7661,63 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); -assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); -assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_190; +reg dummy_d_196; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; - end - end else begin - vns_bankmachine4_next_state <= 1'd1; - end - end else begin - vns_bankmachine4_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7684,27 +7731,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7717,12 +7758,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -7732,24 +7776,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; - end end 3'd4: begin end @@ -7762,29 +7803,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7795,19 +7848,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7815,6 +7883,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7825,41 +7896,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7873,74 +7932,193 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_197; +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_203 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_204; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_206; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; end end else begin + builder_bankmachine4_next_state <= 1'd1; end end else begin + builder_bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -7957,30 +8135,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7994,16 +8168,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8021,15 +8195,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8039,21 +8210,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -8066,35 +8243,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8111,13 +8276,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8129,21 +8294,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8156,189 +8324,101 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; -assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); -assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); -assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); -assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_205; +reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end - end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_207; +reg dummy_d_214; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8346,9 +8426,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8359,30 +8436,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8395,12 +8481,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -8410,24 +8499,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin end @@ -8440,29 +8526,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8476,21 +8577,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8503,12 +8610,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -8518,107 +8625,178 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_213; +reg dummy_d_220; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end - endcase + end // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_214; +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_223; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -8635,30 +8813,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8672,16 +8846,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8699,15 +8873,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8717,21 +8888,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -8744,35 +8921,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8789,13 +8954,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8807,21 +8972,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8834,189 +9002,56 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_221; +reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); -assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); -assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on -always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; - end + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; - end - end else begin - vns_bankmachine6_next_state <= 1'd1; - end - end else begin - vns_bankmachine6_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9024,8 +9059,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -9040,27 +9075,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9073,12 +9102,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -9088,24 +9120,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; - end end 3'd4: begin end @@ -9118,29 +9147,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9151,19 +9192,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9181,12 +9237,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -9196,26 +9255,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9229,75 +9288,191 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_231; +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_240; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; end end else begin + builder_bankmachine6_next_state <= 1'd1; end end else begin + builder_bankmachine6_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9310,33 +9485,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9350,23 +9536,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9377,34 +9566,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9422,15 +9596,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9440,21 +9611,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -9467,35 +9644,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9512,14 +9677,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9530,181 +9695,63 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; -assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); -assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); -assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); -assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_241; +reg dummy_d_247; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; - end - end else begin - vns_bankmachine7_next_state <= 1'd1; - end - end else begin - vns_bankmachine7_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9718,27 +9765,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9751,12 +9792,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -9766,24 +9810,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end end 3'd4: begin end @@ -9796,29 +9837,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9829,19 +9882,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9849,6 +9917,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9859,41 +9930,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9907,74 +9966,193 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_248; +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_257; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; end end else begin + builder_bankmachine7_next_state <= 1'd1; end end else begin + builder_bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9991,30 +10169,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_259; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -10028,16 +10202,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_260; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10055,15 +10229,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10073,21 +10244,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_261; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -10100,35 +10277,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -10145,13 +10310,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -10163,16 +10328,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10190,14 +10355,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10208,380 +10373,672 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); -assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); -assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; -assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); -assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); -assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); -assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); -assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); -assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); -assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on -always @(*) begin - soc_litedramcore_choose_cmd_valids <= 8'd0; - soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; -assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on -always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; - end -// synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; - end + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; - end + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_267; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on -end - + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase // synthesis translate_off -reg dummy_d_261; + dummy_d_267 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_268; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_272; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; +// synthesis translate_off + dummy_d_272 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_274; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_276; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_264; +reg dummy_d_277; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_278; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_279; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_valids <= 8'd0; - soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; -assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; // synthesis translate_off -reg dummy_d_268; +reg dummy_d_282; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_269; +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_284; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_285; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); -assign soc_litedramcore_dfi_p0_reset_n = 1'd1; -assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; -assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; -assign soc_litedramcore_dfi_p1_reset_n = 1'd1; -assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; -assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; -assign soc_litedramcore_dfi_p2_reset_n = 1'd1; -assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; -assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; -assign soc_litedramcore_dfi_p3_reset_n = 1'd1; -assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; -assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; -assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_271; +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; + end +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_287; // synthesis translate_on always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (soc_litedramcore_read_available) begin - if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (soc_litedramcore_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (soc_litedramcore_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - vns_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - vns_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - vns_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - vns_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - vns_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - vns_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - vns_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (soc_litedramcore_write_available) begin - if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_288; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10602,22 +11059,24 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_289; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10638,24 +11097,108 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel3 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_292; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin @@ -10678,25 +11221,25 @@ always @(*) begin end default: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_293; // synthesis translate_on always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_en1 <= 1'd1; + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10720,20 +11263,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_294; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end end 2'd2: begin + main_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10752,25 +11302,30 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_295; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10789,22 +11344,27 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_296; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end 2'd2: begin end @@ -10825,22 +11385,34 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel1 <= 1'd1; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_297; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd1; + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end 2'd2: begin end @@ -10861,24 +11433,30 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_280; +reg dummy_d_298; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end 2'd2: begin @@ -10902,2965 +11480,4978 @@ always @(*) begin default: begin if (1'd0) begin end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12; +assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15; +assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18; +assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21; +assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24; +assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27; +assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30; +assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33; +assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + end + default: begin + main_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + end + default: begin + main_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_next_state <= 2'd2; + end + 2'd2: begin + builder_next_state <= 1'd0; + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value0 <= 8'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value1 <= 14'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; end end endcase // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_dat_r <= 32'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end +assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; +assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r; +assign builder_litedramcore_wishbone_sel = main_wb_bus_sel; +assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc; +assign builder_litedramcore_wishbone_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_litedramcore_wishbone_ack; +assign builder_litedramcore_wishbone_we = main_wb_bus_we; +assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; +assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_litedramcore_wishbone_err; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_416; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_416 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_417; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_417 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_418; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_418 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_419; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_419 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_420; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_420 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_421; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_421 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_422; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_422 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_423; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_423 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_424; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_424 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_425; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_425 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_426; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_426 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_427; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_427 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_428; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_428 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_429; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_429 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_430; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_430 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_431; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_431 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_432; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_432 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_433; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_433 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_434; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_434 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_435; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_435 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_436; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_436 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_437; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_437 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_438; // synthesis translate_on always @(*) begin - soc_litedramcore_en0 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_en0 <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_438 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_439; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_439 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_283; +reg dummy_d_440; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - endcase + builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_440 = dummy_s; // synthesis translate_on end -assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); -assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); -assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); -assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); -assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); -assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); -assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); -assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); -assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); -assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; +assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_441; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; - end - default: begin - soc_litedramcore_interface_wdata <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_441 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_285; +reg dummy_d_442; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; - end - default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_442 = dummy_s; // synthesis translate_on end -assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; -assign vns_roundrobin0_grant = 1'd0; -assign vns_roundrobin1_grant = 1'd0; -assign vns_roundrobin2_grant = 1'd0; -assign vns_roundrobin3_grant = 1'd0; -assign vns_roundrobin4_grant = 1'd0; -assign vns_roundrobin5_grant = 1'd0; -assign vns_roundrobin6_grant = 1'd0; -assign vns_roundrobin7_grant = 1'd0; -assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; -assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; -assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; -assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; -assign soc_litedramcore_wishbone_we = soc_wb_bus_we; -assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; -assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = soc_litedramcore_wishbone_err; -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_done0_w = soc_init_done_storage; -assign vns_csrbank0_init_error0_w = soc_init_error_storage; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; -assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0]; -assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; -assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); -assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; -assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[13:0]; -assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[13:0]; -assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[13:0]; -assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[13:0]; -assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign soc_litedramcore_sel = soc_litedramcore_storage[0]; -assign soc_litedramcore_cke = soc_litedramcore_storage[1]; -assign soc_litedramcore_odt = soc_litedramcore_storage[2]; -assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; -assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; -assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; -assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0]; -assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0]; -assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we; -assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; -assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0]; -assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0]; -assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we; -assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; -assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0]; -assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0]; -assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we; -assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; -assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0]; -assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0]; -assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we; -assign vns_adr = soc_litedramcore_adr; -assign vns_we = soc_litedramcore_we; -assign vns_dat_w = soc_litedramcore_dat_w; -assign soc_litedramcore_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_286; +reg dummy_d_443; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_443 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_444; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_444 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_445; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_445 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_446; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_446 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; +assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; +assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; +assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; +assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csr_interconnect_adr = builder_litedramcore_adr; +assign builder_csr_interconnect_we = builder_litedramcore_we; +assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; +assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r; +assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_447; +// synthesis translate_on +always @(*) begin + builder_rhs_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_447 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_448; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 14'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed1 <= 14'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_448 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_449; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_449 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_450; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_450 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_451; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_451 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_452; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_452 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_453; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_453 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_454; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_454 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_455; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_455 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_456; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6]; end default: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_456 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_457; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 14'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed7 <= 14'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_457 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_458; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_458 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_459; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_459 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_460; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_460 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_461; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_461 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_462; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_462 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_463; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_463 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_464; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_464 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_465; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 21'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed12 <= 21'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_465 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_466; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_466 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_467; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_467 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_468; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 21'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed15 <= 21'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_468 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_469; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_469 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_470; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_470 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_471; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 21'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed18 <= 21'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_471 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_472; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_472 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_473; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_473 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_474; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 21'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed21 <= 21'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_474 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_475; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_475 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_476; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_476 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_477; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 21'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed24 <= 21'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_477 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_478; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_478 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_479; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_479 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_480; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 21'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed27 <= 21'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_480 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_481; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_481 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_482; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_482 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_483; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 21'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed30 <= 21'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_483 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_484; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_484 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_485; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_485 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_486; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 21'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed33 <= 21'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_486 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_487; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_487 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_488; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_488 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_489; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed0 <= 3'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_489 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_490; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 14'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed1 <= 14'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_litedramcore_nop_a; + builder_array_muxed1 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_490 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_491; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed2 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + builder_array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_491 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_492; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed3 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + builder_array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_492 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_493; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed4 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + builder_array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_493 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_494; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed5 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + builder_array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_494 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_495; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed6 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + builder_array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_495 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_496; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed7 <= 3'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_496 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_497; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 14'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed8 <= 14'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_litedramcore_nop_a; + builder_array_muxed8 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_497 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_498; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed9 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + builder_array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_498 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_499; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed10 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + builder_array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_499 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_500; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed11 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + builder_array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_500 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_501; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed12 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + builder_array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_501 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_502; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed13 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + builder_array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_502 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_503; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed14 <= 3'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_503 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_504; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 14'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed15 <= 14'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_litedramcore_nop_a; + builder_array_muxed15 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_504 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_505; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed16 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + builder_array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_505 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_506; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed17 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + builder_array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_506 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_507; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed18 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + builder_array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_507 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_508; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed19 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + builder_array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_508 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_509; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed20 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + builder_array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_509 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_510; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed21 <= 3'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_510 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_511; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 14'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed22 <= 14'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_litedramcore_nop_a; + builder_array_muxed22 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_511 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_512; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed23 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + builder_array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_512 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_513; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed24 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + builder_array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_513 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_514; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed25 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + builder_array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_514 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_515; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed26 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + builder_array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_515 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_516; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed27 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + builder_array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_516 = dummy_s; // synthesis translate_on end -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - soc_ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - vns_state <= vns_next_state; - soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; - soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; - soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; + end + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; + end + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; + end + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; + end + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; + end + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; + end + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; + end + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip0_value <= 1'd0; + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); end - soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip1_value <= 1'd0; + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip2_value <= 1'd0; + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip3_value <= 1'd0; + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip4_value <= 1'd0; + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip5_value <= 1'd0; + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip6_value <= 1'd0; + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip7_value <= 1'd0; + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip8_value <= 1'd0; + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip9_value <= 1'd0; + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip10_value <= 1'd0; + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip11_value <= 1'd0; + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip12_value <= 1'd0; + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip13_value <= 1'd0; + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip14_value <= 1'd0; + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip15_value <= 1'd0; + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]}; - if (soc_litedramcore_inti_p0_rddata_valid) begin - soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - if (soc_litedramcore_inti_p1_rddata_valid) begin - soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - if (soc_litedramcore_inti_p2_rddata_valid) begin - soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - if (soc_litedramcore_inti_p3_rddata_valid) begin - soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin - soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; + end + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; + end + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; + end + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; + end + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; + end + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; + end + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; + end + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; + end + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; + end + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; + end + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; + end + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_inti_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata; + end + if (main_litedramcore_inti_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata; + end + if (main_litedramcore_inti_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata; + end + if (main_litedramcore_inti_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - soc_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - soc_litedramcore_postponer_req_o <= 1'd0; - if (soc_litedramcore_postponer_req_i) begin - soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); - if ((soc_litedramcore_postponer_count == 1'd0)) begin - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (soc_litedramcore_sequencer_start0) begin - soc_litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_litedramcore_sequencer_done1) begin - if ((soc_litedramcore_sequencer_count != 1'd0)) begin - soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); - end - end - end - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd1; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd0; - end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin - soc_litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_counter == 6'd35)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 6'd35)) begin + main_litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_counter != 1'd0)) begin + main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin - soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_zqcs_executer_done <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin + main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_litedramcore_bankmachine0_row_close) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine0_row_open) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd1; - soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; - soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid; + main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first; + main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine0_twtpcon_valid) begin - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin - soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trccon_valid) begin - soc_litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin - soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trascon_valid) begin - soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_litedramcore_bankmachine1_row_close) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine1_row_open) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd1; - soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; - soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid; + main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first; + main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine1_twtpcon_valid) begin - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin - soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trccon_valid) begin - soc_litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin - soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trascon_valid) begin - soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_litedramcore_bankmachine2_row_close) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine2_row_open) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd1; - soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; - soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid; + main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first; + main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine2_twtpcon_valid) begin - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin - soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trccon_valid) begin - soc_litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin - soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trascon_valid) begin - soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_litedramcore_bankmachine3_row_close) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine3_row_open) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd1; - soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; - soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid; + main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first; + main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine3_twtpcon_valid) begin - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin - soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trccon_valid) begin - soc_litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin - soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trascon_valid) begin - soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_litedramcore_bankmachine4_row_close) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine4_row_open) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd1; - soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; - soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid; + main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first; + main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine4_twtpcon_valid) begin - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin - soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trccon_valid) begin - soc_litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin - soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trascon_valid) begin - soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_litedramcore_bankmachine5_row_close) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine5_row_open) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd1; - soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; - soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid; + main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first; + main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine5_twtpcon_valid) begin - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin - soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trccon_valid) begin - soc_litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin - soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trascon_valid) begin - soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_litedramcore_bankmachine6_row_close) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine6_row_open) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd1; - soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; - soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid; + main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first; + main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine6_twtpcon_valid) begin - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin - soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trccon_valid) begin - soc_litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin - soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trascon_valid) begin - soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_litedramcore_bankmachine7_row_close) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine7_row_open) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd1; - soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; - soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid; + main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first; + main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine7_twtpcon_valid) begin - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin - soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trccon_valid) begin - soc_litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin - soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trascon_valid) begin - soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_litedramcore_en0)) begin - soc_litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~soc_litedramcore_max_time0)) begin - soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~soc_litedramcore_en1)) begin - soc_litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~soc_litedramcore_max_time1)) begin - soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (soc_litedramcore_choose_cmd_ce) begin - case (soc_litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13870,26 +16461,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13899,26 +16490,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13928,26 +16519,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13957,26 +16548,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13986,26 +16577,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -14015,26 +16606,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -14044,26 +16635,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -14074,29 +16665,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_litedramcore_choose_req_ce) begin - case (soc_litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -14106,26 +16697,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -14135,26 +16726,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -14164,26 +16755,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -14193,26 +16784,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -14222,26 +16813,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -14251,26 +16842,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -14280,26 +16871,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -14310,578 +16901,802 @@ always @(posedge sys_clk) begin end endcase end - soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; - soc_litedramcore_dfi_p0_address <= vns_array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; - soc_litedramcore_dfi_p1_address <= vns_array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; - soc_litedramcore_dfi_p2_address <= vns_array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; - soc_litedramcore_dfi_p3_address <= vns_array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_litedramcore_trrdcon_valid) begin - soc_litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_array_muxed0; + main_litedramcore_dfi_p0_address <= builder_array_muxed1; + main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2); + main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3); + main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4); + main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5; + main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_array_muxed7; + main_litedramcore_dfi_p1_address <= builder_array_muxed8; + main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9); + main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10); + main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11); + main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12; + main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_array_muxed14; + main_litedramcore_dfi_p2_address <= builder_array_muxed15; + main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16); + main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17); + main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18); + main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19; + main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_array_muxed21; + main_litedramcore_dfi_p3_address <= builder_array_muxed22; + main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23); + main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24); + main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25); + main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26; + main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_trrdcon_ready)) begin - soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); - if ((soc_litedramcore_trrdcon_count == 1'd1)) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; - if ((soc_litedramcore_tfawcon_count < 3'd4)) begin - if ((soc_litedramcore_tfawcon_count == 2'd3)) begin - soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - soc_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_litedramcore_tccdcon_valid) begin - soc_litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_tccdcon_ready)) begin - soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); - if ((soc_litedramcore_tccdcon_count == 1'd1)) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_litedramcore_twtrcon_valid) begin - soc_litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_twtrcon_ready)) begin - soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); - if ((soc_litedramcore_twtrcon_count == 1'd1)) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_litedramcore_dat_w_next_value_ce0) begin + builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0; + end + if (builder_litedramcore_adr_next_value_ce1) begin + builder_litedramcore_adr <= builder_litedramcore_adr_next_value1; + end + if (builder_litedramcore_we_next_value_ce2) begin + builder_litedramcore_we <= builder_litedramcore_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (vns_csrbank0_init_done0_re) begin - soc_init_done_storage <= vns_csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank0_init_done0_re; - if (vns_csrbank0_init_error0_re) begin - soc_init_error_storage <= vns_csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank0_init_error0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[3:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd2: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 2'd3: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd4: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 3'd5: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (vns_csrbank1_half_sys8x_taps0_re) begin - soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; + end + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; - if (vns_csrbank1_wlevel_en0_re) begin - soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; - if (vns_csrbank1_dly_sel0_re) begin - soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[4:0]) + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + end + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + end + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 4'd10: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; end 4'd11: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; end 4'd12: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end 4'd13: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end 4'd14: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd15: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; end 5'd17: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 5'd18: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 5'd19: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; end 5'd20: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; end 5'd21: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; end 5'd22: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 5'd23: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; end 5'd24: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; + end + 5'd25: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; + end + 5'd26: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; + end + 5'd27: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; + end + 5'd28: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; + end + 5'd29: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; + end + 5'd30: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; + end + 5'd31: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; + end + 6'd32: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; + end + 6'd33: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; + end + 6'd34: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; + end + 6'd35: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; + end + 6'd36: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; + end + 6'd37: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; + end + 6'd38: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; + end + 6'd39: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; + end + 6'd40: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; + end + 6'd41: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; + end + 6'd42: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; + end + 6'd43: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; + end + 6'd44: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; + end + 6'd45: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; + end + 6'd46: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; + end + 6'd47: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; + end + 6'd48: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; + end + 6'd49: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; + end + 6'd50: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; + end + 6'd51: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; + end + 6'd52: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank2_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + end + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; + end + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address1_re) begin + main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r; end - soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; - if (vns_csrbank2_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; end - soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; - if (vns_csrbank2_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[13:0] <= vns_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; - if (vns_csrbank2_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata3_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; end - soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; - if (vns_csrbank2_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + if (builder_csrbank2_dfii_pi0_wrdata2_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; end - soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; - if (vns_csrbank2_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + if (builder_csrbank2_dfii_pi0_wrdata1_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; end - soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; - if (vns_csrbank2_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[13:0] <= vns_csrbank2_dfii_pi1_address0_r; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; - if (vns_csrbank2_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end - soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; - if (vns_csrbank2_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address1_re) begin + main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r; end - soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; - if (vns_csrbank2_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; end - soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; - if (vns_csrbank2_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[13:0] <= vns_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; - if (vns_csrbank2_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata3_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; end - soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; - if (vns_csrbank2_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + if (builder_csrbank2_dfii_pi1_wrdata2_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; end - soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; - if (vns_csrbank2_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + if (builder_csrbank2_dfii_pi1_wrdata1_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; end - soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; - if (vns_csrbank2_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[13:0] <= vns_csrbank2_dfii_pi3_address0_r; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; - if (vns_csrbank2_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end - soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; - if (vns_csrbank2_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address1_re) begin + main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r; end - soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + end + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + end + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata3_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; + end + if (builder_csrbank2_dfii_pi2_wrdata2_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; + end + if (builder_csrbank2_dfii_pi2_wrdata1_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; + end + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + end + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; + end + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address1_re) begin + main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r; + end + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + end + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + end + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata3_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; + end + if (builder_csrbank2_dfii_pi3_wrdata2_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; + end + if (builder_csrbank2_dfii_pi3_wrdata1_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; + end + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + end + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; if (sys_rst) begin - soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_a7ddrphy_wlevel_en_storage <= 1'd0; - soc_a7ddrphy_wlevel_en_re <= 1'd0; - soc_a7ddrphy_dly_sel_storage <= 2'd0; - soc_a7ddrphy_dly_sel_re <= 1'd0; - soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_a7ddrphy_dqs_oe_delayed <= 1'd0; - soc_a7ddrphy_dqspattern_o1 <= 8'd0; - soc_a7ddrphy_dq_oe_delayed <= 1'd0; - soc_a7ddrphy_bitslip0_value <= 4'd0; - soc_a7ddrphy_bitslip1_value <= 4'd0; - soc_a7ddrphy_bitslip2_value <= 4'd0; - soc_a7ddrphy_bitslip3_value <= 4'd0; - soc_a7ddrphy_bitslip4_value <= 4'd0; - soc_a7ddrphy_bitslip5_value <= 4'd0; - soc_a7ddrphy_bitslip6_value <= 4'd0; - soc_a7ddrphy_bitslip7_value <= 4'd0; - soc_a7ddrphy_bitslip8_value <= 4'd0; - soc_a7ddrphy_bitslip9_value <= 4'd0; - soc_a7ddrphy_bitslip10_value <= 4'd0; - soc_a7ddrphy_bitslip11_value <= 4'd0; - soc_a7ddrphy_bitslip12_value <= 4'd0; - soc_a7ddrphy_bitslip13_value <= 4'd0; - soc_a7ddrphy_bitslip14_value <= 4'd0; - soc_a7ddrphy_bitslip15_value <= 4'd0; - soc_a7ddrphy_rddata_en_last <= 8'd0; - soc_a7ddrphy_wrdata_en_last <= 4'd0; - soc_litedramcore_storage <= 4'd1; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; - soc_litedramcore_phaseinjector0_command_re <= 1'd0; - soc_litedramcore_phaseinjector0_address_re <= 1'd0; - soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector0_status <= 32'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; - soc_litedramcore_phaseinjector1_command_re <= 1'd0; - soc_litedramcore_phaseinjector1_address_re <= 1'd0; - soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector1_status <= 32'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; - soc_litedramcore_phaseinjector2_command_re <= 1'd0; - soc_litedramcore_phaseinjector2_address_re <= 1'd0; - soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector2_status <= 32'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; - soc_litedramcore_phaseinjector3_command_re <= 1'd0; - soc_litedramcore_phaseinjector3_address_re <= 1'd0; - soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector3_status <= 32'd0; - soc_litedramcore_dfi_p0_address <= 14'd0; - soc_litedramcore_dfi_p0_bank <= 3'd0; - soc_litedramcore_dfi_p0_cas_n <= 1'd1; - soc_litedramcore_dfi_p0_cs_n <= 1'd1; - soc_litedramcore_dfi_p0_ras_n <= 1'd1; - soc_litedramcore_dfi_p0_we_n <= 1'd1; - soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p0_rddata_en <= 1'd0; - soc_litedramcore_dfi_p1_address <= 14'd0; - soc_litedramcore_dfi_p1_bank <= 3'd0; - soc_litedramcore_dfi_p1_cas_n <= 1'd1; - soc_litedramcore_dfi_p1_cs_n <= 1'd1; - soc_litedramcore_dfi_p1_ras_n <= 1'd1; - soc_litedramcore_dfi_p1_we_n <= 1'd1; - soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p1_rddata_en <= 1'd0; - soc_litedramcore_dfi_p2_address <= 14'd0; - soc_litedramcore_dfi_p2_bank <= 3'd0; - soc_litedramcore_dfi_p2_cas_n <= 1'd1; - soc_litedramcore_dfi_p2_cs_n <= 1'd1; - soc_litedramcore_dfi_p2_ras_n <= 1'd1; - soc_litedramcore_dfi_p2_we_n <= 1'd1; - soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p2_rddata_en <= 1'd0; - soc_litedramcore_dfi_p3_address <= 14'd0; - soc_litedramcore_dfi_p3_bank <= 3'd0; - soc_litedramcore_dfi_p3_cas_n <= 1'd1; - soc_litedramcore_dfi_p3_cs_n <= 1'd1; - soc_litedramcore_dfi_p3_ras_n <= 1'd1; - soc_litedramcore_dfi_p3_we_n <= 1'd1; - soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p3_rddata_en <= 1'd0; - soc_litedramcore_timer_count1 <= 10'd781; - soc_litedramcore_postponer_req_o <= 1'd0; - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 6'd0; - soc_litedramcore_sequencer_count <= 1'd0; - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine0_row <= 14'd0; - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trccon_count <= 3'd0; - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trascon_count <= 3'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine1_row <= 14'd0; - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trccon_count <= 3'd0; - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trascon_count <= 3'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine2_row <= 14'd0; - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trccon_count <= 3'd0; - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trascon_count <= 3'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine3_row <= 14'd0; - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trccon_count <= 3'd0; - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trascon_count <= 3'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine4_row <= 14'd0; - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trccon_count <= 3'd0; - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trascon_count <= 3'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine5_row <= 14'd0; - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trccon_count <= 3'd0; - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trascon_count <= 3'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine6_row <= 14'd0; - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trccon_count <= 3'd0; - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trascon_count <= 3'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine7_row <= 14'd0; - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trccon_count <= 3'd0; - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trascon_count <= 3'd0; - soc_litedramcore_choose_cmd_grant <= 3'd0; - soc_litedramcore_choose_req_grant <= 3'd0; - soc_litedramcore_trrdcon_ready <= 1'd0; - soc_litedramcore_trrdcon_count <= 1'd0; - soc_litedramcore_tfawcon_ready <= 1'd1; - soc_litedramcore_tfawcon_window <= 5'd0; - soc_litedramcore_tccdcon_ready <= 1'd0; - soc_litedramcore_tccdcon_count <= 1'd0; - soc_litedramcore_twtrcon_ready <= 1'd0; - soc_litedramcore_twtrcon_count <= 3'd0; - soc_litedramcore_time0 <= 5'd0; - soc_litedramcore_time1 <= 4'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 6'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 6'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 6'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 6'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 14'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 14'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 14'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 14'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 14'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_counter <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_counter <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine0_row <= 14'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine1_row <= 14'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine2_row <= 14'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine3_row <= 14'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine4_row <= 14'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine5_row <= 14'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine6_row <= 14'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine7_row <= 14'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_litedramcore_we <= 1'd0; + builder_state <= 2'd0; end end BUFG BUFG( - .I(soc_clkout0), - .O(soc_clkout_buf0) + .I(main_clkout0), + .O(main_clkout_buf0) ); BUFG BUFG_1( - .I(soc_clkout1), - .O(soc_clkout_buf1) + .I(main_clkout1), + .O(main_clkout_buf1) ); BUFG BUFG_2( - .I(soc_clkout2), - .O(soc_clkout_buf2) + .I(main_clkout2), + .O(main_clkout_buf2) ); BUFG BUFG_3( - .I(soc_clkout3), - .O(soc_clkout_buf3) + .I(main_clkout3), + .O(main_clkout_buf3) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(main_ic_reset) ); OSERDESE2 #( @@ -14902,12 +17717,12 @@ OSERDESE2 #( .D7(1'd0), .D8(1'd1), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_a7ddrphy_sd_clk_se_nodelay) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(main_a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_a7ddrphy_sd_clk_se_nodelay), + .I(main_a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -14921,17 +17736,17 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[0]), - .D2(soc_a7ddrphy_dfi_p0_address[0]), - .D3(soc_a7ddrphy_dfi_p1_address[0]), - .D4(soc_a7ddrphy_dfi_p1_address[0]), - .D5(soc_a7ddrphy_dfi_p2_address[0]), - .D6(soc_a7ddrphy_dfi_p2_address[0]), - .D7(soc_a7ddrphy_dfi_p3_address[0]), - .D8(soc_a7ddrphy_dfi_p3_address[0]), + .D1(main_a7ddrphy_dfi_p0_reset_n), + .D2(main_a7ddrphy_dfi_p0_reset_n), + .D3(main_a7ddrphy_dfi_p1_reset_n), + .D4(main_a7ddrphy_dfi_p1_reset_n), + .D5(main_a7ddrphy_dfi_p2_reset_n), + .D6(main_a7ddrphy_dfi_p2_reset_n), + .D7(main_a7ddrphy_dfi_p3_reset_n), + .D8(main_a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_reset_n) ); OSERDESE2 #( @@ -14943,17 +17758,17 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[1]), - .D2(soc_a7ddrphy_dfi_p0_address[1]), - .D3(soc_a7ddrphy_dfi_p1_address[1]), - .D4(soc_a7ddrphy_dfi_p1_address[1]), - .D5(soc_a7ddrphy_dfi_p2_address[1]), - .D6(soc_a7ddrphy_dfi_p2_address[1]), - .D7(soc_a7ddrphy_dfi_p3_address[1]), - .D8(soc_a7ddrphy_dfi_p3_address[1]), + .D1(main_a7ddrphy_dfi_p0_cs_n), + .D2(main_a7ddrphy_dfi_p0_cs_n), + .D3(main_a7ddrphy_dfi_p1_cs_n), + .D4(main_a7ddrphy_dfi_p1_cs_n), + .D5(main_a7ddrphy_dfi_p2_cs_n), + .D6(main_a7ddrphy_dfi_p2_cs_n), + .D7(main_a7ddrphy_dfi_p3_cs_n), + .D8(main_a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cs_n) ); OSERDESE2 #( @@ -14965,17 +17780,17 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[2]), - .D2(soc_a7ddrphy_dfi_p0_address[2]), - .D3(soc_a7ddrphy_dfi_p1_address[2]), - .D4(soc_a7ddrphy_dfi_p1_address[2]), - .D5(soc_a7ddrphy_dfi_p2_address[2]), - .D6(soc_a7ddrphy_dfi_p2_address[2]), - .D7(soc_a7ddrphy_dfi_p3_address[2]), - .D8(soc_a7ddrphy_dfi_p3_address[2]), + .D1(main_a7ddrphy_dfi_p0_address[0]), + .D2(main_a7ddrphy_dfi_p0_address[0]), + .D3(main_a7ddrphy_dfi_p1_address[0]), + .D4(main_a7ddrphy_dfi_p1_address[0]), + .D5(main_a7ddrphy_dfi_p2_address[0]), + .D6(main_a7ddrphy_dfi_p2_address[0]), + .D7(main_a7ddrphy_dfi_p3_address[0]), + .D8(main_a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[0]) ); OSERDESE2 #( @@ -14987,17 +17802,17 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[3]), - .D2(soc_a7ddrphy_dfi_p0_address[3]), - .D3(soc_a7ddrphy_dfi_p1_address[3]), - .D4(soc_a7ddrphy_dfi_p1_address[3]), - .D5(soc_a7ddrphy_dfi_p2_address[3]), - .D6(soc_a7ddrphy_dfi_p2_address[3]), - .D7(soc_a7ddrphy_dfi_p3_address[3]), - .D8(soc_a7ddrphy_dfi_p3_address[3]), + .D1(main_a7ddrphy_dfi_p0_address[1]), + .D2(main_a7ddrphy_dfi_p0_address[1]), + .D3(main_a7ddrphy_dfi_p1_address[1]), + .D4(main_a7ddrphy_dfi_p1_address[1]), + .D5(main_a7ddrphy_dfi_p2_address[1]), + .D6(main_a7ddrphy_dfi_p2_address[1]), + .D7(main_a7ddrphy_dfi_p3_address[1]), + .D8(main_a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[3]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[1]) ); OSERDESE2 #( @@ -15009,17 +17824,17 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[4]), - .D2(soc_a7ddrphy_dfi_p0_address[4]), - .D3(soc_a7ddrphy_dfi_p1_address[4]), - .D4(soc_a7ddrphy_dfi_p1_address[4]), - .D5(soc_a7ddrphy_dfi_p2_address[4]), - .D6(soc_a7ddrphy_dfi_p2_address[4]), - .D7(soc_a7ddrphy_dfi_p3_address[4]), - .D8(soc_a7ddrphy_dfi_p3_address[4]), + .D1(main_a7ddrphy_dfi_p0_address[2]), + .D2(main_a7ddrphy_dfi_p0_address[2]), + .D3(main_a7ddrphy_dfi_p1_address[2]), + .D4(main_a7ddrphy_dfi_p1_address[2]), + .D5(main_a7ddrphy_dfi_p2_address[2]), + .D6(main_a7ddrphy_dfi_p2_address[2]), + .D7(main_a7ddrphy_dfi_p3_address[2]), + .D8(main_a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[4]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[2]) ); OSERDESE2 #( @@ -15031,17 +17846,17 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[5]), - .D2(soc_a7ddrphy_dfi_p0_address[5]), - .D3(soc_a7ddrphy_dfi_p1_address[5]), - .D4(soc_a7ddrphy_dfi_p1_address[5]), - .D5(soc_a7ddrphy_dfi_p2_address[5]), - .D6(soc_a7ddrphy_dfi_p2_address[5]), - .D7(soc_a7ddrphy_dfi_p3_address[5]), - .D8(soc_a7ddrphy_dfi_p3_address[5]), + .D1(main_a7ddrphy_dfi_p0_address[3]), + .D2(main_a7ddrphy_dfi_p0_address[3]), + .D3(main_a7ddrphy_dfi_p1_address[3]), + .D4(main_a7ddrphy_dfi_p1_address[3]), + .D5(main_a7ddrphy_dfi_p2_address[3]), + .D6(main_a7ddrphy_dfi_p2_address[3]), + .D7(main_a7ddrphy_dfi_p3_address[3]), + .D8(main_a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[5]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[3]) ); OSERDESE2 #( @@ -15053,17 +17868,17 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[6]), - .D2(soc_a7ddrphy_dfi_p0_address[6]), - .D3(soc_a7ddrphy_dfi_p1_address[6]), - .D4(soc_a7ddrphy_dfi_p1_address[6]), - .D5(soc_a7ddrphy_dfi_p2_address[6]), - .D6(soc_a7ddrphy_dfi_p2_address[6]), - .D7(soc_a7ddrphy_dfi_p3_address[6]), - .D8(soc_a7ddrphy_dfi_p3_address[6]), + .D1(main_a7ddrphy_dfi_p0_address[4]), + .D2(main_a7ddrphy_dfi_p0_address[4]), + .D3(main_a7ddrphy_dfi_p1_address[4]), + .D4(main_a7ddrphy_dfi_p1_address[4]), + .D5(main_a7ddrphy_dfi_p2_address[4]), + .D6(main_a7ddrphy_dfi_p2_address[4]), + .D7(main_a7ddrphy_dfi_p3_address[4]), + .D8(main_a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[6]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[4]) ); OSERDESE2 #( @@ -15075,17 +17890,17 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[7]), - .D2(soc_a7ddrphy_dfi_p0_address[7]), - .D3(soc_a7ddrphy_dfi_p1_address[7]), - .D4(soc_a7ddrphy_dfi_p1_address[7]), - .D5(soc_a7ddrphy_dfi_p2_address[7]), - .D6(soc_a7ddrphy_dfi_p2_address[7]), - .D7(soc_a7ddrphy_dfi_p3_address[7]), - .D8(soc_a7ddrphy_dfi_p3_address[7]), + .D1(main_a7ddrphy_dfi_p0_address[5]), + .D2(main_a7ddrphy_dfi_p0_address[5]), + .D3(main_a7ddrphy_dfi_p1_address[5]), + .D4(main_a7ddrphy_dfi_p1_address[5]), + .D5(main_a7ddrphy_dfi_p2_address[5]), + .D6(main_a7ddrphy_dfi_p2_address[5]), + .D7(main_a7ddrphy_dfi_p3_address[5]), + .D8(main_a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[7]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[5]) ); OSERDESE2 #( @@ -15097,17 +17912,17 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[8]), - .D2(soc_a7ddrphy_dfi_p0_address[8]), - .D3(soc_a7ddrphy_dfi_p1_address[8]), - .D4(soc_a7ddrphy_dfi_p1_address[8]), - .D5(soc_a7ddrphy_dfi_p2_address[8]), - .D6(soc_a7ddrphy_dfi_p2_address[8]), - .D7(soc_a7ddrphy_dfi_p3_address[8]), - .D8(soc_a7ddrphy_dfi_p3_address[8]), + .D1(main_a7ddrphy_dfi_p0_address[6]), + .D2(main_a7ddrphy_dfi_p0_address[6]), + .D3(main_a7ddrphy_dfi_p1_address[6]), + .D4(main_a7ddrphy_dfi_p1_address[6]), + .D5(main_a7ddrphy_dfi_p2_address[6]), + .D6(main_a7ddrphy_dfi_p2_address[6]), + .D7(main_a7ddrphy_dfi_p3_address[6]), + .D8(main_a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[8]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[6]) ); OSERDESE2 #( @@ -15119,17 +17934,17 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[9]), - .D2(soc_a7ddrphy_dfi_p0_address[9]), - .D3(soc_a7ddrphy_dfi_p1_address[9]), - .D4(soc_a7ddrphy_dfi_p1_address[9]), - .D5(soc_a7ddrphy_dfi_p2_address[9]), - .D6(soc_a7ddrphy_dfi_p2_address[9]), - .D7(soc_a7ddrphy_dfi_p3_address[9]), - .D8(soc_a7ddrphy_dfi_p3_address[9]), + .D1(main_a7ddrphy_dfi_p0_address[7]), + .D2(main_a7ddrphy_dfi_p0_address[7]), + .D3(main_a7ddrphy_dfi_p1_address[7]), + .D4(main_a7ddrphy_dfi_p1_address[7]), + .D5(main_a7ddrphy_dfi_p2_address[7]), + .D6(main_a7ddrphy_dfi_p2_address[7]), + .D7(main_a7ddrphy_dfi_p3_address[7]), + .D8(main_a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[9]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[7]) ); OSERDESE2 #( @@ -15141,17 +17956,17 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[10]), - .D2(soc_a7ddrphy_dfi_p0_address[10]), - .D3(soc_a7ddrphy_dfi_p1_address[10]), - .D4(soc_a7ddrphy_dfi_p1_address[10]), - .D5(soc_a7ddrphy_dfi_p2_address[10]), - .D6(soc_a7ddrphy_dfi_p2_address[10]), - .D7(soc_a7ddrphy_dfi_p3_address[10]), - .D8(soc_a7ddrphy_dfi_p3_address[10]), + .D1(main_a7ddrphy_dfi_p0_address[8]), + .D2(main_a7ddrphy_dfi_p0_address[8]), + .D3(main_a7ddrphy_dfi_p1_address[8]), + .D4(main_a7ddrphy_dfi_p1_address[8]), + .D5(main_a7ddrphy_dfi_p2_address[8]), + .D6(main_a7ddrphy_dfi_p2_address[8]), + .D7(main_a7ddrphy_dfi_p3_address[8]), + .D8(main_a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[10]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[8]) ); OSERDESE2 #( @@ -15163,17 +17978,17 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[11]), - .D2(soc_a7ddrphy_dfi_p0_address[11]), - .D3(soc_a7ddrphy_dfi_p1_address[11]), - .D4(soc_a7ddrphy_dfi_p1_address[11]), - .D5(soc_a7ddrphy_dfi_p2_address[11]), - .D6(soc_a7ddrphy_dfi_p2_address[11]), - .D7(soc_a7ddrphy_dfi_p3_address[11]), - .D8(soc_a7ddrphy_dfi_p3_address[11]), + .D1(main_a7ddrphy_dfi_p0_address[9]), + .D2(main_a7ddrphy_dfi_p0_address[9]), + .D3(main_a7ddrphy_dfi_p1_address[9]), + .D4(main_a7ddrphy_dfi_p1_address[9]), + .D5(main_a7ddrphy_dfi_p2_address[9]), + .D6(main_a7ddrphy_dfi_p2_address[9]), + .D7(main_a7ddrphy_dfi_p3_address[9]), + .D8(main_a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[11]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[9]) ); OSERDESE2 #( @@ -15185,17 +18000,17 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[12]), - .D2(soc_a7ddrphy_dfi_p0_address[12]), - .D3(soc_a7ddrphy_dfi_p1_address[12]), - .D4(soc_a7ddrphy_dfi_p1_address[12]), - .D5(soc_a7ddrphy_dfi_p2_address[12]), - .D6(soc_a7ddrphy_dfi_p2_address[12]), - .D7(soc_a7ddrphy_dfi_p3_address[12]), - .D8(soc_a7ddrphy_dfi_p3_address[12]), + .D1(main_a7ddrphy_dfi_p0_address[10]), + .D2(main_a7ddrphy_dfi_p0_address[10]), + .D3(main_a7ddrphy_dfi_p1_address[10]), + .D4(main_a7ddrphy_dfi_p1_address[10]), + .D5(main_a7ddrphy_dfi_p2_address[10]), + .D6(main_a7ddrphy_dfi_p2_address[10]), + .D7(main_a7ddrphy_dfi_p3_address[10]), + .D8(main_a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[12]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[10]) ); OSERDESE2 #( @@ -15207,17 +18022,17 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[13]), - .D2(soc_a7ddrphy_dfi_p0_address[13]), - .D3(soc_a7ddrphy_dfi_p1_address[13]), - .D4(soc_a7ddrphy_dfi_p1_address[13]), - .D5(soc_a7ddrphy_dfi_p2_address[13]), - .D6(soc_a7ddrphy_dfi_p2_address[13]), - .D7(soc_a7ddrphy_dfi_p3_address[13]), - .D8(soc_a7ddrphy_dfi_p3_address[13]), + .D1(main_a7ddrphy_dfi_p0_address[11]), + .D2(main_a7ddrphy_dfi_p0_address[11]), + .D3(main_a7ddrphy_dfi_p1_address[11]), + .D4(main_a7ddrphy_dfi_p1_address[11]), + .D5(main_a7ddrphy_dfi_p2_address[11]), + .D6(main_a7ddrphy_dfi_p2_address[11]), + .D7(main_a7ddrphy_dfi_p3_address[11]), + .D8(main_a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[13]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[11]) ); OSERDESE2 #( @@ -15229,17 +18044,17 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[0]), - .D2(soc_a7ddrphy_dfi_p0_bank[0]), - .D3(soc_a7ddrphy_dfi_p1_bank[0]), - .D4(soc_a7ddrphy_dfi_p1_bank[0]), - .D5(soc_a7ddrphy_dfi_p2_bank[0]), - .D6(soc_a7ddrphy_dfi_p2_bank[0]), - .D7(soc_a7ddrphy_dfi_p3_bank[0]), - .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .D1(main_a7ddrphy_dfi_p0_address[12]), + .D2(main_a7ddrphy_dfi_p0_address[12]), + .D3(main_a7ddrphy_dfi_p1_address[12]), + .D4(main_a7ddrphy_dfi_p1_address[12]), + .D5(main_a7ddrphy_dfi_p2_address[12]), + .D6(main_a7ddrphy_dfi_p2_address[12]), + .D7(main_a7ddrphy_dfi_p3_address[12]), + .D8(main_a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[12]) ); OSERDESE2 #( @@ -15251,17 +18066,17 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[1]), - .D2(soc_a7ddrphy_dfi_p0_bank[1]), - .D3(soc_a7ddrphy_dfi_p1_bank[1]), - .D4(soc_a7ddrphy_dfi_p1_bank[1]), - .D5(soc_a7ddrphy_dfi_p2_bank[1]), - .D6(soc_a7ddrphy_dfi_p2_bank[1]), - .D7(soc_a7ddrphy_dfi_p3_bank[1]), - .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .D1(main_a7ddrphy_dfi_p0_address[13]), + .D2(main_a7ddrphy_dfi_p0_address[13]), + .D3(main_a7ddrphy_dfi_p1_address[13]), + .D4(main_a7ddrphy_dfi_p1_address[13]), + .D5(main_a7ddrphy_dfi_p2_address[13]), + .D6(main_a7ddrphy_dfi_p2_address[13]), + .D7(main_a7ddrphy_dfi_p3_address[13]), + .D8(main_a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[13]) ); OSERDESE2 #( @@ -15273,17 +18088,17 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[2]), - .D2(soc_a7ddrphy_dfi_p0_bank[2]), - .D3(soc_a7ddrphy_dfi_p1_bank[2]), - .D4(soc_a7ddrphy_dfi_p1_bank[2]), - .D5(soc_a7ddrphy_dfi_p2_bank[2]), - .D6(soc_a7ddrphy_dfi_p2_bank[2]), - .D7(soc_a7ddrphy_dfi_p3_bank[2]), - .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .D1(main_a7ddrphy_dfi_p0_bank[0]), + .D2(main_a7ddrphy_dfi_p0_bank[0]), + .D3(main_a7ddrphy_dfi_p1_bank[0]), + .D4(main_a7ddrphy_dfi_p1_bank[0]), + .D5(main_a7ddrphy_dfi_p2_bank[0]), + .D6(main_a7ddrphy_dfi_p2_bank[0]), + .D7(main_a7ddrphy_dfi_p3_bank[0]), + .D8(main_a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[0]) ); OSERDESE2 #( @@ -15295,17 +18110,17 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_ras_n), - .D2(soc_a7ddrphy_dfi_p0_ras_n), - .D3(soc_a7ddrphy_dfi_p1_ras_n), - .D4(soc_a7ddrphy_dfi_p1_ras_n), - .D5(soc_a7ddrphy_dfi_p2_ras_n), - .D6(soc_a7ddrphy_dfi_p2_ras_n), - .D7(soc_a7ddrphy_dfi_p3_ras_n), - .D8(soc_a7ddrphy_dfi_p3_ras_n), + .D1(main_a7ddrphy_dfi_p0_bank[1]), + .D2(main_a7ddrphy_dfi_p0_bank[1]), + .D3(main_a7ddrphy_dfi_p1_bank[1]), + .D4(main_a7ddrphy_dfi_p1_bank[1]), + .D5(main_a7ddrphy_dfi_p2_bank[1]), + .D6(main_a7ddrphy_dfi_p2_bank[1]), + .D7(main_a7ddrphy_dfi_p3_bank[1]), + .D8(main_a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ras_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[1]) ); OSERDESE2 #( @@ -15317,17 +18132,17 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cas_n), - .D2(soc_a7ddrphy_dfi_p0_cas_n), - .D3(soc_a7ddrphy_dfi_p1_cas_n), - .D4(soc_a7ddrphy_dfi_p1_cas_n), - .D5(soc_a7ddrphy_dfi_p2_cas_n), - .D6(soc_a7ddrphy_dfi_p2_cas_n), - .D7(soc_a7ddrphy_dfi_p3_cas_n), - .D8(soc_a7ddrphy_dfi_p3_cas_n), + .D1(main_a7ddrphy_dfi_p0_bank[2]), + .D2(main_a7ddrphy_dfi_p0_bank[2]), + .D3(main_a7ddrphy_dfi_p1_bank[2]), + .D4(main_a7ddrphy_dfi_p1_bank[2]), + .D5(main_a7ddrphy_dfi_p2_bank[2]), + .D6(main_a7ddrphy_dfi_p2_bank[2]), + .D7(main_a7ddrphy_dfi_p3_bank[2]), + .D8(main_a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cas_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[2]) ); OSERDESE2 #( @@ -15339,17 +18154,17 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_we_n), - .D2(soc_a7ddrphy_dfi_p0_we_n), - .D3(soc_a7ddrphy_dfi_p1_we_n), - .D4(soc_a7ddrphy_dfi_p1_we_n), - .D5(soc_a7ddrphy_dfi_p2_we_n), - .D6(soc_a7ddrphy_dfi_p2_we_n), - .D7(soc_a7ddrphy_dfi_p3_we_n), - .D8(soc_a7ddrphy_dfi_p3_we_n), + .D1(main_a7ddrphy_dfi_p0_ras_n), + .D2(main_a7ddrphy_dfi_p0_ras_n), + .D3(main_a7ddrphy_dfi_p1_ras_n), + .D4(main_a7ddrphy_dfi_p1_ras_n), + .D5(main_a7ddrphy_dfi_p2_ras_n), + .D6(main_a7ddrphy_dfi_p2_ras_n), + .D7(main_a7ddrphy_dfi_p3_ras_n), + .D8(main_a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_we_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ras_n) ); OSERDESE2 #( @@ -15361,17 +18176,17 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cke), - .D2(soc_a7ddrphy_dfi_p0_cke), - .D3(soc_a7ddrphy_dfi_p1_cke), - .D4(soc_a7ddrphy_dfi_p1_cke), - .D5(soc_a7ddrphy_dfi_p2_cke), - .D6(soc_a7ddrphy_dfi_p2_cke), - .D7(soc_a7ddrphy_dfi_p3_cke), - .D8(soc_a7ddrphy_dfi_p3_cke), + .D1(main_a7ddrphy_dfi_p0_cas_n), + .D2(main_a7ddrphy_dfi_p0_cas_n), + .D3(main_a7ddrphy_dfi_p1_cas_n), + .D4(main_a7ddrphy_dfi_p1_cas_n), + .D5(main_a7ddrphy_dfi_p2_cas_n), + .D6(main_a7ddrphy_dfi_p2_cas_n), + .D7(main_a7ddrphy_dfi_p3_cas_n), + .D8(main_a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cke) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cas_n) ); OSERDESE2 #( @@ -15383,17 +18198,17 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_odt), - .D2(soc_a7ddrphy_dfi_p0_odt), - .D3(soc_a7ddrphy_dfi_p1_odt), - .D4(soc_a7ddrphy_dfi_p1_odt), - .D5(soc_a7ddrphy_dfi_p2_odt), - .D6(soc_a7ddrphy_dfi_p2_odt), - .D7(soc_a7ddrphy_dfi_p3_odt), - .D8(soc_a7ddrphy_dfi_p3_odt), + .D1(main_a7ddrphy_dfi_p0_we_n), + .D2(main_a7ddrphy_dfi_p0_we_n), + .D3(main_a7ddrphy_dfi_p1_we_n), + .D4(main_a7ddrphy_dfi_p1_we_n), + .D5(main_a7ddrphy_dfi_p2_we_n), + .D6(main_a7ddrphy_dfi_p2_we_n), + .D7(main_a7ddrphy_dfi_p3_we_n), + .D8(main_a7ddrphy_dfi_p3_we_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_odt) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_we_n) ); OSERDESE2 #( @@ -15405,17 +18220,17 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_reset_n), - .D2(soc_a7ddrphy_dfi_p0_reset_n), - .D3(soc_a7ddrphy_dfi_p1_reset_n), - .D4(soc_a7ddrphy_dfi_p1_reset_n), - .D5(soc_a7ddrphy_dfi_p2_reset_n), - .D6(soc_a7ddrphy_dfi_p2_reset_n), - .D7(soc_a7ddrphy_dfi_p3_reset_n), - .D8(soc_a7ddrphy_dfi_p3_reset_n), + .D1(main_a7ddrphy_dfi_p0_cke), + .D2(main_a7ddrphy_dfi_p0_cke), + .D3(main_a7ddrphy_dfi_p1_cke), + .D4(main_a7ddrphy_dfi_p1_cke), + .D5(main_a7ddrphy_dfi_p2_cke), + .D6(main_a7ddrphy_dfi_p2_cke), + .D7(main_a7ddrphy_dfi_p3_cke), + .D8(main_a7ddrphy_dfi_p3_cke), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_reset_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cke) ); OSERDESE2 #( @@ -15427,17 +18242,17 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cs_n), - .D2(soc_a7ddrphy_dfi_p0_cs_n), - .D3(soc_a7ddrphy_dfi_p1_cs_n), - .D4(soc_a7ddrphy_dfi_p1_cs_n), - .D5(soc_a7ddrphy_dfi_p2_cs_n), - .D6(soc_a7ddrphy_dfi_p2_cs_n), - .D7(soc_a7ddrphy_dfi_p3_cs_n), - .D8(soc_a7ddrphy_dfi_p3_cs_n), + .D1(main_a7ddrphy_dfi_p0_odt), + .D2(main_a7ddrphy_dfi_p0_odt), + .D3(main_a7ddrphy_dfi_p1_odt), + .D4(main_a7ddrphy_dfi_p1_odt), + .D5(main_a7ddrphy_dfi_p2_odt), + .D6(main_a7ddrphy_dfi_p2_odt), + .D7(main_a7ddrphy_dfi_p3_odt), + .D8(main_a7ddrphy_dfi_p3_odt), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cs_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_odt) ); OSERDESE2 #( @@ -15447,19 +18262,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .D1(main_a7ddrphy_bitslip00[0]), + .D2(main_a7ddrphy_bitslip00[1]), + .D3(main_a7ddrphy_bitslip00[2]), + .D4(main_a7ddrphy_bitslip00[3]), + .D5(main_a7ddrphy_bitslip00[4]), + .D6(main_a7ddrphy_bitslip00[5]), + .D7(main_a7ddrphy_bitslip00[6]), + .D8(main_a7ddrphy_bitslip00[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy0), + .OQ(main_a7ddrphy_dqs_o_no_delay0), + .TQ(main_a7ddrphy_dqs_t0) +); + +IOBUFDS IOBUFDS( + .I(main_a7ddrphy_dqs_o_no_delay0), + .T(main_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( @@ -15469,19 +18295,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .D1(main_a7ddrphy_bitslip10[0]), + .D2(main_a7ddrphy_bitslip10[1]), + .D3(main_a7ddrphy_bitslip10[2]), + .D4(main_a7ddrphy_bitslip10[3]), + .D5(main_a7ddrphy_bitslip10[4]), + .D6(main_a7ddrphy_bitslip10[5]), + .D7(main_a7ddrphy_bitslip10[6]), + .D8(main_a7ddrphy_bitslip10[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy1), + .OQ(main_a7ddrphy_dqs_o_no_delay1), + .TQ(main_a7ddrphy_dqs_t1) +); + +IOBUFDS IOBUFDS_1( + .I(main_a7ddrphy_dqs_o_no_delay1), + .T(main_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( @@ -15491,45 +18328,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip01[0]), + .D2(main_a7ddrphy_bitslip01[1]), + .D3(main_a7ddrphy_bitslip01[2]), + .D4(main_a7ddrphy_bitslip01[3]), + .D5(main_a7ddrphy_bitslip01[4]), + .D6(main_a7ddrphy_bitslip01[5]), + .D7(main_a7ddrphy_bitslip01[6]), + .D8(main_a7ddrphy_bitslip01[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy0), - .OQ(soc_a7ddrphy_dqs_o_no_delay0), - .TQ(soc_a7ddrphy_dqs_t0) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2 ( - .IDATAIN(soc_a7ddrphy_dqs_i[0]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) -); - -IOBUFDS IOBUFDS( - .I(soc_a7ddrphy_dqs_o_no_delay0), - .T(soc_a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]), - .O(soc_a7ddrphy_dqs_i[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[0]) ); OSERDESE2 #( @@ -15539,45 +18350,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip11[0]), + .D2(main_a7ddrphy_bitslip11[1]), + .D3(main_a7ddrphy_bitslip11[2]), + .D4(main_a7ddrphy_bitslip11[3]), + .D5(main_a7ddrphy_bitslip11[4]), + .D6(main_a7ddrphy_bitslip11[5]), + .D7(main_a7ddrphy_bitslip11[6]), + .D8(main_a7ddrphy_bitslip11[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy1), - .OQ(soc_a7ddrphy_dqs_o_no_delay1), - .TQ(soc_a7ddrphy_dqs_t1) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_1 ( - .IDATAIN(soc_a7ddrphy_dqs_i[1]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) -); - -IOBUFDS IOBUFDS_1( - .I(soc_a7ddrphy_dqs_o_no_delay1), - .T(soc_a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]), - .O(soc_a7ddrphy_dqs_i[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[1]) ); OSERDESE2 #( @@ -15589,20 +18374,20 @@ OSERDESE2 #( ) OSERDESE2_29 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .D1(main_a7ddrphy_bitslip02[0]), + .D2(main_a7ddrphy_bitslip02[1]), + .D3(main_a7ddrphy_bitslip02[2]), + .D4(main_a7ddrphy_bitslip02[3]), + .D5(main_a7ddrphy_bitslip02[4]), + .D6(main_a7ddrphy_bitslip02[5]), + .D7(main_a7ddrphy_bitslip02[6]), + .D8(main_a7ddrphy_bitslip02[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay0), - .TQ(soc_a7ddrphy_dq_t0) + .OQ(main_a7ddrphy_dq_o_nodelay0), + .TQ(main_a7ddrphy_dq_t0) ); ISERDESE2 #( @@ -15618,16 +18403,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed0), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data0[7]), - .Q2(soc_a7ddrphy_dq_i_data0[6]), - .Q3(soc_a7ddrphy_dq_i_data0[5]), - .Q4(soc_a7ddrphy_dq_i_data0[4]), - .Q5(soc_a7ddrphy_dq_i_data0[3]), - .Q6(soc_a7ddrphy_dq_i_data0[2]), - .Q7(soc_a7ddrphy_dq_i_data0[1]), - .Q8(soc_a7ddrphy_dq_i_data0[0]) + .DDLY(main_a7ddrphy_dq_i_delayed0), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip03[7]), + .Q2(main_a7ddrphy_bitslip03[6]), + .Q3(main_a7ddrphy_bitslip03[5]), + .Q4(main_a7ddrphy_bitslip03[4]), + .Q5(main_a7ddrphy_bitslip03[3]), + .Q6(main_a7ddrphy_bitslip03[2]), + .Q7(main_a7ddrphy_bitslip03[1]), + .Q8(main_a7ddrphy_bitslip03[0]) ); IDELAYE2 #( @@ -15639,21 +18424,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_2 ( +) IDELAYE2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed0) + .DATAOUT(main_a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_a7ddrphy_dq_o_nodelay0), - .T(soc_a7ddrphy_dq_t0), + .I(main_a7ddrphy_dq_o_nodelay0), + .T(main_a7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_a7ddrphy_dq_i_nodelay0) + .O(main_a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -15665,20 +18450,20 @@ OSERDESE2 #( ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .D1(main_a7ddrphy_bitslip12[0]), + .D2(main_a7ddrphy_bitslip12[1]), + .D3(main_a7ddrphy_bitslip12[2]), + .D4(main_a7ddrphy_bitslip12[3]), + .D5(main_a7ddrphy_bitslip12[4]), + .D6(main_a7ddrphy_bitslip12[5]), + .D7(main_a7ddrphy_bitslip12[6]), + .D8(main_a7ddrphy_bitslip12[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay1), - .TQ(soc_a7ddrphy_dq_t1) + .OQ(main_a7ddrphy_dq_o_nodelay1), + .TQ(main_a7ddrphy_dq_t1) ); ISERDESE2 #( @@ -15694,16 +18479,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed1), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data1[7]), - .Q2(soc_a7ddrphy_dq_i_data1[6]), - .Q3(soc_a7ddrphy_dq_i_data1[5]), - .Q4(soc_a7ddrphy_dq_i_data1[4]), - .Q5(soc_a7ddrphy_dq_i_data1[3]), - .Q6(soc_a7ddrphy_dq_i_data1[2]), - .Q7(soc_a7ddrphy_dq_i_data1[1]), - .Q8(soc_a7ddrphy_dq_i_data1[0]) + .DDLY(main_a7ddrphy_dq_i_delayed1), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip13[7]), + .Q2(main_a7ddrphy_bitslip13[6]), + .Q3(main_a7ddrphy_bitslip13[5]), + .Q4(main_a7ddrphy_bitslip13[4]), + .Q5(main_a7ddrphy_bitslip13[3]), + .Q6(main_a7ddrphy_bitslip13[2]), + .Q7(main_a7ddrphy_bitslip13[1]), + .Q8(main_a7ddrphy_bitslip13[0]) ); IDELAYE2 #( @@ -15715,21 +18500,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_3 ( +) IDELAYE2_1 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed1) + .DATAOUT(main_a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_a7ddrphy_dq_o_nodelay1), - .T(soc_a7ddrphy_dq_t1), + .I(main_a7ddrphy_dq_o_nodelay1), + .T(main_a7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_a7ddrphy_dq_i_nodelay1) + .O(main_a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -15741,20 +18526,20 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .D1(main_a7ddrphy_bitslip20[0]), + .D2(main_a7ddrphy_bitslip20[1]), + .D3(main_a7ddrphy_bitslip20[2]), + .D4(main_a7ddrphy_bitslip20[3]), + .D5(main_a7ddrphy_bitslip20[4]), + .D6(main_a7ddrphy_bitslip20[5]), + .D7(main_a7ddrphy_bitslip20[6]), + .D8(main_a7ddrphy_bitslip20[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay2), - .TQ(soc_a7ddrphy_dq_t2) + .OQ(main_a7ddrphy_dq_o_nodelay2), + .TQ(main_a7ddrphy_dq_t2) ); ISERDESE2 #( @@ -15770,16 +18555,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed2), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data2[7]), - .Q2(soc_a7ddrphy_dq_i_data2[6]), - .Q3(soc_a7ddrphy_dq_i_data2[5]), - .Q4(soc_a7ddrphy_dq_i_data2[4]), - .Q5(soc_a7ddrphy_dq_i_data2[3]), - .Q6(soc_a7ddrphy_dq_i_data2[2]), - .Q7(soc_a7ddrphy_dq_i_data2[1]), - .Q8(soc_a7ddrphy_dq_i_data2[0]) + .DDLY(main_a7ddrphy_dq_i_delayed2), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip21[7]), + .Q2(main_a7ddrphy_bitslip21[6]), + .Q3(main_a7ddrphy_bitslip21[5]), + .Q4(main_a7ddrphy_bitslip21[4]), + .Q5(main_a7ddrphy_bitslip21[3]), + .Q6(main_a7ddrphy_bitslip21[2]), + .Q7(main_a7ddrphy_bitslip21[1]), + .Q8(main_a7ddrphy_bitslip21[0]) ); IDELAYE2 #( @@ -15791,21 +18576,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_4 ( +) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed2) + .DATAOUT(main_a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_a7ddrphy_dq_o_nodelay2), - .T(soc_a7ddrphy_dq_t2), + .I(main_a7ddrphy_dq_o_nodelay2), + .T(main_a7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_a7ddrphy_dq_i_nodelay2) + .O(main_a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -15817,20 +18602,20 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .D1(main_a7ddrphy_bitslip30[0]), + .D2(main_a7ddrphy_bitslip30[1]), + .D3(main_a7ddrphy_bitslip30[2]), + .D4(main_a7ddrphy_bitslip30[3]), + .D5(main_a7ddrphy_bitslip30[4]), + .D6(main_a7ddrphy_bitslip30[5]), + .D7(main_a7ddrphy_bitslip30[6]), + .D8(main_a7ddrphy_bitslip30[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay3), - .TQ(soc_a7ddrphy_dq_t3) + .OQ(main_a7ddrphy_dq_o_nodelay3), + .TQ(main_a7ddrphy_dq_t3) ); ISERDESE2 #( @@ -15846,16 +18631,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed3), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data3[7]), - .Q2(soc_a7ddrphy_dq_i_data3[6]), - .Q3(soc_a7ddrphy_dq_i_data3[5]), - .Q4(soc_a7ddrphy_dq_i_data3[4]), - .Q5(soc_a7ddrphy_dq_i_data3[3]), - .Q6(soc_a7ddrphy_dq_i_data3[2]), - .Q7(soc_a7ddrphy_dq_i_data3[1]), - .Q8(soc_a7ddrphy_dq_i_data3[0]) + .DDLY(main_a7ddrphy_dq_i_delayed3), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip31[7]), + .Q2(main_a7ddrphy_bitslip31[6]), + .Q3(main_a7ddrphy_bitslip31[5]), + .Q4(main_a7ddrphy_bitslip31[4]), + .Q5(main_a7ddrphy_bitslip31[3]), + .Q6(main_a7ddrphy_bitslip31[2]), + .Q7(main_a7ddrphy_bitslip31[1]), + .Q8(main_a7ddrphy_bitslip31[0]) ); IDELAYE2 #( @@ -15867,21 +18652,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_5 ( +) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed3) + .DATAOUT(main_a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_a7ddrphy_dq_o_nodelay3), - .T(soc_a7ddrphy_dq_t3), + .I(main_a7ddrphy_dq_o_nodelay3), + .T(main_a7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_a7ddrphy_dq_i_nodelay3) + .O(main_a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -15893,20 +18678,20 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .D1(main_a7ddrphy_bitslip40[0]), + .D2(main_a7ddrphy_bitslip40[1]), + .D3(main_a7ddrphy_bitslip40[2]), + .D4(main_a7ddrphy_bitslip40[3]), + .D5(main_a7ddrphy_bitslip40[4]), + .D6(main_a7ddrphy_bitslip40[5]), + .D7(main_a7ddrphy_bitslip40[6]), + .D8(main_a7ddrphy_bitslip40[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay4), - .TQ(soc_a7ddrphy_dq_t4) + .OQ(main_a7ddrphy_dq_o_nodelay4), + .TQ(main_a7ddrphy_dq_t4) ); ISERDESE2 #( @@ -15922,16 +18707,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed4), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data4[7]), - .Q2(soc_a7ddrphy_dq_i_data4[6]), - .Q3(soc_a7ddrphy_dq_i_data4[5]), - .Q4(soc_a7ddrphy_dq_i_data4[4]), - .Q5(soc_a7ddrphy_dq_i_data4[3]), - .Q6(soc_a7ddrphy_dq_i_data4[2]), - .Q7(soc_a7ddrphy_dq_i_data4[1]), - .Q8(soc_a7ddrphy_dq_i_data4[0]) + .DDLY(main_a7ddrphy_dq_i_delayed4), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip41[7]), + .Q2(main_a7ddrphy_bitslip41[6]), + .Q3(main_a7ddrphy_bitslip41[5]), + .Q4(main_a7ddrphy_bitslip41[4]), + .Q5(main_a7ddrphy_bitslip41[3]), + .Q6(main_a7ddrphy_bitslip41[2]), + .Q7(main_a7ddrphy_bitslip41[1]), + .Q8(main_a7ddrphy_bitslip41[0]) ); IDELAYE2 #( @@ -15943,21 +18728,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_6 ( +) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed4) + .DATAOUT(main_a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_a7ddrphy_dq_o_nodelay4), - .T(soc_a7ddrphy_dq_t4), + .I(main_a7ddrphy_dq_o_nodelay4), + .T(main_a7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_a7ddrphy_dq_i_nodelay4) + .O(main_a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -15969,20 +18754,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .D1(main_a7ddrphy_bitslip50[0]), + .D2(main_a7ddrphy_bitslip50[1]), + .D3(main_a7ddrphy_bitslip50[2]), + .D4(main_a7ddrphy_bitslip50[3]), + .D5(main_a7ddrphy_bitslip50[4]), + .D6(main_a7ddrphy_bitslip50[5]), + .D7(main_a7ddrphy_bitslip50[6]), + .D8(main_a7ddrphy_bitslip50[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay5), - .TQ(soc_a7ddrphy_dq_t5) + .OQ(main_a7ddrphy_dq_o_nodelay5), + .TQ(main_a7ddrphy_dq_t5) ); ISERDESE2 #( @@ -15998,16 +18783,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed5), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data5[7]), - .Q2(soc_a7ddrphy_dq_i_data5[6]), - .Q3(soc_a7ddrphy_dq_i_data5[5]), - .Q4(soc_a7ddrphy_dq_i_data5[4]), - .Q5(soc_a7ddrphy_dq_i_data5[3]), - .Q6(soc_a7ddrphy_dq_i_data5[2]), - .Q7(soc_a7ddrphy_dq_i_data5[1]), - .Q8(soc_a7ddrphy_dq_i_data5[0]) + .DDLY(main_a7ddrphy_dq_i_delayed5), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip51[7]), + .Q2(main_a7ddrphy_bitslip51[6]), + .Q3(main_a7ddrphy_bitslip51[5]), + .Q4(main_a7ddrphy_bitslip51[4]), + .Q5(main_a7ddrphy_bitslip51[3]), + .Q6(main_a7ddrphy_bitslip51[2]), + .Q7(main_a7ddrphy_bitslip51[1]), + .Q8(main_a7ddrphy_bitslip51[0]) ); IDELAYE2 #( @@ -16019,21 +18804,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_7 ( +) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed5) + .DATAOUT(main_a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_a7ddrphy_dq_o_nodelay5), - .T(soc_a7ddrphy_dq_t5), + .I(main_a7ddrphy_dq_o_nodelay5), + .T(main_a7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_a7ddrphy_dq_i_nodelay5) + .O(main_a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -16045,20 +18830,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .D1(main_a7ddrphy_bitslip60[0]), + .D2(main_a7ddrphy_bitslip60[1]), + .D3(main_a7ddrphy_bitslip60[2]), + .D4(main_a7ddrphy_bitslip60[3]), + .D5(main_a7ddrphy_bitslip60[4]), + .D6(main_a7ddrphy_bitslip60[5]), + .D7(main_a7ddrphy_bitslip60[6]), + .D8(main_a7ddrphy_bitslip60[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay6), - .TQ(soc_a7ddrphy_dq_t6) + .OQ(main_a7ddrphy_dq_o_nodelay6), + .TQ(main_a7ddrphy_dq_t6) ); ISERDESE2 #( @@ -16074,16 +18859,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed6), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data6[7]), - .Q2(soc_a7ddrphy_dq_i_data6[6]), - .Q3(soc_a7ddrphy_dq_i_data6[5]), - .Q4(soc_a7ddrphy_dq_i_data6[4]), - .Q5(soc_a7ddrphy_dq_i_data6[3]), - .Q6(soc_a7ddrphy_dq_i_data6[2]), - .Q7(soc_a7ddrphy_dq_i_data6[1]), - .Q8(soc_a7ddrphy_dq_i_data6[0]) + .DDLY(main_a7ddrphy_dq_i_delayed6), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip61[7]), + .Q2(main_a7ddrphy_bitslip61[6]), + .Q3(main_a7ddrphy_bitslip61[5]), + .Q4(main_a7ddrphy_bitslip61[4]), + .Q5(main_a7ddrphy_bitslip61[3]), + .Q6(main_a7ddrphy_bitslip61[2]), + .Q7(main_a7ddrphy_bitslip61[1]), + .Q8(main_a7ddrphy_bitslip61[0]) ); IDELAYE2 #( @@ -16095,21 +18880,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_8 ( +) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed6) + .DATAOUT(main_a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_a7ddrphy_dq_o_nodelay6), - .T(soc_a7ddrphy_dq_t6), + .I(main_a7ddrphy_dq_o_nodelay6), + .T(main_a7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_a7ddrphy_dq_i_nodelay6) + .O(main_a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -16121,20 +18906,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .D1(main_a7ddrphy_bitslip70[0]), + .D2(main_a7ddrphy_bitslip70[1]), + .D3(main_a7ddrphy_bitslip70[2]), + .D4(main_a7ddrphy_bitslip70[3]), + .D5(main_a7ddrphy_bitslip70[4]), + .D6(main_a7ddrphy_bitslip70[5]), + .D7(main_a7ddrphy_bitslip70[6]), + .D8(main_a7ddrphy_bitslip70[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay7), - .TQ(soc_a7ddrphy_dq_t7) + .OQ(main_a7ddrphy_dq_o_nodelay7), + .TQ(main_a7ddrphy_dq_t7) ); ISERDESE2 #( @@ -16150,16 +18935,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed7), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data7[7]), - .Q2(soc_a7ddrphy_dq_i_data7[6]), - .Q3(soc_a7ddrphy_dq_i_data7[5]), - .Q4(soc_a7ddrphy_dq_i_data7[4]), - .Q5(soc_a7ddrphy_dq_i_data7[3]), - .Q6(soc_a7ddrphy_dq_i_data7[2]), - .Q7(soc_a7ddrphy_dq_i_data7[1]), - .Q8(soc_a7ddrphy_dq_i_data7[0]) + .DDLY(main_a7ddrphy_dq_i_delayed7), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip71[7]), + .Q2(main_a7ddrphy_bitslip71[6]), + .Q3(main_a7ddrphy_bitslip71[5]), + .Q4(main_a7ddrphy_bitslip71[4]), + .Q5(main_a7ddrphy_bitslip71[3]), + .Q6(main_a7ddrphy_bitslip71[2]), + .Q7(main_a7ddrphy_bitslip71[1]), + .Q8(main_a7ddrphy_bitslip71[0]) ); IDELAYE2 #( @@ -16171,21 +18956,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_9 ( +) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed7) + .DATAOUT(main_a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_a7ddrphy_dq_o_nodelay7), - .T(soc_a7ddrphy_dq_t7), + .I(main_a7ddrphy_dq_o_nodelay7), + .T(main_a7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_a7ddrphy_dq_i_nodelay7) + .O(main_a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -16197,20 +18982,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .D1(main_a7ddrphy_bitslip80[0]), + .D2(main_a7ddrphy_bitslip80[1]), + .D3(main_a7ddrphy_bitslip80[2]), + .D4(main_a7ddrphy_bitslip80[3]), + .D5(main_a7ddrphy_bitslip80[4]), + .D6(main_a7ddrphy_bitslip80[5]), + .D7(main_a7ddrphy_bitslip80[6]), + .D8(main_a7ddrphy_bitslip80[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay8), - .TQ(soc_a7ddrphy_dq_t8) + .OQ(main_a7ddrphy_dq_o_nodelay8), + .TQ(main_a7ddrphy_dq_t8) ); ISERDESE2 #( @@ -16226,16 +19011,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed8), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data8[7]), - .Q2(soc_a7ddrphy_dq_i_data8[6]), - .Q3(soc_a7ddrphy_dq_i_data8[5]), - .Q4(soc_a7ddrphy_dq_i_data8[4]), - .Q5(soc_a7ddrphy_dq_i_data8[3]), - .Q6(soc_a7ddrphy_dq_i_data8[2]), - .Q7(soc_a7ddrphy_dq_i_data8[1]), - .Q8(soc_a7ddrphy_dq_i_data8[0]) + .DDLY(main_a7ddrphy_dq_i_delayed8), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip81[7]), + .Q2(main_a7ddrphy_bitslip81[6]), + .Q3(main_a7ddrphy_bitslip81[5]), + .Q4(main_a7ddrphy_bitslip81[4]), + .Q5(main_a7ddrphy_bitslip81[3]), + .Q6(main_a7ddrphy_bitslip81[2]), + .Q7(main_a7ddrphy_bitslip81[1]), + .Q8(main_a7ddrphy_bitslip81[0]) ); IDELAYE2 #( @@ -16247,21 +19032,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_10 ( +) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed8) + .DATAOUT(main_a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_a7ddrphy_dq_o_nodelay8), - .T(soc_a7ddrphy_dq_t8), + .I(main_a7ddrphy_dq_o_nodelay8), + .T(main_a7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_a7ddrphy_dq_i_nodelay8) + .O(main_a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -16273,20 +19058,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .D1(main_a7ddrphy_bitslip90[0]), + .D2(main_a7ddrphy_bitslip90[1]), + .D3(main_a7ddrphy_bitslip90[2]), + .D4(main_a7ddrphy_bitslip90[3]), + .D5(main_a7ddrphy_bitslip90[4]), + .D6(main_a7ddrphy_bitslip90[5]), + .D7(main_a7ddrphy_bitslip90[6]), + .D8(main_a7ddrphy_bitslip90[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay9), - .TQ(soc_a7ddrphy_dq_t9) + .OQ(main_a7ddrphy_dq_o_nodelay9), + .TQ(main_a7ddrphy_dq_t9) ); ISERDESE2 #( @@ -16302,16 +19087,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed9), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data9[7]), - .Q2(soc_a7ddrphy_dq_i_data9[6]), - .Q3(soc_a7ddrphy_dq_i_data9[5]), - .Q4(soc_a7ddrphy_dq_i_data9[4]), - .Q5(soc_a7ddrphy_dq_i_data9[3]), - .Q6(soc_a7ddrphy_dq_i_data9[2]), - .Q7(soc_a7ddrphy_dq_i_data9[1]), - .Q8(soc_a7ddrphy_dq_i_data9[0]) + .DDLY(main_a7ddrphy_dq_i_delayed9), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip91[7]), + .Q2(main_a7ddrphy_bitslip91[6]), + .Q3(main_a7ddrphy_bitslip91[5]), + .Q4(main_a7ddrphy_bitslip91[4]), + .Q5(main_a7ddrphy_bitslip91[3]), + .Q6(main_a7ddrphy_bitslip91[2]), + .Q7(main_a7ddrphy_bitslip91[1]), + .Q8(main_a7ddrphy_bitslip91[0]) ); IDELAYE2 #( @@ -16323,21 +19108,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_11 ( +) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed9) + .DATAOUT(main_a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_a7ddrphy_dq_o_nodelay9), - .T(soc_a7ddrphy_dq_t9), + .I(main_a7ddrphy_dq_o_nodelay9), + .T(main_a7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_a7ddrphy_dq_i_nodelay9) + .O(main_a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -16349,20 +19134,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .D1(main_a7ddrphy_bitslip100[0]), + .D2(main_a7ddrphy_bitslip100[1]), + .D3(main_a7ddrphy_bitslip100[2]), + .D4(main_a7ddrphy_bitslip100[3]), + .D5(main_a7ddrphy_bitslip100[4]), + .D6(main_a7ddrphy_bitslip100[5]), + .D7(main_a7ddrphy_bitslip100[6]), + .D8(main_a7ddrphy_bitslip100[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay10), - .TQ(soc_a7ddrphy_dq_t10) + .OQ(main_a7ddrphy_dq_o_nodelay10), + .TQ(main_a7ddrphy_dq_t10) ); ISERDESE2 #( @@ -16378,16 +19163,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed10), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data10[7]), - .Q2(soc_a7ddrphy_dq_i_data10[6]), - .Q3(soc_a7ddrphy_dq_i_data10[5]), - .Q4(soc_a7ddrphy_dq_i_data10[4]), - .Q5(soc_a7ddrphy_dq_i_data10[3]), - .Q6(soc_a7ddrphy_dq_i_data10[2]), - .Q7(soc_a7ddrphy_dq_i_data10[1]), - .Q8(soc_a7ddrphy_dq_i_data10[0]) + .DDLY(main_a7ddrphy_dq_i_delayed10), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip101[7]), + .Q2(main_a7ddrphy_bitslip101[6]), + .Q3(main_a7ddrphy_bitslip101[5]), + .Q4(main_a7ddrphy_bitslip101[4]), + .Q5(main_a7ddrphy_bitslip101[3]), + .Q6(main_a7ddrphy_bitslip101[2]), + .Q7(main_a7ddrphy_bitslip101[1]), + .Q8(main_a7ddrphy_bitslip101[0]) ); IDELAYE2 #( @@ -16399,21 +19184,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_12 ( +) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed10) + .DATAOUT(main_a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_a7ddrphy_dq_o_nodelay10), - .T(soc_a7ddrphy_dq_t10), + .I(main_a7ddrphy_dq_o_nodelay10), + .T(main_a7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_a7ddrphy_dq_i_nodelay10) + .O(main_a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -16425,20 +19210,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .D1(main_a7ddrphy_bitslip110[0]), + .D2(main_a7ddrphy_bitslip110[1]), + .D3(main_a7ddrphy_bitslip110[2]), + .D4(main_a7ddrphy_bitslip110[3]), + .D5(main_a7ddrphy_bitslip110[4]), + .D6(main_a7ddrphy_bitslip110[5]), + .D7(main_a7ddrphy_bitslip110[6]), + .D8(main_a7ddrphy_bitslip110[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay11), - .TQ(soc_a7ddrphy_dq_t11) + .OQ(main_a7ddrphy_dq_o_nodelay11), + .TQ(main_a7ddrphy_dq_t11) ); ISERDESE2 #( @@ -16454,16 +19239,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed11), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data11[7]), - .Q2(soc_a7ddrphy_dq_i_data11[6]), - .Q3(soc_a7ddrphy_dq_i_data11[5]), - .Q4(soc_a7ddrphy_dq_i_data11[4]), - .Q5(soc_a7ddrphy_dq_i_data11[3]), - .Q6(soc_a7ddrphy_dq_i_data11[2]), - .Q7(soc_a7ddrphy_dq_i_data11[1]), - .Q8(soc_a7ddrphy_dq_i_data11[0]) + .DDLY(main_a7ddrphy_dq_i_delayed11), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip111[7]), + .Q2(main_a7ddrphy_bitslip111[6]), + .Q3(main_a7ddrphy_bitslip111[5]), + .Q4(main_a7ddrphy_bitslip111[4]), + .Q5(main_a7ddrphy_bitslip111[3]), + .Q6(main_a7ddrphy_bitslip111[2]), + .Q7(main_a7ddrphy_bitslip111[1]), + .Q8(main_a7ddrphy_bitslip111[0]) ); IDELAYE2 #( @@ -16475,21 +19260,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_13 ( +) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed11) + .DATAOUT(main_a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_a7ddrphy_dq_o_nodelay11), - .T(soc_a7ddrphy_dq_t11), + .I(main_a7ddrphy_dq_o_nodelay11), + .T(main_a7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_a7ddrphy_dq_i_nodelay11) + .O(main_a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -16501,20 +19286,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .D1(main_a7ddrphy_bitslip120[0]), + .D2(main_a7ddrphy_bitslip120[1]), + .D3(main_a7ddrphy_bitslip120[2]), + .D4(main_a7ddrphy_bitslip120[3]), + .D5(main_a7ddrphy_bitslip120[4]), + .D6(main_a7ddrphy_bitslip120[5]), + .D7(main_a7ddrphy_bitslip120[6]), + .D8(main_a7ddrphy_bitslip120[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay12), - .TQ(soc_a7ddrphy_dq_t12) + .OQ(main_a7ddrphy_dq_o_nodelay12), + .TQ(main_a7ddrphy_dq_t12) ); ISERDESE2 #( @@ -16530,16 +19315,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed12), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data12[7]), - .Q2(soc_a7ddrphy_dq_i_data12[6]), - .Q3(soc_a7ddrphy_dq_i_data12[5]), - .Q4(soc_a7ddrphy_dq_i_data12[4]), - .Q5(soc_a7ddrphy_dq_i_data12[3]), - .Q6(soc_a7ddrphy_dq_i_data12[2]), - .Q7(soc_a7ddrphy_dq_i_data12[1]), - .Q8(soc_a7ddrphy_dq_i_data12[0]) + .DDLY(main_a7ddrphy_dq_i_delayed12), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip121[7]), + .Q2(main_a7ddrphy_bitslip121[6]), + .Q3(main_a7ddrphy_bitslip121[5]), + .Q4(main_a7ddrphy_bitslip121[4]), + .Q5(main_a7ddrphy_bitslip121[3]), + .Q6(main_a7ddrphy_bitslip121[2]), + .Q7(main_a7ddrphy_bitslip121[1]), + .Q8(main_a7ddrphy_bitslip121[0]) ); IDELAYE2 #( @@ -16551,21 +19336,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_14 ( +) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed12) + .DATAOUT(main_a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_a7ddrphy_dq_o_nodelay12), - .T(soc_a7ddrphy_dq_t12), + .I(main_a7ddrphy_dq_o_nodelay12), + .T(main_a7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_a7ddrphy_dq_i_nodelay12) + .O(main_a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -16577,20 +19362,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .D1(main_a7ddrphy_bitslip130[0]), + .D2(main_a7ddrphy_bitslip130[1]), + .D3(main_a7ddrphy_bitslip130[2]), + .D4(main_a7ddrphy_bitslip130[3]), + .D5(main_a7ddrphy_bitslip130[4]), + .D6(main_a7ddrphy_bitslip130[5]), + .D7(main_a7ddrphy_bitslip130[6]), + .D8(main_a7ddrphy_bitslip130[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay13), - .TQ(soc_a7ddrphy_dq_t13) + .OQ(main_a7ddrphy_dq_o_nodelay13), + .TQ(main_a7ddrphy_dq_t13) ); ISERDESE2 #( @@ -16606,16 +19391,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed13), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data13[7]), - .Q2(soc_a7ddrphy_dq_i_data13[6]), - .Q3(soc_a7ddrphy_dq_i_data13[5]), - .Q4(soc_a7ddrphy_dq_i_data13[4]), - .Q5(soc_a7ddrphy_dq_i_data13[3]), - .Q6(soc_a7ddrphy_dq_i_data13[2]), - .Q7(soc_a7ddrphy_dq_i_data13[1]), - .Q8(soc_a7ddrphy_dq_i_data13[0]) + .DDLY(main_a7ddrphy_dq_i_delayed13), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip131[7]), + .Q2(main_a7ddrphy_bitslip131[6]), + .Q3(main_a7ddrphy_bitslip131[5]), + .Q4(main_a7ddrphy_bitslip131[4]), + .Q5(main_a7ddrphy_bitslip131[3]), + .Q6(main_a7ddrphy_bitslip131[2]), + .Q7(main_a7ddrphy_bitslip131[1]), + .Q8(main_a7ddrphy_bitslip131[0]) ); IDELAYE2 #( @@ -16627,21 +19412,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_15 ( +) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed13) + .DATAOUT(main_a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_a7ddrphy_dq_o_nodelay13), - .T(soc_a7ddrphy_dq_t13), + .I(main_a7ddrphy_dq_o_nodelay13), + .T(main_a7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_a7ddrphy_dq_i_nodelay13) + .O(main_a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -16653,20 +19438,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .D1(main_a7ddrphy_bitslip140[0]), + .D2(main_a7ddrphy_bitslip140[1]), + .D3(main_a7ddrphy_bitslip140[2]), + .D4(main_a7ddrphy_bitslip140[3]), + .D5(main_a7ddrphy_bitslip140[4]), + .D6(main_a7ddrphy_bitslip140[5]), + .D7(main_a7ddrphy_bitslip140[6]), + .D8(main_a7ddrphy_bitslip140[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay14), - .TQ(soc_a7ddrphy_dq_t14) + .OQ(main_a7ddrphy_dq_o_nodelay14), + .TQ(main_a7ddrphy_dq_t14) ); ISERDESE2 #( @@ -16682,16 +19467,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed14), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data14[7]), - .Q2(soc_a7ddrphy_dq_i_data14[6]), - .Q3(soc_a7ddrphy_dq_i_data14[5]), - .Q4(soc_a7ddrphy_dq_i_data14[4]), - .Q5(soc_a7ddrphy_dq_i_data14[3]), - .Q6(soc_a7ddrphy_dq_i_data14[2]), - .Q7(soc_a7ddrphy_dq_i_data14[1]), - .Q8(soc_a7ddrphy_dq_i_data14[0]) + .DDLY(main_a7ddrphy_dq_i_delayed14), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip141[7]), + .Q2(main_a7ddrphy_bitslip141[6]), + .Q3(main_a7ddrphy_bitslip141[5]), + .Q4(main_a7ddrphy_bitslip141[4]), + .Q5(main_a7ddrphy_bitslip141[3]), + .Q6(main_a7ddrphy_bitslip141[2]), + .Q7(main_a7ddrphy_bitslip141[1]), + .Q8(main_a7ddrphy_bitslip141[0]) ); IDELAYE2 #( @@ -16703,21 +19488,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_16 ( +) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed14) + .DATAOUT(main_a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_a7ddrphy_dq_o_nodelay14), - .T(soc_a7ddrphy_dq_t14), + .I(main_a7ddrphy_dq_o_nodelay14), + .T(main_a7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_a7ddrphy_dq_i_nodelay14) + .O(main_a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -16729,20 +19514,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .D1(main_a7ddrphy_bitslip150[0]), + .D2(main_a7ddrphy_bitslip150[1]), + .D3(main_a7ddrphy_bitslip150[2]), + .D4(main_a7ddrphy_bitslip150[3]), + .D5(main_a7ddrphy_bitslip150[4]), + .D6(main_a7ddrphy_bitslip150[5]), + .D7(main_a7ddrphy_bitslip150[6]), + .D8(main_a7ddrphy_bitslip150[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay15), - .TQ(soc_a7ddrphy_dq_t15) + .OQ(main_a7ddrphy_dq_o_nodelay15), + .TQ(main_a7ddrphy_dq_t15) ); ISERDESE2 #( @@ -16758,16 +19543,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed15), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data15[7]), - .Q2(soc_a7ddrphy_dq_i_data15[6]), - .Q3(soc_a7ddrphy_dq_i_data15[5]), - .Q4(soc_a7ddrphy_dq_i_data15[4]), - .Q5(soc_a7ddrphy_dq_i_data15[3]), - .Q6(soc_a7ddrphy_dq_i_data15[2]), - .Q7(soc_a7ddrphy_dq_i_data15[1]), - .Q8(soc_a7ddrphy_dq_i_data15[0]) + .DDLY(main_a7ddrphy_dq_i_delayed15), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip151[7]), + .Q2(main_a7ddrphy_bitslip151[6]), + .Q3(main_a7ddrphy_bitslip151[5]), + .Q4(main_a7ddrphy_bitslip151[4]), + .Q5(main_a7ddrphy_bitslip151[3]), + .Q6(main_a7ddrphy_bitslip151[2]), + .Q7(main_a7ddrphy_bitslip151[1]), + .Q8(main_a7ddrphy_bitslip151[0]) ); IDELAYE2 #( @@ -16779,134 +19564,182 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_17 ( +) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed15) + .DATAOUT(main_a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_a7ddrphy_dq_o_nodelay15), - .T(soc_a7ddrphy_dq_t15), + .I(main_a7ddrphy_dq_o_nodelay15), + .T(main_a7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_a7ddrphy_dq_i_nodelay15) + .O(main_a7ddrphy_dq_i_nodelay15) ); reg [23:0] storage[0:15]; reg [23:0] memdat; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_1[0:15]; reg [23:0] memdat_1; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_2[0:15]; reg [23:0] memdat_2; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_3[0:15]; reg [23:0] memdat_3; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_4[0:15]; reg [23:0] memdat_4; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_5[0:15]; reg [23:0] memdat_5; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_6[0:15]; reg [23:0] memdat_6; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_7[0:15]; reg [23:0] memdat_7; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +FD FD( + .C(main_clkin), + .D(main_reset), + .Q(builder_reset0) +); + +FD FD_1( + .C(main_clkin), + .D(builder_reset0), + .Q(builder_reset1) +); + +FD FD_2( + .C(main_clkin), + .D(builder_reset1), + .Q(builder_reset2) +); + +FD FD_3( + .C(main_clkin), + .D(builder_reset2), + .Q(builder_reset3) +); + +FD FD_4( + .C(main_clkin), + .D(builder_reset3), + .Q(builder_reset4) +); + +FD FD_5( + .C(main_clkin), + .D(builder_reset4), + .Q(builder_reset5) +); + +FD FD_6( + .C(main_clkin), + .D(builder_reset5), + .Q(builder_reset6) +); + +FD FD_7( + .C(main_clkin), + .D(builder_reset6), + .Q(builder_reset7) +); PLLE2_ADV #( .CLKFBOUT_MULT(5'd16), @@ -16923,15 +19756,16 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb), - .CLKIN1(soc_clkin), - .RST(soc_reset), - .CLKFBOUT(vns_pll_fb), - .CLKOUT0(soc_clkout0), - .CLKOUT1(soc_clkout1), - .CLKOUT2(soc_clkout2), - .CLKOUT3(soc_clkout3), - .LOCKED(soc_locked) + .CLKFBIN(builder_pll_fb), + .CLKIN1(main_clkin), + .PWRDWN(main_power_down), + .RST(builder_reset7), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout0), + .CLKOUT1(main_clkout1), + .CLKOUT2(main_clkout2), + .CLKOUT3(main_clkout3), + .LOCKED(main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -16940,8 +19774,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16949,8 +19783,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(iodelay_rst) ); @@ -16960,8 +19794,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16969,8 +19803,8 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), .Q(sys_rst) ); @@ -16980,8 +19814,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16989,9 +19823,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -17000,8 +19834,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17009,9 +19843,9 @@ PLLE2_ADV #( ) FDPE_7 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) + .D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init index 921f352..0d0118b 100644 --- a/litedram/generated/genesys2/litedram_core.init +++ b/litedram/generated/genesys2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d8658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -518,79 +518,78 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842b0c4 -fbe1fff8fbc1fff0 -f821ff51f8010010 -f88100d83be10020 +7c0802a63842bbc4 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-41524420676e697a -383025783040204d -0000000a2e2e2e78 +6e69686374697753 +204d415244532067 +7774666f73206f74 +746e6f6320657261 +0000000a2e6c6f72 +6e69686374697753 +204d415244532067 +7764726168206f74 +746e6f6320657261 +0000000a2e6c6f72 +7165204b43742020 +746e656c61766975 +25203a7370617420 +0000000000000a64 +6c432f646d432020 +28206e616373206b +000a2964252d6425 +00000000007c2020 +203a74736562207c +00000000000a6425 +6e69747465532020 +6c432f646d432067 +2079616c6564206b +6174206425206f74 +000000000a2e7370 +7320617461442020 +0000000a3a6e6163 +203a747365622020 +302562202c64256d +6000000000206432 656c206574697257 0a3a676e696c6576 0000000000000000 +616c206574697257 +61632079636e6574 +6f6974617262696c +00000000000a3a6e +0000202d3a64256d +002064253a64256d +5144206574697257 +617274205351442d +000a3a676e696e69 76656c2064616552 000a3a676e696c65 -302562202c64256d -0000007c203a6432 -000000000000207c -256d203a74736562 -6432302562202c64 -0000000000000020 -6f6e204d41524453 -207265646e752077 -6572617774666f73 -6c6f72746e6f6320 -000000000000000a -2f646e616d6d6f43 -6e616373206b6c43 -0000000000000a3a -0000000000000031 -0000000000000030 -203a74736562207c -00000000000a6425 -6163732061746144 -00000000000a3a6e -00007c203a64256d -0000000000006425 -000000000000007c -203a79616c656420 -0000000a64323025 +696c616974696e49 +52445320676e697a +3025783040204d41 +000a2e2e2e786c38 +0000000042756c25 +4b756c252e756c25 +0000000000004269 +4d756c252e756c25 +0000000000004269 +47756c252e756c25 +0000000000004269 +2d78257830207325 +0000002078257830 +000000000d202020 +3a65746972572020 +0000000000000000 +3a64616552202020 +0000000000000000 64656570736d654d -7025783020746120 -000000000a2e2e2e -203a736574697257 -7370624d20646c25 -000000000000000a -20203a7364616552 -7370624d20646c25 -000000000000000a +2820702520746120 +0000000000000000 +0000000a2e2e2e29 +2065746972572020 +00203a6465657073 +000000000000732f +2064616552202020 +00203a6465657073 20747365746d654d -2e70257830207461 -00000000000a2e2e -726520737562202d +0028207025207461 +7265207375622020 2520203a73726f72 00000a646c252f64 -652072646461202d +6520726464612020 25203a73726f7272 00000a646c252f64 -652061746164202d +6520617461642020 25203a73726f7272 00000a646c252f64 20747365746d654d 00000000000a4f4b 20747365746d654d -00000000000a4b4f +60000000000a4b4f +3736353433323130 +6665646362613938 +0000000000000000 +0000000000007830 0000000000000000 00000000000000ff 000000000000ffff @@ -2095,5 +2445,5 @@ e8010010ebc1fff0 0000ffffffffffff 00ffffffffffffff ffffffffffffffff -0000000000007830 +ffffffffffffffff 0000000000000001 diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v index 2afd926..598620b 100644 --- a/litedram/generated/genesys2/litedram_core.v +++ b/litedram/generated/genesys2/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (--------) & LiteX (2ec4604c) on 2020-08-06 07:16:18 +// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:22 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -48,2069 +48,2482 @@ module litedram_core( output wire [255:0] user_port_native_0_rdata_data ); -reg [13:0] soc_litedramcore_adr = 14'd0; -reg soc_litedramcore_we = 1'd0; -wire [31:0] soc_litedramcore_dat_w; -wire [31:0] soc_litedramcore_dat_r; -wire [29:0] soc_litedramcore_wishbone_adr; -wire [31:0] soc_litedramcore_wishbone_dat_w; -wire [31:0] soc_litedramcore_wishbone_dat_r; -wire [3:0] soc_litedramcore_wishbone_sel; -wire soc_litedramcore_wishbone_cyc; -wire soc_litedramcore_wishbone_stb; -reg soc_litedramcore_wishbone_ack = 1'd0; -wire soc_litedramcore_wishbone_we; -wire [2:0] soc_litedramcore_wishbone_cti; -wire [1:0] soc_litedramcore_wishbone_bte; -reg soc_litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_reset; -wire soc_locked; -wire soc_clkin; -wire soc_clkout0; -wire soc_clkout_buf0; -wire soc_clkout1; -wire soc_clkout_buf1; -wire soc_clkout2; -wire soc_clkout_buf2; -wire soc_clkout3; -wire soc_clkout_buf3; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_k7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_k7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_k7ddrphy_wlevel_en_storage = 1'd0; -reg soc_k7ddrphy_wlevel_en_re = 1'd0; -wire soc_k7ddrphy_wlevel_strobe_re; -wire soc_k7ddrphy_wlevel_strobe_r; -wire soc_k7ddrphy_wlevel_strobe_we; -reg soc_k7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_k7ddrphy_cdly_rst_re; -wire soc_k7ddrphy_cdly_rst_r; -wire soc_k7ddrphy_cdly_rst_we; -reg soc_k7ddrphy_cdly_rst_w = 1'd0; -wire soc_k7ddrphy_cdly_inc_re; -wire soc_k7ddrphy_cdly_inc_r; -wire soc_k7ddrphy_cdly_inc_we; -reg soc_k7ddrphy_cdly_inc_w = 1'd0; -reg [3:0] soc_k7ddrphy_dly_sel_storage = 4'd0; -reg soc_k7ddrphy_dly_sel_re = 1'd0; -wire soc_k7ddrphy_rdly_dq_rst_re; -wire soc_k7ddrphy_rdly_dq_rst_r; -wire soc_k7ddrphy_rdly_dq_rst_we; -reg soc_k7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_k7ddrphy_rdly_dq_inc_re; -wire soc_k7ddrphy_rdly_dq_inc_r; -wire soc_k7ddrphy_rdly_dq_inc_we; -reg soc_k7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_k7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_k7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_k7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_k7ddrphy_rdly_dq_bitslip_re; -wire soc_k7ddrphy_rdly_dq_bitslip_r; -wire soc_k7ddrphy_rdly_dq_bitslip_we; -reg soc_k7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire soc_k7ddrphy_wdly_dq_rst_re; -wire soc_k7ddrphy_wdly_dq_rst_r; -wire soc_k7ddrphy_wdly_dq_rst_we; -reg soc_k7ddrphy_wdly_dq_rst_w = 1'd0; -wire soc_k7ddrphy_wdly_dq_inc_re; -wire soc_k7ddrphy_wdly_dq_inc_r; -wire soc_k7ddrphy_wdly_dq_inc_we; -reg soc_k7ddrphy_wdly_dq_inc_w = 1'd0; -wire soc_k7ddrphy_wdly_dqs_rst_re; -wire soc_k7ddrphy_wdly_dqs_rst_r; -wire soc_k7ddrphy_wdly_dqs_rst_we; -reg soc_k7ddrphy_wdly_dqs_rst_w = 1'd0; -wire soc_k7ddrphy_wdly_dqs_inc_re; -wire soc_k7ddrphy_wdly_dqs_inc_r; -wire soc_k7ddrphy_wdly_dqs_inc_we; -reg soc_k7ddrphy_wdly_dqs_inc_w = 1'd0; -wire [14:0] soc_k7ddrphy_dfi_p0_address; -wire [2:0] soc_k7ddrphy_dfi_p0_bank; -wire soc_k7ddrphy_dfi_p0_cas_n; -wire soc_k7ddrphy_dfi_p0_cs_n; -wire soc_k7ddrphy_dfi_p0_ras_n; -wire soc_k7ddrphy_dfi_p0_we_n; -wire soc_k7ddrphy_dfi_p0_cke; -wire soc_k7ddrphy_dfi_p0_odt; -wire soc_k7ddrphy_dfi_p0_reset_n; -wire soc_k7ddrphy_dfi_p0_act_n; -wire [63:0] soc_k7ddrphy_dfi_p0_wrdata; -wire soc_k7ddrphy_dfi_p0_wrdata_en; -wire [7:0] soc_k7ddrphy_dfi_p0_wrdata_mask; -wire soc_k7ddrphy_dfi_p0_rddata_en; -reg [63:0] soc_k7ddrphy_dfi_p0_rddata = 64'd0; -reg soc_k7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [14:0] soc_k7ddrphy_dfi_p1_address; -wire [2:0] soc_k7ddrphy_dfi_p1_bank; -wire soc_k7ddrphy_dfi_p1_cas_n; -wire soc_k7ddrphy_dfi_p1_cs_n; -wire soc_k7ddrphy_dfi_p1_ras_n; -wire soc_k7ddrphy_dfi_p1_we_n; -wire soc_k7ddrphy_dfi_p1_cke; -wire soc_k7ddrphy_dfi_p1_odt; -wire soc_k7ddrphy_dfi_p1_reset_n; -wire soc_k7ddrphy_dfi_p1_act_n; -wire [63:0] soc_k7ddrphy_dfi_p1_wrdata; -wire soc_k7ddrphy_dfi_p1_wrdata_en; -wire [7:0] soc_k7ddrphy_dfi_p1_wrdata_mask; -wire soc_k7ddrphy_dfi_p1_rddata_en; -reg [63:0] soc_k7ddrphy_dfi_p1_rddata = 64'd0; -reg soc_k7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [14:0] soc_k7ddrphy_dfi_p2_address; -wire [2:0] soc_k7ddrphy_dfi_p2_bank; -wire soc_k7ddrphy_dfi_p2_cas_n; -wire soc_k7ddrphy_dfi_p2_cs_n; -wire soc_k7ddrphy_dfi_p2_ras_n; -wire soc_k7ddrphy_dfi_p2_we_n; -wire soc_k7ddrphy_dfi_p2_cke; -wire soc_k7ddrphy_dfi_p2_odt; -wire soc_k7ddrphy_dfi_p2_reset_n; -wire soc_k7ddrphy_dfi_p2_act_n; -wire [63:0] soc_k7ddrphy_dfi_p2_wrdata; -wire soc_k7ddrphy_dfi_p2_wrdata_en; -wire [7:0] soc_k7ddrphy_dfi_p2_wrdata_mask; -wire soc_k7ddrphy_dfi_p2_rddata_en; -reg [63:0] soc_k7ddrphy_dfi_p2_rddata = 64'd0; -reg soc_k7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [14:0] soc_k7ddrphy_dfi_p3_address; -wire [2:0] soc_k7ddrphy_dfi_p3_bank; -wire soc_k7ddrphy_dfi_p3_cas_n; -wire soc_k7ddrphy_dfi_p3_cs_n; -wire soc_k7ddrphy_dfi_p3_ras_n; -wire soc_k7ddrphy_dfi_p3_we_n; -wire soc_k7ddrphy_dfi_p3_cke; -wire soc_k7ddrphy_dfi_p3_odt; -wire soc_k7ddrphy_dfi_p3_reset_n; -wire soc_k7ddrphy_dfi_p3_act_n; -wire [63:0] soc_k7ddrphy_dfi_p3_wrdata; -wire soc_k7ddrphy_dfi_p3_wrdata_en; -wire [7:0] soc_k7ddrphy_dfi_p3_wrdata_mask; -wire soc_k7ddrphy_dfi_p3_rddata_en; -reg [63:0] soc_k7ddrphy_dfi_p3_rddata = 64'd0; -reg soc_k7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_k7ddrphy_sd_clk_se_nodelay; -wire soc_k7ddrphy_sd_clk_se_delayed; -wire soc_k7ddrphy_address0; -wire soc_k7ddrphy_address1; -wire soc_k7ddrphy_address2; -wire soc_k7ddrphy_address3; -wire soc_k7ddrphy_address4; -wire soc_k7ddrphy_address5; -wire soc_k7ddrphy_address6; -wire soc_k7ddrphy_address7; -wire soc_k7ddrphy_address8; -wire soc_k7ddrphy_address9; -wire soc_k7ddrphy_address10; -wire soc_k7ddrphy_address11; -wire soc_k7ddrphy_address12; -wire soc_k7ddrphy_address13; -wire soc_k7ddrphy_address14; -wire soc_k7ddrphy_bank0; -wire soc_k7ddrphy_bank1; -wire soc_k7ddrphy_bank2; -wire soc_k7ddrphy_cmd0; -wire soc_k7ddrphy_cmd1; -wire soc_k7ddrphy_cmd2; -wire soc_k7ddrphy_cmd3; -wire soc_k7ddrphy_cmd4; -wire soc_k7ddrphy_cmd5; -wire soc_k7ddrphy_cmd6; -reg soc_k7ddrphy_dqs_oe = 1'd0; -reg soc_k7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_k7ddrphy_dqspattern0; -wire soc_k7ddrphy_dqspattern1; -reg [7:0] soc_k7ddrphy_dqspattern_o = 8'd0; -wire soc_k7ddrphy_dm_o_nodelay0; -wire soc_k7ddrphy_dm_o_nodelay1; -wire soc_k7ddrphy_dm_o_nodelay2; -wire soc_k7ddrphy_dm_o_nodelay3; -wire [3:0] soc_k7ddrphy_dqs_i; -wire [3:0] soc_k7ddrphy_dqs_i_delayed; -wire soc_k7ddrphy_dqs_o_no_delay0; -wire soc_k7ddrphy_dqs_o_delayed0; -wire soc_k7ddrphy_dqs_t0; -wire soc_k7ddrphy0; -wire soc_k7ddrphy_dqs_o_no_delay1; -wire soc_k7ddrphy_dqs_o_delayed1; -wire soc_k7ddrphy_dqs_t1; -wire soc_k7ddrphy1; -wire soc_k7ddrphy_dqs_o_no_delay2; -wire soc_k7ddrphy_dqs_o_delayed2; -wire soc_k7ddrphy_dqs_t2; -wire soc_k7ddrphy2; -wire soc_k7ddrphy_dqs_o_no_delay3; -wire soc_k7ddrphy_dqs_o_delayed3; -wire soc_k7ddrphy_dqs_t3; -wire soc_k7ddrphy3; -wire soc_k7ddrphy_dq_oe; -reg soc_k7ddrphy_dq_oe_delayed = 1'd0; -wire soc_k7ddrphy_dq_o_nodelay0; -wire soc_k7ddrphy_dq_o_delayed0; -wire soc_k7ddrphy_dq_i_nodelay0; -wire soc_k7ddrphy_dq_i_delayed0; -wire soc_k7ddrphy_dq_t0; -wire [7:0] soc_k7ddrphy_dq_i_data0; -wire [7:0] soc_k7ddrphy_bitslip0_i; -reg [7:0] soc_k7ddrphy_bitslip0_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip0_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip0_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay1; -wire soc_k7ddrphy_dq_o_delayed1; -wire soc_k7ddrphy_dq_i_nodelay1; -wire soc_k7ddrphy_dq_i_delayed1; -wire soc_k7ddrphy_dq_t1; -wire [7:0] soc_k7ddrphy_dq_i_data1; -wire [7:0] soc_k7ddrphy_bitslip1_i; -reg [7:0] soc_k7ddrphy_bitslip1_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip1_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip1_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay2; -wire soc_k7ddrphy_dq_o_delayed2; -wire soc_k7ddrphy_dq_i_nodelay2; -wire soc_k7ddrphy_dq_i_delayed2; -wire soc_k7ddrphy_dq_t2; -wire [7:0] soc_k7ddrphy_dq_i_data2; -wire [7:0] soc_k7ddrphy_bitslip2_i; -reg [7:0] soc_k7ddrphy_bitslip2_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip2_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip2_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay3; -wire soc_k7ddrphy_dq_o_delayed3; -wire soc_k7ddrphy_dq_i_nodelay3; -wire soc_k7ddrphy_dq_i_delayed3; -wire soc_k7ddrphy_dq_t3; -wire [7:0] soc_k7ddrphy_dq_i_data3; -wire [7:0] soc_k7ddrphy_bitslip3_i; -reg [7:0] soc_k7ddrphy_bitslip3_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip3_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip3_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay4; -wire soc_k7ddrphy_dq_o_delayed4; -wire soc_k7ddrphy_dq_i_nodelay4; -wire soc_k7ddrphy_dq_i_delayed4; -wire soc_k7ddrphy_dq_t4; -wire [7:0] soc_k7ddrphy_dq_i_data4; -wire [7:0] soc_k7ddrphy_bitslip4_i; -reg [7:0] soc_k7ddrphy_bitslip4_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip4_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip4_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay5; -wire soc_k7ddrphy_dq_o_delayed5; -wire soc_k7ddrphy_dq_i_nodelay5; -wire soc_k7ddrphy_dq_i_delayed5; -wire soc_k7ddrphy_dq_t5; -wire [7:0] soc_k7ddrphy_dq_i_data5; -wire [7:0] soc_k7ddrphy_bitslip5_i; -reg [7:0] soc_k7ddrphy_bitslip5_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip5_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip5_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay6; -wire soc_k7ddrphy_dq_o_delayed6; -wire soc_k7ddrphy_dq_i_nodelay6; -wire soc_k7ddrphy_dq_i_delayed6; -wire soc_k7ddrphy_dq_t6; -wire [7:0] soc_k7ddrphy_dq_i_data6; -wire [7:0] soc_k7ddrphy_bitslip6_i; -reg [7:0] soc_k7ddrphy_bitslip6_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip6_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip6_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay7; -wire soc_k7ddrphy_dq_o_delayed7; -wire soc_k7ddrphy_dq_i_nodelay7; -wire soc_k7ddrphy_dq_i_delayed7; -wire soc_k7ddrphy_dq_t7; -wire [7:0] soc_k7ddrphy_dq_i_data7; -wire [7:0] soc_k7ddrphy_bitslip7_i; -reg [7:0] soc_k7ddrphy_bitslip7_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip7_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip7_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay8; -wire soc_k7ddrphy_dq_o_delayed8; -wire soc_k7ddrphy_dq_i_nodelay8; -wire soc_k7ddrphy_dq_i_delayed8; -wire soc_k7ddrphy_dq_t8; -wire [7:0] soc_k7ddrphy_dq_i_data8; -wire [7:0] soc_k7ddrphy_bitslip8_i; -reg [7:0] soc_k7ddrphy_bitslip8_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip8_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip8_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay9; -wire soc_k7ddrphy_dq_o_delayed9; -wire soc_k7ddrphy_dq_i_nodelay9; -wire soc_k7ddrphy_dq_i_delayed9; -wire soc_k7ddrphy_dq_t9; -wire [7:0] soc_k7ddrphy_dq_i_data9; -wire [7:0] soc_k7ddrphy_bitslip9_i; -reg [7:0] soc_k7ddrphy_bitslip9_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip9_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip9_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay10; -wire soc_k7ddrphy_dq_o_delayed10; -wire soc_k7ddrphy_dq_i_nodelay10; -wire soc_k7ddrphy_dq_i_delayed10; -wire soc_k7ddrphy_dq_t10; -wire [7:0] soc_k7ddrphy_dq_i_data10; -wire [7:0] soc_k7ddrphy_bitslip10_i; -reg [7:0] soc_k7ddrphy_bitslip10_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip10_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip10_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay11; -wire soc_k7ddrphy_dq_o_delayed11; -wire soc_k7ddrphy_dq_i_nodelay11; -wire soc_k7ddrphy_dq_i_delayed11; -wire soc_k7ddrphy_dq_t11; -wire [7:0] soc_k7ddrphy_dq_i_data11; -wire [7:0] soc_k7ddrphy_bitslip11_i; -reg [7:0] soc_k7ddrphy_bitslip11_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip11_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip11_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay12; -wire soc_k7ddrphy_dq_o_delayed12; -wire soc_k7ddrphy_dq_i_nodelay12; -wire soc_k7ddrphy_dq_i_delayed12; -wire soc_k7ddrphy_dq_t12; -wire [7:0] soc_k7ddrphy_dq_i_data12; -wire [7:0] soc_k7ddrphy_bitslip12_i; -reg [7:0] soc_k7ddrphy_bitslip12_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip12_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip12_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay13; -wire soc_k7ddrphy_dq_o_delayed13; -wire soc_k7ddrphy_dq_i_nodelay13; -wire soc_k7ddrphy_dq_i_delayed13; -wire soc_k7ddrphy_dq_t13; -wire [7:0] soc_k7ddrphy_dq_i_data13; -wire [7:0] soc_k7ddrphy_bitslip13_i; -reg [7:0] soc_k7ddrphy_bitslip13_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip13_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip13_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay14; -wire soc_k7ddrphy_dq_o_delayed14; -wire soc_k7ddrphy_dq_i_nodelay14; -wire soc_k7ddrphy_dq_i_delayed14; -wire soc_k7ddrphy_dq_t14; -wire [7:0] soc_k7ddrphy_dq_i_data14; -wire [7:0] soc_k7ddrphy_bitslip14_i; -reg [7:0] soc_k7ddrphy_bitslip14_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip14_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip14_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay15; -wire soc_k7ddrphy_dq_o_delayed15; -wire soc_k7ddrphy_dq_i_nodelay15; -wire soc_k7ddrphy_dq_i_delayed15; -wire soc_k7ddrphy_dq_t15; -wire [7:0] soc_k7ddrphy_dq_i_data15; -wire [7:0] soc_k7ddrphy_bitslip15_i; -reg [7:0] soc_k7ddrphy_bitslip15_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip15_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip15_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay16; -wire soc_k7ddrphy_dq_o_delayed16; -wire soc_k7ddrphy_dq_i_nodelay16; -wire soc_k7ddrphy_dq_i_delayed16; -wire soc_k7ddrphy_dq_t16; -wire [7:0] soc_k7ddrphy_dq_i_data16; -wire [7:0] soc_k7ddrphy_bitslip16_i; -reg [7:0] soc_k7ddrphy_bitslip16_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip16_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip16_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay17; -wire soc_k7ddrphy_dq_o_delayed17; -wire soc_k7ddrphy_dq_i_nodelay17; -wire soc_k7ddrphy_dq_i_delayed17; -wire soc_k7ddrphy_dq_t17; -wire [7:0] soc_k7ddrphy_dq_i_data17; -wire [7:0] soc_k7ddrphy_bitslip17_i; -reg [7:0] soc_k7ddrphy_bitslip17_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip17_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip17_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay18; -wire soc_k7ddrphy_dq_o_delayed18; -wire soc_k7ddrphy_dq_i_nodelay18; -wire soc_k7ddrphy_dq_i_delayed18; -wire soc_k7ddrphy_dq_t18; -wire [7:0] soc_k7ddrphy_dq_i_data18; -wire [7:0] soc_k7ddrphy_bitslip18_i; -reg [7:0] soc_k7ddrphy_bitslip18_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip18_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip18_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay19; -wire soc_k7ddrphy_dq_o_delayed19; -wire soc_k7ddrphy_dq_i_nodelay19; -wire soc_k7ddrphy_dq_i_delayed19; -wire soc_k7ddrphy_dq_t19; -wire [7:0] soc_k7ddrphy_dq_i_data19; -wire [7:0] soc_k7ddrphy_bitslip19_i; -reg [7:0] soc_k7ddrphy_bitslip19_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip19_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip19_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay20; -wire soc_k7ddrphy_dq_o_delayed20; -wire soc_k7ddrphy_dq_i_nodelay20; -wire soc_k7ddrphy_dq_i_delayed20; -wire soc_k7ddrphy_dq_t20; -wire [7:0] soc_k7ddrphy_dq_i_data20; -wire [7:0] soc_k7ddrphy_bitslip20_i; -reg [7:0] soc_k7ddrphy_bitslip20_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip20_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip20_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay21; -wire soc_k7ddrphy_dq_o_delayed21; -wire soc_k7ddrphy_dq_i_nodelay21; -wire soc_k7ddrphy_dq_i_delayed21; -wire soc_k7ddrphy_dq_t21; -wire [7:0] soc_k7ddrphy_dq_i_data21; -wire [7:0] soc_k7ddrphy_bitslip21_i; -reg [7:0] soc_k7ddrphy_bitslip21_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip21_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip21_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay22; -wire soc_k7ddrphy_dq_o_delayed22; -wire soc_k7ddrphy_dq_i_nodelay22; -wire soc_k7ddrphy_dq_i_delayed22; -wire soc_k7ddrphy_dq_t22; -wire [7:0] soc_k7ddrphy_dq_i_data22; -wire [7:0] soc_k7ddrphy_bitslip22_i; -reg [7:0] soc_k7ddrphy_bitslip22_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip22_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip22_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay23; -wire soc_k7ddrphy_dq_o_delayed23; -wire soc_k7ddrphy_dq_i_nodelay23; -wire soc_k7ddrphy_dq_i_delayed23; -wire soc_k7ddrphy_dq_t23; -wire [7:0] soc_k7ddrphy_dq_i_data23; -wire [7:0] soc_k7ddrphy_bitslip23_i; -reg [7:0] soc_k7ddrphy_bitslip23_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip23_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip23_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay24; -wire soc_k7ddrphy_dq_o_delayed24; -wire soc_k7ddrphy_dq_i_nodelay24; -wire soc_k7ddrphy_dq_i_delayed24; -wire soc_k7ddrphy_dq_t24; -wire [7:0] soc_k7ddrphy_dq_i_data24; -wire [7:0] soc_k7ddrphy_bitslip24_i; -reg [7:0] soc_k7ddrphy_bitslip24_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip24_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip24_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay25; -wire soc_k7ddrphy_dq_o_delayed25; -wire soc_k7ddrphy_dq_i_nodelay25; -wire soc_k7ddrphy_dq_i_delayed25; -wire soc_k7ddrphy_dq_t25; -wire [7:0] soc_k7ddrphy_dq_i_data25; -wire [7:0] soc_k7ddrphy_bitslip25_i; -reg [7:0] soc_k7ddrphy_bitslip25_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip25_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip25_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay26; -wire soc_k7ddrphy_dq_o_delayed26; -wire soc_k7ddrphy_dq_i_nodelay26; -wire soc_k7ddrphy_dq_i_delayed26; -wire soc_k7ddrphy_dq_t26; -wire [7:0] soc_k7ddrphy_dq_i_data26; -wire [7:0] soc_k7ddrphy_bitslip26_i; -reg [7:0] soc_k7ddrphy_bitslip26_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip26_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip26_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay27; -wire soc_k7ddrphy_dq_o_delayed27; -wire soc_k7ddrphy_dq_i_nodelay27; -wire soc_k7ddrphy_dq_i_delayed27; -wire soc_k7ddrphy_dq_t27; -wire [7:0] soc_k7ddrphy_dq_i_data27; -wire [7:0] soc_k7ddrphy_bitslip27_i; -reg [7:0] soc_k7ddrphy_bitslip27_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip27_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip27_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay28; -wire soc_k7ddrphy_dq_o_delayed28; -wire soc_k7ddrphy_dq_i_nodelay28; -wire soc_k7ddrphy_dq_i_delayed28; -wire soc_k7ddrphy_dq_t28; -wire [7:0] soc_k7ddrphy_dq_i_data28; -wire [7:0] soc_k7ddrphy_bitslip28_i; -reg [7:0] soc_k7ddrphy_bitslip28_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip28_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip28_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay29; -wire soc_k7ddrphy_dq_o_delayed29; -wire soc_k7ddrphy_dq_i_nodelay29; -wire soc_k7ddrphy_dq_i_delayed29; -wire soc_k7ddrphy_dq_t29; -wire [7:0] soc_k7ddrphy_dq_i_data29; -wire [7:0] soc_k7ddrphy_bitslip29_i; -reg [7:0] soc_k7ddrphy_bitslip29_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip29_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip29_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay30; -wire soc_k7ddrphy_dq_o_delayed30; -wire soc_k7ddrphy_dq_i_nodelay30; -wire soc_k7ddrphy_dq_i_delayed30; -wire soc_k7ddrphy_dq_t30; -wire [7:0] soc_k7ddrphy_dq_i_data30; -wire [7:0] soc_k7ddrphy_bitslip30_i; -reg [7:0] soc_k7ddrphy_bitslip30_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip30_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip30_r = 24'd0; -wire soc_k7ddrphy_dq_o_nodelay31; -wire soc_k7ddrphy_dq_o_delayed31; -wire soc_k7ddrphy_dq_i_nodelay31; -wire soc_k7ddrphy_dq_i_delayed31; -wire soc_k7ddrphy_dq_t31; -wire [7:0] soc_k7ddrphy_dq_i_data31; -wire [7:0] soc_k7ddrphy_bitslip31_i; -reg [7:0] soc_k7ddrphy_bitslip31_o = 8'd0; -reg [3:0] soc_k7ddrphy_bitslip31_value = 4'd0; -reg [23:0] soc_k7ddrphy_bitslip31_r = 24'd0; -wire [7:0] soc_k7ddrphy_rddata_en; -reg [7:0] soc_k7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_k7ddrphy_wrdata_en; -reg [3:0] soc_k7ddrphy_wrdata_en_last = 4'd0; -wire [14:0] soc_litedramcore_inti_p0_address; -wire [2:0] soc_litedramcore_inti_p0_bank; -reg soc_litedramcore_inti_p0_cas_n = 1'd1; -reg soc_litedramcore_inti_p0_cs_n = 1'd1; -reg soc_litedramcore_inti_p0_ras_n = 1'd1; -reg soc_litedramcore_inti_p0_we_n = 1'd1; -wire soc_litedramcore_inti_p0_cke; -wire soc_litedramcore_inti_p0_odt; -wire soc_litedramcore_inti_p0_reset_n; -reg soc_litedramcore_inti_p0_act_n = 1'd1; -wire [63:0] soc_litedramcore_inti_p0_wrdata; -wire soc_litedramcore_inti_p0_wrdata_en; -wire [7:0] soc_litedramcore_inti_p0_wrdata_mask; -wire soc_litedramcore_inti_p0_rddata_en; -reg [63:0] soc_litedramcore_inti_p0_rddata = 64'd0; -reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p1_address; -wire [2:0] soc_litedramcore_inti_p1_bank; -reg soc_litedramcore_inti_p1_cas_n = 1'd1; -reg soc_litedramcore_inti_p1_cs_n = 1'd1; -reg soc_litedramcore_inti_p1_ras_n = 1'd1; -reg soc_litedramcore_inti_p1_we_n = 1'd1; -wire soc_litedramcore_inti_p1_cke; -wire soc_litedramcore_inti_p1_odt; -wire soc_litedramcore_inti_p1_reset_n; -reg soc_litedramcore_inti_p1_act_n = 1'd1; -wire [63:0] soc_litedramcore_inti_p1_wrdata; -wire soc_litedramcore_inti_p1_wrdata_en; -wire [7:0] soc_litedramcore_inti_p1_wrdata_mask; -wire soc_litedramcore_inti_p1_rddata_en; -reg [63:0] soc_litedramcore_inti_p1_rddata = 64'd0; -reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p2_address; -wire [2:0] soc_litedramcore_inti_p2_bank; -reg soc_litedramcore_inti_p2_cas_n = 1'd1; -reg soc_litedramcore_inti_p2_cs_n = 1'd1; -reg soc_litedramcore_inti_p2_ras_n = 1'd1; -reg soc_litedramcore_inti_p2_we_n = 1'd1; -wire soc_litedramcore_inti_p2_cke; -wire soc_litedramcore_inti_p2_odt; -wire soc_litedramcore_inti_p2_reset_n; -reg soc_litedramcore_inti_p2_act_n = 1'd1; -wire [63:0] soc_litedramcore_inti_p2_wrdata; -wire soc_litedramcore_inti_p2_wrdata_en; -wire [7:0] soc_litedramcore_inti_p2_wrdata_mask; -wire soc_litedramcore_inti_p2_rddata_en; -reg [63:0] soc_litedramcore_inti_p2_rddata = 64'd0; -reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p3_address; -wire [2:0] soc_litedramcore_inti_p3_bank; -reg soc_litedramcore_inti_p3_cas_n = 1'd1; -reg soc_litedramcore_inti_p3_cs_n = 1'd1; -reg soc_litedramcore_inti_p3_ras_n = 1'd1; -reg soc_litedramcore_inti_p3_we_n = 1'd1; -wire soc_litedramcore_inti_p3_cke; -wire soc_litedramcore_inti_p3_odt; -wire soc_litedramcore_inti_p3_reset_n; -reg soc_litedramcore_inti_p3_act_n = 1'd1; -wire [63:0] soc_litedramcore_inti_p3_wrdata; -wire soc_litedramcore_inti_p3_wrdata_en; -wire [7:0] soc_litedramcore_inti_p3_wrdata_mask; -wire soc_litedramcore_inti_p3_rddata_en; -reg [63:0] soc_litedramcore_inti_p3_rddata = 64'd0; -reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [63:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [7:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [63:0] soc_litedramcore_slave_p0_rddata = 64'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [63:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [7:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [63:0] soc_litedramcore_slave_p1_rddata = 64'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [63:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [7:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [63:0] soc_litedramcore_slave_p2_rddata = 64'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [63:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [7:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [63:0] soc_litedramcore_slave_p3_rddata = 64'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] soc_litedramcore_master_p0_address = 15'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [63:0] soc_litedramcore_master_p0_wrdata = 64'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] soc_litedramcore_master_p0_wrdata_mask = 8'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [14:0] soc_litedramcore_master_p1_address = 15'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [63:0] soc_litedramcore_master_p1_wrdata = 64'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] soc_litedramcore_master_p1_wrdata_mask = 8'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [14:0] soc_litedramcore_master_p2_address = 15'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [63:0] soc_litedramcore_master_p2_wrdata = 64'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [7:0] soc_litedramcore_master_p2_wrdata_mask = 8'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [14:0] soc_litedramcore_master_p3_address = 15'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [63:0] soc_litedramcore_master_p3_wrdata = 64'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [7:0] soc_litedramcore_master_p3_wrdata_mask = 8'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_re; -wire soc_litedramcore_phaseinjector0_command_issue_r; -wire soc_litedramcore_phaseinjector0_command_issue_we; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector0_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector0_status = 64'd0; -wire soc_litedramcore_phaseinjector0_we; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_re; -wire soc_litedramcore_phaseinjector1_command_issue_r; -wire soc_litedramcore_phaseinjector1_command_issue_we; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector1_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector1_status = 64'd0; -wire soc_litedramcore_phaseinjector1_we; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_re; -wire soc_litedramcore_phaseinjector2_command_issue_r; -wire soc_litedramcore_phaseinjector2_command_issue_we; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector2_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector2_wrdata_storage = 64'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector2_status = 64'd0; -wire soc_litedramcore_phaseinjector2_we; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_re; -wire soc_litedramcore_phaseinjector3_command_issue_r; -wire soc_litedramcore_phaseinjector3_command_issue_we; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector3_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector3_wrdata_storage = 64'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [63:0] soc_litedramcore_phaseinjector3_status = 64'd0; -wire soc_litedramcore_phaseinjector3_we; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [21:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [21:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [21:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [21:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [21:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [21:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [21:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [21:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [255:0] soc_litedramcore_interface_wdata = 256'd0; -reg [31:0] soc_litedramcore_interface_wdata_we = 32'd0; -wire [255:0] soc_litedramcore_interface_rdata; -reg [14:0] soc_litedramcore_dfi_p0_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [63:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [7:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p1_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [63:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [7:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p2_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [63:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [7:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p3_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [63:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [7:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [63:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [14:0] soc_litedramcore_cmd_payload_a = 15'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [21:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine0_row = 15'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [21:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine1_row = 15'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [21:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine2_row = 15'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [21:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine3_row = 15'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [21:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine4_row = 15'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [21:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine5_row = 15'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [21:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine6_row = 15'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [21:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine7_row = 15'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; -wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] soc_litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; -wire soc_litedramcore_choose_cmd_cmd_payload_is_read; -wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] soc_litedramcore_choose_req_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_req_cmd_payload_is_cmd; -wire soc_litedramcore_choose_req_cmd_payload_is_read; -wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; -reg [14:0] soc_litedramcore_nop_a = 15'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; -wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; -wire [31:0] soc_wb_bus_dat_r; -wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; -wire soc_wb_bus_stb; -wire soc_wb_bus_ack; -wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [24:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [255:0] soc_user_port_wdata_payload_data; -wire [31:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [255:0] soc_user_port_rdata_payload_data; -reg vns_state = 1'd0; -reg vns_next_state = 1'd0; -wire vns_pll_fb; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire vns_roundrobin0_request; -wire vns_roundrobin0_grant; -wire vns_roundrobin0_ce; -wire vns_roundrobin1_request; -wire vns_roundrobin1_grant; -wire vns_roundrobin1_ce; -wire vns_roundrobin2_request; -wire vns_roundrobin2_grant; -wire vns_roundrobin2_ce; -wire vns_roundrobin3_request; -wire vns_roundrobin3_grant; -wire vns_roundrobin3_ce; -wire vns_roundrobin4_request; -wire vns_roundrobin4_grant; -wire vns_roundrobin4_ce; -wire vns_roundrobin5_request; -wire vns_roundrobin5_grant; -wire vns_roundrobin5_ce; -wire vns_roundrobin6_request; -wire vns_roundrobin6_grant; -wire vns_roundrobin6_ce; -wire vns_roundrobin7_request; -wire vns_roundrobin7_grant; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [31:0] vns_interface0_bank_bus_dat_w; -reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; -wire vns_csrbank0_init_done0_re; -wire vns_csrbank0_init_done0_r; -wire vns_csrbank0_init_done0_we; -wire vns_csrbank0_init_done0_w; -wire vns_csrbank0_init_error0_re; -wire vns_csrbank0_init_error0_r; -wire vns_csrbank0_init_error0_we; -wire vns_csrbank0_init_error0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [31:0] vns_interface1_bank_bus_dat_w; -reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; -wire vns_csrbank1_half_sys8x_taps0_re; -wire [4:0] vns_csrbank1_half_sys8x_taps0_r; -wire vns_csrbank1_half_sys8x_taps0_we; -wire [4:0] vns_csrbank1_half_sys8x_taps0_w; -wire vns_csrbank1_wlevel_en0_re; -wire vns_csrbank1_wlevel_en0_r; -wire vns_csrbank1_wlevel_en0_we; -wire vns_csrbank1_wlevel_en0_w; -wire vns_csrbank1_dly_sel0_re; -wire [3:0] vns_csrbank1_dly_sel0_r; -wire vns_csrbank1_dly_sel0_we; -wire [3:0] vns_csrbank1_dly_sel0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [31:0] vns_interface2_bank_bus_dat_w; -reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; -wire vns_csrbank2_dfii_control0_re; -wire [3:0] vns_csrbank2_dfii_control0_r; -wire vns_csrbank2_dfii_control0_we; -wire [3:0] vns_csrbank2_dfii_control0_w; -wire vns_csrbank2_dfii_pi0_command0_re; -wire [5:0] vns_csrbank2_dfii_pi0_command0_r; -wire vns_csrbank2_dfii_pi0_command0_we; -wire [5:0] vns_csrbank2_dfii_pi0_command0_w; -wire vns_csrbank2_dfii_pi0_address0_re; -wire [14:0] vns_csrbank2_dfii_pi0_address0_r; -wire vns_csrbank2_dfii_pi0_address0_we; -wire [14:0] vns_csrbank2_dfii_pi0_address0_w; -wire vns_csrbank2_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; -wire vns_csrbank2_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; -wire vns_csrbank2_dfii_pi0_wrdata1_re; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata1_r; -wire vns_csrbank2_dfii_pi0_wrdata1_we; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata1_w; -wire vns_csrbank2_dfii_pi0_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; -wire vns_csrbank2_dfii_pi0_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; -wire vns_csrbank2_dfii_pi0_rddata1_re; -wire [31:0] vns_csrbank2_dfii_pi0_rddata1_r; -wire vns_csrbank2_dfii_pi0_rddata1_we; -wire [31:0] vns_csrbank2_dfii_pi0_rddata1_w; -wire vns_csrbank2_dfii_pi0_rddata0_re; -wire [31:0] vns_csrbank2_dfii_pi0_rddata0_r; -wire vns_csrbank2_dfii_pi0_rddata0_we; -wire [31:0] vns_csrbank2_dfii_pi0_rddata0_w; -wire vns_csrbank2_dfii_pi1_command0_re; -wire [5:0] vns_csrbank2_dfii_pi1_command0_r; -wire vns_csrbank2_dfii_pi1_command0_we; -wire [5:0] vns_csrbank2_dfii_pi1_command0_w; -wire vns_csrbank2_dfii_pi1_address0_re; -wire [14:0] vns_csrbank2_dfii_pi1_address0_r; -wire vns_csrbank2_dfii_pi1_address0_we; -wire [14:0] vns_csrbank2_dfii_pi1_address0_w; -wire vns_csrbank2_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; -wire vns_csrbank2_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; -wire vns_csrbank2_dfii_pi1_wrdata1_re; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata1_r; -wire vns_csrbank2_dfii_pi1_wrdata1_we; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata1_w; -wire vns_csrbank2_dfii_pi1_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; -wire vns_csrbank2_dfii_pi1_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; -wire vns_csrbank2_dfii_pi1_rddata1_re; -wire [31:0] vns_csrbank2_dfii_pi1_rddata1_r; -wire vns_csrbank2_dfii_pi1_rddata1_we; -wire [31:0] vns_csrbank2_dfii_pi1_rddata1_w; -wire vns_csrbank2_dfii_pi1_rddata0_re; -wire [31:0] vns_csrbank2_dfii_pi1_rddata0_r; -wire vns_csrbank2_dfii_pi1_rddata0_we; -wire [31:0] vns_csrbank2_dfii_pi1_rddata0_w; -wire vns_csrbank2_dfii_pi2_command0_re; -wire [5:0] vns_csrbank2_dfii_pi2_command0_r; -wire vns_csrbank2_dfii_pi2_command0_we; -wire [5:0] vns_csrbank2_dfii_pi2_command0_w; -wire vns_csrbank2_dfii_pi2_address0_re; -wire [14:0] vns_csrbank2_dfii_pi2_address0_r; -wire vns_csrbank2_dfii_pi2_address0_we; -wire [14:0] vns_csrbank2_dfii_pi2_address0_w; -wire vns_csrbank2_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; -wire vns_csrbank2_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; -wire vns_csrbank2_dfii_pi2_wrdata1_re; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata1_r; -wire vns_csrbank2_dfii_pi2_wrdata1_we; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata1_w; -wire vns_csrbank2_dfii_pi2_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; -wire vns_csrbank2_dfii_pi2_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; -wire vns_csrbank2_dfii_pi2_rddata1_re; -wire [31:0] vns_csrbank2_dfii_pi2_rddata1_r; -wire vns_csrbank2_dfii_pi2_rddata1_we; -wire [31:0] vns_csrbank2_dfii_pi2_rddata1_w; -wire vns_csrbank2_dfii_pi2_rddata0_re; -wire [31:0] vns_csrbank2_dfii_pi2_rddata0_r; -wire vns_csrbank2_dfii_pi2_rddata0_we; -wire [31:0] vns_csrbank2_dfii_pi2_rddata0_w; -wire vns_csrbank2_dfii_pi3_command0_re; -wire [5:0] vns_csrbank2_dfii_pi3_command0_r; -wire vns_csrbank2_dfii_pi3_command0_we; -wire [5:0] vns_csrbank2_dfii_pi3_command0_w; -wire vns_csrbank2_dfii_pi3_address0_re; -wire [14:0] vns_csrbank2_dfii_pi3_address0_r; -wire vns_csrbank2_dfii_pi3_address0_we; -wire [14:0] vns_csrbank2_dfii_pi3_address0_w; -wire vns_csrbank2_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; -wire vns_csrbank2_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; -wire vns_csrbank2_dfii_pi3_wrdata1_re; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata1_r; -wire vns_csrbank2_dfii_pi3_wrdata1_we; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata1_w; -wire vns_csrbank2_dfii_pi3_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; -wire vns_csrbank2_dfii_pi3_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; -wire vns_csrbank2_dfii_pi3_rddata1_re; -wire [31:0] vns_csrbank2_dfii_pi3_rddata1_r; -wire vns_csrbank2_dfii_pi3_rddata1_we; -wire [31:0] vns_csrbank2_dfii_pi3_rddata1_w; -wire vns_csrbank2_dfii_pi3_rddata0_re; -wire [31:0] vns_csrbank2_dfii_pi3_rddata0_r; -wire vns_csrbank2_dfii_pi3_rddata0_we; -wire [31:0] vns_csrbank2_dfii_pi3_rddata0_w; -wire vns_csrbank2_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [31:0] vns_dat_w; -wire [31:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [14:0] vns_rhs_array_muxed1 = 15'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [14:0] vns_rhs_array_muxed7 = 15'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [21:0] vns_rhs_array_muxed12 = 22'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [21:0] vns_rhs_array_muxed15 = 22'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [21:0] vns_rhs_array_muxed18 = 22'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [21:0] vns_rhs_array_muxed21 = 22'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [21:0] vns_rhs_array_muxed24 = 22'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [21:0] vns_rhs_array_muxed27 = 22'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [21:0] vns_rhs_array_muxed30 = 22'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [21:0] vns_rhs_array_muxed33 = 22'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [14:0] vns_array_muxed1 = 15'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [14:0] vns_array_muxed8 = 15'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [14:0] vns_array_muxed15 = 15'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [14:0] vns_array_muxed22 = 15'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl3_expr; +wire main_reset; +reg main_power_down = 1'd0; +wire main_locked; +wire main_clkin; +wire main_clkout0; +wire main_clkout_buf0; +wire main_clkout1; +wire main_clkout_buf1; +wire main_clkout2; +wire main_clkout_buf2; +wire main_clkout3; +wire main_clkout_buf3; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_k7ddrphy_rst_storage = 1'd0; +reg main_k7ddrphy_rst_re = 1'd0; +reg [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_k7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_k7ddrphy_wlevel_en_storage = 1'd0; +reg main_k7ddrphy_wlevel_en_re = 1'd0; +reg main_k7ddrphy_wlevel_strobe_re = 1'd0; +wire main_k7ddrphy_wlevel_strobe_r; +reg main_k7ddrphy_wlevel_strobe_we = 1'd0; +reg main_k7ddrphy_wlevel_strobe_w = 1'd0; +reg main_k7ddrphy_cdly_rst_re = 1'd0; +wire main_k7ddrphy_cdly_rst_r; +reg main_k7ddrphy_cdly_rst_we = 1'd0; +reg main_k7ddrphy_cdly_rst_w = 1'd0; +reg main_k7ddrphy_cdly_inc_re = 1'd0; +wire main_k7ddrphy_cdly_inc_r; +reg main_k7ddrphy_cdly_inc_we = 1'd0; +reg main_k7ddrphy_cdly_inc_w = 1'd0; +reg [3:0] main_k7ddrphy_dly_sel_storage = 4'd0; +reg main_k7ddrphy_dly_sel_re = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_re = 1'd0; +wire main_k7ddrphy_rdly_dq_rst_r; +reg main_k7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_re = 1'd0; +wire main_k7ddrphy_rdly_dq_inc_r; +reg main_k7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire main_k7ddrphy_rdly_dq_bitslip_rst_r; +reg main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_k7ddrphy_rdly_dq_bitslip_r; +reg main_k7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_re = 1'd0; +wire main_k7ddrphy_wdly_dq_rst_r; +reg main_k7ddrphy_wdly_dq_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_re = 1'd0; +wire main_k7ddrphy_wdly_dq_inc_r; +reg main_k7ddrphy_wdly_dq_inc_we = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_re = 1'd0; +wire main_k7ddrphy_wdly_dqs_rst_r; +reg main_k7ddrphy_wdly_dqs_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_re = 1'd0; +wire main_k7ddrphy_wdly_dqs_inc_r; +reg main_k7ddrphy_wdly_dqs_inc_we = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire main_k7ddrphy_wdly_dq_bitslip_rst_r; +reg main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_k7ddrphy_wdly_dq_bitslip_r; +reg main_k7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_k7ddrphy_rdphase_storage = 2'd1; +reg main_k7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_k7ddrphy_wrphase_storage = 2'd2; +reg main_k7ddrphy_wrphase_re = 1'd0; +wire [14:0] main_k7ddrphy_dfi_p0_address; +wire [2:0] main_k7ddrphy_dfi_p0_bank; +wire main_k7ddrphy_dfi_p0_cas_n; +wire main_k7ddrphy_dfi_p0_cs_n; +wire main_k7ddrphy_dfi_p0_ras_n; +wire main_k7ddrphy_dfi_p0_we_n; +wire main_k7ddrphy_dfi_p0_cke; +wire main_k7ddrphy_dfi_p0_odt; +wire main_k7ddrphy_dfi_p0_reset_n; +wire main_k7ddrphy_dfi_p0_act_n; +wire [63:0] main_k7ddrphy_dfi_p0_wrdata; +wire main_k7ddrphy_dfi_p0_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p0_wrdata_mask; +wire main_k7ddrphy_dfi_p0_rddata_en; +reg [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0; +wire main_k7ddrphy_dfi_p0_rddata_valid; +wire [14:0] main_k7ddrphy_dfi_p1_address; +wire [2:0] main_k7ddrphy_dfi_p1_bank; +wire main_k7ddrphy_dfi_p1_cas_n; +wire main_k7ddrphy_dfi_p1_cs_n; +wire main_k7ddrphy_dfi_p1_ras_n; +wire main_k7ddrphy_dfi_p1_we_n; +wire main_k7ddrphy_dfi_p1_cke; +wire main_k7ddrphy_dfi_p1_odt; +wire main_k7ddrphy_dfi_p1_reset_n; +wire main_k7ddrphy_dfi_p1_act_n; +wire [63:0] main_k7ddrphy_dfi_p1_wrdata; +wire main_k7ddrphy_dfi_p1_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p1_wrdata_mask; +wire main_k7ddrphy_dfi_p1_rddata_en; +reg [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0; +wire main_k7ddrphy_dfi_p1_rddata_valid; +wire [14:0] main_k7ddrphy_dfi_p2_address; +wire [2:0] main_k7ddrphy_dfi_p2_bank; +wire main_k7ddrphy_dfi_p2_cas_n; +wire main_k7ddrphy_dfi_p2_cs_n; +wire main_k7ddrphy_dfi_p2_ras_n; +wire main_k7ddrphy_dfi_p2_we_n; +wire main_k7ddrphy_dfi_p2_cke; +wire main_k7ddrphy_dfi_p2_odt; +wire main_k7ddrphy_dfi_p2_reset_n; +wire main_k7ddrphy_dfi_p2_act_n; +wire [63:0] main_k7ddrphy_dfi_p2_wrdata; +wire main_k7ddrphy_dfi_p2_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p2_wrdata_mask; +wire main_k7ddrphy_dfi_p2_rddata_en; +reg [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0; +wire main_k7ddrphy_dfi_p2_rddata_valid; +wire [14:0] main_k7ddrphy_dfi_p3_address; +wire [2:0] main_k7ddrphy_dfi_p3_bank; +wire main_k7ddrphy_dfi_p3_cas_n; +wire main_k7ddrphy_dfi_p3_cs_n; +wire main_k7ddrphy_dfi_p3_ras_n; +wire main_k7ddrphy_dfi_p3_we_n; +wire main_k7ddrphy_dfi_p3_cke; +wire main_k7ddrphy_dfi_p3_odt; +wire main_k7ddrphy_dfi_p3_reset_n; +wire main_k7ddrphy_dfi_p3_act_n; +wire [63:0] main_k7ddrphy_dfi_p3_wrdata; +wire main_k7ddrphy_dfi_p3_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p3_wrdata_mask; +wire main_k7ddrphy_dfi_p3_rddata_en; +reg [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0; +wire main_k7ddrphy_dfi_p3_rddata_valid; +wire main_k7ddrphy_sd_clk_se_nodelay; +wire main_k7ddrphy_sd_clk_se_delayed; +wire main_k7ddrphy_oq0; +wire main_k7ddrphy_oq1; +wire main_k7ddrphy_oq2; +wire main_k7ddrphy_oq3; +wire main_k7ddrphy_oq4; +wire main_k7ddrphy_oq5; +wire main_k7ddrphy_oq6; +wire main_k7ddrphy_oq7; +wire main_k7ddrphy_oq8; +wire main_k7ddrphy_oq9; +wire main_k7ddrphy_oq10; +wire main_k7ddrphy_oq11; +wire main_k7ddrphy_oq12; +wire main_k7ddrphy_oq13; +wire main_k7ddrphy_oq14; +wire main_k7ddrphy_oq15; +wire main_k7ddrphy_oq16; +wire main_k7ddrphy_oq17; +wire main_k7ddrphy_oq18; +wire main_k7ddrphy_oq19; +wire main_k7ddrphy_oq20; +wire main_k7ddrphy_oq21; +wire main_k7ddrphy_oq22; +wire main_k7ddrphy_oq23; +wire main_k7ddrphy_oq24; +reg main_k7ddrphy_dqs_oe = 1'd0; +wire main_k7ddrphy_dqs_preamble; +wire main_k7ddrphy_dqs_postamble; +wire main_k7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_dqspattern0 = 1'd0; +reg main_k7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_k7ddrphy_dqspattern_o = 8'd0; +wire main_k7ddrphy_dqs_o_no_delay0; +wire main_k7ddrphy_dqs_o_delayed0; +wire main_k7ddrphy_dqs_t0; +reg [7:0] main_k7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0; +wire main_k7ddrphy0; +wire main_k7ddrphy_dqs_o_no_delay1; +wire main_k7ddrphy_dqs_o_delayed1; +wire main_k7ddrphy_dqs_t1; +reg [7:0] main_k7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0; +wire main_k7ddrphy1; +wire main_k7ddrphy_dqs_o_no_delay2; +wire main_k7ddrphy_dqs_o_delayed2; +wire main_k7ddrphy_dqs_t2; +reg [7:0] main_k7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0; +wire main_k7ddrphy2; +wire main_k7ddrphy_dqs_o_no_delay3; +wire main_k7ddrphy_dqs_o_delayed3; +wire main_k7ddrphy_dqs_t3; +reg [7:0] main_k7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0; +wire main_k7ddrphy3; +wire main_k7ddrphy_dm_o_nodelay0; +reg [7:0] main_k7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0; +wire main_k7ddrphy_dm_o_nodelay1; +reg [7:0] main_k7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0; +wire main_k7ddrphy_dm_o_nodelay2; +reg [7:0] main_k7ddrphy_bitslip21 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0; +wire main_k7ddrphy_dm_o_nodelay3; +reg [7:0] main_k7ddrphy_bitslip31 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0; +wire main_k7ddrphy_dq_oe; +wire main_k7ddrphy_dq_oe_delay_tappeddelayline; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_k7ddrphy_dq_o_nodelay0; +wire main_k7ddrphy_dq_o_delayed0; +wire main_k7ddrphy_dq_i_nodelay0; +wire main_k7ddrphy_dq_i_delayed0; +wire main_k7ddrphy_dq_t0; +reg [7:0] main_k7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip03; +reg [7:0] main_k7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay1; +wire main_k7ddrphy_dq_o_delayed1; +wire main_k7ddrphy_dq_i_nodelay1; +wire main_k7ddrphy_dq_i_delayed1; +wire main_k7ddrphy_dq_t1; +reg [7:0] main_k7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip13; +reg [7:0] main_k7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay2; +wire main_k7ddrphy_dq_o_delayed2; +wire main_k7ddrphy_dq_i_nodelay2; +wire main_k7ddrphy_dq_i_delayed2; +wire main_k7ddrphy_dq_t2; +reg [7:0] main_k7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip23; +reg [7:0] main_k7ddrphy_bitslip24 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay3; +wire main_k7ddrphy_dq_o_delayed3; +wire main_k7ddrphy_dq_i_nodelay3; +wire main_k7ddrphy_dq_i_delayed3; +wire main_k7ddrphy_dq_t3; +reg [7:0] main_k7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip33; +reg [7:0] main_k7ddrphy_bitslip34 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay4; +wire main_k7ddrphy_dq_o_delayed4; +wire main_k7ddrphy_dq_i_nodelay4; +wire main_k7ddrphy_dq_i_delayed4; +wire main_k7ddrphy_dq_t4; +reg [7:0] main_k7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip41; +reg [7:0] main_k7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay5; +wire main_k7ddrphy_dq_o_delayed5; +wire main_k7ddrphy_dq_i_nodelay5; +wire main_k7ddrphy_dq_i_delayed5; +wire main_k7ddrphy_dq_t5; +reg [7:0] main_k7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip51; +reg [7:0] main_k7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay6; +wire main_k7ddrphy_dq_o_delayed6; +wire main_k7ddrphy_dq_i_nodelay6; +wire main_k7ddrphy_dq_i_delayed6; +wire main_k7ddrphy_dq_t6; +reg [7:0] main_k7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip61; +reg [7:0] main_k7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay7; +wire main_k7ddrphy_dq_o_delayed7; +wire main_k7ddrphy_dq_i_nodelay7; +wire main_k7ddrphy_dq_i_delayed7; +wire main_k7ddrphy_dq_t7; +reg [7:0] main_k7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip71; +reg [7:0] main_k7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay8; +wire main_k7ddrphy_dq_o_delayed8; +wire main_k7ddrphy_dq_i_nodelay8; +wire main_k7ddrphy_dq_i_delayed8; +wire main_k7ddrphy_dq_t8; +reg [7:0] main_k7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip81; +reg [7:0] main_k7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay9; +wire main_k7ddrphy_dq_o_delayed9; +wire main_k7ddrphy_dq_i_nodelay9; +wire main_k7ddrphy_dq_i_delayed9; +wire main_k7ddrphy_dq_t9; +reg [7:0] main_k7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip91; +reg [7:0] main_k7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay10; +wire main_k7ddrphy_dq_o_delayed10; +wire main_k7ddrphy_dq_i_nodelay10; +wire main_k7ddrphy_dq_i_delayed10; +wire main_k7ddrphy_dq_t10; +reg [7:0] main_k7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip101; +reg [7:0] main_k7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay11; +wire main_k7ddrphy_dq_o_delayed11; +wire main_k7ddrphy_dq_i_nodelay11; +wire main_k7ddrphy_dq_i_delayed11; +wire main_k7ddrphy_dq_t11; +reg [7:0] main_k7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip111; +reg [7:0] main_k7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay12; +wire main_k7ddrphy_dq_o_delayed12; +wire main_k7ddrphy_dq_i_nodelay12; +wire main_k7ddrphy_dq_i_delayed12; +wire main_k7ddrphy_dq_t12; +reg [7:0] main_k7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip121; +reg [7:0] main_k7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay13; +wire main_k7ddrphy_dq_o_delayed13; +wire main_k7ddrphy_dq_i_nodelay13; +wire main_k7ddrphy_dq_i_delayed13; +wire main_k7ddrphy_dq_t13; +reg [7:0] main_k7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip131; +reg [7:0] main_k7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay14; +wire main_k7ddrphy_dq_o_delayed14; +wire main_k7ddrphy_dq_i_nodelay14; +wire main_k7ddrphy_dq_i_delayed14; +wire main_k7ddrphy_dq_t14; +reg [7:0] main_k7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip141; +reg [7:0] main_k7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay15; +wire main_k7ddrphy_dq_o_delayed15; +wire main_k7ddrphy_dq_i_nodelay15; +wire main_k7ddrphy_dq_i_delayed15; +wire main_k7ddrphy_dq_t15; +reg [7:0] main_k7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip151; +reg [7:0] main_k7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay16; +wire main_k7ddrphy_dq_o_delayed16; +wire main_k7ddrphy_dq_i_nodelay16; +wire main_k7ddrphy_dq_i_delayed16; +wire main_k7ddrphy_dq_t16; +reg [7:0] main_k7ddrphy_bitslip160 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip161; +reg [7:0] main_k7ddrphy_bitslip162 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay17; +wire main_k7ddrphy_dq_o_delayed17; +wire main_k7ddrphy_dq_i_nodelay17; +wire main_k7ddrphy_dq_i_delayed17; +wire main_k7ddrphy_dq_t17; +reg [7:0] main_k7ddrphy_bitslip170 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip171; +reg [7:0] main_k7ddrphy_bitslip172 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay18; +wire main_k7ddrphy_dq_o_delayed18; +wire main_k7ddrphy_dq_i_nodelay18; +wire main_k7ddrphy_dq_i_delayed18; +wire main_k7ddrphy_dq_t18; +reg [7:0] main_k7ddrphy_bitslip180 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip181; +reg [7:0] main_k7ddrphy_bitslip182 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay19; +wire main_k7ddrphy_dq_o_delayed19; +wire main_k7ddrphy_dq_i_nodelay19; +wire main_k7ddrphy_dq_i_delayed19; +wire main_k7ddrphy_dq_t19; +reg [7:0] main_k7ddrphy_bitslip190 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip191; +reg [7:0] main_k7ddrphy_bitslip192 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay20; +wire main_k7ddrphy_dq_o_delayed20; +wire main_k7ddrphy_dq_i_nodelay20; +wire main_k7ddrphy_dq_i_delayed20; +wire main_k7ddrphy_dq_t20; +reg [7:0] main_k7ddrphy_bitslip200 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip201; +reg [7:0] main_k7ddrphy_bitslip202 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay21; +wire main_k7ddrphy_dq_o_delayed21; +wire main_k7ddrphy_dq_i_nodelay21; +wire main_k7ddrphy_dq_i_delayed21; +wire main_k7ddrphy_dq_t21; +reg [7:0] main_k7ddrphy_bitslip210 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip211; +reg [7:0] main_k7ddrphy_bitslip212 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay22; +wire main_k7ddrphy_dq_o_delayed22; +wire main_k7ddrphy_dq_i_nodelay22; +wire main_k7ddrphy_dq_i_delayed22; +wire main_k7ddrphy_dq_t22; +reg [7:0] main_k7ddrphy_bitslip220 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip221; +reg [7:0] main_k7ddrphy_bitslip222 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay23; +wire main_k7ddrphy_dq_o_delayed23; +wire main_k7ddrphy_dq_i_nodelay23; +wire main_k7ddrphy_dq_i_delayed23; +wire main_k7ddrphy_dq_t23; +reg [7:0] main_k7ddrphy_bitslip230 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip231; +reg [7:0] main_k7ddrphy_bitslip232 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay24; +wire main_k7ddrphy_dq_o_delayed24; +wire main_k7ddrphy_dq_i_nodelay24; +wire main_k7ddrphy_dq_i_delayed24; +wire main_k7ddrphy_dq_t24; +reg [7:0] main_k7ddrphy_bitslip240 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip241; +reg [7:0] main_k7ddrphy_bitslip242 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay25; +wire main_k7ddrphy_dq_o_delayed25; +wire main_k7ddrphy_dq_i_nodelay25; +wire main_k7ddrphy_dq_i_delayed25; +wire main_k7ddrphy_dq_t25; +reg [7:0] main_k7ddrphy_bitslip250 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip251; +reg [7:0] main_k7ddrphy_bitslip252 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay26; +wire main_k7ddrphy_dq_o_delayed26; +wire main_k7ddrphy_dq_i_nodelay26; +wire main_k7ddrphy_dq_i_delayed26; +wire main_k7ddrphy_dq_t26; +reg [7:0] main_k7ddrphy_bitslip260 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip261; +reg [7:0] main_k7ddrphy_bitslip262 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay27; +wire main_k7ddrphy_dq_o_delayed27; +wire main_k7ddrphy_dq_i_nodelay27; +wire main_k7ddrphy_dq_i_delayed27; +wire main_k7ddrphy_dq_t27; +reg [7:0] main_k7ddrphy_bitslip270 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip271; +reg [7:0] main_k7ddrphy_bitslip272 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay28; +wire main_k7ddrphy_dq_o_delayed28; +wire main_k7ddrphy_dq_i_nodelay28; +wire main_k7ddrphy_dq_i_delayed28; +wire main_k7ddrphy_dq_t28; +reg [7:0] main_k7ddrphy_bitslip280 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip281; +reg [7:0] main_k7ddrphy_bitslip282 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay29; +wire main_k7ddrphy_dq_o_delayed29; +wire main_k7ddrphy_dq_i_nodelay29; +wire main_k7ddrphy_dq_i_delayed29; +wire main_k7ddrphy_dq_t29; +reg [7:0] main_k7ddrphy_bitslip290 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip291; +reg [7:0] main_k7ddrphy_bitslip292 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay30; +wire main_k7ddrphy_dq_o_delayed30; +wire main_k7ddrphy_dq_i_nodelay30; +wire main_k7ddrphy_dq_i_delayed30; +wire main_k7ddrphy_dq_t30; +reg [7:0] main_k7ddrphy_bitslip300 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip301; +reg [7:0] main_k7ddrphy_bitslip302 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0; +wire main_k7ddrphy_dq_o_nodelay31; +wire main_k7ddrphy_dq_o_delayed31; +wire main_k7ddrphy_dq_i_nodelay31; +wire main_k7ddrphy_dq_i_delayed31; +wire main_k7ddrphy_dq_t31; +reg [7:0] main_k7ddrphy_bitslip310 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0; +wire [7:0] main_k7ddrphy_bitslip311; +reg [7:0] main_k7ddrphy_bitslip312 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [14:0] main_litedramcore_inti_p0_address; +wire [2:0] main_litedramcore_inti_p0_bank; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; +wire main_litedramcore_inti_p0_cke; +wire main_litedramcore_inti_p0_odt; +wire main_litedramcore_inti_p0_reset_n; +reg main_litedramcore_inti_p0_act_n = 1'd1; +wire [63:0] main_litedramcore_inti_p0_wrdata; +wire main_litedramcore_inti_p0_wrdata_en; +wire [7:0] main_litedramcore_inti_p0_wrdata_mask; +wire main_litedramcore_inti_p0_rddata_en; +reg [63:0] main_litedramcore_inti_p0_rddata = 64'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p1_address; +wire [2:0] main_litedramcore_inti_p1_bank; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; +wire main_litedramcore_inti_p1_cke; +wire main_litedramcore_inti_p1_odt; +wire main_litedramcore_inti_p1_reset_n; +reg main_litedramcore_inti_p1_act_n = 1'd1; +wire [63:0] main_litedramcore_inti_p1_wrdata; +wire main_litedramcore_inti_p1_wrdata_en; +wire [7:0] main_litedramcore_inti_p1_wrdata_mask; +wire main_litedramcore_inti_p1_rddata_en; +reg [63:0] main_litedramcore_inti_p1_rddata = 64'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p2_address; +wire [2:0] main_litedramcore_inti_p2_bank; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; +wire main_litedramcore_inti_p2_cke; +wire main_litedramcore_inti_p2_odt; +wire main_litedramcore_inti_p2_reset_n; +reg main_litedramcore_inti_p2_act_n = 1'd1; +wire [63:0] main_litedramcore_inti_p2_wrdata; +wire main_litedramcore_inti_p2_wrdata_en; +wire [7:0] main_litedramcore_inti_p2_wrdata_mask; +wire main_litedramcore_inti_p2_rddata_en; +reg [63:0] main_litedramcore_inti_p2_rddata = 64'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p3_address; +wire [2:0] main_litedramcore_inti_p3_bank; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; +wire main_litedramcore_inti_p3_cke; +wire main_litedramcore_inti_p3_odt; +wire main_litedramcore_inti_p3_reset_n; +reg main_litedramcore_inti_p3_act_n = 1'd1; +wire [63:0] main_litedramcore_inti_p3_wrdata; +wire main_litedramcore_inti_p3_wrdata_en; +wire [7:0] main_litedramcore_inti_p3_wrdata_mask; +wire main_litedramcore_inti_p3_rddata_en; +reg [63:0] main_litedramcore_inti_p3_rddata = 64'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_ras_n; +wire main_litedramcore_slave_p0_we_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_act_n; +wire [63:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [7:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p0_rddata_en; +reg [63:0] main_litedramcore_slave_p0_rddata = 64'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_ras_n; +wire main_litedramcore_slave_p1_we_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_act_n; +wire [63:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [7:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p1_rddata_en; +reg [63:0] main_litedramcore_slave_p1_rddata = 64'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_ras_n; +wire main_litedramcore_slave_p2_we_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_act_n; +wire [63:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [7:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p2_rddata_en; +reg [63:0] main_litedramcore_slave_p2_rddata = 64'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_ras_n; +wire main_litedramcore_slave_p3_we_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_act_n; +wire [63:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [7:0] main_litedramcore_slave_p3_wrdata_mask; +wire main_litedramcore_slave_p3_rddata_en; +reg [63:0] main_litedramcore_slave_p3_rddata = 64'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p0_wrdata = 64'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire [63:0] main_litedramcore_master_p0_rddata; +wire main_litedramcore_master_p0_rddata_valid; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p1_wrdata = 64'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire [63:0] main_litedramcore_master_p1_rddata; +wire main_litedramcore_master_p1_rddata_valid; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p2_wrdata = 64'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire [63:0] main_litedramcore_master_p2_rddata; +wire main_litedramcore_master_p2_rddata_valid; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p3_wrdata = 64'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire [63:0] main_litedramcore_master_p3_rddata; +wire main_litedramcore_master_p3_rddata_valid; +wire main_litedramcore_sel; +wire main_litedramcore_cke; +wire main_litedramcore_odt; +wire main_litedramcore_reset_n; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_we; +wire [21:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_we; +wire [21:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_we; +wire [21:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_we; +wire [21:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_we; +wire [21:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_we; +wire [21:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_we; +wire [21:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_we; +wire [21:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_rdata_valid; +reg [255:0] main_litedramcore_interface_wdata = 256'd0; +reg [31:0] main_litedramcore_interface_wdata_we = 32'd0; +wire [255:0] main_litedramcore_interface_rdata; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +wire main_litedramcore_dfi_p0_odt; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [63:0] main_litedramcore_dfi_p0_rddata; +wire main_litedramcore_dfi_p0_rddata_valid; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +wire main_litedramcore_dfi_p1_odt; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [63:0] main_litedramcore_dfi_p1_rddata; +wire main_litedramcore_dfi_p1_rddata_valid; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +wire main_litedramcore_dfi_p2_odt; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [63:0] main_litedramcore_dfi_p2_rddata; +wire main_litedramcore_dfi_p2_rddata_valid; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +wire main_litedramcore_dfi_p3_odt; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [63:0] main_litedramcore_dfi_p3_rddata; +wire main_litedramcore_dfi_p3_rddata_valid; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_timer_wait; +wire main_litedramcore_timer_done0; +wire [9:0] main_litedramcore_timer_count0; +wire main_litedramcore_timer_done1; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_done0; +wire main_litedramcore_sequencer_start1; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_zqcs_timer_wait; +wire main_litedramcore_zqcs_timer_done0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +wire main_litedramcore_zqcs_timer_done1; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +wire main_litedramcore_bankmachine0_req_valid; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_we; +wire [21:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +wire main_litedramcore_bankmachine1_req_valid; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_we; +wire [21:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +wire main_litedramcore_bankmachine2_req_valid; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_we; +wire [21:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +wire main_litedramcore_bankmachine3_req_valid; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_we; +wire [21:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +wire main_litedramcore_bankmachine4_req_valid; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_we; +wire [21:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +wire main_litedramcore_bankmachine5_req_valid; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_we; +wire [21:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +wire main_litedramcore_bankmachine6_req_valid; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_we; +wire [21:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +wire main_litedramcore_bankmachine7_req_valid; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_we; +wire [21:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +wire main_litedramcore_ras_allowed; +wire main_litedramcore_cas_allowed; +wire [1:0] main_litedramcore_rdcmdphase; +wire [1:0] main_litedramcore_wrcmdphase; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire main_litedramcore_choose_cmd_ce; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire main_litedramcore_choose_req_ce; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +wire main_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; +wire main_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] main_litedramcore_tfawcon_count; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +wire main_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; +wire main_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_write_available; +reg main_litedramcore_en0 = 1'd0; +wire main_litedramcore_max_time0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; +wire main_litedramcore_max_time1; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire main_litedramcore_go_to_refresh; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; +wire [29:0] main_wb_bus_adr; +wire [31:0] main_wb_bus_dat_w; +wire [31:0] main_wb_bus_dat_r; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_cyc; +wire main_wb_bus_stb; +wire main_wb_bus_ack; +wire main_wb_bus_we; +wire [2:0] main_wb_bus_cti; +wire [1:0] main_wb_bus_bte; +wire main_wb_bus_err; +wire main_user_port_cmd_valid; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_payload_we; +wire [24:0] main_user_port_cmd_payload_addr; +wire main_user_port_wdata_valid; +wire main_user_port_wdata_ready; +wire [255:0] main_user_port_wdata_payload_data; +wire [31:0] main_user_port_wdata_payload_we; +wire main_user_port_rdata_valid; +wire main_user_port_rdata_ready; +wire [255:0] main_user_port_rdata_payload_data; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +wire builder_pll_fb; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +wire builder_roundrobin0_request; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_ce; +wire builder_roundrobin1_request; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_ce; +wire builder_roundrobin2_request; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_ce; +wire builder_roundrobin3_request; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_ce; +wire builder_roundrobin4_request; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_ce; +wire builder_roundrobin5_request; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_ce; +wire builder_roundrobin6_request; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_ce; +wire builder_roundrobin7_request; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_ce; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [7:0] builder_litedramcore_dat_w = 8'd0; +wire [7:0] builder_litedramcore_dat_r; +wire [29:0] builder_litedramcore_wishbone_adr; +wire [31:0] builder_litedramcore_wishbone_dat_w; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] builder_litedramcore_wishbone_sel; +wire builder_litedramcore_wishbone_cyc; +wire builder_litedramcore_wishbone_stb; +reg builder_litedramcore_wishbone_ack = 1'd0; +wire builder_litedramcore_wishbone_we; +wire [2:0] builder_litedramcore_wishbone_cti; +wire [1:0] builder_litedramcore_wishbone_bte; +reg builder_litedramcore_wishbone_err = 1'd0; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [7:0] builder_interface0_bank_bus_dat_w; +reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_init_error0_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [7:0] builder_interface1_bank_bus_dat_w; +reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [3:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [3:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [7:0] builder_interface2_bank_bus_dat_w; +reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi0_address1_r; +reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi0_address1_w; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_wrdata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_r; +reg builder_csrbank2_dfii_pi0_wrdata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_w; +reg builder_csrbank2_dfii_pi0_wrdata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_r; +reg builder_csrbank2_dfii_pi0_wrdata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_w; +reg builder_csrbank2_dfii_pi0_wrdata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_r; +reg builder_csrbank2_dfii_pi0_wrdata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_w; +reg builder_csrbank2_dfii_pi0_wrdata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_r; +reg builder_csrbank2_dfii_pi0_wrdata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_w; +reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; +reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; +reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; +reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata7_r; +reg builder_csrbank2_dfii_pi0_rddata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata7_w; +reg builder_csrbank2_dfii_pi0_rddata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata6_r; +reg builder_csrbank2_dfii_pi0_rddata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata6_w; +reg builder_csrbank2_dfii_pi0_rddata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata5_r; +reg builder_csrbank2_dfii_pi0_rddata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata5_w; +reg builder_csrbank2_dfii_pi0_rddata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata4_r; +reg builder_csrbank2_dfii_pi0_rddata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata4_w; +reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; +reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; +reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; +reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi1_address1_r; +reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi1_address1_w; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_wrdata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_r; +reg builder_csrbank2_dfii_pi1_wrdata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_w; +reg builder_csrbank2_dfii_pi1_wrdata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_r; +reg builder_csrbank2_dfii_pi1_wrdata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_w; +reg builder_csrbank2_dfii_pi1_wrdata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_r; +reg builder_csrbank2_dfii_pi1_wrdata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_w; +reg builder_csrbank2_dfii_pi1_wrdata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_r; +reg builder_csrbank2_dfii_pi1_wrdata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_w; +reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; +reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; +reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; +reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata7_r; +reg builder_csrbank2_dfii_pi1_rddata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata7_w; +reg builder_csrbank2_dfii_pi1_rddata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata6_r; +reg builder_csrbank2_dfii_pi1_rddata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata6_w; +reg builder_csrbank2_dfii_pi1_rddata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata5_r; +reg builder_csrbank2_dfii_pi1_rddata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata5_w; +reg builder_csrbank2_dfii_pi1_rddata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata4_r; +reg builder_csrbank2_dfii_pi1_rddata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata4_w; +reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; +reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; +reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; +reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi2_address1_r; +reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi2_address1_w; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_wrdata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_r; +reg builder_csrbank2_dfii_pi2_wrdata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_w; +reg builder_csrbank2_dfii_pi2_wrdata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_r; +reg builder_csrbank2_dfii_pi2_wrdata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_w; +reg builder_csrbank2_dfii_pi2_wrdata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_r; +reg builder_csrbank2_dfii_pi2_wrdata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_w; +reg builder_csrbank2_dfii_pi2_wrdata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_r; +reg builder_csrbank2_dfii_pi2_wrdata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_w; +reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; +reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; +reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; +reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata7_r; +reg builder_csrbank2_dfii_pi2_rddata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata7_w; +reg builder_csrbank2_dfii_pi2_rddata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata6_r; +reg builder_csrbank2_dfii_pi2_rddata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata6_w; +reg builder_csrbank2_dfii_pi2_rddata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata5_r; +reg builder_csrbank2_dfii_pi2_rddata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata5_w; +reg builder_csrbank2_dfii_pi2_rddata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata4_r; +reg builder_csrbank2_dfii_pi2_rddata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata4_w; +reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; +reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; +reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; +reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi3_address1_r; +reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi3_address1_w; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_wrdata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_r; +reg builder_csrbank2_dfii_pi3_wrdata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_w; +reg builder_csrbank2_dfii_pi3_wrdata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_r; +reg builder_csrbank2_dfii_pi3_wrdata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_w; +reg builder_csrbank2_dfii_pi3_wrdata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_r; +reg builder_csrbank2_dfii_pi3_wrdata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_w; +reg builder_csrbank2_dfii_pi3_wrdata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_r; +reg builder_csrbank2_dfii_pi3_wrdata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_w; +reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; +reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; +reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; +reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata7_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata7_r; +reg builder_csrbank2_dfii_pi3_rddata7_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata7_w; +reg builder_csrbank2_dfii_pi3_rddata6_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata6_r; +reg builder_csrbank2_dfii_pi3_rddata6_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata6_w; +reg builder_csrbank2_dfii_pi3_rddata5_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata5_r; +reg builder_csrbank2_dfii_pi3_rddata5_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata5_w; +reg builder_csrbank2_dfii_pi3_rddata4_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata4_r; +reg builder_csrbank2_dfii_pi3_rddata4_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata4_w; +reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; +reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; +reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; +reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +wire builder_csrbank2_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [7:0] builder_csr_interconnect_dat_w; +wire [7:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [14:0] builder_rhs_array_muxed1 = 15'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [14:0] builder_rhs_array_muxed7 = 15'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [21:0] builder_rhs_array_muxed12 = 22'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [21:0] builder_rhs_array_muxed15 = 22'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [21:0] builder_rhs_array_muxed18 = 22'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [21:0] builder_rhs_array_muxed21 = 22'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [21:0] builder_rhs_array_muxed24 = 22'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [21:0] builder_rhs_array_muxed27 = 22'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [21:0] builder_rhs_array_muxed30 = 22'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [21:0] builder_rhs_array_muxed33 = 22'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [14:0] builder_array_muxed1 = 15'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [14:0] builder_array_muxed8 = 15'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [14:0] builder_array_muxed15 = 15'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [14:0] builder_array_muxed22 = 15'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl3; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; -assign soc_wb_bus_adr = wb_ctrl_adr; -assign soc_wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = soc_wb_bus_dat_r; -assign soc_wb_bus_sel = wb_ctrl_sel; -assign soc_wb_bus_cyc = wb_ctrl_cyc; -assign soc_wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = soc_wb_bus_ack; -assign soc_wb_bus_we = wb_ctrl_we; -assign soc_wb_bus_cti = wb_ctrl_cti; -assign soc_wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = soc_wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; -assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; -assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; -assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; -assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; -assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; +assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; +assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign main_reset = rst; +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble); +assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble); // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - vns_next_state <= 1'd0; - vns_next_state <= vns_state; - case (vns_state) - 1'd1: begin - vns_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - vns_next_state <= 1'd1; - end - end - endcase + main_k7ddrphy_dfi_p0_rddata <= 64'd0; + main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0]; + main_k7ddrphy_dfi_p0_rddata[32] <= main_k7ddrphy_bitslip04[1]; + main_k7ddrphy_dfi_p0_rddata[1] <= main_k7ddrphy_bitslip14[0]; + main_k7ddrphy_dfi_p0_rddata[33] <= main_k7ddrphy_bitslip14[1]; + main_k7ddrphy_dfi_p0_rddata[2] <= main_k7ddrphy_bitslip24[0]; + main_k7ddrphy_dfi_p0_rddata[34] <= main_k7ddrphy_bitslip24[1]; + main_k7ddrphy_dfi_p0_rddata[3] <= main_k7ddrphy_bitslip34[0]; + main_k7ddrphy_dfi_p0_rddata[35] <= main_k7ddrphy_bitslip34[1]; + main_k7ddrphy_dfi_p0_rddata[4] <= main_k7ddrphy_bitslip42[0]; + main_k7ddrphy_dfi_p0_rddata[36] <= main_k7ddrphy_bitslip42[1]; + main_k7ddrphy_dfi_p0_rddata[5] <= main_k7ddrphy_bitslip52[0]; + main_k7ddrphy_dfi_p0_rddata[37] <= main_k7ddrphy_bitslip52[1]; + main_k7ddrphy_dfi_p0_rddata[6] <= main_k7ddrphy_bitslip62[0]; + main_k7ddrphy_dfi_p0_rddata[38] <= main_k7ddrphy_bitslip62[1]; + main_k7ddrphy_dfi_p0_rddata[7] <= main_k7ddrphy_bitslip72[0]; + main_k7ddrphy_dfi_p0_rddata[39] <= main_k7ddrphy_bitslip72[1]; + main_k7ddrphy_dfi_p0_rddata[8] <= main_k7ddrphy_bitslip82[0]; + main_k7ddrphy_dfi_p0_rddata[40] <= main_k7ddrphy_bitslip82[1]; + main_k7ddrphy_dfi_p0_rddata[9] <= main_k7ddrphy_bitslip92[0]; + main_k7ddrphy_dfi_p0_rddata[41] <= main_k7ddrphy_bitslip92[1]; + main_k7ddrphy_dfi_p0_rddata[10] <= main_k7ddrphy_bitslip102[0]; + main_k7ddrphy_dfi_p0_rddata[42] <= main_k7ddrphy_bitslip102[1]; + main_k7ddrphy_dfi_p0_rddata[11] <= main_k7ddrphy_bitslip112[0]; + main_k7ddrphy_dfi_p0_rddata[43] <= main_k7ddrphy_bitslip112[1]; + main_k7ddrphy_dfi_p0_rddata[12] <= main_k7ddrphy_bitslip122[0]; + main_k7ddrphy_dfi_p0_rddata[44] <= main_k7ddrphy_bitslip122[1]; + main_k7ddrphy_dfi_p0_rddata[13] <= main_k7ddrphy_bitslip132[0]; + main_k7ddrphy_dfi_p0_rddata[45] <= main_k7ddrphy_bitslip132[1]; + main_k7ddrphy_dfi_p0_rddata[14] <= main_k7ddrphy_bitslip142[0]; + main_k7ddrphy_dfi_p0_rddata[46] <= main_k7ddrphy_bitslip142[1]; + main_k7ddrphy_dfi_p0_rddata[15] <= main_k7ddrphy_bitslip152[0]; + main_k7ddrphy_dfi_p0_rddata[47] <= main_k7ddrphy_bitslip152[1]; + main_k7ddrphy_dfi_p0_rddata[16] <= main_k7ddrphy_bitslip162[0]; + main_k7ddrphy_dfi_p0_rddata[48] <= main_k7ddrphy_bitslip162[1]; + main_k7ddrphy_dfi_p0_rddata[17] <= main_k7ddrphy_bitslip172[0]; + main_k7ddrphy_dfi_p0_rddata[49] <= main_k7ddrphy_bitslip172[1]; + main_k7ddrphy_dfi_p0_rddata[18] <= main_k7ddrphy_bitslip182[0]; + main_k7ddrphy_dfi_p0_rddata[50] <= main_k7ddrphy_bitslip182[1]; + main_k7ddrphy_dfi_p0_rddata[19] <= main_k7ddrphy_bitslip192[0]; + main_k7ddrphy_dfi_p0_rddata[51] <= main_k7ddrphy_bitslip192[1]; + main_k7ddrphy_dfi_p0_rddata[20] <= main_k7ddrphy_bitslip202[0]; + main_k7ddrphy_dfi_p0_rddata[52] <= main_k7ddrphy_bitslip202[1]; + main_k7ddrphy_dfi_p0_rddata[21] <= main_k7ddrphy_bitslip212[0]; + main_k7ddrphy_dfi_p0_rddata[53] <= main_k7ddrphy_bitslip212[1]; + main_k7ddrphy_dfi_p0_rddata[22] <= main_k7ddrphy_bitslip222[0]; + main_k7ddrphy_dfi_p0_rddata[54] <= main_k7ddrphy_bitslip222[1]; + main_k7ddrphy_dfi_p0_rddata[23] <= main_k7ddrphy_bitslip232[0]; + main_k7ddrphy_dfi_p0_rddata[55] <= main_k7ddrphy_bitslip232[1]; + main_k7ddrphy_dfi_p0_rddata[24] <= main_k7ddrphy_bitslip242[0]; + main_k7ddrphy_dfi_p0_rddata[56] <= main_k7ddrphy_bitslip242[1]; + main_k7ddrphy_dfi_p0_rddata[25] <= main_k7ddrphy_bitslip252[0]; + main_k7ddrphy_dfi_p0_rddata[57] <= main_k7ddrphy_bitslip252[1]; + main_k7ddrphy_dfi_p0_rddata[26] <= main_k7ddrphy_bitslip262[0]; + main_k7ddrphy_dfi_p0_rddata[58] <= main_k7ddrphy_bitslip262[1]; + main_k7ddrphy_dfi_p0_rddata[27] <= main_k7ddrphy_bitslip272[0]; + main_k7ddrphy_dfi_p0_rddata[59] <= main_k7ddrphy_bitslip272[1]; + main_k7ddrphy_dfi_p0_rddata[28] <= main_k7ddrphy_bitslip282[0]; + main_k7ddrphy_dfi_p0_rddata[60] <= main_k7ddrphy_bitslip282[1]; + main_k7ddrphy_dfi_p0_rddata[29] <= main_k7ddrphy_bitslip292[0]; + main_k7ddrphy_dfi_p0_rddata[61] <= main_k7ddrphy_bitslip292[1]; + main_k7ddrphy_dfi_p0_rddata[30] <= main_k7ddrphy_bitslip302[0]; + main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1]; + main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0]; + main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on @@ -2120,14 +2533,71 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_wishbone_ack <= 1'd0; - case (vns_state) - 1'd1: begin - soc_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase + main_k7ddrphy_dfi_p1_rddata <= 64'd0; + main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2]; + main_k7ddrphy_dfi_p1_rddata[32] <= main_k7ddrphy_bitslip04[3]; + main_k7ddrphy_dfi_p1_rddata[1] <= main_k7ddrphy_bitslip14[2]; + main_k7ddrphy_dfi_p1_rddata[33] <= main_k7ddrphy_bitslip14[3]; + main_k7ddrphy_dfi_p1_rddata[2] <= main_k7ddrphy_bitslip24[2]; + main_k7ddrphy_dfi_p1_rddata[34] <= main_k7ddrphy_bitslip24[3]; + main_k7ddrphy_dfi_p1_rddata[3] <= main_k7ddrphy_bitslip34[2]; + main_k7ddrphy_dfi_p1_rddata[35] <= main_k7ddrphy_bitslip34[3]; + main_k7ddrphy_dfi_p1_rddata[4] <= main_k7ddrphy_bitslip42[2]; + main_k7ddrphy_dfi_p1_rddata[36] <= main_k7ddrphy_bitslip42[3]; + main_k7ddrphy_dfi_p1_rddata[5] <= main_k7ddrphy_bitslip52[2]; + main_k7ddrphy_dfi_p1_rddata[37] <= main_k7ddrphy_bitslip52[3]; + main_k7ddrphy_dfi_p1_rddata[6] <= main_k7ddrphy_bitslip62[2]; + main_k7ddrphy_dfi_p1_rddata[38] <= main_k7ddrphy_bitslip62[3]; + main_k7ddrphy_dfi_p1_rddata[7] <= main_k7ddrphy_bitslip72[2]; + main_k7ddrphy_dfi_p1_rddata[39] <= main_k7ddrphy_bitslip72[3]; + main_k7ddrphy_dfi_p1_rddata[8] <= main_k7ddrphy_bitslip82[2]; + main_k7ddrphy_dfi_p1_rddata[40] <= main_k7ddrphy_bitslip82[3]; + main_k7ddrphy_dfi_p1_rddata[9] <= main_k7ddrphy_bitslip92[2]; + main_k7ddrphy_dfi_p1_rddata[41] <= main_k7ddrphy_bitslip92[3]; + main_k7ddrphy_dfi_p1_rddata[10] <= main_k7ddrphy_bitslip102[2]; + main_k7ddrphy_dfi_p1_rddata[42] <= main_k7ddrphy_bitslip102[3]; + main_k7ddrphy_dfi_p1_rddata[11] <= main_k7ddrphy_bitslip112[2]; + main_k7ddrphy_dfi_p1_rddata[43] <= main_k7ddrphy_bitslip112[3]; + main_k7ddrphy_dfi_p1_rddata[12] <= main_k7ddrphy_bitslip122[2]; + main_k7ddrphy_dfi_p1_rddata[44] <= main_k7ddrphy_bitslip122[3]; + main_k7ddrphy_dfi_p1_rddata[13] <= main_k7ddrphy_bitslip132[2]; + main_k7ddrphy_dfi_p1_rddata[45] <= main_k7ddrphy_bitslip132[3]; + main_k7ddrphy_dfi_p1_rddata[14] <= main_k7ddrphy_bitslip142[2]; + main_k7ddrphy_dfi_p1_rddata[46] <= main_k7ddrphy_bitslip142[3]; + main_k7ddrphy_dfi_p1_rddata[15] <= main_k7ddrphy_bitslip152[2]; + main_k7ddrphy_dfi_p1_rddata[47] <= main_k7ddrphy_bitslip152[3]; + main_k7ddrphy_dfi_p1_rddata[16] <= main_k7ddrphy_bitslip162[2]; + main_k7ddrphy_dfi_p1_rddata[48] <= main_k7ddrphy_bitslip162[3]; + main_k7ddrphy_dfi_p1_rddata[17] <= main_k7ddrphy_bitslip172[2]; + main_k7ddrphy_dfi_p1_rddata[49] <= main_k7ddrphy_bitslip172[3]; + main_k7ddrphy_dfi_p1_rddata[18] <= main_k7ddrphy_bitslip182[2]; + main_k7ddrphy_dfi_p1_rddata[50] <= main_k7ddrphy_bitslip182[3]; + main_k7ddrphy_dfi_p1_rddata[19] <= main_k7ddrphy_bitslip192[2]; + main_k7ddrphy_dfi_p1_rddata[51] <= main_k7ddrphy_bitslip192[3]; + main_k7ddrphy_dfi_p1_rddata[20] <= main_k7ddrphy_bitslip202[2]; + main_k7ddrphy_dfi_p1_rddata[52] <= main_k7ddrphy_bitslip202[3]; + main_k7ddrphy_dfi_p1_rddata[21] <= main_k7ddrphy_bitslip212[2]; + main_k7ddrphy_dfi_p1_rddata[53] <= main_k7ddrphy_bitslip212[3]; + main_k7ddrphy_dfi_p1_rddata[22] <= main_k7ddrphy_bitslip222[2]; + main_k7ddrphy_dfi_p1_rddata[54] <= main_k7ddrphy_bitslip222[3]; + main_k7ddrphy_dfi_p1_rddata[23] <= main_k7ddrphy_bitslip232[2]; + main_k7ddrphy_dfi_p1_rddata[55] <= main_k7ddrphy_bitslip232[3]; + main_k7ddrphy_dfi_p1_rddata[24] <= main_k7ddrphy_bitslip242[2]; + main_k7ddrphy_dfi_p1_rddata[56] <= main_k7ddrphy_bitslip242[3]; + main_k7ddrphy_dfi_p1_rddata[25] <= main_k7ddrphy_bitslip252[2]; + main_k7ddrphy_dfi_p1_rddata[57] <= main_k7ddrphy_bitslip252[3]; + main_k7ddrphy_dfi_p1_rddata[26] <= main_k7ddrphy_bitslip262[2]; + main_k7ddrphy_dfi_p1_rddata[58] <= main_k7ddrphy_bitslip262[3]; + main_k7ddrphy_dfi_p1_rddata[27] <= main_k7ddrphy_bitslip272[2]; + main_k7ddrphy_dfi_p1_rddata[59] <= main_k7ddrphy_bitslip272[3]; + main_k7ddrphy_dfi_p1_rddata[28] <= main_k7ddrphy_bitslip282[2]; + main_k7ddrphy_dfi_p1_rddata[60] <= main_k7ddrphy_bitslip282[3]; + main_k7ddrphy_dfi_p1_rddata[29] <= main_k7ddrphy_bitslip292[2]; + main_k7ddrphy_dfi_p1_rddata[61] <= main_k7ddrphy_bitslip292[3]; + main_k7ddrphy_dfi_p1_rddata[30] <= main_k7ddrphy_bitslip302[2]; + main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3]; + main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2]; + main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on @@ -2137,16 +2607,71 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_adr <= 14'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; - end - end - endcase + main_k7ddrphy_dfi_p2_rddata <= 64'd0; + main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4]; + main_k7ddrphy_dfi_p2_rddata[32] <= main_k7ddrphy_bitslip04[5]; + main_k7ddrphy_dfi_p2_rddata[1] <= main_k7ddrphy_bitslip14[4]; + main_k7ddrphy_dfi_p2_rddata[33] <= main_k7ddrphy_bitslip14[5]; + main_k7ddrphy_dfi_p2_rddata[2] <= main_k7ddrphy_bitslip24[4]; + main_k7ddrphy_dfi_p2_rddata[34] <= main_k7ddrphy_bitslip24[5]; + main_k7ddrphy_dfi_p2_rddata[3] <= main_k7ddrphy_bitslip34[4]; + main_k7ddrphy_dfi_p2_rddata[35] <= main_k7ddrphy_bitslip34[5]; + main_k7ddrphy_dfi_p2_rddata[4] <= main_k7ddrphy_bitslip42[4]; + main_k7ddrphy_dfi_p2_rddata[36] <= main_k7ddrphy_bitslip42[5]; + main_k7ddrphy_dfi_p2_rddata[5] <= main_k7ddrphy_bitslip52[4]; + main_k7ddrphy_dfi_p2_rddata[37] <= main_k7ddrphy_bitslip52[5]; + main_k7ddrphy_dfi_p2_rddata[6] <= main_k7ddrphy_bitslip62[4]; + main_k7ddrphy_dfi_p2_rddata[38] <= main_k7ddrphy_bitslip62[5]; + main_k7ddrphy_dfi_p2_rddata[7] <= main_k7ddrphy_bitslip72[4]; + main_k7ddrphy_dfi_p2_rddata[39] <= main_k7ddrphy_bitslip72[5]; + main_k7ddrphy_dfi_p2_rddata[8] <= main_k7ddrphy_bitslip82[4]; + main_k7ddrphy_dfi_p2_rddata[40] <= main_k7ddrphy_bitslip82[5]; + main_k7ddrphy_dfi_p2_rddata[9] <= main_k7ddrphy_bitslip92[4]; + main_k7ddrphy_dfi_p2_rddata[41] <= main_k7ddrphy_bitslip92[5]; + main_k7ddrphy_dfi_p2_rddata[10] <= main_k7ddrphy_bitslip102[4]; + main_k7ddrphy_dfi_p2_rddata[42] <= main_k7ddrphy_bitslip102[5]; + main_k7ddrphy_dfi_p2_rddata[11] <= main_k7ddrphy_bitslip112[4]; + main_k7ddrphy_dfi_p2_rddata[43] <= main_k7ddrphy_bitslip112[5]; + main_k7ddrphy_dfi_p2_rddata[12] <= main_k7ddrphy_bitslip122[4]; + main_k7ddrphy_dfi_p2_rddata[44] <= main_k7ddrphy_bitslip122[5]; + main_k7ddrphy_dfi_p2_rddata[13] <= main_k7ddrphy_bitslip132[4]; + main_k7ddrphy_dfi_p2_rddata[45] <= main_k7ddrphy_bitslip132[5]; + main_k7ddrphy_dfi_p2_rddata[14] <= main_k7ddrphy_bitslip142[4]; + main_k7ddrphy_dfi_p2_rddata[46] <= main_k7ddrphy_bitslip142[5]; + main_k7ddrphy_dfi_p2_rddata[15] <= main_k7ddrphy_bitslip152[4]; + main_k7ddrphy_dfi_p2_rddata[47] <= main_k7ddrphy_bitslip152[5]; + main_k7ddrphy_dfi_p2_rddata[16] <= main_k7ddrphy_bitslip162[4]; + main_k7ddrphy_dfi_p2_rddata[48] <= main_k7ddrphy_bitslip162[5]; + main_k7ddrphy_dfi_p2_rddata[17] <= main_k7ddrphy_bitslip172[4]; + main_k7ddrphy_dfi_p2_rddata[49] <= main_k7ddrphy_bitslip172[5]; + main_k7ddrphy_dfi_p2_rddata[18] <= main_k7ddrphy_bitslip182[4]; + main_k7ddrphy_dfi_p2_rddata[50] <= main_k7ddrphy_bitslip182[5]; + main_k7ddrphy_dfi_p2_rddata[19] <= main_k7ddrphy_bitslip192[4]; + main_k7ddrphy_dfi_p2_rddata[51] <= main_k7ddrphy_bitslip192[5]; + main_k7ddrphy_dfi_p2_rddata[20] <= main_k7ddrphy_bitslip202[4]; + main_k7ddrphy_dfi_p2_rddata[52] <= main_k7ddrphy_bitslip202[5]; + main_k7ddrphy_dfi_p2_rddata[21] <= main_k7ddrphy_bitslip212[4]; + main_k7ddrphy_dfi_p2_rddata[53] <= main_k7ddrphy_bitslip212[5]; + main_k7ddrphy_dfi_p2_rddata[22] <= main_k7ddrphy_bitslip222[4]; + main_k7ddrphy_dfi_p2_rddata[54] <= main_k7ddrphy_bitslip222[5]; + main_k7ddrphy_dfi_p2_rddata[23] <= main_k7ddrphy_bitslip232[4]; + main_k7ddrphy_dfi_p2_rddata[55] <= main_k7ddrphy_bitslip232[5]; + main_k7ddrphy_dfi_p2_rddata[24] <= main_k7ddrphy_bitslip242[4]; + main_k7ddrphy_dfi_p2_rddata[56] <= main_k7ddrphy_bitslip242[5]; + main_k7ddrphy_dfi_p2_rddata[25] <= main_k7ddrphy_bitslip252[4]; + main_k7ddrphy_dfi_p2_rddata[57] <= main_k7ddrphy_bitslip252[5]; + main_k7ddrphy_dfi_p2_rddata[26] <= main_k7ddrphy_bitslip262[4]; + main_k7ddrphy_dfi_p2_rddata[58] <= main_k7ddrphy_bitslip262[5]; + main_k7ddrphy_dfi_p2_rddata[27] <= main_k7ddrphy_bitslip272[4]; + main_k7ddrphy_dfi_p2_rddata[59] <= main_k7ddrphy_bitslip272[5]; + main_k7ddrphy_dfi_p2_rddata[28] <= main_k7ddrphy_bitslip282[4]; + main_k7ddrphy_dfi_p2_rddata[60] <= main_k7ddrphy_bitslip282[5]; + main_k7ddrphy_dfi_p2_rddata[29] <= main_k7ddrphy_bitslip292[4]; + main_k7ddrphy_dfi_p2_rddata[61] <= main_k7ddrphy_bitslip292[5]; + main_k7ddrphy_dfi_p2_rddata[30] <= main_k7ddrphy_bitslip302[4]; + main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5]; + main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4]; + main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -2156,172 +2681,116 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_we <= 1'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); - end - end - endcase + main_k7ddrphy_dfi_p3_rddata <= 64'd0; + main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6]; + main_k7ddrphy_dfi_p3_rddata[32] <= main_k7ddrphy_bitslip04[7]; + main_k7ddrphy_dfi_p3_rddata[1] <= main_k7ddrphy_bitslip14[6]; + main_k7ddrphy_dfi_p3_rddata[33] <= main_k7ddrphy_bitslip14[7]; + main_k7ddrphy_dfi_p3_rddata[2] <= main_k7ddrphy_bitslip24[6]; + main_k7ddrphy_dfi_p3_rddata[34] <= main_k7ddrphy_bitslip24[7]; + main_k7ddrphy_dfi_p3_rddata[3] <= main_k7ddrphy_bitslip34[6]; + main_k7ddrphy_dfi_p3_rddata[35] <= main_k7ddrphy_bitslip34[7]; + main_k7ddrphy_dfi_p3_rddata[4] <= main_k7ddrphy_bitslip42[6]; + main_k7ddrphy_dfi_p3_rddata[36] <= main_k7ddrphy_bitslip42[7]; + main_k7ddrphy_dfi_p3_rddata[5] <= main_k7ddrphy_bitslip52[6]; + main_k7ddrphy_dfi_p3_rddata[37] <= main_k7ddrphy_bitslip52[7]; + main_k7ddrphy_dfi_p3_rddata[6] <= main_k7ddrphy_bitslip62[6]; + main_k7ddrphy_dfi_p3_rddata[38] <= main_k7ddrphy_bitslip62[7]; + main_k7ddrphy_dfi_p3_rddata[7] <= main_k7ddrphy_bitslip72[6]; + main_k7ddrphy_dfi_p3_rddata[39] <= main_k7ddrphy_bitslip72[7]; + main_k7ddrphy_dfi_p3_rddata[8] <= main_k7ddrphy_bitslip82[6]; + main_k7ddrphy_dfi_p3_rddata[40] <= main_k7ddrphy_bitslip82[7]; + main_k7ddrphy_dfi_p3_rddata[9] <= main_k7ddrphy_bitslip92[6]; + main_k7ddrphy_dfi_p3_rddata[41] <= main_k7ddrphy_bitslip92[7]; + main_k7ddrphy_dfi_p3_rddata[10] <= main_k7ddrphy_bitslip102[6]; + main_k7ddrphy_dfi_p3_rddata[42] <= main_k7ddrphy_bitslip102[7]; + main_k7ddrphy_dfi_p3_rddata[11] <= main_k7ddrphy_bitslip112[6]; + main_k7ddrphy_dfi_p3_rddata[43] <= main_k7ddrphy_bitslip112[7]; + main_k7ddrphy_dfi_p3_rddata[12] <= main_k7ddrphy_bitslip122[6]; + main_k7ddrphy_dfi_p3_rddata[44] <= main_k7ddrphy_bitslip122[7]; + main_k7ddrphy_dfi_p3_rddata[13] <= main_k7ddrphy_bitslip132[6]; + main_k7ddrphy_dfi_p3_rddata[45] <= main_k7ddrphy_bitslip132[7]; + main_k7ddrphy_dfi_p3_rddata[14] <= main_k7ddrphy_bitslip142[6]; + main_k7ddrphy_dfi_p3_rddata[46] <= main_k7ddrphy_bitslip142[7]; + main_k7ddrphy_dfi_p3_rddata[15] <= main_k7ddrphy_bitslip152[6]; + main_k7ddrphy_dfi_p3_rddata[47] <= main_k7ddrphy_bitslip152[7]; + main_k7ddrphy_dfi_p3_rddata[16] <= main_k7ddrphy_bitslip162[6]; + main_k7ddrphy_dfi_p3_rddata[48] <= main_k7ddrphy_bitslip162[7]; + main_k7ddrphy_dfi_p3_rddata[17] <= main_k7ddrphy_bitslip172[6]; + main_k7ddrphy_dfi_p3_rddata[49] <= main_k7ddrphy_bitslip172[7]; + main_k7ddrphy_dfi_p3_rddata[18] <= main_k7ddrphy_bitslip182[6]; + main_k7ddrphy_dfi_p3_rddata[50] <= main_k7ddrphy_bitslip182[7]; + main_k7ddrphy_dfi_p3_rddata[19] <= main_k7ddrphy_bitslip192[6]; + main_k7ddrphy_dfi_p3_rddata[51] <= main_k7ddrphy_bitslip192[7]; + main_k7ddrphy_dfi_p3_rddata[20] <= main_k7ddrphy_bitslip202[6]; + main_k7ddrphy_dfi_p3_rddata[52] <= main_k7ddrphy_bitslip202[7]; + main_k7ddrphy_dfi_p3_rddata[21] <= main_k7ddrphy_bitslip212[6]; + main_k7ddrphy_dfi_p3_rddata[53] <= main_k7ddrphy_bitslip212[7]; + main_k7ddrphy_dfi_p3_rddata[22] <= main_k7ddrphy_bitslip222[6]; + main_k7ddrphy_dfi_p3_rddata[54] <= main_k7ddrphy_bitslip222[7]; + main_k7ddrphy_dfi_p3_rddata[23] <= main_k7ddrphy_bitslip232[6]; + main_k7ddrphy_dfi_p3_rddata[55] <= main_k7ddrphy_bitslip232[7]; + main_k7ddrphy_dfi_p3_rddata[24] <= main_k7ddrphy_bitslip242[6]; + main_k7ddrphy_dfi_p3_rddata[56] <= main_k7ddrphy_bitslip242[7]; + main_k7ddrphy_dfi_p3_rddata[25] <= main_k7ddrphy_bitslip252[6]; + main_k7ddrphy_dfi_p3_rddata[57] <= main_k7ddrphy_bitslip252[7]; + main_k7ddrphy_dfi_p3_rddata[26] <= main_k7ddrphy_bitslip262[6]; + main_k7ddrphy_dfi_p3_rddata[58] <= main_k7ddrphy_bitslip262[7]; + main_k7ddrphy_dfi_p3_rddata[27] <= main_k7ddrphy_bitslip272[6]; + main_k7ddrphy_dfi_p3_rddata[59] <= main_k7ddrphy_bitslip272[7]; + main_k7ddrphy_dfi_p3_rddata[28] <= main_k7ddrphy_bitslip282[6]; + main_k7ddrphy_dfi_p3_rddata[60] <= main_k7ddrphy_bitslip282[7]; + main_k7ddrphy_dfi_p3_rddata[29] <= main_k7ddrphy_bitslip292[6]; + main_k7ddrphy_dfi_p3_rddata[61] <= main_k7ddrphy_bitslip292[7]; + main_k7ddrphy_dfi_p3_rddata[30] <= main_k7ddrphy_bitslip302[6]; + main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7]; + main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6]; + main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end -assign soc_reset = rst; -assign pll_locked = soc_locked; -assign soc_clkin = clk; -assign iodelay_clk = soc_clkout_buf0; -assign sys_clk = soc_clkout_buf1; -assign sys4x_clk = soc_clkout_buf2; -assign sys4x_dqs_clk = soc_clkout_buf3; -assign soc_k7ddrphy_bitslip0_i = soc_k7ddrphy_dq_i_data0; +assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dfi_p0_rddata <= 64'd0; - soc_k7ddrphy_dfi_p0_rddata[0] <= soc_k7ddrphy_bitslip0_o[0]; - soc_k7ddrphy_dfi_p0_rddata[32] <= soc_k7ddrphy_bitslip0_o[1]; - soc_k7ddrphy_dfi_p0_rddata[1] <= soc_k7ddrphy_bitslip1_o[0]; - soc_k7ddrphy_dfi_p0_rddata[33] <= soc_k7ddrphy_bitslip1_o[1]; - soc_k7ddrphy_dfi_p0_rddata[2] <= soc_k7ddrphy_bitslip2_o[0]; - soc_k7ddrphy_dfi_p0_rddata[34] <= soc_k7ddrphy_bitslip2_o[1]; - soc_k7ddrphy_dfi_p0_rddata[3] <= soc_k7ddrphy_bitslip3_o[0]; - soc_k7ddrphy_dfi_p0_rddata[35] <= soc_k7ddrphy_bitslip3_o[1]; - soc_k7ddrphy_dfi_p0_rddata[4] <= soc_k7ddrphy_bitslip4_o[0]; - soc_k7ddrphy_dfi_p0_rddata[36] <= soc_k7ddrphy_bitslip4_o[1]; - soc_k7ddrphy_dfi_p0_rddata[5] <= soc_k7ddrphy_bitslip5_o[0]; - soc_k7ddrphy_dfi_p0_rddata[37] <= soc_k7ddrphy_bitslip5_o[1]; - soc_k7ddrphy_dfi_p0_rddata[6] <= soc_k7ddrphy_bitslip6_o[0]; - soc_k7ddrphy_dfi_p0_rddata[38] <= soc_k7ddrphy_bitslip6_o[1]; - soc_k7ddrphy_dfi_p0_rddata[7] <= soc_k7ddrphy_bitslip7_o[0]; - soc_k7ddrphy_dfi_p0_rddata[39] <= soc_k7ddrphy_bitslip7_o[1]; - soc_k7ddrphy_dfi_p0_rddata[8] <= soc_k7ddrphy_bitslip8_o[0]; - soc_k7ddrphy_dfi_p0_rddata[40] <= soc_k7ddrphy_bitslip8_o[1]; - soc_k7ddrphy_dfi_p0_rddata[9] <= soc_k7ddrphy_bitslip9_o[0]; - soc_k7ddrphy_dfi_p0_rddata[41] <= soc_k7ddrphy_bitslip9_o[1]; - soc_k7ddrphy_dfi_p0_rddata[10] <= soc_k7ddrphy_bitslip10_o[0]; - soc_k7ddrphy_dfi_p0_rddata[42] <= soc_k7ddrphy_bitslip10_o[1]; - soc_k7ddrphy_dfi_p0_rddata[11] <= soc_k7ddrphy_bitslip11_o[0]; - soc_k7ddrphy_dfi_p0_rddata[43] <= soc_k7ddrphy_bitslip11_o[1]; - soc_k7ddrphy_dfi_p0_rddata[12] <= soc_k7ddrphy_bitslip12_o[0]; - soc_k7ddrphy_dfi_p0_rddata[44] <= soc_k7ddrphy_bitslip12_o[1]; - soc_k7ddrphy_dfi_p0_rddata[13] <= soc_k7ddrphy_bitslip13_o[0]; - soc_k7ddrphy_dfi_p0_rddata[45] <= soc_k7ddrphy_bitslip13_o[1]; - soc_k7ddrphy_dfi_p0_rddata[14] <= soc_k7ddrphy_bitslip14_o[0]; - soc_k7ddrphy_dfi_p0_rddata[46] <= soc_k7ddrphy_bitslip14_o[1]; - soc_k7ddrphy_dfi_p0_rddata[15] <= soc_k7ddrphy_bitslip15_o[0]; - soc_k7ddrphy_dfi_p0_rddata[47] <= soc_k7ddrphy_bitslip15_o[1]; - soc_k7ddrphy_dfi_p0_rddata[16] <= soc_k7ddrphy_bitslip16_o[0]; - soc_k7ddrphy_dfi_p0_rddata[48] <= soc_k7ddrphy_bitslip16_o[1]; - soc_k7ddrphy_dfi_p0_rddata[17] <= soc_k7ddrphy_bitslip17_o[0]; - soc_k7ddrphy_dfi_p0_rddata[49] <= soc_k7ddrphy_bitslip17_o[1]; - soc_k7ddrphy_dfi_p0_rddata[18] <= soc_k7ddrphy_bitslip18_o[0]; - soc_k7ddrphy_dfi_p0_rddata[50] <= soc_k7ddrphy_bitslip18_o[1]; - soc_k7ddrphy_dfi_p0_rddata[19] <= soc_k7ddrphy_bitslip19_o[0]; - soc_k7ddrphy_dfi_p0_rddata[51] <= soc_k7ddrphy_bitslip19_o[1]; - soc_k7ddrphy_dfi_p0_rddata[20] <= soc_k7ddrphy_bitslip20_o[0]; - soc_k7ddrphy_dfi_p0_rddata[52] <= soc_k7ddrphy_bitslip20_o[1]; - soc_k7ddrphy_dfi_p0_rddata[21] <= soc_k7ddrphy_bitslip21_o[0]; - soc_k7ddrphy_dfi_p0_rddata[53] <= soc_k7ddrphy_bitslip21_o[1]; - soc_k7ddrphy_dfi_p0_rddata[22] <= soc_k7ddrphy_bitslip22_o[0]; - soc_k7ddrphy_dfi_p0_rddata[54] <= soc_k7ddrphy_bitslip22_o[1]; - soc_k7ddrphy_dfi_p0_rddata[23] <= soc_k7ddrphy_bitslip23_o[0]; - soc_k7ddrphy_dfi_p0_rddata[55] <= soc_k7ddrphy_bitslip23_o[1]; - soc_k7ddrphy_dfi_p0_rddata[24] <= soc_k7ddrphy_bitslip24_o[0]; - soc_k7ddrphy_dfi_p0_rddata[56] <= soc_k7ddrphy_bitslip24_o[1]; - soc_k7ddrphy_dfi_p0_rddata[25] <= soc_k7ddrphy_bitslip25_o[0]; - soc_k7ddrphy_dfi_p0_rddata[57] <= soc_k7ddrphy_bitslip25_o[1]; - soc_k7ddrphy_dfi_p0_rddata[26] <= soc_k7ddrphy_bitslip26_o[0]; - soc_k7ddrphy_dfi_p0_rddata[58] <= soc_k7ddrphy_bitslip26_o[1]; - soc_k7ddrphy_dfi_p0_rddata[27] <= soc_k7ddrphy_bitslip27_o[0]; - soc_k7ddrphy_dfi_p0_rddata[59] <= soc_k7ddrphy_bitslip27_o[1]; - soc_k7ddrphy_dfi_p0_rddata[28] <= soc_k7ddrphy_bitslip28_o[0]; - soc_k7ddrphy_dfi_p0_rddata[60] <= soc_k7ddrphy_bitslip28_o[1]; - soc_k7ddrphy_dfi_p0_rddata[29] <= soc_k7ddrphy_bitslip29_o[0]; - soc_k7ddrphy_dfi_p0_rddata[61] <= soc_k7ddrphy_bitslip29_o[1]; - soc_k7ddrphy_dfi_p0_rddata[30] <= soc_k7ddrphy_bitslip30_o[0]; - soc_k7ddrphy_dfi_p0_rddata[62] <= soc_k7ddrphy_bitslip30_o[1]; - soc_k7ddrphy_dfi_p0_rddata[31] <= soc_k7ddrphy_bitslip31_o[0]; - soc_k7ddrphy_dfi_p0_rddata[63] <= soc_k7ddrphy_bitslip31_o[1]; + main_k7ddrphy_dqs_oe <= 1'd0; + if (main_k7ddrphy_wlevel_en_storage) begin + main_k7ddrphy_dqs_oe <= 1'd1; + end else begin + main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe; + end // synthesis translate_off dummy_d_4 = dummy_s; // synthesis translate_on end +assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); +assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); // synthesis translate_off reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dfi_p1_rddata <= 64'd0; - soc_k7ddrphy_dfi_p1_rddata[0] <= soc_k7ddrphy_bitslip0_o[2]; - soc_k7ddrphy_dfi_p1_rddata[32] <= soc_k7ddrphy_bitslip0_o[3]; - soc_k7ddrphy_dfi_p1_rddata[1] <= soc_k7ddrphy_bitslip1_o[2]; - soc_k7ddrphy_dfi_p1_rddata[33] <= soc_k7ddrphy_bitslip1_o[3]; - soc_k7ddrphy_dfi_p1_rddata[2] <= soc_k7ddrphy_bitslip2_o[2]; - soc_k7ddrphy_dfi_p1_rddata[34] <= soc_k7ddrphy_bitslip2_o[3]; - soc_k7ddrphy_dfi_p1_rddata[3] <= soc_k7ddrphy_bitslip3_o[2]; - soc_k7ddrphy_dfi_p1_rddata[35] <= soc_k7ddrphy_bitslip3_o[3]; - soc_k7ddrphy_dfi_p1_rddata[4] <= soc_k7ddrphy_bitslip4_o[2]; - soc_k7ddrphy_dfi_p1_rddata[36] <= soc_k7ddrphy_bitslip4_o[3]; - soc_k7ddrphy_dfi_p1_rddata[5] <= soc_k7ddrphy_bitslip5_o[2]; - soc_k7ddrphy_dfi_p1_rddata[37] <= soc_k7ddrphy_bitslip5_o[3]; - soc_k7ddrphy_dfi_p1_rddata[6] <= soc_k7ddrphy_bitslip6_o[2]; - soc_k7ddrphy_dfi_p1_rddata[38] <= soc_k7ddrphy_bitslip6_o[3]; - soc_k7ddrphy_dfi_p1_rddata[7] <= soc_k7ddrphy_bitslip7_o[2]; - soc_k7ddrphy_dfi_p1_rddata[39] <= soc_k7ddrphy_bitslip7_o[3]; - soc_k7ddrphy_dfi_p1_rddata[8] <= soc_k7ddrphy_bitslip8_o[2]; - soc_k7ddrphy_dfi_p1_rddata[40] <= soc_k7ddrphy_bitslip8_o[3]; - soc_k7ddrphy_dfi_p1_rddata[9] <= soc_k7ddrphy_bitslip9_o[2]; - soc_k7ddrphy_dfi_p1_rddata[41] <= soc_k7ddrphy_bitslip9_o[3]; - soc_k7ddrphy_dfi_p1_rddata[10] <= soc_k7ddrphy_bitslip10_o[2]; - soc_k7ddrphy_dfi_p1_rddata[42] <= soc_k7ddrphy_bitslip10_o[3]; - soc_k7ddrphy_dfi_p1_rddata[11] <= soc_k7ddrphy_bitslip11_o[2]; - soc_k7ddrphy_dfi_p1_rddata[43] <= soc_k7ddrphy_bitslip11_o[3]; - soc_k7ddrphy_dfi_p1_rddata[12] <= soc_k7ddrphy_bitslip12_o[2]; - soc_k7ddrphy_dfi_p1_rddata[44] <= soc_k7ddrphy_bitslip12_o[3]; - soc_k7ddrphy_dfi_p1_rddata[13] <= soc_k7ddrphy_bitslip13_o[2]; - soc_k7ddrphy_dfi_p1_rddata[45] <= soc_k7ddrphy_bitslip13_o[3]; - soc_k7ddrphy_dfi_p1_rddata[14] <= soc_k7ddrphy_bitslip14_o[2]; - soc_k7ddrphy_dfi_p1_rddata[46] <= soc_k7ddrphy_bitslip14_o[3]; - soc_k7ddrphy_dfi_p1_rddata[15] <= soc_k7ddrphy_bitslip15_o[2]; - soc_k7ddrphy_dfi_p1_rddata[47] <= soc_k7ddrphy_bitslip15_o[3]; - soc_k7ddrphy_dfi_p1_rddata[16] <= soc_k7ddrphy_bitslip16_o[2]; - soc_k7ddrphy_dfi_p1_rddata[48] <= soc_k7ddrphy_bitslip16_o[3]; - soc_k7ddrphy_dfi_p1_rddata[17] <= soc_k7ddrphy_bitslip17_o[2]; - soc_k7ddrphy_dfi_p1_rddata[49] <= soc_k7ddrphy_bitslip17_o[3]; - soc_k7ddrphy_dfi_p1_rddata[18] <= soc_k7ddrphy_bitslip18_o[2]; - soc_k7ddrphy_dfi_p1_rddata[50] <= soc_k7ddrphy_bitslip18_o[3]; - soc_k7ddrphy_dfi_p1_rddata[19] <= soc_k7ddrphy_bitslip19_o[2]; - soc_k7ddrphy_dfi_p1_rddata[51] <= soc_k7ddrphy_bitslip19_o[3]; - soc_k7ddrphy_dfi_p1_rddata[20] <= soc_k7ddrphy_bitslip20_o[2]; - soc_k7ddrphy_dfi_p1_rddata[52] <= soc_k7ddrphy_bitslip20_o[3]; - soc_k7ddrphy_dfi_p1_rddata[21] <= soc_k7ddrphy_bitslip21_o[2]; - soc_k7ddrphy_dfi_p1_rddata[53] <= soc_k7ddrphy_bitslip21_o[3]; - soc_k7ddrphy_dfi_p1_rddata[22] <= soc_k7ddrphy_bitslip22_o[2]; - soc_k7ddrphy_dfi_p1_rddata[54] <= soc_k7ddrphy_bitslip22_o[3]; - soc_k7ddrphy_dfi_p1_rddata[23] <= soc_k7ddrphy_bitslip23_o[2]; - soc_k7ddrphy_dfi_p1_rddata[55] <= soc_k7ddrphy_bitslip23_o[3]; - soc_k7ddrphy_dfi_p1_rddata[24] <= soc_k7ddrphy_bitslip24_o[2]; - soc_k7ddrphy_dfi_p1_rddata[56] <= soc_k7ddrphy_bitslip24_o[3]; - soc_k7ddrphy_dfi_p1_rddata[25] <= soc_k7ddrphy_bitslip25_o[2]; - soc_k7ddrphy_dfi_p1_rddata[57] <= soc_k7ddrphy_bitslip25_o[3]; - soc_k7ddrphy_dfi_p1_rddata[26] <= soc_k7ddrphy_bitslip26_o[2]; - soc_k7ddrphy_dfi_p1_rddata[58] <= soc_k7ddrphy_bitslip26_o[3]; - soc_k7ddrphy_dfi_p1_rddata[27] <= soc_k7ddrphy_bitslip27_o[2]; - soc_k7ddrphy_dfi_p1_rddata[59] <= soc_k7ddrphy_bitslip27_o[3]; - soc_k7ddrphy_dfi_p1_rddata[28] <= soc_k7ddrphy_bitslip28_o[2]; - soc_k7ddrphy_dfi_p1_rddata[60] <= soc_k7ddrphy_bitslip28_o[3]; - soc_k7ddrphy_dfi_p1_rddata[29] <= soc_k7ddrphy_bitslip29_o[2]; - soc_k7ddrphy_dfi_p1_rddata[61] <= soc_k7ddrphy_bitslip29_o[3]; - soc_k7ddrphy_dfi_p1_rddata[30] <= soc_k7ddrphy_bitslip30_o[2]; - soc_k7ddrphy_dfi_p1_rddata[62] <= soc_k7ddrphy_bitslip30_o[3]; - soc_k7ddrphy_dfi_p1_rddata[31] <= soc_k7ddrphy_bitslip31_o[2]; - soc_k7ddrphy_dfi_p1_rddata[63] <= soc_k7ddrphy_bitslip31_o[3]; + main_k7ddrphy_dqspattern_o <= 8'd0; + main_k7ddrphy_dqspattern_o <= 7'd85; + if (main_k7ddrphy_dqspattern0) begin + main_k7ddrphy_dqspattern_o <= 5'd21; + end + if (main_k7ddrphy_dqspattern1) begin + main_k7ddrphy_dqspattern_o <= 7'd84; + end + if (main_k7ddrphy_wlevel_en_storage) begin + main_k7ddrphy_dqspattern_o <= 1'd0; + if (main_k7ddrphy_wlevel_strobe_re) begin + main_k7ddrphy_dqspattern_o <= 1'd1; + end + end // synthesis translate_off dummy_d_5 = dummy_s; // synthesis translate_on @@ -2331,71 +2800,33 @@ end reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dfi_p2_rddata <= 64'd0; - soc_k7ddrphy_dfi_p2_rddata[0] <= soc_k7ddrphy_bitslip0_o[4]; - soc_k7ddrphy_dfi_p2_rddata[32] <= soc_k7ddrphy_bitslip0_o[5]; - soc_k7ddrphy_dfi_p2_rddata[1] <= soc_k7ddrphy_bitslip1_o[4]; - soc_k7ddrphy_dfi_p2_rddata[33] <= soc_k7ddrphy_bitslip1_o[5]; - soc_k7ddrphy_dfi_p2_rddata[2] <= soc_k7ddrphy_bitslip2_o[4]; - soc_k7ddrphy_dfi_p2_rddata[34] <= soc_k7ddrphy_bitslip2_o[5]; - soc_k7ddrphy_dfi_p2_rddata[3] <= soc_k7ddrphy_bitslip3_o[4]; - soc_k7ddrphy_dfi_p2_rddata[35] <= soc_k7ddrphy_bitslip3_o[5]; - soc_k7ddrphy_dfi_p2_rddata[4] <= soc_k7ddrphy_bitslip4_o[4]; - soc_k7ddrphy_dfi_p2_rddata[36] <= soc_k7ddrphy_bitslip4_o[5]; - soc_k7ddrphy_dfi_p2_rddata[5] <= soc_k7ddrphy_bitslip5_o[4]; - soc_k7ddrphy_dfi_p2_rddata[37] <= soc_k7ddrphy_bitslip5_o[5]; - soc_k7ddrphy_dfi_p2_rddata[6] <= soc_k7ddrphy_bitslip6_o[4]; - soc_k7ddrphy_dfi_p2_rddata[38] <= soc_k7ddrphy_bitslip6_o[5]; - soc_k7ddrphy_dfi_p2_rddata[7] <= soc_k7ddrphy_bitslip7_o[4]; - soc_k7ddrphy_dfi_p2_rddata[39] <= soc_k7ddrphy_bitslip7_o[5]; - soc_k7ddrphy_dfi_p2_rddata[8] <= soc_k7ddrphy_bitslip8_o[4]; - soc_k7ddrphy_dfi_p2_rddata[40] <= soc_k7ddrphy_bitslip8_o[5]; - soc_k7ddrphy_dfi_p2_rddata[9] <= soc_k7ddrphy_bitslip9_o[4]; - soc_k7ddrphy_dfi_p2_rddata[41] <= soc_k7ddrphy_bitslip9_o[5]; - soc_k7ddrphy_dfi_p2_rddata[10] <= soc_k7ddrphy_bitslip10_o[4]; - soc_k7ddrphy_dfi_p2_rddata[42] <= soc_k7ddrphy_bitslip10_o[5]; - soc_k7ddrphy_dfi_p2_rddata[11] <= soc_k7ddrphy_bitslip11_o[4]; - soc_k7ddrphy_dfi_p2_rddata[43] <= soc_k7ddrphy_bitslip11_o[5]; - soc_k7ddrphy_dfi_p2_rddata[12] <= soc_k7ddrphy_bitslip12_o[4]; - soc_k7ddrphy_dfi_p2_rddata[44] <= soc_k7ddrphy_bitslip12_o[5]; - soc_k7ddrphy_dfi_p2_rddata[13] <= soc_k7ddrphy_bitslip13_o[4]; - soc_k7ddrphy_dfi_p2_rddata[45] <= soc_k7ddrphy_bitslip13_o[5]; - soc_k7ddrphy_dfi_p2_rddata[14] <= soc_k7ddrphy_bitslip14_o[4]; - soc_k7ddrphy_dfi_p2_rddata[46] <= soc_k7ddrphy_bitslip14_o[5]; - soc_k7ddrphy_dfi_p2_rddata[15] <= soc_k7ddrphy_bitslip15_o[4]; - soc_k7ddrphy_dfi_p2_rddata[47] <= soc_k7ddrphy_bitslip15_o[5]; - soc_k7ddrphy_dfi_p2_rddata[16] <= soc_k7ddrphy_bitslip16_o[4]; - soc_k7ddrphy_dfi_p2_rddata[48] <= soc_k7ddrphy_bitslip16_o[5]; - soc_k7ddrphy_dfi_p2_rddata[17] <= soc_k7ddrphy_bitslip17_o[4]; - soc_k7ddrphy_dfi_p2_rddata[49] <= soc_k7ddrphy_bitslip17_o[5]; - soc_k7ddrphy_dfi_p2_rddata[18] <= soc_k7ddrphy_bitslip18_o[4]; - soc_k7ddrphy_dfi_p2_rddata[50] <= soc_k7ddrphy_bitslip18_o[5]; - soc_k7ddrphy_dfi_p2_rddata[19] <= soc_k7ddrphy_bitslip19_o[4]; - soc_k7ddrphy_dfi_p2_rddata[51] <= soc_k7ddrphy_bitslip19_o[5]; - soc_k7ddrphy_dfi_p2_rddata[20] <= soc_k7ddrphy_bitslip20_o[4]; - soc_k7ddrphy_dfi_p2_rddata[52] <= soc_k7ddrphy_bitslip20_o[5]; - soc_k7ddrphy_dfi_p2_rddata[21] <= soc_k7ddrphy_bitslip21_o[4]; - soc_k7ddrphy_dfi_p2_rddata[53] <= soc_k7ddrphy_bitslip21_o[5]; - soc_k7ddrphy_dfi_p2_rddata[22] <= soc_k7ddrphy_bitslip22_o[4]; - soc_k7ddrphy_dfi_p2_rddata[54] <= soc_k7ddrphy_bitslip22_o[5]; - soc_k7ddrphy_dfi_p2_rddata[23] <= soc_k7ddrphy_bitslip23_o[4]; - soc_k7ddrphy_dfi_p2_rddata[55] <= soc_k7ddrphy_bitslip23_o[5]; - soc_k7ddrphy_dfi_p2_rddata[24] <= soc_k7ddrphy_bitslip24_o[4]; - soc_k7ddrphy_dfi_p2_rddata[56] <= soc_k7ddrphy_bitslip24_o[5]; - soc_k7ddrphy_dfi_p2_rddata[25] <= soc_k7ddrphy_bitslip25_o[4]; - soc_k7ddrphy_dfi_p2_rddata[57] <= soc_k7ddrphy_bitslip25_o[5]; - soc_k7ddrphy_dfi_p2_rddata[26] <= soc_k7ddrphy_bitslip26_o[4]; - soc_k7ddrphy_dfi_p2_rddata[58] <= soc_k7ddrphy_bitslip26_o[5]; - soc_k7ddrphy_dfi_p2_rddata[27] <= soc_k7ddrphy_bitslip27_o[4]; - soc_k7ddrphy_dfi_p2_rddata[59] <= soc_k7ddrphy_bitslip27_o[5]; - soc_k7ddrphy_dfi_p2_rddata[28] <= soc_k7ddrphy_bitslip28_o[4]; - soc_k7ddrphy_dfi_p2_rddata[60] <= soc_k7ddrphy_bitslip28_o[5]; - soc_k7ddrphy_dfi_p2_rddata[29] <= soc_k7ddrphy_bitslip29_o[4]; - soc_k7ddrphy_dfi_p2_rddata[61] <= soc_k7ddrphy_bitslip29_o[5]; - soc_k7ddrphy_dfi_p2_rddata[30] <= soc_k7ddrphy_bitslip30_o[4]; - soc_k7ddrphy_dfi_p2_rddata[62] <= soc_k7ddrphy_bitslip30_o[5]; - soc_k7ddrphy_dfi_p2_rddata[31] <= soc_k7ddrphy_bitslip31_o[4]; - soc_k7ddrphy_dfi_p2_rddata[63] <= soc_k7ddrphy_bitslip31_o[5]; + main_k7ddrphy_bitslip00 <= 8'd0; + case (main_k7ddrphy_bitslip0_value0) + 1'd0: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_6 = dummy_s; // synthesis translate_on @@ -2405,145 +2836,105 @@ end reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dfi_p3_rddata <= 64'd0; - soc_k7ddrphy_dfi_p3_rddata[0] <= soc_k7ddrphy_bitslip0_o[6]; - soc_k7ddrphy_dfi_p3_rddata[32] <= soc_k7ddrphy_bitslip0_o[7]; - soc_k7ddrphy_dfi_p3_rddata[1] <= soc_k7ddrphy_bitslip1_o[6]; - soc_k7ddrphy_dfi_p3_rddata[33] <= soc_k7ddrphy_bitslip1_o[7]; - soc_k7ddrphy_dfi_p3_rddata[2] <= soc_k7ddrphy_bitslip2_o[6]; - soc_k7ddrphy_dfi_p3_rddata[34] <= soc_k7ddrphy_bitslip2_o[7]; - soc_k7ddrphy_dfi_p3_rddata[3] <= soc_k7ddrphy_bitslip3_o[6]; - soc_k7ddrphy_dfi_p3_rddata[35] <= soc_k7ddrphy_bitslip3_o[7]; - soc_k7ddrphy_dfi_p3_rddata[4] <= soc_k7ddrphy_bitslip4_o[6]; - soc_k7ddrphy_dfi_p3_rddata[36] <= soc_k7ddrphy_bitslip4_o[7]; - soc_k7ddrphy_dfi_p3_rddata[5] <= soc_k7ddrphy_bitslip5_o[6]; - soc_k7ddrphy_dfi_p3_rddata[37] <= soc_k7ddrphy_bitslip5_o[7]; - soc_k7ddrphy_dfi_p3_rddata[6] <= soc_k7ddrphy_bitslip6_o[6]; - soc_k7ddrphy_dfi_p3_rddata[38] <= soc_k7ddrphy_bitslip6_o[7]; - soc_k7ddrphy_dfi_p3_rddata[7] <= soc_k7ddrphy_bitslip7_o[6]; - soc_k7ddrphy_dfi_p3_rddata[39] <= soc_k7ddrphy_bitslip7_o[7]; - soc_k7ddrphy_dfi_p3_rddata[8] <= soc_k7ddrphy_bitslip8_o[6]; - soc_k7ddrphy_dfi_p3_rddata[40] <= soc_k7ddrphy_bitslip8_o[7]; - soc_k7ddrphy_dfi_p3_rddata[9] <= soc_k7ddrphy_bitslip9_o[6]; - soc_k7ddrphy_dfi_p3_rddata[41] <= soc_k7ddrphy_bitslip9_o[7]; - soc_k7ddrphy_dfi_p3_rddata[10] <= soc_k7ddrphy_bitslip10_o[6]; - soc_k7ddrphy_dfi_p3_rddata[42] <= soc_k7ddrphy_bitslip10_o[7]; - soc_k7ddrphy_dfi_p3_rddata[11] <= soc_k7ddrphy_bitslip11_o[6]; - soc_k7ddrphy_dfi_p3_rddata[43] <= soc_k7ddrphy_bitslip11_o[7]; - soc_k7ddrphy_dfi_p3_rddata[12] <= soc_k7ddrphy_bitslip12_o[6]; - soc_k7ddrphy_dfi_p3_rddata[44] <= soc_k7ddrphy_bitslip12_o[7]; - soc_k7ddrphy_dfi_p3_rddata[13] <= soc_k7ddrphy_bitslip13_o[6]; - soc_k7ddrphy_dfi_p3_rddata[45] <= soc_k7ddrphy_bitslip13_o[7]; - soc_k7ddrphy_dfi_p3_rddata[14] <= soc_k7ddrphy_bitslip14_o[6]; - soc_k7ddrphy_dfi_p3_rddata[46] <= soc_k7ddrphy_bitslip14_o[7]; - soc_k7ddrphy_dfi_p3_rddata[15] <= soc_k7ddrphy_bitslip15_o[6]; - soc_k7ddrphy_dfi_p3_rddata[47] <= soc_k7ddrphy_bitslip15_o[7]; - soc_k7ddrphy_dfi_p3_rddata[16] <= soc_k7ddrphy_bitslip16_o[6]; - soc_k7ddrphy_dfi_p3_rddata[48] <= soc_k7ddrphy_bitslip16_o[7]; - soc_k7ddrphy_dfi_p3_rddata[17] <= soc_k7ddrphy_bitslip17_o[6]; - soc_k7ddrphy_dfi_p3_rddata[49] <= soc_k7ddrphy_bitslip17_o[7]; - soc_k7ddrphy_dfi_p3_rddata[18] <= soc_k7ddrphy_bitslip18_o[6]; - soc_k7ddrphy_dfi_p3_rddata[50] <= soc_k7ddrphy_bitslip18_o[7]; - soc_k7ddrphy_dfi_p3_rddata[19] <= soc_k7ddrphy_bitslip19_o[6]; - soc_k7ddrphy_dfi_p3_rddata[51] <= soc_k7ddrphy_bitslip19_o[7]; - soc_k7ddrphy_dfi_p3_rddata[20] <= soc_k7ddrphy_bitslip20_o[6]; - soc_k7ddrphy_dfi_p3_rddata[52] <= soc_k7ddrphy_bitslip20_o[7]; - soc_k7ddrphy_dfi_p3_rddata[21] <= soc_k7ddrphy_bitslip21_o[6]; - soc_k7ddrphy_dfi_p3_rddata[53] <= soc_k7ddrphy_bitslip21_o[7]; - soc_k7ddrphy_dfi_p3_rddata[22] <= soc_k7ddrphy_bitslip22_o[6]; - soc_k7ddrphy_dfi_p3_rddata[54] <= soc_k7ddrphy_bitslip22_o[7]; - soc_k7ddrphy_dfi_p3_rddata[23] <= soc_k7ddrphy_bitslip23_o[6]; - soc_k7ddrphy_dfi_p3_rddata[55] <= soc_k7ddrphy_bitslip23_o[7]; - soc_k7ddrphy_dfi_p3_rddata[24] <= soc_k7ddrphy_bitslip24_o[6]; - soc_k7ddrphy_dfi_p3_rddata[56] <= soc_k7ddrphy_bitslip24_o[7]; - soc_k7ddrphy_dfi_p3_rddata[25] <= soc_k7ddrphy_bitslip25_o[6]; - soc_k7ddrphy_dfi_p3_rddata[57] <= soc_k7ddrphy_bitslip25_o[7]; - soc_k7ddrphy_dfi_p3_rddata[26] <= soc_k7ddrphy_bitslip26_o[6]; - soc_k7ddrphy_dfi_p3_rddata[58] <= soc_k7ddrphy_bitslip26_o[7]; - soc_k7ddrphy_dfi_p3_rddata[27] <= soc_k7ddrphy_bitslip27_o[6]; - soc_k7ddrphy_dfi_p3_rddata[59] <= soc_k7ddrphy_bitslip27_o[7]; - soc_k7ddrphy_dfi_p3_rddata[28] <= soc_k7ddrphy_bitslip28_o[6]; - soc_k7ddrphy_dfi_p3_rddata[60] <= soc_k7ddrphy_bitslip28_o[7]; - soc_k7ddrphy_dfi_p3_rddata[29] <= soc_k7ddrphy_bitslip29_o[6]; - soc_k7ddrphy_dfi_p3_rddata[61] <= soc_k7ddrphy_bitslip29_o[7]; - soc_k7ddrphy_dfi_p3_rddata[30] <= soc_k7ddrphy_bitslip30_o[6]; - soc_k7ddrphy_dfi_p3_rddata[62] <= soc_k7ddrphy_bitslip30_o[7]; - soc_k7ddrphy_dfi_p3_rddata[31] <= soc_k7ddrphy_bitslip31_o[6]; - soc_k7ddrphy_dfi_p3_rddata[63] <= soc_k7ddrphy_bitslip31_o[7]; + main_k7ddrphy_bitslip10 <= 8'd0; + case (main_k7ddrphy_bitslip1_value0) + 1'd0: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_7 = dummy_s; // synthesis translate_on end -assign soc_k7ddrphy_bitslip1_i = soc_k7ddrphy_dq_i_data1; -assign soc_k7ddrphy_bitslip2_i = soc_k7ddrphy_dq_i_data2; -assign soc_k7ddrphy_bitslip3_i = soc_k7ddrphy_dq_i_data3; -assign soc_k7ddrphy_bitslip4_i = soc_k7ddrphy_dq_i_data4; -assign soc_k7ddrphy_bitslip5_i = soc_k7ddrphy_dq_i_data5; -assign soc_k7ddrphy_bitslip6_i = soc_k7ddrphy_dq_i_data6; -assign soc_k7ddrphy_bitslip7_i = soc_k7ddrphy_dq_i_data7; -assign soc_k7ddrphy_bitslip8_i = soc_k7ddrphy_dq_i_data8; -assign soc_k7ddrphy_bitslip9_i = soc_k7ddrphy_dq_i_data9; -assign soc_k7ddrphy_bitslip10_i = soc_k7ddrphy_dq_i_data10; -assign soc_k7ddrphy_bitslip11_i = soc_k7ddrphy_dq_i_data11; -assign soc_k7ddrphy_bitslip12_i = soc_k7ddrphy_dq_i_data12; -assign soc_k7ddrphy_bitslip13_i = soc_k7ddrphy_dq_i_data13; -assign soc_k7ddrphy_bitslip14_i = soc_k7ddrphy_dq_i_data14; -assign soc_k7ddrphy_bitslip15_i = soc_k7ddrphy_dq_i_data15; -assign soc_k7ddrphy_bitslip16_i = soc_k7ddrphy_dq_i_data16; -assign soc_k7ddrphy_bitslip17_i = soc_k7ddrphy_dq_i_data17; -assign soc_k7ddrphy_bitslip18_i = soc_k7ddrphy_dq_i_data18; -assign soc_k7ddrphy_bitslip19_i = soc_k7ddrphy_dq_i_data19; -assign soc_k7ddrphy_bitslip20_i = soc_k7ddrphy_dq_i_data20; -assign soc_k7ddrphy_bitslip21_i = soc_k7ddrphy_dq_i_data21; -assign soc_k7ddrphy_bitslip22_i = soc_k7ddrphy_dq_i_data22; -assign soc_k7ddrphy_bitslip23_i = soc_k7ddrphy_dq_i_data23; -assign soc_k7ddrphy_bitslip24_i = soc_k7ddrphy_dq_i_data24; -assign soc_k7ddrphy_bitslip25_i = soc_k7ddrphy_dq_i_data25; -assign soc_k7ddrphy_bitslip26_i = soc_k7ddrphy_dq_i_data26; -assign soc_k7ddrphy_bitslip27_i = soc_k7ddrphy_dq_i_data27; -assign soc_k7ddrphy_bitslip28_i = soc_k7ddrphy_dq_i_data28; -assign soc_k7ddrphy_bitslip29_i = soc_k7ddrphy_dq_i_data29; -assign soc_k7ddrphy_bitslip30_i = soc_k7ddrphy_dq_i_data30; -assign soc_k7ddrphy_bitslip31_i = soc_k7ddrphy_dq_i_data31; -assign soc_k7ddrphy_rddata_en = {soc_k7ddrphy_rddata_en_last, soc_k7ddrphy_dfi_p2_rddata_en}; -assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p2_wrdata_en}; -assign soc_k7ddrphy_dq_oe = soc_k7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dqs_oe <= 1'd0; - if (soc_k7ddrphy_wlevel_en_storage) begin - soc_k7ddrphy_dqs_oe <= 1'd1; - end else begin - soc_k7ddrphy_dqs_oe <= soc_k7ddrphy_dq_oe; - end + main_k7ddrphy_bitslip20 <= 8'd0; + case (main_k7ddrphy_bitslip2_value0) + 1'd0: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_8 = dummy_s; // synthesis translate_on end -assign soc_k7ddrphy_dqspattern0 = (soc_k7ddrphy_wrdata_en[1] & (~soc_k7ddrphy_wrdata_en[2])); -assign soc_k7ddrphy_dqspattern1 = (soc_k7ddrphy_wrdata_en[3] & (~soc_k7ddrphy_wrdata_en[2])); // synthesis translate_off reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_k7ddrphy_dqspattern_o <= 8'd0; - soc_k7ddrphy_dqspattern_o <= 7'd85; - if (soc_k7ddrphy_dqspattern0) begin - soc_k7ddrphy_dqspattern_o <= 5'd21; - end - if (soc_k7ddrphy_dqspattern1) begin - soc_k7ddrphy_dqspattern_o <= 7'd84; - end - if (soc_k7ddrphy_wlevel_en_storage) begin - soc_k7ddrphy_dqspattern_o <= 1'd0; - if (soc_k7ddrphy_wlevel_strobe_re) begin - soc_k7ddrphy_dqspattern_o <= 1'd1; + main_k7ddrphy_bitslip30 <= 8'd0; + case (main_k7ddrphy_bitslip3_value0) + 1'd0: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[8:1]; end - end + 1'd1: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_9 = dummy_s; // synthesis translate_on @@ -2553,55 +2944,31 @@ end reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip0_o <= 8'd0; - case (soc_k7ddrphy_bitslip0_value) + main_k7ddrphy_bitslip01 <= 8'd0; + case (main_k7ddrphy_bitslip0_value1) 1'd0: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[7:0]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[8:1]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[9:2]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[10:3]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[11:4]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[12:5]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[13:6]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[22:15]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8]; end endcase // synthesis translate_off @@ -2613,55 +2980,31 @@ end reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip1_o <= 8'd0; - case (soc_k7ddrphy_bitslip1_value) + main_k7ddrphy_bitslip11 <= 8'd0; + case (main_k7ddrphy_bitslip1_value1) 1'd0: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[7:0]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[8:1]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[9:2]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[10:3]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[11:4]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[12:5]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[13:6]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[22:15]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8]; end endcase // synthesis translate_off @@ -2673,55 +3016,31 @@ end reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip2_o <= 8'd0; - case (soc_k7ddrphy_bitslip2_value) + main_k7ddrphy_bitslip21 <= 8'd0; + case (main_k7ddrphy_bitslip2_value1) 1'd0: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[7:0]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[8:1]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[9:2]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[10:3]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[11:4]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[12:5]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[13:6]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[22:15]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8]; end endcase // synthesis translate_off @@ -2733,55 +3052,31 @@ end reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip3_o <= 8'd0; - case (soc_k7ddrphy_bitslip3_value) + main_k7ddrphy_bitslip31 <= 8'd0; + case (main_k7ddrphy_bitslip3_value1) 1'd0: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[7:0]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[8:1]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[9:2]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[10:3]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[11:4]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[12:5]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[13:6]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[22:15]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8]; end endcase // synthesis translate_off @@ -2793,55 +3088,31 @@ end reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip4_o <= 8'd0; - case (soc_k7ddrphy_bitslip4_value) + main_k7ddrphy_bitslip02 <= 8'd0; + case (main_k7ddrphy_bitslip0_value2) 1'd0: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[7:0]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[8:1]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[9:2]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[10:3]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[11:4]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[12:5]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[13:6]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[22:15]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8]; end endcase // synthesis translate_off @@ -2853,55 +3124,31 @@ end reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip5_o <= 8'd0; - case (soc_k7ddrphy_bitslip5_value) + main_k7ddrphy_bitslip04 <= 8'd0; + case (main_k7ddrphy_bitslip0_value3) 1'd0: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[7:0]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[8:1]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[9:2]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[10:3]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[11:4]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[12:5]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[13:6]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[22:15]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8]; end endcase // synthesis translate_off @@ -2913,55 +3160,31 @@ end reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip6_o <= 8'd0; - case (soc_k7ddrphy_bitslip6_value) + main_k7ddrphy_bitslip12 <= 8'd0; + case (main_k7ddrphy_bitslip1_value2) 1'd0: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[7:0]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[8:1]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[9:2]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[10:3]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[11:4]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[12:5]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[13:6]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[22:15]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8]; end endcase // synthesis translate_off @@ -2973,55 +3196,31 @@ end reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip7_o <= 8'd0; - case (soc_k7ddrphy_bitslip7_value) + main_k7ddrphy_bitslip14 <= 8'd0; + case (main_k7ddrphy_bitslip1_value3) 1'd0: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[7:0]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[8:1]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[9:2]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[10:3]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[11:4]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[12:5]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[13:6]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[22:15]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8]; end endcase // synthesis translate_off @@ -3033,55 +3232,31 @@ end reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip8_o <= 8'd0; - case (soc_k7ddrphy_bitslip8_value) + main_k7ddrphy_bitslip22 <= 8'd0; + case (main_k7ddrphy_bitslip2_value2) 1'd0: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[7:0]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[8:1]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[9:2]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[10:3]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[11:4]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[12:5]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[13:6]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[22:15]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8]; end endcase // synthesis translate_off @@ -3093,55 +3268,31 @@ end reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip9_o <= 8'd0; - case (soc_k7ddrphy_bitslip9_value) + main_k7ddrphy_bitslip24 <= 8'd0; + case (main_k7ddrphy_bitslip2_value3) 1'd0: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[7:0]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[8:1]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[9:2]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[10:3]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[11:4]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[12:5]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[13:6]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[22:15]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8]; end endcase // synthesis translate_off @@ -3153,55 +3304,31 @@ end reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip10_o <= 8'd0; - case (soc_k7ddrphy_bitslip10_value) + main_k7ddrphy_bitslip32 <= 8'd0; + case (main_k7ddrphy_bitslip3_value2) 1'd0: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[7:0]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[8:1]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[9:2]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[10:3]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[11:4]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[12:5]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[13:6]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[22:15]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8]; end endcase // synthesis translate_off @@ -3213,55 +3340,31 @@ end reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip11_o <= 8'd0; - case (soc_k7ddrphy_bitslip11_value) + main_k7ddrphy_bitslip34 <= 8'd0; + case (main_k7ddrphy_bitslip3_value3) 1'd0: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[7:0]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[8:1]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[9:2]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[10:3]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[11:4]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[12:5]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[13:6]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[22:15]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8]; end endcase // synthesis translate_off @@ -3273,55 +3376,31 @@ end reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip12_o <= 8'd0; - case (soc_k7ddrphy_bitslip12_value) + main_k7ddrphy_bitslip40 <= 8'd0; + case (main_k7ddrphy_bitslip4_value0) 1'd0: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[7:0]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[8:1]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[9:2]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[10:3]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[11:4]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[12:5]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[13:6]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[22:15]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8]; end endcase // synthesis translate_off @@ -3333,55 +3412,31 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip13_o <= 8'd0; - case (soc_k7ddrphy_bitslip13_value) + main_k7ddrphy_bitslip42 <= 8'd0; + case (main_k7ddrphy_bitslip4_value1) 1'd0: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[7:0]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[8:1]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[9:2]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[10:3]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[11:4]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[12:5]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[13:6]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[22:15]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8]; end endcase // synthesis translate_off @@ -3393,55 +3448,31 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip14_o <= 8'd0; - case (soc_k7ddrphy_bitslip14_value) + main_k7ddrphy_bitslip50 <= 8'd0; + case (main_k7ddrphy_bitslip5_value0) 1'd0: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[7:0]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[8:1]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[9:2]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[10:3]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[11:4]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[12:5]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[13:6]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[22:15]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8]; end endcase // synthesis translate_off @@ -3453,55 +3484,31 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip15_o <= 8'd0; - case (soc_k7ddrphy_bitslip15_value) + main_k7ddrphy_bitslip52 <= 8'd0; + case (main_k7ddrphy_bitslip5_value1) 1'd0: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[7:0]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[8:1]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[9:2]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[10:3]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[11:4]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[12:5]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[13:6]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[22:15]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8]; end endcase // synthesis translate_off @@ -3513,55 +3520,31 @@ end reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip16_o <= 8'd0; - case (soc_k7ddrphy_bitslip16_value) + main_k7ddrphy_bitslip60 <= 8'd0; + case (main_k7ddrphy_bitslip6_value0) 1'd0: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[7:0]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[8:1]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[9:2]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[10:3]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[11:4]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[12:5]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[13:6]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[22:15]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8]; end endcase // synthesis translate_off @@ -3573,55 +3556,31 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip17_o <= 8'd0; - case (soc_k7ddrphy_bitslip17_value) + main_k7ddrphy_bitslip62 <= 8'd0; + case (main_k7ddrphy_bitslip6_value1) 1'd0: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[7:0]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[8:1]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[9:2]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[10:3]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[11:4]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[12:5]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[13:6]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[22:15]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8]; end endcase // synthesis translate_off @@ -3633,55 +3592,31 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip18_o <= 8'd0; - case (soc_k7ddrphy_bitslip18_value) + main_k7ddrphy_bitslip70 <= 8'd0; + case (main_k7ddrphy_bitslip7_value0) 1'd0: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[7:0]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[8:1]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[9:2]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[10:3]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[11:4]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[12:5]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[13:6]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[22:15]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8]; end endcase // synthesis translate_off @@ -3693,55 +3628,31 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip19_o <= 8'd0; - case (soc_k7ddrphy_bitslip19_value) + main_k7ddrphy_bitslip72 <= 8'd0; + case (main_k7ddrphy_bitslip7_value1) 1'd0: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[7:0]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[8:1]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[9:2]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[10:3]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[11:4]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[12:5]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[13:6]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[22:15]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8]; end endcase // synthesis translate_off @@ -3753,55 +3664,31 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip20_o <= 8'd0; - case (soc_k7ddrphy_bitslip20_value) + main_k7ddrphy_bitslip80 <= 8'd0; + case (main_k7ddrphy_bitslip8_value0) 1'd0: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[7:0]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[8:1]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[9:2]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[10:3]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[11:4]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[12:5]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[13:6]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[22:15]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8]; end endcase // synthesis translate_off @@ -3813,55 +3700,31 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip21_o <= 8'd0; - case (soc_k7ddrphy_bitslip21_value) + main_k7ddrphy_bitslip82 <= 8'd0; + case (main_k7ddrphy_bitslip8_value1) 1'd0: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[7:0]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[8:1]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[9:2]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[10:3]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[11:4]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[12:5]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[13:6]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[22:15]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8]; end endcase // synthesis translate_off @@ -3873,55 +3736,31 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip22_o <= 8'd0; - case (soc_k7ddrphy_bitslip22_value) + main_k7ddrphy_bitslip90 <= 8'd0; + case (main_k7ddrphy_bitslip9_value0) 1'd0: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[7:0]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[8:1]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[9:2]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[10:3]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[11:4]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[12:5]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[13:6]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[22:15]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8]; end endcase // synthesis translate_off @@ -3933,55 +3772,31 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip23_o <= 8'd0; - case (soc_k7ddrphy_bitslip23_value) + main_k7ddrphy_bitslip92 <= 8'd0; + case (main_k7ddrphy_bitslip9_value1) 1'd0: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[7:0]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[8:1]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[9:2]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[10:3]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[11:4]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[12:5]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[13:6]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[22:15]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8]; end endcase // synthesis translate_off @@ -3993,55 +3808,31 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip24_o <= 8'd0; - case (soc_k7ddrphy_bitslip24_value) + main_k7ddrphy_bitslip100 <= 8'd0; + case (main_k7ddrphy_bitslip10_value0) 1'd0: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[7:0]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[8:1]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[9:2]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[10:3]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[11:4]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[12:5]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[13:6]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[22:15]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8]; end endcase // synthesis translate_off @@ -4053,55 +3844,31 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip25_o <= 8'd0; - case (soc_k7ddrphy_bitslip25_value) + main_k7ddrphy_bitslip102 <= 8'd0; + case (main_k7ddrphy_bitslip10_value1) 1'd0: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[7:0]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[8:1]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[9:2]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[10:3]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[11:4]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[12:5]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[13:6]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[22:15]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8]; end endcase // synthesis translate_off @@ -4113,55 +3880,31 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip26_o <= 8'd0; - case (soc_k7ddrphy_bitslip26_value) + main_k7ddrphy_bitslip110 <= 8'd0; + case (main_k7ddrphy_bitslip11_value0) 1'd0: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[7:0]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[8:1]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[9:2]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[10:3]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[11:4]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[12:5]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[13:6]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[22:15]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8]; end endcase // synthesis translate_off @@ -4173,55 +3916,31 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip27_o <= 8'd0; - case (soc_k7ddrphy_bitslip27_value) + main_k7ddrphy_bitslip112 <= 8'd0; + case (main_k7ddrphy_bitslip11_value1) 1'd0: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[7:0]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[8:1]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[9:2]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[10:3]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[11:4]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[12:5]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[13:6]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[22:15]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8]; end endcase // synthesis translate_off @@ -4233,55 +3952,31 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip28_o <= 8'd0; - case (soc_k7ddrphy_bitslip28_value) + main_k7ddrphy_bitslip120 <= 8'd0; + case (main_k7ddrphy_bitslip12_value0) 1'd0: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[7:0]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[8:1]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[9:2]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[10:3]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[11:4]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[12:5]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[13:6]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[22:15]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8]; end endcase // synthesis translate_off @@ -4293,55 +3988,31 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip29_o <= 8'd0; - case (soc_k7ddrphy_bitslip29_value) + main_k7ddrphy_bitslip122 <= 8'd0; + case (main_k7ddrphy_bitslip12_value1) 1'd0: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[7:0]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[8:1]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[9:2]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[10:3]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[11:4]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[12:5]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[13:6]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[22:15]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8]; end endcase // synthesis translate_off @@ -4353,55 +4024,31 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip30_o <= 8'd0; - case (soc_k7ddrphy_bitslip30_value) + main_k7ddrphy_bitslip130 <= 8'd0; + case (main_k7ddrphy_bitslip13_value0) 1'd0: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[7:0]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[8:1]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[9:2]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[10:3]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[11:4]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[12:5]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[13:6]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[22:15]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8]; end endcase // synthesis translate_off @@ -4413,200 +4060,69 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - soc_k7ddrphy_bitslip31_o <= 8'd0; - case (soc_k7ddrphy_bitslip31_value) + main_k7ddrphy_bitslip132 <= 8'd0; + case (main_k7ddrphy_bitslip13_value1) 1'd0: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[7:0]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[8:1]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[9:2]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[10:3]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[11:4]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[12:5]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[13:6]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[14:7]; - end - 4'd8: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[15:8]; - end - 4'd9: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[16:9]; - end - 4'd10: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[17:10]; - end - 4'd11: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[18:11]; - end - 4'd12: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[19:12]; - end - 4'd13: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[20:13]; - end - 4'd14: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[21:14]; - end - 4'd15: begin - soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[22:15]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8]; end endcase // synthesis translate_off dummy_d_41 = dummy_s; // synthesis translate_on end -assign soc_k7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; -assign soc_k7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; -assign soc_k7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; -assign soc_k7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; -assign soc_k7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; -assign soc_k7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; -assign soc_k7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; -assign soc_k7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; -assign soc_k7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; -assign soc_k7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; -assign soc_k7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; -assign soc_k7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; -assign soc_k7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; -assign soc_k7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; -assign soc_litedramcore_master_p0_rddata = soc_k7ddrphy_dfi_p0_rddata; -assign soc_litedramcore_master_p0_rddata_valid = soc_k7ddrphy_dfi_p0_rddata_valid; -assign soc_k7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; -assign soc_k7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; -assign soc_k7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; -assign soc_k7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; -assign soc_k7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; -assign soc_k7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; -assign soc_k7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; -assign soc_k7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; -assign soc_k7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; -assign soc_k7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; -assign soc_k7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; -assign soc_k7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; -assign soc_k7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; -assign soc_k7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; -assign soc_litedramcore_master_p1_rddata = soc_k7ddrphy_dfi_p1_rddata; -assign soc_litedramcore_master_p1_rddata_valid = soc_k7ddrphy_dfi_p1_rddata_valid; -assign soc_k7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; -assign soc_k7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; -assign soc_k7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; -assign soc_k7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; -assign soc_k7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; -assign soc_k7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; -assign soc_k7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; -assign soc_k7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; -assign soc_k7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; -assign soc_k7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; -assign soc_k7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; -assign soc_k7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; -assign soc_k7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; -assign soc_k7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; -assign soc_litedramcore_master_p2_rddata = soc_k7ddrphy_dfi_p2_rddata; -assign soc_litedramcore_master_p2_rddata_valid = soc_k7ddrphy_dfi_p2_rddata_valid; -assign soc_k7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; -assign soc_k7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; -assign soc_k7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; -assign soc_k7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; -assign soc_k7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; -assign soc_k7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; -assign soc_k7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; -assign soc_k7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; -assign soc_k7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; -assign soc_k7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; -assign soc_k7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; -assign soc_k7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; -assign soc_k7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; -assign soc_k7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; -assign soc_litedramcore_master_p3_rddata = soc_k7ddrphy_dfi_p3_rddata; -assign soc_litedramcore_master_p3_rddata_valid = soc_k7ddrphy_dfi_p3_rddata_valid; -assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; -assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; -assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; -assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; -assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; -assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; -assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; -assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; -assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; -assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; -assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; -assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; -assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; -assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; -assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; -assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; -assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; -assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; -assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; -assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; -assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; -assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; -assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; -assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; -assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; -assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; -assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; -assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; -assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; -assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; -assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; -assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; -assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; -assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; -assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; -assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; -assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; -assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; -assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; -assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; -assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; -assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; -assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; -assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; -assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; -assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; -assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; -assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; -assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; -assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; -assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; -assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; -assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; -assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; -assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; -assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; -assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; -assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; -assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; -assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; -assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; -assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; -assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; -assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_42; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; - end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; - end + main_k7ddrphy_bitslip140 <= 8'd0; + case (main_k7ddrphy_bitslip14_value0) + 1'd0: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_42 = dummy_s; // synthesis translate_on @@ -4616,12 +4132,33 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; - end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; - end + main_k7ddrphy_bitslip142 <= 8'd0; + case (main_k7ddrphy_bitslip14_value1) + 1'd0: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_43 = dummy_s; // synthesis translate_on @@ -4631,12 +4168,33 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; - end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; - end + main_k7ddrphy_bitslip150 <= 8'd0; + case (main_k7ddrphy_bitslip15_value0) + 1'd0: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_44 = dummy_s; // synthesis translate_on @@ -4646,12 +4204,33 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; - end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; - end + main_k7ddrphy_bitslip152 <= 8'd0; + case (main_k7ddrphy_bitslip15_value1) + 1'd0: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_45 = dummy_s; // synthesis translate_on @@ -4661,12 +4240,33 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; - end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; - end + main_k7ddrphy_bitslip160 <= 8'd0; + case (main_k7ddrphy_bitslip16_value0) + 1'd0: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_46 = dummy_s; // synthesis translate_on @@ -4676,11 +4276,33 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; - end else begin - end + main_k7ddrphy_bitslip162 <= 8'd0; + case (main_k7ddrphy_bitslip16_value1) + 1'd0: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_47 = dummy_s; // synthesis translate_on @@ -4690,12 +4312,33 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; - end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; - end + main_k7ddrphy_bitslip170 <= 8'd0; + case (main_k7ddrphy_bitslip17_value0) + 1'd0: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_48 = dummy_s; // synthesis translate_on @@ -4705,11 +4348,33 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end else begin - end + main_k7ddrphy_bitslip172 <= 8'd0; + case (main_k7ddrphy_bitslip17_value1) + 1'd0: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_49 = dummy_s; // synthesis translate_on @@ -4719,12 +4384,33 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; - end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; - end + main_k7ddrphy_bitslip180 <= 8'd0; + case (main_k7ddrphy_bitslip18_value0) + 1'd0: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_50 = dummy_s; // synthesis translate_on @@ -4734,12 +4420,33 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; - end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; - end + main_k7ddrphy_bitslip182 <= 8'd0; + case (main_k7ddrphy_bitslip18_value1) + 1'd0: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_51 = dummy_s; // synthesis translate_on @@ -4749,12 +4456,33 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; - end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; - end + main_k7ddrphy_bitslip190 <= 8'd0; + case (main_k7ddrphy_bitslip19_value0) + 1'd0: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_52 = dummy_s; // synthesis translate_on @@ -4764,12 +4492,33 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; - end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; - end + main_k7ddrphy_bitslip192 <= 8'd0; + case (main_k7ddrphy_bitslip19_value1) + 1'd0: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_53 = dummy_s; // synthesis translate_on @@ -4779,12 +4528,33 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; - end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; - end + main_k7ddrphy_bitslip200 <= 8'd0; + case (main_k7ddrphy_bitslip20_value0) + 1'd0: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_54 = dummy_s; // synthesis translate_on @@ -4794,11 +4564,33 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; - end + main_k7ddrphy_bitslip202 <= 8'd0; + case (main_k7ddrphy_bitslip20_value1) + 1'd0: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_55 = dummy_s; // synthesis translate_on @@ -4808,12 +4600,33 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; - end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; - end + main_k7ddrphy_bitslip210 <= 8'd0; + case (main_k7ddrphy_bitslip21_value0) + 1'd0: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_56 = dummy_s; // synthesis translate_on @@ -4823,11 +4636,33 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; - end + main_k7ddrphy_bitslip212 <= 8'd0; + case (main_k7ddrphy_bitslip21_value1) + 1'd0: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_57 = dummy_s; // synthesis translate_on @@ -4837,27 +4672,69 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 8'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; - end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; - end -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on -always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; - end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; - end + main_k7ddrphy_bitslip220 <= 8'd0; + case (main_k7ddrphy_bitslip22_value0) + 1'd0: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8]; + end + endcase +// synthesis translate_off + dummy_d_58 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_59; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_bitslip222 <= 8'd0; + case (main_k7ddrphy_bitslip22_value1) + 1'd0: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_59 = dummy_s; // synthesis translate_on @@ -4867,12 +4744,33 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; - end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; - end + main_k7ddrphy_bitslip230 <= 8'd0; + case (main_k7ddrphy_bitslip23_value0) + 1'd0: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_60 = dummy_s; // synthesis translate_on @@ -4882,11 +4780,33 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; - end + main_k7ddrphy_bitslip232 <= 8'd0; + case (main_k7ddrphy_bitslip23_value1) + 1'd0: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_61 = dummy_s; // synthesis translate_on @@ -4896,12 +4816,33 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; - end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; - end + main_k7ddrphy_bitslip240 <= 8'd0; + case (main_k7ddrphy_bitslip24_value0) + 1'd0: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_62 = dummy_s; // synthesis translate_on @@ -4911,12 +4852,33 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; - end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; - end + main_k7ddrphy_bitslip242 <= 8'd0; + case (main_k7ddrphy_bitslip24_value1) + 1'd0: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_63 = dummy_s; // synthesis translate_on @@ -4926,12 +4888,33 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; - end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; - end + main_k7ddrphy_bitslip250 <= 8'd0; + case (main_k7ddrphy_bitslip25_value0) + 1'd0: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_64 = dummy_s; // synthesis translate_on @@ -4941,12 +4924,33 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; - end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; - end + main_k7ddrphy_bitslip252 <= 8'd0; + case (main_k7ddrphy_bitslip25_value1) + 1'd0: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_65 = dummy_s; // synthesis translate_on @@ -4956,11 +4960,33 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; - end else begin - end + main_k7ddrphy_bitslip260 <= 8'd0; + case (main_k7ddrphy_bitslip26_value0) + 1'd0: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_66 = dummy_s; // synthesis translate_on @@ -4970,12 +4996,33 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; - end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; - end + main_k7ddrphy_bitslip262 <= 8'd0; + case (main_k7ddrphy_bitslip26_value1) + 1'd0: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_67 = dummy_s; // synthesis translate_on @@ -4985,11 +5032,33 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; - end else begin - end + main_k7ddrphy_bitslip270 <= 8'd0; + case (main_k7ddrphy_bitslip27_value0) + 1'd0: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_68 = dummy_s; // synthesis translate_on @@ -4999,12 +5068,33 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; - end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; - end + main_k7ddrphy_bitslip272 <= 8'd0; + case (main_k7ddrphy_bitslip27_value1) + 1'd0: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_69 = dummy_s; // synthesis translate_on @@ -5014,11 +5104,33 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end + main_k7ddrphy_bitslip280 <= 8'd0; + case (main_k7ddrphy_bitslip28_value0) + 1'd0: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_70 = dummy_s; // synthesis translate_on @@ -5028,12 +5140,33 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; - end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; - end + main_k7ddrphy_bitslip282 <= 8'd0; + case (main_k7ddrphy_bitslip28_value1) + 1'd0: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_71 = dummy_s; // synthesis translate_on @@ -5043,12 +5176,33 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; - end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; - end + main_k7ddrphy_bitslip290 <= 8'd0; + case (main_k7ddrphy_bitslip29_value0) + 1'd0: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_72 = dummy_s; // synthesis translate_on @@ -5058,12 +5212,33 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; - end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; - end + main_k7ddrphy_bitslip292 <= 8'd0; + case (main_k7ddrphy_bitslip29_value1) + 1'd0: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_73 = dummy_s; // synthesis translate_on @@ -5073,12 +5248,33 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; - end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; - end + main_k7ddrphy_bitslip300 <= 8'd0; + case (main_k7ddrphy_bitslip30_value0) + 1'd0: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_74 = dummy_s; // synthesis translate_on @@ -5088,11 +5284,33 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; - end + main_k7ddrphy_bitslip302 <= 8'd0; + case (main_k7ddrphy_bitslip30_value1) + 1'd0: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_75 = dummy_s; // synthesis translate_on @@ -5102,12 +5320,33 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; - end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; - end + main_k7ddrphy_bitslip310 <= 8'd0; + case (main_k7ddrphy_bitslip31_value0) + 1'd0: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_76 = dummy_s; // synthesis translate_on @@ -5117,25 +5356,175 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; - end + main_k7ddrphy_bitslip312 <= 8'd0; + case (main_k7ddrphy_bitslip31_value1) + 1'd0: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[8:1]; + end + 1'd1: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[9:2]; + end + 2'd2: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[10:3]; + end + 2'd3: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[11:4]; + end + 3'd4: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[12:5]; + end + 3'd5: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[13:6]; + end + 3'd6: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[14:7]; + end + 3'd7: begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_77 = dummy_s; // synthesis translate_on end +assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_k7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_k7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_k7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_k7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_k7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_k7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_k7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_k7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_k7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_k7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_k7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_k7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_k7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_k7ddrphy_dfi_p0_rddata_valid; +assign main_k7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_k7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_k7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_k7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_k7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_k7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_k7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_k7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_k7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_k7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_k7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_k7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_k7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_k7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_k7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_k7ddrphy_dfi_p1_rddata_valid; +assign main_k7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_k7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_k7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_k7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_k7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_k7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_k7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_k7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_k7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_k7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_k7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_k7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_k7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_k7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_k7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_k7ddrphy_dfi_p2_rddata_valid; +assign main_k7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_k7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_k7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_k7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_k7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_k7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_k7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_k7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_k7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_k7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_k7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_k7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_k7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_k7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_k7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_k7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 8'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -5146,11 +5535,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -5161,11 +5550,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -5176,11 +5565,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -5191,11 +5580,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -5206,11 +5595,10 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + main_litedramcore_slave_p1_rddata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -5221,11 +5609,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -5236,9 +5624,9 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end // synthesis translate_off @@ -5250,11 +5638,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -5265,10 +5653,11 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end else begin + main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -5279,11 +5668,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -5294,11 +5683,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -5309,11 +5698,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + main_litedramcore_master_p1_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; + main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -5324,11 +5713,10 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + main_litedramcore_inti_p2_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -5339,11 +5727,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -5354,10 +5742,10 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata <= 64'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; + main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -5368,11 +5756,11 @@ end reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p1_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -5383,10 +5771,11 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end else begin - soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -5397,11 +5786,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 8'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -5412,11 +5801,11 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_97 = dummy_s; @@ -5427,11 +5816,11 @@ end reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -5442,11 +5831,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -5457,11 +5846,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -5472,11 +5861,10 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + main_litedramcore_slave_p2_rddata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -5487,11 +5875,11 @@ end reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -5502,9 +5890,9 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off @@ -5516,11 +5904,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; + main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -5531,10 +5919,11 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end else begin + main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -5545,11 +5934,11 @@ end reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -5560,11 +5949,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -5575,11 +5964,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + main_litedramcore_master_p2_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -5590,11 +5979,10 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + main_litedramcore_inti_p3_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -5605,11 +5993,11 @@ end reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata <= 64'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -5620,11 +6008,10 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -5635,11 +6022,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 8'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -5650,38 +6037,26 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; // synthesis translate_off reg dummy_d_114; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + main_litedramcore_master_p3_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end else begin - soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_114 = dummy_s; @@ -5692,11 +6067,11 @@ end reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_115 = dummy_s; @@ -5707,11 +6082,11 @@ end reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_116 = dummy_s; @@ -5722,32 +6097,26 @@ end reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; -assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; -assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); -assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); -assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; -assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_118 = dummy_s; @@ -5758,11 +6127,10 @@ end reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + main_litedramcore_slave_p3_rddata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_119 = dummy_s; @@ -5773,11 +6141,11 @@ end reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_inti_p1_we_n <= 1'd1; + main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_120 = dummy_s; @@ -5788,32 +6156,25 @@ end reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_121 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; -assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; -assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); -assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); -assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; -assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_122; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_122 = dummy_s; @@ -5824,11 +6185,10 @@ end reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + main_litedramcore_inti_p1_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; + main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_123 = dummy_s; @@ -5839,11 +6199,11 @@ end reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_124 = dummy_s; @@ -5854,32 +6214,26 @@ end reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end else begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_125 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; -assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; -assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); -assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); -assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; -assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_126; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_126 = dummy_s; @@ -5890,11 +6244,11 @@ end reg dummy_d_127; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + main_litedramcore_master_p3_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_127 = dummy_s; @@ -5905,11 +6259,10 @@ end reg dummy_d_128; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + main_litedramcore_inti_p0_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_128 = dummy_s; @@ -5920,126 +6273,26 @@ end reg dummy_d_129; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_129 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; -assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; -assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); -assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); -assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; -assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; -assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; -assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; -assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; -assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; -assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; -assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; -assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; -assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; -assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; -assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; -assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; -assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; -assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; -assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; -assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; -assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; -assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; -assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; -assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; -assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; -assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; -assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; -assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; -assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; -assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; -assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; -assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; -assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; -assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; -assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; -assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; -assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; -assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; -assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; -assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; -assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; -assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; -assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; -assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; -assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; -assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; -assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; -assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; -assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; -assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; -assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; -assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; -assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; -assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; -assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; -assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; -assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; -assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; -assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; -assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; -assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; -assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); -assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; -assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; -assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; -assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); -assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); -assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; -assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; -assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); -assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); -assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); -assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; -assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; // synthesis translate_off reg dummy_d_130; // synthesis translate_on always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (soc_litedramcore_wants_refresh) begin - vns_refresher_next_state <= 1'd1; - end - end - end - endcase + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + end // synthesis translate_off dummy_d_130 = dummy_s; // synthesis translate_on @@ -6049,20 +6302,12 @@ end reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_master_p3_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; + end else begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; + end // synthesis translate_off dummy_d_131 = dummy_s; // synthesis translate_on @@ -6072,29 +6317,11 @@ end reg dummy_d_132; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase + main_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; + end // synthesis translate_off dummy_d_132 = dummy_s; // synthesis translate_on @@ -6104,23 +6331,12 @@ end reg dummy_d_133; // synthesis translate_on always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; + end // synthesis translate_off dummy_d_133 = dummy_s; // synthesis translate_on @@ -6130,181 +6346,72 @@ end reg dummy_d_134; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase + main_litedramcore_master_p0_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; + end else begin + main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; + end // synthesis translate_off dummy_d_134 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; -assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); -assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_135; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_135 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); -assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); -assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_136; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); - end + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; + end else begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_136 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_137; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_137 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off reg dummy_d_138; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end - end else begin - vns_bankmachine0_next_state <= 1'd1; - end - end else begin - vns_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; + end else begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; + end // synthesis translate_off dummy_d_138 = dummy_s; // synthesis translate_on @@ -6314,39 +6421,11 @@ end reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_slave_p0_rddata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; + end else begin + end // synthesis translate_off dummy_d_139 = dummy_s; // synthesis translate_on @@ -6356,33 +6435,12 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; + end else begin + main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; + end // synthesis translate_off dummy_d_140 = dummy_s; // synthesis translate_on @@ -6392,45 +6450,11 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + end else begin + end // synthesis translate_off dummy_d_141 = dummy_s; // synthesis translate_on @@ -6440,30 +6464,12 @@ end reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; + end else begin + main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; + end // synthesis translate_off dummy_d_142 = dummy_s; // synthesis translate_on @@ -6473,34 +6479,12 @@ end reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; + end else begin + main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; + end // synthesis translate_off dummy_d_143 = dummy_s; // synthesis translate_on @@ -6510,42 +6494,12 @@ end reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; + end else begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; + end // synthesis translate_off dummy_d_144 = dummy_s; // synthesis translate_on @@ -6555,42 +6509,12 @@ end reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; + end else begin + main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; + end // synthesis translate_off dummy_d_145 = dummy_s; // synthesis translate_on @@ -6600,42 +6524,12 @@ end reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_master_p0_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; + end else begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; + end // synthesis translate_off dummy_d_146 = dummy_s; // synthesis translate_on @@ -6645,42 +6539,12 @@ end reg dummy_d_147; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; + end else begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; + end // synthesis translate_off dummy_d_147 = dummy_s; // synthesis translate_on @@ -6690,30 +6554,12 @@ end reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_master_p0_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; + end else begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; + end // synthesis translate_off dummy_d_148 = dummy_s; // synthesis translate_on @@ -6723,78 +6569,39 @@ end reg dummy_d_149; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; + end else begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; + end // synthesis translate_off dummy_d_149 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p2_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p3_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p0_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p1_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p2_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p3_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; // synthesis translate_off reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + end else begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_150 = dummy_s; // synthesis translate_on @@ -6804,185 +6611,78 @@ end reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_151 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; -assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); -assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off reg dummy_d_152; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_inti_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); end else begin - soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_152 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); -assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); -assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); // synthesis translate_off reg dummy_d_153; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); - end + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_153 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]); +assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); +assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_154; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_inti_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + main_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_154 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off reg dummy_d_155; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; - end - end else begin - vns_bankmachine1_next_state <= 1'd1; - end - end else begin - vns_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase + main_litedramcore_inti_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_155 = dummy_s; // synthesis translate_on @@ -6992,39 +6692,12 @@ end reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); + end else begin + main_litedramcore_inti_p1_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_156 = dummy_s; // synthesis translate_on @@ -7034,81 +6707,33 @@ end reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + end else begin + main_litedramcore_inti_p1_we_n <= 1'd1; + end // synthesis translate_off dummy_d_157 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]); +assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); +assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); + end else begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_158 = dummy_s; // synthesis translate_on @@ -7118,30 +6743,12 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_159 = dummy_s; // synthesis translate_on @@ -7151,34 +6758,12 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_160 = dummy_s; // synthesis translate_on @@ -7188,87 +6773,33 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end // synthesis translate_off dummy_d_161 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]); +assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); +assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + end else begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_162 = dummy_s; // synthesis translate_on @@ -7278,42 +6809,12 @@ end reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_163 = dummy_s; // synthesis translate_on @@ -7323,360 +6824,425 @@ end reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_inti_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + end else begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_164 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_165; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_165 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]); +assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]); +assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; + end else begin + builder_refresher_next_state <= 1'd0; + end + end end 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; + end end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end + if (1'd1) begin + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_167; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin end 2'd3: begin end - 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end default: begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_169; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin + 2'd3: begin end default: begin end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_170; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_169; +reg dummy_d_171; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); -assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); // synthesis translate_off -reg dummy_d_170; +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_171; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_172; +reg dummy_d_174; // synthesis translate_on always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin - vns_bankmachine2_next_state <= 1'd1; + builder_bankmachine0_next_state <= 1'd1; end end else begin - vns_bankmachine2_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -7689,44 +7255,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -7740,20 +7291,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7770,15 +7318,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7788,23 +7333,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7821,30 +7369,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7855,24 +7399,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_180; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7885,41 +7447,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7930,34 +7484,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -7975,14 +7514,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -7993,16 +7532,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -8020,14 +7559,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8038,16 +7577,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -8055,9 +7594,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8068,30 +7604,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_185; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8104,12 +7649,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end end else begin end end else begin @@ -8119,26 +7667,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_186; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8152,26 +7700,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_187; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -8182,179 +7733,194 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; -assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); -assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_186; +reg dummy_d_188; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); -assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); -assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_187; +reg dummy_d_189; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_188; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_189; +reg dummy_d_191; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; end end else begin - vns_bankmachine3_next_state <= 1'd1; + builder_bankmachine1_next_state <= 1'd1; end end else begin - vns_bankmachine3_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -8367,44 +7933,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -8418,20 +7969,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8448,15 +7996,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8466,23 +8011,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8499,30 +8047,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8533,24 +8077,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8563,41 +8125,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8608,34 +8162,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -8653,14 +8192,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8671,16 +8210,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -8698,14 +8237,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -8716,16 +8255,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -8733,9 +8272,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8746,30 +8282,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8782,12 +8327,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -8797,26 +8345,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_203; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8830,26 +8378,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_204; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -8860,174 +8411,186 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_203; +reg dummy_d_205; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); -assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); -assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_204; +reg dummy_d_206; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_205; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_206; +reg dummy_d_208; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; end end else begin - vns_bankmachine4_next_state <= 1'd1; + builder_bankmachine2_next_state <= 1'd1; end end else begin - vns_bankmachine4_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -9045,12 +8608,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end end else begin end end else begin @@ -9060,26 +8626,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -9096,26 +8659,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -9126,42 +8689,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9174,33 +8719,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9214,17 +8770,20 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_214; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9241,14 +8800,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9259,21 +8818,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9286,41 +8848,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9331,34 +8885,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -9376,14 +8915,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9394,16 +8933,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -9411,9 +8950,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9424,30 +8960,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9460,12 +9005,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; + end else begin + end end else begin end end else begin @@ -9475,26 +9023,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_220; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9508,26 +9056,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_221; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -9538,179 +9089,194 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; -assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); -assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_220; +reg dummy_d_222; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); -assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); -assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_221; +reg dummy_d_223; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_222; +reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_223; +reg dummy_d_225; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; + builder_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; end end else begin - vns_bankmachine5_next_state <= 1'd1; + builder_bankmachine3_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; + builder_bankmachine3_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_224; +reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -9723,44 +9289,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -9774,20 +9325,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9804,15 +9352,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9822,23 +9367,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9855,30 +9403,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9889,20 +9430,38 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9919,14 +9478,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9937,21 +9496,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9964,41 +9526,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10009,34 +9563,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -10054,14 +9593,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10072,16 +9611,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -10089,9 +9628,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -10102,30 +9638,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -10138,12 +9683,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; + end else begin + end end else begin end end else begin @@ -10153,26 +9701,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_237; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10186,26 +9734,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_238; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -10216,179 +9767,194 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_237; +reg dummy_d_239; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); -assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); -assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_238; +reg dummy_d_240; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_239; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_240; +reg dummy_d_242; // synthesis translate_on always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; end end else begin - vns_bankmachine6_next_state <= 1'd1; + builder_bankmachine4_next_state <= 1'd1; end end else begin - vns_bankmachine6_next_state <= 2'd3; + builder_bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -10401,44 +9967,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -10452,20 +10003,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10482,15 +10030,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10500,23 +10045,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -10533,30 +10081,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10567,24 +10111,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -10597,41 +10159,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10642,34 +10196,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -10687,14 +10226,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10705,16 +10244,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -10732,14 +10271,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -10750,16 +10289,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -10767,9 +10306,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -10780,30 +10316,39 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -10816,12 +10361,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -10831,26 +10379,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_254; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10864,26 +10412,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_255; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -10894,174 +10445,252 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; -assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); -assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_254; +reg dummy_d_256; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); -assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); -assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_255; +reg dummy_d_257; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_256; +reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_257; +reg dummy_d_259; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; end end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin - vns_bankmachine7_next_state <= 1'd1; + builder_bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine7_next_state <= 2'd3; + builder_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -11079,12 +10708,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -11094,26 +10723,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -11130,19 +10759,19 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -11160,13 +10789,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -11178,23 +10807,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -11211,30 +10840,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -11248,16 +10877,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_267; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -11275,14 +10904,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -11293,16 +10922,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_264; +reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -11320,13 +10949,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -11338,16 +10967,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_269; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -11365,13 +10994,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -11383,16 +11012,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_270; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -11400,6 +11029,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -11410,44 +11042,32 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_267; +reg dummy_d_271; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -11458,30 +11078,36 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_272; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -11494,12 +11120,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -11509,3880 +11138,8464 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_272 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_273 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_275 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_276; +// synthesis translate_on +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end + end else begin + builder_bankmachine6_next_state <= 1'd1; + end + end else begin + builder_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_276 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_277; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_277 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_278; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_278 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_279; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_279 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_281 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_285; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_285 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_287; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_287 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_288; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_289 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; + +// synthesis translate_off +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_292; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_292 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_293; +// synthesis translate_on +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_293 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_295; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_295 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_296; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_rdcmdphase = (main_k7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_wrcmdphase = (main_k7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; + end +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; + end +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; + end +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; + end +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; + end +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; + end +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) + 1'd1: begin + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; + end + end + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + builder_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + builder_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + builder_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + builder_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + builder_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + builder_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + builder_multiplexer_next_state <= 1'd1; + end + default: begin + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; + end + end + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end + end + endcase +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end + end + endcase +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel3 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel0 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + main_litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel1 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel2 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12; +assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15; +assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18; +assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21; +assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24; +assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27; +assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30; +assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33; +assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata <= 256'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + end + default: begin + main_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata_we <= 32'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + end + default: begin + main_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_next_state <= 2'd2; + end + 2'd2: begin + builder_next_state <= 1'd0; + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value1 <= 14'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_dat_r <= 32'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value0 <= 8'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; + end + endcase +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end +assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; +assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r; +assign builder_litedramcore_wishbone_sel = main_wb_bus_sel; +assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc; +assign builder_litedramcore_wishbone_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_litedramcore_wishbone_ack; +assign builder_litedramcore_wishbone_we = main_wb_bus_we; +assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; +assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_litedramcore_wishbone_err; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_cdly_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_cdly_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_cdly_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_cdly_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0]; + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dqs_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dqs_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end +assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage; +assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0]; +assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_416; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_416 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_417; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi0_rddata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_417 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_418; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi0_rddata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_418 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_419; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi0_rddata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_419 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_420; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi0_rddata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_420 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_421; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi0_rddata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_421 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_422; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi0_rddata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_422 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_423; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi0_rddata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_423 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_424; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi0_rddata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_424 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_425; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_425 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_426; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_426 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_427; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_427 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_428; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_428 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_429; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_429 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_430; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_430 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_431; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_431 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_432; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_432 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_433; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_433 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_434; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_434 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_435; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_435 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_436; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_436 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_437; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_437 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_438; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_438 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_439; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_439 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_440; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_440 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_441; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_441 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_442; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_442 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_443; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi1_wrdata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_443 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_444; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi1_wrdata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_444 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_445; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + builder_csrbank2_dfii_pi1_wrdata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_445 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_446; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + builder_csrbank2_dfii_pi1_wrdata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_446 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_447; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi1_wrdata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_447 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_448; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi1_wrdata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_448 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_449; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi1_wrdata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_449 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_450; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi1_wrdata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_450 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_451; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_451 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_452; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_452 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_453; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_453 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_454; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_454 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_455; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_455 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_456; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_456 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_457; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_457 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_458; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_458 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_459; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi1_rddata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_459 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_460; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi1_rddata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_460 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_461; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi1_rddata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_461 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_462; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi1_rddata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_462 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_463; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi1_rddata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_463 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_464; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi1_rddata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_464 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_465; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi1_rddata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_465 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_466; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi1_rddata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_466 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_467; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_467 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_468; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_468 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_469; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_469 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_470; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_470 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_471; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_471 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_472; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_472 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_473; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_473 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_474; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_474 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_475; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_475 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_476; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_476 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_477; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_477 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_478; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_478 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_479; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_479 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_480; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_480 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_481; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_481 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_482; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_482 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_483; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_483 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_484; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_484 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_485; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi2_wrdata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_485 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_486; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi2_wrdata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_486 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_487; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi2_wrdata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_487 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_488; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi2_wrdata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_488 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_489; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi2_wrdata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_489 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_490; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi2_wrdata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_490 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_491; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi2_wrdata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_491 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_492; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi2_wrdata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_492 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_493; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_493 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_494; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_494 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_495; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_495 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_496; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_496 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_497; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_497 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_498; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_498 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_499; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_499 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_500; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_500 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_501; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin + builder_csrbank2_dfii_pi2_rddata7_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_501 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_502; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin + builder_csrbank2_dfii_pi2_rddata7_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_502 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_503; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin + builder_csrbank2_dfii_pi2_rddata6_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_503 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_504; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin + builder_csrbank2_dfii_pi2_rddata6_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_504 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_505; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin + builder_csrbank2_dfii_pi2_rddata5_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_505 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_506; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin + builder_csrbank2_dfii_pi2_rddata5_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_506 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_507; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin + builder_csrbank2_dfii_pi2_rddata4_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_507 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_508; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin + builder_csrbank2_dfii_pi2_rddata4_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_508 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_509; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin + builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_509 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_510; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin + builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_510 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_511; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin + builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_511 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_512; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin + builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_512 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_513; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin + builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_513 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_514; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin + builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_514 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_515; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin + builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_515 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_516; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_516 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_517; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_517 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_518; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_518 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_519; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_519 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_520; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_520 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_521; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin + builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_521 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_522; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin + builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_522 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_523; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_523 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_524; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_524 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; // synthesis translate_off -reg dummy_d_270; +reg dummy_d_525; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) - 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_525 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); -assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); -assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; -assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); -assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); -assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); -assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); -assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); -assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); -assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_271; +reg dummy_d_526; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_valids <= 8'd0; - soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_526 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; -assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; +assign builder_csrbank2_dfii_pi3_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_272; +reg dummy_d_527; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + builder_csrbank2_dfii_pi3_wrdata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin + builder_csrbank2_dfii_pi3_wrdata7_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_527 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_528; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + builder_csrbank2_dfii_pi3_wrdata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin + builder_csrbank2_dfii_pi3_wrdata7_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_528 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_274; +reg dummy_d_529; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + builder_csrbank2_dfii_pi3_wrdata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin + builder_csrbank2_dfii_pi3_wrdata6_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_529 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_530; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin + builder_csrbank2_dfii_pi3_wrdata6_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_530 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_276; +reg dummy_d_531; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin + builder_csrbank2_dfii_pi3_wrdata5_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_531 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_532; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin + builder_csrbank2_dfii_pi3_wrdata5_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_532 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_278; +reg dummy_d_533; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin + builder_csrbank2_dfii_pi3_wrdata4_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_533 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_534; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin + builder_csrbank2_dfii_pi3_wrdata4_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_534 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_280; +reg dummy_d_535; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_535 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_536; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_536 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_537; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_537 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_283; +reg dummy_d_538; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_valids <= 8'd0; - soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_538 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; -assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_539; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_539 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_285; +reg dummy_d_540; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_540 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_286; +reg dummy_d_541; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_541 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); -assign soc_litedramcore_dfi_p0_reset_n = 1'd1; -assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; -assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; -assign soc_litedramcore_dfi_p1_reset_n = 1'd1; -assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; -assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; -assign soc_litedramcore_dfi_p2_reset_n = 1'd1; -assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; -assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; -assign soc_litedramcore_dfi_p3_reset_n = 1'd1; -assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; -assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; -assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_287; +reg dummy_d_542; // synthesis translate_on always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) - 1'd1: begin - if (soc_litedramcore_read_available) begin - if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; - end - end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (soc_litedramcore_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - vns_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - vns_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - vns_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - vns_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - vns_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - vns_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - vns_multiplexer_next_state <= 1'd1; - end - default: begin - if (soc_litedramcore_write_available) begin - if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; - end - end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; - end - end - endcase + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_542 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_288; +reg dummy_d_543; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata7_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin + builder_csrbank2_dfii_pi3_rddata7_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_543 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_544; // synthesis translate_on always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_rddata7_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin + builder_csrbank2_dfii_pi3_rddata7_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_544 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_290; +reg dummy_d_545; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_rddata6_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin + builder_csrbank2_dfii_pi3_rddata6_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_545 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_546; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - endcase + builder_csrbank2_dfii_pi3_rddata6_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin + builder_csrbank2_dfii_pi3_rddata6_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_546 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_292; +reg dummy_d_547; // synthesis translate_on -always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - endcase +always @(*) begin + builder_csrbank2_dfii_pi3_rddata5_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin + builder_csrbank2_dfii_pi3_rddata5_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_547 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_548; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata5_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin + builder_csrbank2_dfii_pi3_rddata5_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_548 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_294; +reg dummy_d_549; // synthesis translate_on always @(*) begin - soc_litedramcore_en0 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_en0 <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_rddata4_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin + builder_csrbank2_dfii_pi3_rddata4_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_549 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_550; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_rddata4_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin + builder_csrbank2_dfii_pi3_rddata4_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_550 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_296; +reg dummy_d_551; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - endcase + builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin + builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_551 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_552; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin + builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_552 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_298; +reg dummy_d_553; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin + builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_553 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_554; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - endcase + builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin + builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_554 = dummy_s; // synthesis translate_on end -assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); -assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); -assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); -assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); -assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); -assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); -assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); -assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); -assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); -assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_300; +reg dummy_d_555; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata <= 256'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; - end - default: begin - soc_litedramcore_interface_wdata <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin + builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_555 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_556; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata_we <= 32'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; - end - default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin + builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_556 = dummy_s; // synthesis translate_on end -assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; -assign vns_roundrobin0_grant = 1'd0; -assign vns_roundrobin1_grant = 1'd0; -assign vns_roundrobin2_grant = 1'd0; -assign vns_roundrobin3_grant = 1'd0; -assign vns_roundrobin4_grant = 1'd0; -assign vns_roundrobin5_grant = 1'd0; -assign vns_roundrobin6_grant = 1'd0; -assign vns_roundrobin7_grant = 1'd0; -assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; -assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; -assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; -assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; -assign soc_litedramcore_wishbone_we = soc_wb_bus_we; -assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; -assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = soc_litedramcore_wishbone_err; -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_done0_w = soc_init_done_storage; -assign vns_csrbank0_init_error0_w = soc_init_error_storage; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; -assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign soc_k7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_k7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_k7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_k7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_k7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign soc_k7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[3:0]; -assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign soc_k7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_k7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_k7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_k7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_k7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_k7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_k7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign soc_k7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign soc_k7ddrphy_wdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_wdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd10)); -assign soc_k7ddrphy_wdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd10)); -assign soc_k7ddrphy_wdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_wdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd11)); -assign soc_k7ddrphy_wdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd11)); -assign soc_k7ddrphy_wdly_dqs_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_wdly_dqs_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd12)); -assign soc_k7ddrphy_wdly_dqs_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd12)); -assign soc_k7ddrphy_wdly_dqs_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_k7ddrphy_wdly_dqs_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd13)); -assign soc_k7ddrphy_wdly_dqs_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd13)); -assign vns_csrbank1_half_sys8x_taps0_w = soc_k7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank1_wlevel_en0_w = soc_k7ddrphy_wlevel_en_storage; -assign vns_csrbank1_dly_sel0_w = soc_k7ddrphy_dly_sel_storage[3:0]; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); -assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; -assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 1'd1)); -assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 1'd1)); -assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 2'd2)); -assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 2'd2)); -assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank2_dfii_pi0_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank2_dfii_pi0_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank2_dfii_pi0_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank2_dfii_pi0_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd9)); -assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd10)); -assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank2_dfii_pi1_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank2_dfii_pi1_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd14)); -assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd14)); -assign vns_csrbank2_dfii_pi1_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd15)); -assign vns_csrbank2_dfii_pi1_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd15)); -assign vns_csrbank2_dfii_pi1_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank2_dfii_pi1_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd17)); -assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd18)); -assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd18)); -assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank2_dfii_pi2_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank2_dfii_pi2_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank2_dfii_pi2_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank2_dfii_pi2_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank2_dfii_pi2_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank2_dfii_pi2_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd25)); -assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd25)); -assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd26)); -assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd26)); -assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd27)); -assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd27)); -assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd28)); -assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd28)); -assign vns_csrbank2_dfii_pi3_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank2_dfii_pi3_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank2_dfii_pi3_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank2_dfii_pi3_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank2_dfii_pi3_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 6'd32)); -assign vns_csrbank2_dfii_pi3_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 6'd32)); -assign soc_litedramcore_sel = soc_litedramcore_storage[0]; -assign soc_litedramcore_cke = soc_litedramcore_storage[1]; -assign soc_litedramcore_odt = soc_litedramcore_storage[2]; -assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; -assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; -assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; -assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[14:0]; -assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[63:32]; -assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_status[63:32]; -assign vns_csrbank2_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_status[31:0]; -assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata0_we; -assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; -assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[14:0]; -assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[63:32]; -assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_status[63:32]; -assign vns_csrbank2_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_status[31:0]; -assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata0_we; -assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; -assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[14:0]; -assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[63:32]; -assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_status[63:32]; -assign vns_csrbank2_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_status[31:0]; -assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata0_we; -assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; -assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[14:0]; -assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[63:32]; -assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_status[63:32]; -assign vns_csrbank2_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_status[31:0]; -assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata0_we; -assign vns_adr = soc_litedramcore_adr; -assign vns_we = soc_litedramcore_we; -assign vns_dat_w = soc_litedramcore_dat_w; -assign soc_litedramcore_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_302; +reg dummy_d_557; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_557 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_558; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin + builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_558 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; +assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata7_w = main_litedramcore_phaseinjector0_wrdata_storage[63:56]; +assign builder_csrbank2_dfii_pi0_wrdata6_w = main_litedramcore_phaseinjector0_wrdata_storage[55:48]; +assign builder_csrbank2_dfii_pi0_wrdata5_w = main_litedramcore_phaseinjector0_wrdata_storage[47:40]; +assign builder_csrbank2_dfii_pi0_wrdata4_w = main_litedramcore_phaseinjector0_wrdata_storage[39:32]; +assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi0_rddata7_w = main_litedramcore_phaseinjector0_rddata_status[63:56]; +assign builder_csrbank2_dfii_pi0_rddata6_w = main_litedramcore_phaseinjector0_rddata_status[55:48]; +assign builder_csrbank2_dfii_pi0_rddata5_w = main_litedramcore_phaseinjector0_rddata_status[47:40]; +assign builder_csrbank2_dfii_pi0_rddata4_w = main_litedramcore_phaseinjector0_rddata_status[39:32]; +assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; +assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata7_w = main_litedramcore_phaseinjector1_wrdata_storage[63:56]; +assign builder_csrbank2_dfii_pi1_wrdata6_w = main_litedramcore_phaseinjector1_wrdata_storage[55:48]; +assign builder_csrbank2_dfii_pi1_wrdata5_w = main_litedramcore_phaseinjector1_wrdata_storage[47:40]; +assign builder_csrbank2_dfii_pi1_wrdata4_w = main_litedramcore_phaseinjector1_wrdata_storage[39:32]; +assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi1_rddata7_w = main_litedramcore_phaseinjector1_rddata_status[63:56]; +assign builder_csrbank2_dfii_pi1_rddata6_w = main_litedramcore_phaseinjector1_rddata_status[55:48]; +assign builder_csrbank2_dfii_pi1_rddata5_w = main_litedramcore_phaseinjector1_rddata_status[47:40]; +assign builder_csrbank2_dfii_pi1_rddata4_w = main_litedramcore_phaseinjector1_rddata_status[39:32]; +assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; +assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata7_w = main_litedramcore_phaseinjector2_wrdata_storage[63:56]; +assign builder_csrbank2_dfii_pi2_wrdata6_w = main_litedramcore_phaseinjector2_wrdata_storage[55:48]; +assign builder_csrbank2_dfii_pi2_wrdata5_w = main_litedramcore_phaseinjector2_wrdata_storage[47:40]; +assign builder_csrbank2_dfii_pi2_wrdata4_w = main_litedramcore_phaseinjector2_wrdata_storage[39:32]; +assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi2_rddata7_w = main_litedramcore_phaseinjector2_rddata_status[63:56]; +assign builder_csrbank2_dfii_pi2_rddata6_w = main_litedramcore_phaseinjector2_rddata_status[55:48]; +assign builder_csrbank2_dfii_pi2_rddata5_w = main_litedramcore_phaseinjector2_rddata_status[47:40]; +assign builder_csrbank2_dfii_pi2_rddata4_w = main_litedramcore_phaseinjector2_rddata_status[39:32]; +assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; +assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata7_w = main_litedramcore_phaseinjector3_wrdata_storage[63:56]; +assign builder_csrbank2_dfii_pi3_wrdata6_w = main_litedramcore_phaseinjector3_wrdata_storage[55:48]; +assign builder_csrbank2_dfii_pi3_wrdata5_w = main_litedramcore_phaseinjector3_wrdata_storage[47:40]; +assign builder_csrbank2_dfii_pi3_wrdata4_w = main_litedramcore_phaseinjector3_wrdata_storage[39:32]; +assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi3_rddata7_w = main_litedramcore_phaseinjector3_rddata_status[63:56]; +assign builder_csrbank2_dfii_pi3_rddata6_w = main_litedramcore_phaseinjector3_rddata_status[55:48]; +assign builder_csrbank2_dfii_pi3_rddata5_w = main_litedramcore_phaseinjector3_rddata_status[47:40]; +assign builder_csrbank2_dfii_pi3_rddata4_w = main_litedramcore_phaseinjector3_rddata_status[39:32]; +assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csr_interconnect_adr = builder_litedramcore_adr; +assign builder_csr_interconnect_we = builder_litedramcore_we; +assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; +assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r; +assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_559; +// synthesis translate_on +always @(*) begin + builder_rhs_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_559 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_560; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 15'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed1 <= 15'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_560 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_561; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_561 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_562; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_562 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_563; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_563 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_564; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_564 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_565; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_565 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_566; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_566 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_567; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_567 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_568; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6]; end default: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_568 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_569; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 15'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed7 <= 15'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_569 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_570; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_570 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_571; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_571 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_572; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_572 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_573; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_573 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_574; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_574 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_575; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_575 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_576; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_576 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_577; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 22'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed12 <= 22'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_577 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_578; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_578 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_579; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_579 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_580; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 22'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed15 <= 22'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_580 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_581; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_581 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_582; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_582 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_583; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 22'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed18 <= 22'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_583 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_584; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_584 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_585; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_585 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_586; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 22'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed21 <= 22'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_586 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_587; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_587 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_588; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_588 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_589; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 22'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed24 <= 22'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_589 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_590; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_590 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_591; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_591 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_592; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 22'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed27 <= 22'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_592 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_593; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_593 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_594; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_594 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_595; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 22'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed30 <= 22'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_595 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_596; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_596 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_597; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_597 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_598; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 22'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed33 <= 22'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_598 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_599; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_599 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_600; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_600 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_601; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed0 <= 3'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_601 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_602; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 15'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed1 <= 15'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_litedramcore_nop_a; + builder_array_muxed1 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_602 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_603; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed2 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + builder_array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_603 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_604; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed3 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + builder_array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_604 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_605; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed4 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + builder_array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_605 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_606; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed5 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + builder_array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_606 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_607; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed6 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + builder_array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_607 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_608; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed7 <= 3'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_608 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_609; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 15'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed8 <= 15'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_litedramcore_nop_a; + builder_array_muxed8 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_609 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_610; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed9 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + builder_array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_610 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_611; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed10 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + builder_array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_611 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_612; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed11 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + builder_array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_612 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_613; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed12 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + builder_array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_356 = dummy_s; + dummy_d_613 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_357; +reg dummy_d_614; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed13 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + builder_array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_614 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_615; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed14 <= 3'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_615 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_359; +reg dummy_d_616; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 15'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed15 <= 15'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_litedramcore_nop_a; + builder_array_muxed15 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_359 = dummy_s; + dummy_d_616 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_360; +reg dummy_d_617; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed16 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + builder_array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_360 = dummy_s; + dummy_d_617 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_361; +reg dummy_d_618; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed17 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + builder_array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_361 = dummy_s; + dummy_d_618 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_362; +reg dummy_d_619; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed18 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + builder_array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_362 = dummy_s; + dummy_d_619 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_363; +reg dummy_d_620; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed19 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + builder_array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_363 = dummy_s; + dummy_d_620 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_364; +reg dummy_d_621; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed20 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + builder_array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_364 = dummy_s; + dummy_d_621 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_365; +reg dummy_d_622; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed21 <= 3'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_365 = dummy_s; + dummy_d_622 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_366; +reg dummy_d_623; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 15'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed22 <= 15'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_litedramcore_nop_a; + builder_array_muxed22 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_366 = dummy_s; + dummy_d_623 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_367; +reg dummy_d_624; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed23 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + builder_array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_367 = dummy_s; + dummy_d_624 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_368; +reg dummy_d_625; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed24 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + builder_array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_368 = dummy_s; + dummy_d_625 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_369; +reg dummy_d_626; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed25 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + builder_array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_369 = dummy_s; + dummy_d_626 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_370; +reg dummy_d_627; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed26 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + builder_array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_370 = dummy_s; + dummy_d_627 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_371; +reg dummy_d_628; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed27 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + builder_array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_371 = dummy_s; + dummy_d_628 = dummy_s; // synthesis translate_on end -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - soc_ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - vns_state <= vns_next_state; - soc_k7ddrphy_dqs_oe_delayed <= ((soc_k7ddrphy_dqspattern0 | soc_k7ddrphy_dqs_oe) | soc_k7ddrphy_dqspattern1); - soc_k7ddrphy_dq_oe_delayed <= ((soc_k7ddrphy_dqspattern0 | soc_k7ddrphy_dq_oe) | soc_k7ddrphy_dqspattern1); - soc_k7ddrphy_rddata_en_last <= soc_k7ddrphy_rddata_en; - soc_k7ddrphy_dfi_p0_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); - soc_k7ddrphy_dfi_p1_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); - soc_k7ddrphy_dfi_p2_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); - soc_k7ddrphy_dfi_p3_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); - soc_k7ddrphy_wrdata_en_last <= soc_k7ddrphy_wrdata_en; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip0_value <= (soc_k7ddrphy_bitslip0_value + 1'd1); + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value0 <= (main_k7ddrphy_bitslip0_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value0 <= 3'd7; + end + main_k7ddrphy_bitslip0_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip0_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value0 <= (main_k7ddrphy_bitslip1_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value0 <= 3'd7; + end + main_k7ddrphy_bitslip1_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip1_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value0 <= (main_k7ddrphy_bitslip2_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value0 <= 3'd7; + end + main_k7ddrphy_bitslip2_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip2_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value0 <= (main_k7ddrphy_bitslip3_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value0 <= 3'd7; + end + main_k7ddrphy_bitslip3_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip3_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value1 <= (main_k7ddrphy_bitslip0_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value1 <= 3'd7; + end + main_k7ddrphy_bitslip0_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[4], main_k7ddrphy_dfi_p3_wrdata_mask[0], main_k7ddrphy_dfi_p2_wrdata_mask[4], main_k7ddrphy_dfi_p2_wrdata_mask[0], main_k7ddrphy_dfi_p1_wrdata_mask[4], main_k7ddrphy_dfi_p1_wrdata_mask[0], main_k7ddrphy_dfi_p0_wrdata_mask[4], main_k7ddrphy_dfi_p0_wrdata_mask[0]}, main_k7ddrphy_bitslip0_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value1 <= (main_k7ddrphy_bitslip1_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value1 <= 3'd7; + end + main_k7ddrphy_bitslip1_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[5], main_k7ddrphy_dfi_p3_wrdata_mask[1], main_k7ddrphy_dfi_p2_wrdata_mask[5], main_k7ddrphy_dfi_p2_wrdata_mask[1], main_k7ddrphy_dfi_p1_wrdata_mask[5], main_k7ddrphy_dfi_p1_wrdata_mask[1], main_k7ddrphy_dfi_p0_wrdata_mask[5], main_k7ddrphy_dfi_p0_wrdata_mask[1]}, main_k7ddrphy_bitslip1_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value1 <= (main_k7ddrphy_bitslip2_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value1 <= 3'd7; + end + main_k7ddrphy_bitslip2_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[6], main_k7ddrphy_dfi_p3_wrdata_mask[2], main_k7ddrphy_dfi_p2_wrdata_mask[6], main_k7ddrphy_dfi_p2_wrdata_mask[2], main_k7ddrphy_dfi_p1_wrdata_mask[6], main_k7ddrphy_dfi_p1_wrdata_mask[2], main_k7ddrphy_dfi_p0_wrdata_mask[6], main_k7ddrphy_dfi_p0_wrdata_mask[2]}, main_k7ddrphy_bitslip2_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value1 <= (main_k7ddrphy_bitslip3_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value1 <= 3'd7; + end + main_k7ddrphy_bitslip3_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[7], main_k7ddrphy_dfi_p3_wrdata_mask[3], main_k7ddrphy_dfi_p2_wrdata_mask[7], main_k7ddrphy_dfi_p2_wrdata_mask[3], main_k7ddrphy_dfi_p1_wrdata_mask[7], main_k7ddrphy_dfi_p1_wrdata_mask[3], main_k7ddrphy_dfi_p0_wrdata_mask[7], main_k7ddrphy_dfi_p0_wrdata_mask[3]}, main_k7ddrphy_bitslip3_r1[15:8]}; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dq_oe_delay_tappeddelayline; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value2 <= (main_k7ddrphy_bitslip0_value2 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value2 <= 3'd7; + end + main_k7ddrphy_bitslip0_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[32], main_k7ddrphy_dfi_p3_wrdata[0], main_k7ddrphy_dfi_p2_wrdata[32], main_k7ddrphy_dfi_p2_wrdata[0], main_k7ddrphy_dfi_p1_wrdata[32], main_k7ddrphy_dfi_p1_wrdata[0], main_k7ddrphy_dfi_p0_wrdata[32], main_k7ddrphy_dfi_p0_wrdata[0]}, main_k7ddrphy_bitslip0_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value3 <= (main_k7ddrphy_bitslip0_value3 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value3 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip0_value <= 1'd0; + main_k7ddrphy_bitslip0_r3 <= {main_k7ddrphy_bitslip03, main_k7ddrphy_bitslip0_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value2 <= (main_k7ddrphy_bitslip1_value2 + 1'd1); end - soc_k7ddrphy_bitslip0_r <= {soc_k7ddrphy_bitslip0_i, soc_k7ddrphy_bitslip0_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip1_value <= (soc_k7ddrphy_bitslip1_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value2 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip1_value <= 1'd0; + main_k7ddrphy_bitslip1_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[33], main_k7ddrphy_dfi_p3_wrdata[1], main_k7ddrphy_dfi_p2_wrdata[33], main_k7ddrphy_dfi_p2_wrdata[1], main_k7ddrphy_dfi_p1_wrdata[33], main_k7ddrphy_dfi_p1_wrdata[1], main_k7ddrphy_dfi_p0_wrdata[33], main_k7ddrphy_dfi_p0_wrdata[1]}, main_k7ddrphy_bitslip1_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value3 <= (main_k7ddrphy_bitslip1_value3 + 1'd1); end - soc_k7ddrphy_bitslip1_r <= {soc_k7ddrphy_bitslip1_i, soc_k7ddrphy_bitslip1_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip2_value <= (soc_k7ddrphy_bitslip2_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value3 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip2_value <= 1'd0; + main_k7ddrphy_bitslip1_r3 <= {main_k7ddrphy_bitslip13, main_k7ddrphy_bitslip1_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value2 <= (main_k7ddrphy_bitslip2_value2 + 1'd1); end - soc_k7ddrphy_bitslip2_r <= {soc_k7ddrphy_bitslip2_i, soc_k7ddrphy_bitslip2_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip3_value <= (soc_k7ddrphy_bitslip3_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value2 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip3_value <= 1'd0; + main_k7ddrphy_bitslip2_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[34], main_k7ddrphy_dfi_p3_wrdata[2], main_k7ddrphy_dfi_p2_wrdata[34], main_k7ddrphy_dfi_p2_wrdata[2], main_k7ddrphy_dfi_p1_wrdata[34], main_k7ddrphy_dfi_p1_wrdata[2], main_k7ddrphy_dfi_p0_wrdata[34], main_k7ddrphy_dfi_p0_wrdata[2]}, main_k7ddrphy_bitslip2_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value3 <= (main_k7ddrphy_bitslip2_value3 + 1'd1); end - soc_k7ddrphy_bitslip3_r <= {soc_k7ddrphy_bitslip3_i, soc_k7ddrphy_bitslip3_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip4_value <= (soc_k7ddrphy_bitslip4_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value3 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip4_value <= 1'd0; + main_k7ddrphy_bitslip2_r3 <= {main_k7ddrphy_bitslip23, main_k7ddrphy_bitslip2_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value2 <= (main_k7ddrphy_bitslip3_value2 + 1'd1); end - soc_k7ddrphy_bitslip4_r <= {soc_k7ddrphy_bitslip4_i, soc_k7ddrphy_bitslip4_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip5_value <= (soc_k7ddrphy_bitslip5_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value2 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip5_value <= 1'd0; + main_k7ddrphy_bitslip3_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[35], main_k7ddrphy_dfi_p3_wrdata[3], main_k7ddrphy_dfi_p2_wrdata[35], main_k7ddrphy_dfi_p2_wrdata[3], main_k7ddrphy_dfi_p1_wrdata[35], main_k7ddrphy_dfi_p1_wrdata[3], main_k7ddrphy_dfi_p0_wrdata[35], main_k7ddrphy_dfi_p0_wrdata[3]}, main_k7ddrphy_bitslip3_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value3 <= (main_k7ddrphy_bitslip3_value3 + 1'd1); end - soc_k7ddrphy_bitslip5_r <= {soc_k7ddrphy_bitslip5_i, soc_k7ddrphy_bitslip5_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip6_value <= (soc_k7ddrphy_bitslip6_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value3 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip6_value <= 1'd0; + main_k7ddrphy_bitslip3_r3 <= {main_k7ddrphy_bitslip33, main_k7ddrphy_bitslip3_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip4_value0 <= (main_k7ddrphy_bitslip4_value0 + 1'd1); end - soc_k7ddrphy_bitslip6_r <= {soc_k7ddrphy_bitslip6_i, soc_k7ddrphy_bitslip6_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip7_value <= (soc_k7ddrphy_bitslip7_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip4_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip7_value <= 1'd0; + main_k7ddrphy_bitslip4_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[36], main_k7ddrphy_dfi_p3_wrdata[4], main_k7ddrphy_dfi_p2_wrdata[36], main_k7ddrphy_dfi_p2_wrdata[4], main_k7ddrphy_dfi_p1_wrdata[36], main_k7ddrphy_dfi_p1_wrdata[4], main_k7ddrphy_dfi_p0_wrdata[36], main_k7ddrphy_dfi_p0_wrdata[4]}, main_k7ddrphy_bitslip4_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip4_value1 <= (main_k7ddrphy_bitslip4_value1 + 1'd1); end - soc_k7ddrphy_bitslip7_r <= {soc_k7ddrphy_bitslip7_i, soc_k7ddrphy_bitslip7_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip8_value <= (soc_k7ddrphy_bitslip8_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip4_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip8_value <= 1'd0; + main_k7ddrphy_bitslip4_r1 <= {main_k7ddrphy_bitslip41, main_k7ddrphy_bitslip4_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip5_value0 <= (main_k7ddrphy_bitslip5_value0 + 1'd1); end - soc_k7ddrphy_bitslip8_r <= {soc_k7ddrphy_bitslip8_i, soc_k7ddrphy_bitslip8_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip9_value <= (soc_k7ddrphy_bitslip9_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip5_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip9_value <= 1'd0; + main_k7ddrphy_bitslip5_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[37], main_k7ddrphy_dfi_p3_wrdata[5], main_k7ddrphy_dfi_p2_wrdata[37], main_k7ddrphy_dfi_p2_wrdata[5], main_k7ddrphy_dfi_p1_wrdata[37], main_k7ddrphy_dfi_p1_wrdata[5], main_k7ddrphy_dfi_p0_wrdata[37], main_k7ddrphy_dfi_p0_wrdata[5]}, main_k7ddrphy_bitslip5_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip5_value1 <= (main_k7ddrphy_bitslip5_value1 + 1'd1); end - soc_k7ddrphy_bitslip9_r <= {soc_k7ddrphy_bitslip9_i, soc_k7ddrphy_bitslip9_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip10_value <= (soc_k7ddrphy_bitslip10_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip5_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip10_value <= 1'd0; + main_k7ddrphy_bitslip5_r1 <= {main_k7ddrphy_bitslip51, main_k7ddrphy_bitslip5_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip6_value0 <= (main_k7ddrphy_bitslip6_value0 + 1'd1); end - soc_k7ddrphy_bitslip10_r <= {soc_k7ddrphy_bitslip10_i, soc_k7ddrphy_bitslip10_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip11_value <= (soc_k7ddrphy_bitslip11_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip6_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip11_value <= 1'd0; + main_k7ddrphy_bitslip6_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[38], main_k7ddrphy_dfi_p3_wrdata[6], main_k7ddrphy_dfi_p2_wrdata[38], main_k7ddrphy_dfi_p2_wrdata[6], main_k7ddrphy_dfi_p1_wrdata[38], main_k7ddrphy_dfi_p1_wrdata[6], main_k7ddrphy_dfi_p0_wrdata[38], main_k7ddrphy_dfi_p0_wrdata[6]}, main_k7ddrphy_bitslip6_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip6_value1 <= (main_k7ddrphy_bitslip6_value1 + 1'd1); end - soc_k7ddrphy_bitslip11_r <= {soc_k7ddrphy_bitslip11_i, soc_k7ddrphy_bitslip11_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip12_value <= (soc_k7ddrphy_bitslip12_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip6_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip12_value <= 1'd0; + main_k7ddrphy_bitslip6_r1 <= {main_k7ddrphy_bitslip61, main_k7ddrphy_bitslip6_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip7_value0 <= (main_k7ddrphy_bitslip7_value0 + 1'd1); end - soc_k7ddrphy_bitslip12_r <= {soc_k7ddrphy_bitslip12_i, soc_k7ddrphy_bitslip12_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip13_value <= (soc_k7ddrphy_bitslip13_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip7_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip13_value <= 1'd0; + main_k7ddrphy_bitslip7_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[39], main_k7ddrphy_dfi_p3_wrdata[7], main_k7ddrphy_dfi_p2_wrdata[39], main_k7ddrphy_dfi_p2_wrdata[7], main_k7ddrphy_dfi_p1_wrdata[39], main_k7ddrphy_dfi_p1_wrdata[7], main_k7ddrphy_dfi_p0_wrdata[39], main_k7ddrphy_dfi_p0_wrdata[7]}, main_k7ddrphy_bitslip7_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip7_value1 <= (main_k7ddrphy_bitslip7_value1 + 1'd1); end - soc_k7ddrphy_bitslip13_r <= {soc_k7ddrphy_bitslip13_i, soc_k7ddrphy_bitslip13_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip14_value <= (soc_k7ddrphy_bitslip14_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip7_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip14_value <= 1'd0; + main_k7ddrphy_bitslip7_r1 <= {main_k7ddrphy_bitslip71, main_k7ddrphy_bitslip7_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip8_value0 <= (main_k7ddrphy_bitslip8_value0 + 1'd1); end - soc_k7ddrphy_bitslip14_r <= {soc_k7ddrphy_bitslip14_i, soc_k7ddrphy_bitslip14_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip15_value <= (soc_k7ddrphy_bitslip15_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip8_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip15_value <= 1'd0; + main_k7ddrphy_bitslip8_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[40], main_k7ddrphy_dfi_p3_wrdata[8], main_k7ddrphy_dfi_p2_wrdata[40], main_k7ddrphy_dfi_p2_wrdata[8], main_k7ddrphy_dfi_p1_wrdata[40], main_k7ddrphy_dfi_p1_wrdata[8], main_k7ddrphy_dfi_p0_wrdata[40], main_k7ddrphy_dfi_p0_wrdata[8]}, main_k7ddrphy_bitslip8_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip8_value1 <= (main_k7ddrphy_bitslip8_value1 + 1'd1); end - soc_k7ddrphy_bitslip15_r <= {soc_k7ddrphy_bitslip15_i, soc_k7ddrphy_bitslip15_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip16_value <= (soc_k7ddrphy_bitslip16_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip8_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip16_value <= 1'd0; + main_k7ddrphy_bitslip8_r1 <= {main_k7ddrphy_bitslip81, main_k7ddrphy_bitslip8_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip9_value0 <= (main_k7ddrphy_bitslip9_value0 + 1'd1); end - soc_k7ddrphy_bitslip16_r <= {soc_k7ddrphy_bitslip16_i, soc_k7ddrphy_bitslip16_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip17_value <= (soc_k7ddrphy_bitslip17_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip9_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip17_value <= 1'd0; + main_k7ddrphy_bitslip9_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[41], main_k7ddrphy_dfi_p3_wrdata[9], main_k7ddrphy_dfi_p2_wrdata[41], main_k7ddrphy_dfi_p2_wrdata[9], main_k7ddrphy_dfi_p1_wrdata[41], main_k7ddrphy_dfi_p1_wrdata[9], main_k7ddrphy_dfi_p0_wrdata[41], main_k7ddrphy_dfi_p0_wrdata[9]}, main_k7ddrphy_bitslip9_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip9_value1 <= (main_k7ddrphy_bitslip9_value1 + 1'd1); end - soc_k7ddrphy_bitslip17_r <= {soc_k7ddrphy_bitslip17_i, soc_k7ddrphy_bitslip17_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip18_value <= (soc_k7ddrphy_bitslip18_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip9_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip18_value <= 1'd0; + main_k7ddrphy_bitslip9_r1 <= {main_k7ddrphy_bitslip91, main_k7ddrphy_bitslip9_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip10_value0 <= (main_k7ddrphy_bitslip10_value0 + 1'd1); end - soc_k7ddrphy_bitslip18_r <= {soc_k7ddrphy_bitslip18_i, soc_k7ddrphy_bitslip18_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip19_value <= (soc_k7ddrphy_bitslip19_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip10_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip19_value <= 1'd0; + main_k7ddrphy_bitslip10_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[42], main_k7ddrphy_dfi_p3_wrdata[10], main_k7ddrphy_dfi_p2_wrdata[42], main_k7ddrphy_dfi_p2_wrdata[10], main_k7ddrphy_dfi_p1_wrdata[42], main_k7ddrphy_dfi_p1_wrdata[10], main_k7ddrphy_dfi_p0_wrdata[42], main_k7ddrphy_dfi_p0_wrdata[10]}, main_k7ddrphy_bitslip10_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip10_value1 <= (main_k7ddrphy_bitslip10_value1 + 1'd1); end - soc_k7ddrphy_bitslip19_r <= {soc_k7ddrphy_bitslip19_i, soc_k7ddrphy_bitslip19_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip20_value <= (soc_k7ddrphy_bitslip20_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip10_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip20_value <= 1'd0; + main_k7ddrphy_bitslip10_r1 <= {main_k7ddrphy_bitslip101, main_k7ddrphy_bitslip10_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip11_value0 <= (main_k7ddrphy_bitslip11_value0 + 1'd1); end - soc_k7ddrphy_bitslip20_r <= {soc_k7ddrphy_bitslip20_i, soc_k7ddrphy_bitslip20_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip21_value <= (soc_k7ddrphy_bitslip21_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip11_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip21_value <= 1'd0; + main_k7ddrphy_bitslip11_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[43], main_k7ddrphy_dfi_p3_wrdata[11], main_k7ddrphy_dfi_p2_wrdata[43], main_k7ddrphy_dfi_p2_wrdata[11], main_k7ddrphy_dfi_p1_wrdata[43], main_k7ddrphy_dfi_p1_wrdata[11], main_k7ddrphy_dfi_p0_wrdata[43], main_k7ddrphy_dfi_p0_wrdata[11]}, main_k7ddrphy_bitslip11_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip11_value1 <= (main_k7ddrphy_bitslip11_value1 + 1'd1); end - soc_k7ddrphy_bitslip21_r <= {soc_k7ddrphy_bitslip21_i, soc_k7ddrphy_bitslip21_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip22_value <= (soc_k7ddrphy_bitslip22_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip11_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip22_value <= 1'd0; + main_k7ddrphy_bitslip11_r1 <= {main_k7ddrphy_bitslip111, main_k7ddrphy_bitslip11_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip12_value0 <= (main_k7ddrphy_bitslip12_value0 + 1'd1); end - soc_k7ddrphy_bitslip22_r <= {soc_k7ddrphy_bitslip22_i, soc_k7ddrphy_bitslip22_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip23_value <= (soc_k7ddrphy_bitslip23_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip12_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip23_value <= 1'd0; + main_k7ddrphy_bitslip12_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[44], main_k7ddrphy_dfi_p3_wrdata[12], main_k7ddrphy_dfi_p2_wrdata[44], main_k7ddrphy_dfi_p2_wrdata[12], main_k7ddrphy_dfi_p1_wrdata[44], main_k7ddrphy_dfi_p1_wrdata[12], main_k7ddrphy_dfi_p0_wrdata[44], main_k7ddrphy_dfi_p0_wrdata[12]}, main_k7ddrphy_bitslip12_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip12_value1 <= (main_k7ddrphy_bitslip12_value1 + 1'd1); end - soc_k7ddrphy_bitslip23_r <= {soc_k7ddrphy_bitslip23_i, soc_k7ddrphy_bitslip23_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip24_value <= (soc_k7ddrphy_bitslip24_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip12_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip24_value <= 1'd0; + main_k7ddrphy_bitslip12_r1 <= {main_k7ddrphy_bitslip121, main_k7ddrphy_bitslip12_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip13_value0 <= (main_k7ddrphy_bitslip13_value0 + 1'd1); end - soc_k7ddrphy_bitslip24_r <= {soc_k7ddrphy_bitslip24_i, soc_k7ddrphy_bitslip24_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip25_value <= (soc_k7ddrphy_bitslip25_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip13_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip25_value <= 1'd0; + main_k7ddrphy_bitslip13_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[45], main_k7ddrphy_dfi_p3_wrdata[13], main_k7ddrphy_dfi_p2_wrdata[45], main_k7ddrphy_dfi_p2_wrdata[13], main_k7ddrphy_dfi_p1_wrdata[45], main_k7ddrphy_dfi_p1_wrdata[13], main_k7ddrphy_dfi_p0_wrdata[45], main_k7ddrphy_dfi_p0_wrdata[13]}, main_k7ddrphy_bitslip13_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip13_value1 <= (main_k7ddrphy_bitslip13_value1 + 1'd1); end - soc_k7ddrphy_bitslip25_r <= {soc_k7ddrphy_bitslip25_i, soc_k7ddrphy_bitslip25_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip26_value <= (soc_k7ddrphy_bitslip26_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip13_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip26_value <= 1'd0; + main_k7ddrphy_bitslip13_r1 <= {main_k7ddrphy_bitslip131, main_k7ddrphy_bitslip13_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip14_value0 <= (main_k7ddrphy_bitslip14_value0 + 1'd1); end - soc_k7ddrphy_bitslip26_r <= {soc_k7ddrphy_bitslip26_i, soc_k7ddrphy_bitslip26_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip27_value <= (soc_k7ddrphy_bitslip27_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip14_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip27_value <= 1'd0; + main_k7ddrphy_bitslip14_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[46], main_k7ddrphy_dfi_p3_wrdata[14], main_k7ddrphy_dfi_p2_wrdata[46], main_k7ddrphy_dfi_p2_wrdata[14], main_k7ddrphy_dfi_p1_wrdata[46], main_k7ddrphy_dfi_p1_wrdata[14], main_k7ddrphy_dfi_p0_wrdata[46], main_k7ddrphy_dfi_p0_wrdata[14]}, main_k7ddrphy_bitslip14_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip14_value1 <= (main_k7ddrphy_bitslip14_value1 + 1'd1); end - soc_k7ddrphy_bitslip27_r <= {soc_k7ddrphy_bitslip27_i, soc_k7ddrphy_bitslip27_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip28_value <= (soc_k7ddrphy_bitslip28_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip14_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip28_value <= 1'd0; + main_k7ddrphy_bitslip14_r1 <= {main_k7ddrphy_bitslip141, main_k7ddrphy_bitslip14_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip15_value0 <= (main_k7ddrphy_bitslip15_value0 + 1'd1); end - soc_k7ddrphy_bitslip28_r <= {soc_k7ddrphy_bitslip28_i, soc_k7ddrphy_bitslip28_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip29_value <= (soc_k7ddrphy_bitslip29_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip15_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip29_value <= 1'd0; + main_k7ddrphy_bitslip15_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[47], main_k7ddrphy_dfi_p3_wrdata[15], main_k7ddrphy_dfi_p2_wrdata[47], main_k7ddrphy_dfi_p2_wrdata[15], main_k7ddrphy_dfi_p1_wrdata[47], main_k7ddrphy_dfi_p1_wrdata[15], main_k7ddrphy_dfi_p0_wrdata[47], main_k7ddrphy_dfi_p0_wrdata[15]}, main_k7ddrphy_bitslip15_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip15_value1 <= (main_k7ddrphy_bitslip15_value1 + 1'd1); end - soc_k7ddrphy_bitslip29_r <= {soc_k7ddrphy_bitslip29_i, soc_k7ddrphy_bitslip29_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip30_value <= (soc_k7ddrphy_bitslip30_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip15_value1 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip30_value <= 1'd0; + main_k7ddrphy_bitslip15_r1 <= {main_k7ddrphy_bitslip151, main_k7ddrphy_bitslip15_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip16_value0 <= (main_k7ddrphy_bitslip16_value0 + 1'd1); end - soc_k7ddrphy_bitslip30_r <= {soc_k7ddrphy_bitslip30_i, soc_k7ddrphy_bitslip30_r[23:8]}; - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin - soc_k7ddrphy_bitslip31_value <= (soc_k7ddrphy_bitslip31_value + 1'd1); + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip16_value0 <= 3'd7; end - if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_k7ddrphy_bitslip31_value <= 1'd0; + main_k7ddrphy_bitslip16_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[48], main_k7ddrphy_dfi_p3_wrdata[16], main_k7ddrphy_dfi_p2_wrdata[48], main_k7ddrphy_dfi_p2_wrdata[16], main_k7ddrphy_dfi_p1_wrdata[48], main_k7ddrphy_dfi_p1_wrdata[16], main_k7ddrphy_dfi_p0_wrdata[48], main_k7ddrphy_dfi_p0_wrdata[16]}, main_k7ddrphy_bitslip16_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip16_value1 <= (main_k7ddrphy_bitslip16_value1 + 1'd1); end - soc_k7ddrphy_bitslip31_r <= {soc_k7ddrphy_bitslip31_i, soc_k7ddrphy_bitslip31_r[23:8]}; - if (soc_litedramcore_inti_p0_rddata_valid) begin - soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip16_value1 <= 3'd7; end - if (soc_litedramcore_inti_p1_rddata_valid) begin - soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + main_k7ddrphy_bitslip16_r1 <= {main_k7ddrphy_bitslip161, main_k7ddrphy_bitslip16_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip17_value0 <= (main_k7ddrphy_bitslip17_value0 + 1'd1); end - if (soc_litedramcore_inti_p2_rddata_valid) begin - soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip17_value0 <= 3'd7; end - if (soc_litedramcore_inti_p3_rddata_valid) begin - soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + main_k7ddrphy_bitslip17_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[49], main_k7ddrphy_dfi_p3_wrdata[17], main_k7ddrphy_dfi_p2_wrdata[49], main_k7ddrphy_dfi_p2_wrdata[17], main_k7ddrphy_dfi_p1_wrdata[49], main_k7ddrphy_dfi_p1_wrdata[17], main_k7ddrphy_dfi_p0_wrdata[49], main_k7ddrphy_dfi_p0_wrdata[17]}, main_k7ddrphy_bitslip17_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip17_value1 <= (main_k7ddrphy_bitslip17_value1 + 1'd1); end - if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin - soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip17_value1 <= 3'd7; + end + main_k7ddrphy_bitslip17_r1 <= {main_k7ddrphy_bitslip171, main_k7ddrphy_bitslip17_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip18_value0 <= (main_k7ddrphy_bitslip18_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip18_value0 <= 3'd7; + end + main_k7ddrphy_bitslip18_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[50], main_k7ddrphy_dfi_p3_wrdata[18], main_k7ddrphy_dfi_p2_wrdata[50], main_k7ddrphy_dfi_p2_wrdata[18], main_k7ddrphy_dfi_p1_wrdata[50], main_k7ddrphy_dfi_p1_wrdata[18], main_k7ddrphy_dfi_p0_wrdata[50], main_k7ddrphy_dfi_p0_wrdata[18]}, main_k7ddrphy_bitslip18_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip18_value1 <= (main_k7ddrphy_bitslip18_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip18_value1 <= 3'd7; + end + main_k7ddrphy_bitslip18_r1 <= {main_k7ddrphy_bitslip181, main_k7ddrphy_bitslip18_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip19_value0 <= (main_k7ddrphy_bitslip19_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip19_value0 <= 3'd7; + end + main_k7ddrphy_bitslip19_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[51], main_k7ddrphy_dfi_p3_wrdata[19], main_k7ddrphy_dfi_p2_wrdata[51], main_k7ddrphy_dfi_p2_wrdata[19], main_k7ddrphy_dfi_p1_wrdata[51], main_k7ddrphy_dfi_p1_wrdata[19], main_k7ddrphy_dfi_p0_wrdata[51], main_k7ddrphy_dfi_p0_wrdata[19]}, main_k7ddrphy_bitslip19_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip19_value1 <= (main_k7ddrphy_bitslip19_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip19_value1 <= 3'd7; + end + main_k7ddrphy_bitslip19_r1 <= {main_k7ddrphy_bitslip191, main_k7ddrphy_bitslip19_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip20_value0 <= (main_k7ddrphy_bitslip20_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip20_value0 <= 3'd7; + end + main_k7ddrphy_bitslip20_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[52], main_k7ddrphy_dfi_p3_wrdata[20], main_k7ddrphy_dfi_p2_wrdata[52], main_k7ddrphy_dfi_p2_wrdata[20], main_k7ddrphy_dfi_p1_wrdata[52], main_k7ddrphy_dfi_p1_wrdata[20], main_k7ddrphy_dfi_p0_wrdata[52], main_k7ddrphy_dfi_p0_wrdata[20]}, main_k7ddrphy_bitslip20_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip20_value1 <= (main_k7ddrphy_bitslip20_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip20_value1 <= 3'd7; + end + main_k7ddrphy_bitslip20_r1 <= {main_k7ddrphy_bitslip201, main_k7ddrphy_bitslip20_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip21_value0 <= (main_k7ddrphy_bitslip21_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip21_value0 <= 3'd7; + end + main_k7ddrphy_bitslip21_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[53], main_k7ddrphy_dfi_p3_wrdata[21], main_k7ddrphy_dfi_p2_wrdata[53], main_k7ddrphy_dfi_p2_wrdata[21], main_k7ddrphy_dfi_p1_wrdata[53], main_k7ddrphy_dfi_p1_wrdata[21], main_k7ddrphy_dfi_p0_wrdata[53], main_k7ddrphy_dfi_p0_wrdata[21]}, main_k7ddrphy_bitslip21_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip21_value1 <= (main_k7ddrphy_bitslip21_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip21_value1 <= 3'd7; + end + main_k7ddrphy_bitslip21_r1 <= {main_k7ddrphy_bitslip211, main_k7ddrphy_bitslip21_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip22_value0 <= (main_k7ddrphy_bitslip22_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip22_value0 <= 3'd7; + end + main_k7ddrphy_bitslip22_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[54], main_k7ddrphy_dfi_p3_wrdata[22], main_k7ddrphy_dfi_p2_wrdata[54], main_k7ddrphy_dfi_p2_wrdata[22], main_k7ddrphy_dfi_p1_wrdata[54], main_k7ddrphy_dfi_p1_wrdata[22], main_k7ddrphy_dfi_p0_wrdata[54], main_k7ddrphy_dfi_p0_wrdata[22]}, main_k7ddrphy_bitslip22_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip22_value1 <= (main_k7ddrphy_bitslip22_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip22_value1 <= 3'd7; + end + main_k7ddrphy_bitslip22_r1 <= {main_k7ddrphy_bitslip221, main_k7ddrphy_bitslip22_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip23_value0 <= (main_k7ddrphy_bitslip23_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip23_value0 <= 3'd7; + end + main_k7ddrphy_bitslip23_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[55], main_k7ddrphy_dfi_p3_wrdata[23], main_k7ddrphy_dfi_p2_wrdata[55], main_k7ddrphy_dfi_p2_wrdata[23], main_k7ddrphy_dfi_p1_wrdata[55], main_k7ddrphy_dfi_p1_wrdata[23], main_k7ddrphy_dfi_p0_wrdata[55], main_k7ddrphy_dfi_p0_wrdata[23]}, main_k7ddrphy_bitslip23_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip23_value1 <= (main_k7ddrphy_bitslip23_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip23_value1 <= 3'd7; + end + main_k7ddrphy_bitslip23_r1 <= {main_k7ddrphy_bitslip231, main_k7ddrphy_bitslip23_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip24_value0 <= (main_k7ddrphy_bitslip24_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip24_value0 <= 3'd7; + end + main_k7ddrphy_bitslip24_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[56], main_k7ddrphy_dfi_p3_wrdata[24], main_k7ddrphy_dfi_p2_wrdata[56], main_k7ddrphy_dfi_p2_wrdata[24], main_k7ddrphy_dfi_p1_wrdata[56], main_k7ddrphy_dfi_p1_wrdata[24], main_k7ddrphy_dfi_p0_wrdata[56], main_k7ddrphy_dfi_p0_wrdata[24]}, main_k7ddrphy_bitslip24_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip24_value1 <= (main_k7ddrphy_bitslip24_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip24_value1 <= 3'd7; + end + main_k7ddrphy_bitslip24_r1 <= {main_k7ddrphy_bitslip241, main_k7ddrphy_bitslip24_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip25_value0 <= (main_k7ddrphy_bitslip25_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip25_value0 <= 3'd7; + end + main_k7ddrphy_bitslip25_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[57], main_k7ddrphy_dfi_p3_wrdata[25], main_k7ddrphy_dfi_p2_wrdata[57], main_k7ddrphy_dfi_p2_wrdata[25], main_k7ddrphy_dfi_p1_wrdata[57], main_k7ddrphy_dfi_p1_wrdata[25], main_k7ddrphy_dfi_p0_wrdata[57], main_k7ddrphy_dfi_p0_wrdata[25]}, main_k7ddrphy_bitslip25_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip25_value1 <= (main_k7ddrphy_bitslip25_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip25_value1 <= 3'd7; + end + main_k7ddrphy_bitslip25_r1 <= {main_k7ddrphy_bitslip251, main_k7ddrphy_bitslip25_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip26_value0 <= (main_k7ddrphy_bitslip26_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip26_value0 <= 3'd7; + end + main_k7ddrphy_bitslip26_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[58], main_k7ddrphy_dfi_p3_wrdata[26], main_k7ddrphy_dfi_p2_wrdata[58], main_k7ddrphy_dfi_p2_wrdata[26], main_k7ddrphy_dfi_p1_wrdata[58], main_k7ddrphy_dfi_p1_wrdata[26], main_k7ddrphy_dfi_p0_wrdata[58], main_k7ddrphy_dfi_p0_wrdata[26]}, main_k7ddrphy_bitslip26_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip26_value1 <= (main_k7ddrphy_bitslip26_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip26_value1 <= 3'd7; + end + main_k7ddrphy_bitslip26_r1 <= {main_k7ddrphy_bitslip261, main_k7ddrphy_bitslip26_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip27_value0 <= (main_k7ddrphy_bitslip27_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip27_value0 <= 3'd7; + end + main_k7ddrphy_bitslip27_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[59], main_k7ddrphy_dfi_p3_wrdata[27], main_k7ddrphy_dfi_p2_wrdata[59], main_k7ddrphy_dfi_p2_wrdata[27], main_k7ddrphy_dfi_p1_wrdata[59], main_k7ddrphy_dfi_p1_wrdata[27], main_k7ddrphy_dfi_p0_wrdata[59], main_k7ddrphy_dfi_p0_wrdata[27]}, main_k7ddrphy_bitslip27_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip27_value1 <= (main_k7ddrphy_bitslip27_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip27_value1 <= 3'd7; + end + main_k7ddrphy_bitslip27_r1 <= {main_k7ddrphy_bitslip271, main_k7ddrphy_bitslip27_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip28_value0 <= (main_k7ddrphy_bitslip28_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip28_value0 <= 3'd7; + end + main_k7ddrphy_bitslip28_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[60], main_k7ddrphy_dfi_p3_wrdata[28], main_k7ddrphy_dfi_p2_wrdata[60], main_k7ddrphy_dfi_p2_wrdata[28], main_k7ddrphy_dfi_p1_wrdata[60], main_k7ddrphy_dfi_p1_wrdata[28], main_k7ddrphy_dfi_p0_wrdata[60], main_k7ddrphy_dfi_p0_wrdata[28]}, main_k7ddrphy_bitslip28_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip28_value1 <= (main_k7ddrphy_bitslip28_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip28_value1 <= 3'd7; + end + main_k7ddrphy_bitslip28_r1 <= {main_k7ddrphy_bitslip281, main_k7ddrphy_bitslip28_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip29_value0 <= (main_k7ddrphy_bitslip29_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip29_value0 <= 3'd7; + end + main_k7ddrphy_bitslip29_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[61], main_k7ddrphy_dfi_p3_wrdata[29], main_k7ddrphy_dfi_p2_wrdata[61], main_k7ddrphy_dfi_p2_wrdata[29], main_k7ddrphy_dfi_p1_wrdata[61], main_k7ddrphy_dfi_p1_wrdata[29], main_k7ddrphy_dfi_p0_wrdata[61], main_k7ddrphy_dfi_p0_wrdata[29]}, main_k7ddrphy_bitslip29_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip29_value1 <= (main_k7ddrphy_bitslip29_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip29_value1 <= 3'd7; + end + main_k7ddrphy_bitslip29_r1 <= {main_k7ddrphy_bitslip291, main_k7ddrphy_bitslip29_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip30_value0 <= (main_k7ddrphy_bitslip30_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip30_value0 <= 3'd7; + end + main_k7ddrphy_bitslip30_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[62], main_k7ddrphy_dfi_p3_wrdata[30], main_k7ddrphy_dfi_p2_wrdata[62], main_k7ddrphy_dfi_p2_wrdata[30], main_k7ddrphy_dfi_p1_wrdata[62], main_k7ddrphy_dfi_p1_wrdata[30], main_k7ddrphy_dfi_p0_wrdata[62], main_k7ddrphy_dfi_p0_wrdata[30]}, main_k7ddrphy_bitslip30_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip30_value1 <= (main_k7ddrphy_bitslip30_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip30_value1 <= 3'd7; + end + main_k7ddrphy_bitslip30_r1 <= {main_k7ddrphy_bitslip301, main_k7ddrphy_bitslip30_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip31_value0 <= (main_k7ddrphy_bitslip31_value0 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip31_value0 <= 3'd7; + end + main_k7ddrphy_bitslip31_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[63], main_k7ddrphy_dfi_p3_wrdata[31], main_k7ddrphy_dfi_p2_wrdata[63], main_k7ddrphy_dfi_p2_wrdata[31], main_k7ddrphy_dfi_p1_wrdata[63], main_k7ddrphy_dfi_p1_wrdata[31], main_k7ddrphy_dfi_p0_wrdata[63], main_k7ddrphy_dfi_p0_wrdata[31]}, main_k7ddrphy_bitslip31_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip31_value1 <= (main_k7ddrphy_bitslip31_value1 + 1'd1); + end + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip31_value1 <= 3'd7; + end + main_k7ddrphy_bitslip31_r1 <= {main_k7ddrphy_bitslip311, main_k7ddrphy_bitslip31_r1[15:8]}; + main_k7ddrphy_rddata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_rddata_en | main_k7ddrphy_dfi_p1_rddata_en) | main_k7ddrphy_dfi_p2_rddata_en) | main_k7ddrphy_dfi_p3_rddata_en); + main_k7ddrphy_rddata_en_tappeddelayline1 <= main_k7ddrphy_rddata_en_tappeddelayline0; + main_k7ddrphy_rddata_en_tappeddelayline2 <= main_k7ddrphy_rddata_en_tappeddelayline1; + main_k7ddrphy_rddata_en_tappeddelayline3 <= main_k7ddrphy_rddata_en_tappeddelayline2; + main_k7ddrphy_rddata_en_tappeddelayline4 <= main_k7ddrphy_rddata_en_tappeddelayline3; + main_k7ddrphy_rddata_en_tappeddelayline5 <= main_k7ddrphy_rddata_en_tappeddelayline4; + main_k7ddrphy_rddata_en_tappeddelayline6 <= main_k7ddrphy_rddata_en_tappeddelayline5; + main_k7ddrphy_rddata_en_tappeddelayline7 <= main_k7ddrphy_rddata_en_tappeddelayline6; + main_k7ddrphy_wrdata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_wrdata_en | main_k7ddrphy_dfi_p1_wrdata_en) | main_k7ddrphy_dfi_p2_wrdata_en) | main_k7ddrphy_dfi_p3_wrdata_en); + main_k7ddrphy_wrdata_en_tappeddelayline1 <= main_k7ddrphy_wrdata_en_tappeddelayline0; + main_k7ddrphy_wrdata_en_tappeddelayline2 <= main_k7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_inti_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata; + end + if (main_litedramcore_inti_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata; + end + if (main_litedramcore_inti_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata; + end + if (main_litedramcore_inti_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - soc_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - soc_litedramcore_postponer_req_o <= 1'd0; - if (soc_litedramcore_postponer_req_i) begin - soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); - if ((soc_litedramcore_postponer_count == 1'd0)) begin - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (soc_litedramcore_sequencer_start0) begin - soc_litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_litedramcore_sequencer_done1) begin - if ((soc_litedramcore_sequencer_count != 1'd0)) begin - soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); - end - end - end - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd1; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd0; - end - if ((soc_litedramcore_sequencer_counter == 6'd55)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 6'd55)) begin - soc_litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_counter == 6'd55)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 6'd55)) begin + main_litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_counter != 1'd0)) begin + main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin - soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_zqcs_executer_done <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin + main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_litedramcore_bankmachine0_row_close) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine0_row_open) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd1; - soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; - soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid; + main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first; + main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine0_twtpcon_valid) begin - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin - soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trccon_valid) begin - soc_litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin - soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trascon_valid) begin - soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_litedramcore_bankmachine1_row_close) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine1_row_open) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd1; - soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; - soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid; + main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first; + main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine1_twtpcon_valid) begin - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin - soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trccon_valid) begin - soc_litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin - soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trascon_valid) begin - soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_litedramcore_bankmachine2_row_close) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine2_row_open) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd1; - soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; - soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid; + main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first; + main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine2_twtpcon_valid) begin - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin - soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trccon_valid) begin - soc_litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin - soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trascon_valid) begin - soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_litedramcore_bankmachine3_row_close) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine3_row_open) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd1; - soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; - soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid; + main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first; + main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine3_twtpcon_valid) begin - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin - soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trccon_valid) begin - soc_litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin - soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trascon_valid) begin - soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_litedramcore_bankmachine4_row_close) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine4_row_open) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd1; - soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; - soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid; + main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first; + main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine4_twtpcon_valid) begin - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin - soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trccon_valid) begin - soc_litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin - soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trascon_valid) begin - soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_litedramcore_bankmachine5_row_close) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine5_row_open) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd1; - soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; - soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid; + main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first; + main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine5_twtpcon_valid) begin - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin - soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trccon_valid) begin - soc_litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin - soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trascon_valid) begin - soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_litedramcore_bankmachine6_row_close) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine6_row_open) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd1; - soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; - soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid; + main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first; + main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine6_twtpcon_valid) begin - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin - soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trccon_valid) begin - soc_litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin - soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trascon_valid) begin - soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_litedramcore_bankmachine7_row_close) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine7_row_open) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd1; - soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; - soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid; + main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first; + main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine7_twtpcon_valid) begin - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin - soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trccon_valid) begin - soc_litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin - soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trascon_valid) begin - soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_litedramcore_en0)) begin - soc_litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~soc_litedramcore_max_time0)) begin - soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~soc_litedramcore_en1)) begin - soc_litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~soc_litedramcore_max_time1)) begin - soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (soc_litedramcore_choose_cmd_ce) begin - case (soc_litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -15392,26 +19605,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -15421,26 +19634,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -15450,26 +19663,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -15479,26 +19692,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -15508,26 +19721,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -15537,26 +19750,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -15566,26 +19779,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -15596,29 +19809,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_litedramcore_choose_req_ce) begin - case (soc_litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -15628,26 +19841,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -15657,26 +19870,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -15686,26 +19899,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -15715,26 +19928,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -15744,26 +19957,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -15773,26 +19986,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -15802,26 +20015,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -15832,641 +20045,999 @@ always @(posedge sys_clk) begin end endcase end - soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; - soc_litedramcore_dfi_p0_address <= vns_array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; - soc_litedramcore_dfi_p1_address <= vns_array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; - soc_litedramcore_dfi_p2_address <= vns_array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; - soc_litedramcore_dfi_p3_address <= vns_array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_litedramcore_trrdcon_valid) begin - soc_litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_array_muxed0; + main_litedramcore_dfi_p0_address <= builder_array_muxed1; + main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2); + main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3); + main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4); + main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5; + main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_array_muxed7; + main_litedramcore_dfi_p1_address <= builder_array_muxed8; + main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9); + main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10); + main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11); + main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12; + main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_array_muxed14; + main_litedramcore_dfi_p2_address <= builder_array_muxed15; + main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16); + main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17); + main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18); + main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19; + main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_array_muxed21; + main_litedramcore_dfi_p3_address <= builder_array_muxed22; + main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23); + main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24); + main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25); + main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26; + main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_trrdcon_ready)) begin - soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); - if ((soc_litedramcore_trrdcon_count == 1'd1)) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; - if ((soc_litedramcore_tfawcon_count < 3'd4)) begin - if ((soc_litedramcore_tfawcon_count == 2'd3)) begin - soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - soc_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_litedramcore_tccdcon_valid) begin - soc_litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_tccdcon_ready)) begin - soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); - if ((soc_litedramcore_tccdcon_count == 1'd1)) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_litedramcore_twtrcon_valid) begin - soc_litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_twtrcon_ready)) begin - soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); - if ((soc_litedramcore_twtrcon_count == 1'd1)) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_litedramcore_dat_w_next_value_ce0) begin + builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0; + end + if (builder_litedramcore_adr_next_value_ce1) begin + builder_litedramcore_adr <= builder_litedramcore_adr_next_value1; + end + if (builder_litedramcore_we_next_value_ce2) begin + builder_litedramcore_we <= builder_litedramcore_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (vns_csrbank0_init_done0_re) begin - soc_init_done_storage <= vns_csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank0_init_done0_re; - if (vns_csrbank0_init_error0_re) begin - soc_init_error_storage <= vns_csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank0_init_error0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[3:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd2: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 2'd3: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_cdly_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wlevel_strobe_w; end 3'd4: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_cdly_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_rst_w; end 3'd5: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_inc_w; end 3'd6: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 3'd7: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_rst_w; end 4'd8: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_inc_w; end 4'd9: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_rst_w; end 4'd10: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_w; end 4'd11: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_rst_w; end 4'd12: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dqs_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_inc_w; end 4'd13: begin - vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dqs_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_rst_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_inc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_rst_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_w; + end + 5'd17: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; + end + 5'd18: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (vns_csrbank1_half_sys8x_taps0_re) begin - soc_k7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + if (builder_csrbank1_rst0_re) begin + main_k7ddrphy_rst_storage <= builder_csrbank1_rst0_r; + end + main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - soc_k7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; - if (vns_csrbank1_wlevel_en0_re) begin - soc_k7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_k7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - soc_k7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; - if (vns_csrbank1_dly_sel0_re) begin - soc_k7ddrphy_dly_sel_storage[3:0] <= vns_csrbank1_dly_sel0_r; + main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r; end - soc_k7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[5:0]) + main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_rdphase0_re) begin + main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + end + main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + end + main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata7_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata6_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata5_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata4_w; end 4'd10: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; end 4'd11: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; end 4'd12: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end 4'd13: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 4'd14: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata7_w; end 4'd15: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata6_w; end 5'd16: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata5_w; end 5'd17: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata4_w; end 5'd18: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; end 5'd19: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; end 5'd20: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end 5'd21: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end 5'd22: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 5'd23: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata1_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 5'd24: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; end 5'd25: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 5'd26: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 5'd27: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata7_w; end 5'd28: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata6_w; end 5'd29: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata5_w; end 5'd30: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata4_w; end 5'd31: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; end 6'd32: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; + end + 6'd33: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; + end + 6'd34: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; + end + 6'd35: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata7_w; + end + 6'd36: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata6_w; + end + 6'd37: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata5_w; + end + 6'd38: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata4_w; + end + 6'd39: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; + end + 6'd40: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; + end + 6'd41: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; + end + 6'd42: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; + end + 6'd43: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; + end + 6'd44: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; + end + 6'd45: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; + end + 6'd46: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; + end + 6'd47: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; + end + 6'd48: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata7_w; + end + 6'd49: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata6_w; + end + 6'd50: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata5_w; + end + 6'd51: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata4_w; + end + 6'd52: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; + end + 6'd53: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; + end + 6'd54: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; + end + 6'd55: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; + end + 6'd56: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata7_w; + end + 6'd57: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata6_w; + end + 6'd58: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata5_w; + end + 6'd59: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata4_w; + end + 6'd60: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; + end + 6'd61: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; + end + 6'd62: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; + end + 6'd63: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; + end + 7'd64: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; + end + 7'd65: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; + end + 7'd66: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; + end + 7'd67: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; + end + 7'd68: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; + end + 7'd69: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata7_w; + end + 7'd70: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata6_w; + end + 7'd71: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata5_w; + end + 7'd72: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata4_w; + end + 7'd73: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; + end + 7'd74: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; + end + 7'd75: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; + end + 7'd76: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; + end + 7'd77: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata7_w; + end + 7'd78: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata6_w; + end + 7'd79: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata5_w; + end + 7'd80: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata4_w; + end + 7'd81: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; + end + 7'd82: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; + end + 7'd83: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; + end + 7'd84: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank2_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + end + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; + end + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address1_re) begin + main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r; end - soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; - if (vns_csrbank2_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; end - soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; - if (vns_csrbank2_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[14:0] <= vns_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; - if (vns_csrbank2_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata7_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi0_wrdata7_r; end - soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; - if (vns_csrbank2_dfii_pi0_wrdata1_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi0_wrdata1_r; + if (builder_csrbank2_dfii_pi0_wrdata6_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi0_wrdata6_r; end - if (vns_csrbank2_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + if (builder_csrbank2_dfii_pi0_wrdata5_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi0_wrdata5_r; end - soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; - if (vns_csrbank2_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + if (builder_csrbank2_dfii_pi0_wrdata4_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi0_wrdata4_r; end - soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; - if (vns_csrbank2_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[14:0] <= vns_csrbank2_dfii_pi1_address0_r; + if (builder_csrbank2_dfii_pi0_wrdata3_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; end - soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; - if (vns_csrbank2_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + if (builder_csrbank2_dfii_pi0_wrdata2_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; end - soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; - if (vns_csrbank2_dfii_pi1_wrdata1_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi1_wrdata1_r; + if (builder_csrbank2_dfii_pi0_wrdata1_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; end - if (vns_csrbank2_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; - if (vns_csrbank2_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end - soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; - if (vns_csrbank2_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[14:0] <= vns_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address1_re) begin + main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r; end - soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; - if (vns_csrbank2_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; end - soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; - if (vns_csrbank2_dfii_pi2_wrdata1_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi2_wrdata1_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - if (vns_csrbank2_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata7_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi1_wrdata7_r; end - soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; - if (vns_csrbank2_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + if (builder_csrbank2_dfii_pi1_wrdata6_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi1_wrdata6_r; end - soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; - if (vns_csrbank2_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[14:0] <= vns_csrbank2_dfii_pi3_address0_r; + if (builder_csrbank2_dfii_pi1_wrdata5_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi1_wrdata5_r; end - soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; - if (vns_csrbank2_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + if (builder_csrbank2_dfii_pi1_wrdata4_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi1_wrdata4_r; end - soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; - if (vns_csrbank2_dfii_pi3_wrdata1_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi3_wrdata1_r; + if (builder_csrbank2_dfii_pi1_wrdata3_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; end - if (vns_csrbank2_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + if (builder_csrbank2_dfii_pi1_wrdata2_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; end - soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + if (builder_csrbank2_dfii_pi1_wrdata1_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; + end + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + end + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; + end + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address1_re) begin + main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r; + end + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + end + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + end + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata7_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi2_wrdata7_r; + end + if (builder_csrbank2_dfii_pi2_wrdata6_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi2_wrdata6_r; + end + if (builder_csrbank2_dfii_pi2_wrdata5_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi2_wrdata5_r; + end + if (builder_csrbank2_dfii_pi2_wrdata4_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi2_wrdata4_r; + end + if (builder_csrbank2_dfii_pi2_wrdata3_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; + end + if (builder_csrbank2_dfii_pi2_wrdata2_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; + end + if (builder_csrbank2_dfii_pi2_wrdata1_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; + end + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + end + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; + end + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address1_re) begin + main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r; + end + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + end + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + end + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata7_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi3_wrdata7_r; + end + if (builder_csrbank2_dfii_pi3_wrdata6_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi3_wrdata6_r; + end + if (builder_csrbank2_dfii_pi3_wrdata5_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi3_wrdata5_r; + end + if (builder_csrbank2_dfii_pi3_wrdata4_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi3_wrdata4_r; + end + if (builder_csrbank2_dfii_pi3_wrdata3_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; + end + if (builder_csrbank2_dfii_pi3_wrdata2_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; + end + if (builder_csrbank2_dfii_pi3_wrdata1_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; + end + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + end + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; if (sys_rst) begin - soc_k7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_k7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_k7ddrphy_wlevel_en_storage <= 1'd0; - soc_k7ddrphy_wlevel_en_re <= 1'd0; - soc_k7ddrphy_dly_sel_storage <= 4'd0; - soc_k7ddrphy_dly_sel_re <= 1'd0; - soc_k7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_k7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_k7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_k7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_k7ddrphy_dqs_oe_delayed <= 1'd0; - soc_k7ddrphy_dq_oe_delayed <= 1'd0; - soc_k7ddrphy_bitslip0_value <= 4'd0; - soc_k7ddrphy_bitslip1_value <= 4'd0; - soc_k7ddrphy_bitslip2_value <= 4'd0; - soc_k7ddrphy_bitslip3_value <= 4'd0; - soc_k7ddrphy_bitslip4_value <= 4'd0; - soc_k7ddrphy_bitslip5_value <= 4'd0; - soc_k7ddrphy_bitslip6_value <= 4'd0; - soc_k7ddrphy_bitslip7_value <= 4'd0; - soc_k7ddrphy_bitslip8_value <= 4'd0; - soc_k7ddrphy_bitslip9_value <= 4'd0; - soc_k7ddrphy_bitslip10_value <= 4'd0; - soc_k7ddrphy_bitslip11_value <= 4'd0; - soc_k7ddrphy_bitslip12_value <= 4'd0; - soc_k7ddrphy_bitslip13_value <= 4'd0; - soc_k7ddrphy_bitslip14_value <= 4'd0; - soc_k7ddrphy_bitslip15_value <= 4'd0; - soc_k7ddrphy_bitslip16_value <= 4'd0; - soc_k7ddrphy_bitslip17_value <= 4'd0; - soc_k7ddrphy_bitslip18_value <= 4'd0; - soc_k7ddrphy_bitslip19_value <= 4'd0; - soc_k7ddrphy_bitslip20_value <= 4'd0; - soc_k7ddrphy_bitslip21_value <= 4'd0; - soc_k7ddrphy_bitslip22_value <= 4'd0; - soc_k7ddrphy_bitslip23_value <= 4'd0; - soc_k7ddrphy_bitslip24_value <= 4'd0; - soc_k7ddrphy_bitslip25_value <= 4'd0; - soc_k7ddrphy_bitslip26_value <= 4'd0; - soc_k7ddrphy_bitslip27_value <= 4'd0; - soc_k7ddrphy_bitslip28_value <= 4'd0; - soc_k7ddrphy_bitslip29_value <= 4'd0; - soc_k7ddrphy_bitslip30_value <= 4'd0; - soc_k7ddrphy_bitslip31_value <= 4'd0; - soc_k7ddrphy_rddata_en_last <= 8'd0; - soc_k7ddrphy_wrdata_en_last <= 4'd0; - soc_litedramcore_storage <= 4'd1; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; - soc_litedramcore_phaseinjector0_command_re <= 1'd0; - soc_litedramcore_phaseinjector0_address_re <= 1'd0; - soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector0_status <= 64'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; - soc_litedramcore_phaseinjector1_command_re <= 1'd0; - soc_litedramcore_phaseinjector1_address_re <= 1'd0; - soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector1_status <= 64'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; - soc_litedramcore_phaseinjector2_command_re <= 1'd0; - soc_litedramcore_phaseinjector2_address_re <= 1'd0; - soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector2_status <= 64'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; - soc_litedramcore_phaseinjector3_command_re <= 1'd0; - soc_litedramcore_phaseinjector3_address_re <= 1'd0; - soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector3_status <= 64'd0; - soc_litedramcore_dfi_p0_address <= 15'd0; - soc_litedramcore_dfi_p0_bank <= 3'd0; - soc_litedramcore_dfi_p0_cas_n <= 1'd1; - soc_litedramcore_dfi_p0_cs_n <= 1'd1; - soc_litedramcore_dfi_p0_ras_n <= 1'd1; - soc_litedramcore_dfi_p0_we_n <= 1'd1; - soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p0_rddata_en <= 1'd0; - soc_litedramcore_dfi_p1_address <= 15'd0; - soc_litedramcore_dfi_p1_bank <= 3'd0; - soc_litedramcore_dfi_p1_cas_n <= 1'd1; - soc_litedramcore_dfi_p1_cs_n <= 1'd1; - soc_litedramcore_dfi_p1_ras_n <= 1'd1; - soc_litedramcore_dfi_p1_we_n <= 1'd1; - soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p1_rddata_en <= 1'd0; - soc_litedramcore_dfi_p2_address <= 15'd0; - soc_litedramcore_dfi_p2_bank <= 3'd0; - soc_litedramcore_dfi_p2_cas_n <= 1'd1; - soc_litedramcore_dfi_p2_cs_n <= 1'd1; - soc_litedramcore_dfi_p2_ras_n <= 1'd1; - soc_litedramcore_dfi_p2_we_n <= 1'd1; - soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p2_rddata_en <= 1'd0; - soc_litedramcore_dfi_p3_address <= 15'd0; - soc_litedramcore_dfi_p3_bank <= 3'd0; - soc_litedramcore_dfi_p3_cas_n <= 1'd1; - soc_litedramcore_dfi_p3_cs_n <= 1'd1; - soc_litedramcore_dfi_p3_ras_n <= 1'd1; - soc_litedramcore_dfi_p3_we_n <= 1'd1; - soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p3_rddata_en <= 1'd0; - soc_litedramcore_timer_count1 <= 10'd781; - soc_litedramcore_postponer_req_o <= 1'd0; - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 6'd0; - soc_litedramcore_sequencer_count <= 1'd0; - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine0_row <= 15'd0; - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trccon_count <= 3'd0; - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trascon_count <= 3'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine1_row <= 15'd0; - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trccon_count <= 3'd0; - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trascon_count <= 3'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine2_row <= 15'd0; - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trccon_count <= 3'd0; - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trascon_count <= 3'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine3_row <= 15'd0; - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trccon_count <= 3'd0; - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trascon_count <= 3'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine4_row <= 15'd0; - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trccon_count <= 3'd0; - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trascon_count <= 3'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine5_row <= 15'd0; - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trccon_count <= 3'd0; - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trascon_count <= 3'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine6_row <= 15'd0; - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trccon_count <= 3'd0; - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trascon_count <= 3'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine7_row <= 15'd0; - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trccon_count <= 3'd0; - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trascon_count <= 3'd0; - soc_litedramcore_choose_cmd_grant <= 3'd0; - soc_litedramcore_choose_req_grant <= 3'd0; - soc_litedramcore_trrdcon_ready <= 1'd0; - soc_litedramcore_trrdcon_count <= 1'd0; - soc_litedramcore_tfawcon_ready <= 1'd1; - soc_litedramcore_tfawcon_window <= 5'd0; - soc_litedramcore_tccdcon_ready <= 1'd0; - soc_litedramcore_tccdcon_count <= 1'd0; - soc_litedramcore_twtrcon_ready <= 1'd0; - soc_litedramcore_twtrcon_count <= 3'd0; - soc_litedramcore_time0 <= 5'd0; - soc_litedramcore_time1 <= 4'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; + main_k7ddrphy_rst_storage <= 1'd0; + main_k7ddrphy_rst_re <= 1'd0; + main_k7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_k7ddrphy_half_sys8x_taps_re <= 1'd0; + main_k7ddrphy_wlevel_en_storage <= 1'd0; + main_k7ddrphy_wlevel_en_re <= 1'd0; + main_k7ddrphy_dly_sel_storage <= 4'd0; + main_k7ddrphy_dly_sel_re <= 1'd0; + main_k7ddrphy_rdphase_storage <= 2'd1; + main_k7ddrphy_rdphase_re <= 1'd0; + main_k7ddrphy_wrphase_storage <= 2'd2; + main_k7ddrphy_wrphase_re <= 1'd0; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_k7ddrphy_bitslip0_value0 <= 3'd7; + main_k7ddrphy_bitslip1_value0 <= 3'd7; + main_k7ddrphy_bitslip2_value0 <= 3'd7; + main_k7ddrphy_bitslip3_value0 <= 3'd7; + main_k7ddrphy_bitslip0_value1 <= 3'd7; + main_k7ddrphy_bitslip1_value1 <= 3'd7; + main_k7ddrphy_bitslip2_value1 <= 3'd7; + main_k7ddrphy_bitslip3_value1 <= 3'd7; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_k7ddrphy_bitslip0_value2 <= 3'd7; + main_k7ddrphy_bitslip0_value3 <= 3'd7; + main_k7ddrphy_bitslip1_value2 <= 3'd7; + main_k7ddrphy_bitslip1_value3 <= 3'd7; + main_k7ddrphy_bitslip2_value2 <= 3'd7; + main_k7ddrphy_bitslip2_value3 <= 3'd7; + main_k7ddrphy_bitslip3_value2 <= 3'd7; + main_k7ddrphy_bitslip3_value3 <= 3'd7; + main_k7ddrphy_bitslip4_value0 <= 3'd7; + main_k7ddrphy_bitslip4_value1 <= 3'd7; + main_k7ddrphy_bitslip5_value0 <= 3'd7; + main_k7ddrphy_bitslip5_value1 <= 3'd7; + main_k7ddrphy_bitslip6_value0 <= 3'd7; + main_k7ddrphy_bitslip6_value1 <= 3'd7; + main_k7ddrphy_bitslip7_value0 <= 3'd7; + main_k7ddrphy_bitslip7_value1 <= 3'd7; + main_k7ddrphy_bitslip8_value0 <= 3'd7; + main_k7ddrphy_bitslip8_value1 <= 3'd7; + main_k7ddrphy_bitslip9_value0 <= 3'd7; + main_k7ddrphy_bitslip9_value1 <= 3'd7; + main_k7ddrphy_bitslip10_value0 <= 3'd7; + main_k7ddrphy_bitslip10_value1 <= 3'd7; + main_k7ddrphy_bitslip11_value0 <= 3'd7; + main_k7ddrphy_bitslip11_value1 <= 3'd7; + main_k7ddrphy_bitslip12_value0 <= 3'd7; + main_k7ddrphy_bitslip12_value1 <= 3'd7; + main_k7ddrphy_bitslip13_value0 <= 3'd7; + main_k7ddrphy_bitslip13_value1 <= 3'd7; + main_k7ddrphy_bitslip14_value0 <= 3'd7; + main_k7ddrphy_bitslip14_value1 <= 3'd7; + main_k7ddrphy_bitslip15_value0 <= 3'd7; + main_k7ddrphy_bitslip15_value1 <= 3'd7; + main_k7ddrphy_bitslip16_value0 <= 3'd7; + main_k7ddrphy_bitslip16_value1 <= 3'd7; + main_k7ddrphy_bitslip17_value0 <= 3'd7; + main_k7ddrphy_bitslip17_value1 <= 3'd7; + main_k7ddrphy_bitslip18_value0 <= 3'd7; + main_k7ddrphy_bitslip18_value1 <= 3'd7; + main_k7ddrphy_bitslip19_value0 <= 3'd7; + main_k7ddrphy_bitslip19_value1 <= 3'd7; + main_k7ddrphy_bitslip20_value0 <= 3'd7; + main_k7ddrphy_bitslip20_value1 <= 3'd7; + main_k7ddrphy_bitslip21_value0 <= 3'd7; + main_k7ddrphy_bitslip21_value1 <= 3'd7; + main_k7ddrphy_bitslip22_value0 <= 3'd7; + main_k7ddrphy_bitslip22_value1 <= 3'd7; + main_k7ddrphy_bitslip23_value0 <= 3'd7; + main_k7ddrphy_bitslip23_value1 <= 3'd7; + main_k7ddrphy_bitslip24_value0 <= 3'd7; + main_k7ddrphy_bitslip24_value1 <= 3'd7; + main_k7ddrphy_bitslip25_value0 <= 3'd7; + main_k7ddrphy_bitslip25_value1 <= 3'd7; + main_k7ddrphy_bitslip26_value0 <= 3'd7; + main_k7ddrphy_bitslip26_value1 <= 3'd7; + main_k7ddrphy_bitslip27_value0 <= 3'd7; + main_k7ddrphy_bitslip27_value1 <= 3'd7; + main_k7ddrphy_bitslip28_value0 <= 3'd7; + main_k7ddrphy_bitslip28_value1 <= 3'd7; + main_k7ddrphy_bitslip29_value0 <= 3'd7; + main_k7ddrphy_bitslip29_value1 <= 3'd7; + main_k7ddrphy_bitslip30_value0 <= 3'd7; + main_k7ddrphy_bitslip30_value1 <= 3'd7; + main_k7ddrphy_bitslip31_value0 <= 3'd7; + main_k7ddrphy_bitslip31_value1 <= 3'd7; + main_k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 6'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 64'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 6'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 64'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 6'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 64'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 6'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 64'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 15'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 15'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 15'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 15'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 15'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_counter <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_counter <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine0_row <= 15'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine1_row <= 15'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine2_row <= 15'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine3_row <= 15'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine4_row <= 15'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine5_row <= 15'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine6_row <= 15'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine7_row <= 15'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_litedramcore_we <= 1'd0; + builder_state <= 2'd0; end end BUFG BUFG( - .I(soc_clkout0), - .O(soc_clkout_buf0) + .I(main_clkout0), + .O(main_clkout_buf0) ); BUFG BUFG_1( - .I(soc_clkout1), - .O(soc_clkout_buf1) + .I(main_clkout1), + .O(main_clkout_buf1) ); BUFG BUFG_2( - .I(soc_clkout2), - .O(soc_clkout_buf2) + .I(main_clkout2), + .O(main_clkout_buf2) ); BUFG BUFG_3( - .I(soc_clkout3), - .O(soc_clkout_buf3) + .I(main_clkout3), + .O(main_clkout_buf3) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(main_ic_reset) ); OSERDESE2 #( @@ -16487,8 +21058,8 @@ OSERDESE2 #( .D7(1'd0), .D8(1'd1), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_sd_clk_se_nodelay) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_sd_clk_se_nodelay) ); ODELAYE2 #( @@ -16502,16 +21073,16 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_sd_clk_se_delayed), - .ODATAIN(soc_k7ddrphy_sd_clk_se_nodelay) + .DATAOUT(main_k7ddrphy_sd_clk_se_delayed), + .ODATAIN(main_k7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_k7ddrphy_sd_clk_se_delayed), + .I(main_k7ddrphy_sd_clk_se_delayed), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -16525,17 +21096,17 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[0]), - .D2(soc_k7ddrphy_dfi_p0_address[0]), - .D3(soc_k7ddrphy_dfi_p1_address[0]), - .D4(soc_k7ddrphy_dfi_p1_address[0]), - .D5(soc_k7ddrphy_dfi_p2_address[0]), - .D6(soc_k7ddrphy_dfi_p2_address[0]), - .D7(soc_k7ddrphy_dfi_p3_address[0]), - .D8(soc_k7ddrphy_dfi_p3_address[0]), + .D1(main_k7ddrphy_dfi_p0_reset_n), + .D2(main_k7ddrphy_dfi_p0_reset_n), + .D3(main_k7ddrphy_dfi_p1_reset_n), + .D4(main_k7ddrphy_dfi_p1_reset_n), + .D5(main_k7ddrphy_dfi_p2_reset_n), + .D6(main_k7ddrphy_dfi_p2_reset_n), + .D7(main_k7ddrphy_dfi_p3_reset_n), + .D8(main_k7ddrphy_dfi_p3_reset_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address0) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq0) ); ODELAYE2 #( @@ -16549,12 +21120,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_1 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[0]), - .ODATAIN(soc_k7ddrphy_address0) + .DATAOUT(ddram_reset_n), + .ODATAIN(main_k7ddrphy_oq0) ); OSERDESE2 #( @@ -16566,17 +21137,17 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[1]), - .D2(soc_k7ddrphy_dfi_p0_address[1]), - .D3(soc_k7ddrphy_dfi_p1_address[1]), - .D4(soc_k7ddrphy_dfi_p1_address[1]), - .D5(soc_k7ddrphy_dfi_p2_address[1]), - .D6(soc_k7ddrphy_dfi_p2_address[1]), - .D7(soc_k7ddrphy_dfi_p3_address[1]), - .D8(soc_k7ddrphy_dfi_p3_address[1]), + .D1(main_k7ddrphy_dfi_p0_cs_n), + .D2(main_k7ddrphy_dfi_p0_cs_n), + .D3(main_k7ddrphy_dfi_p1_cs_n), + .D4(main_k7ddrphy_dfi_p1_cs_n), + .D5(main_k7ddrphy_dfi_p2_cs_n), + .D6(main_k7ddrphy_dfi_p2_cs_n), + .D7(main_k7ddrphy_dfi_p3_cs_n), + .D8(main_k7ddrphy_dfi_p3_cs_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address1) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq1) ); ODELAYE2 #( @@ -16590,12 +21161,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_2 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[1]), - .ODATAIN(soc_k7ddrphy_address1) + .DATAOUT(ddram_cs_n), + .ODATAIN(main_k7ddrphy_oq1) ); OSERDESE2 #( @@ -16607,17 +21178,17 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[2]), - .D2(soc_k7ddrphy_dfi_p0_address[2]), - .D3(soc_k7ddrphy_dfi_p1_address[2]), - .D4(soc_k7ddrphy_dfi_p1_address[2]), - .D5(soc_k7ddrphy_dfi_p2_address[2]), - .D6(soc_k7ddrphy_dfi_p2_address[2]), - .D7(soc_k7ddrphy_dfi_p3_address[2]), - .D8(soc_k7ddrphy_dfi_p3_address[2]), + .D1(main_k7ddrphy_dfi_p0_address[0]), + .D2(main_k7ddrphy_dfi_p0_address[0]), + .D3(main_k7ddrphy_dfi_p1_address[0]), + .D4(main_k7ddrphy_dfi_p1_address[0]), + .D5(main_k7ddrphy_dfi_p2_address[0]), + .D6(main_k7ddrphy_dfi_p2_address[0]), + .D7(main_k7ddrphy_dfi_p3_address[0]), + .D8(main_k7ddrphy_dfi_p3_address[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address2) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq2) ); ODELAYE2 #( @@ -16631,12 +21202,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_3 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[2]), - .ODATAIN(soc_k7ddrphy_address2) + .DATAOUT(ddram_a[0]), + .ODATAIN(main_k7ddrphy_oq2) ); OSERDESE2 #( @@ -16648,17 +21219,17 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[3]), - .D2(soc_k7ddrphy_dfi_p0_address[3]), - .D3(soc_k7ddrphy_dfi_p1_address[3]), - .D4(soc_k7ddrphy_dfi_p1_address[3]), - .D5(soc_k7ddrphy_dfi_p2_address[3]), - .D6(soc_k7ddrphy_dfi_p2_address[3]), - .D7(soc_k7ddrphy_dfi_p3_address[3]), - .D8(soc_k7ddrphy_dfi_p3_address[3]), + .D1(main_k7ddrphy_dfi_p0_address[1]), + .D2(main_k7ddrphy_dfi_p0_address[1]), + .D3(main_k7ddrphy_dfi_p1_address[1]), + .D4(main_k7ddrphy_dfi_p1_address[1]), + .D5(main_k7ddrphy_dfi_p2_address[1]), + .D6(main_k7ddrphy_dfi_p2_address[1]), + .D7(main_k7ddrphy_dfi_p3_address[1]), + .D8(main_k7ddrphy_dfi_p3_address[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address3) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq3) ); ODELAYE2 #( @@ -16672,12 +21243,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_4 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[3]), - .ODATAIN(soc_k7ddrphy_address3) + .DATAOUT(ddram_a[1]), + .ODATAIN(main_k7ddrphy_oq3) ); OSERDESE2 #( @@ -16689,17 +21260,17 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[4]), - .D2(soc_k7ddrphy_dfi_p0_address[4]), - .D3(soc_k7ddrphy_dfi_p1_address[4]), - .D4(soc_k7ddrphy_dfi_p1_address[4]), - .D5(soc_k7ddrphy_dfi_p2_address[4]), - .D6(soc_k7ddrphy_dfi_p2_address[4]), - .D7(soc_k7ddrphy_dfi_p3_address[4]), - .D8(soc_k7ddrphy_dfi_p3_address[4]), + .D1(main_k7ddrphy_dfi_p0_address[2]), + .D2(main_k7ddrphy_dfi_p0_address[2]), + .D3(main_k7ddrphy_dfi_p1_address[2]), + .D4(main_k7ddrphy_dfi_p1_address[2]), + .D5(main_k7ddrphy_dfi_p2_address[2]), + .D6(main_k7ddrphy_dfi_p2_address[2]), + .D7(main_k7ddrphy_dfi_p3_address[2]), + .D8(main_k7ddrphy_dfi_p3_address[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address4) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq4) ); ODELAYE2 #( @@ -16713,12 +21284,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_5 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[4]), - .ODATAIN(soc_k7ddrphy_address4) + .DATAOUT(ddram_a[2]), + .ODATAIN(main_k7ddrphy_oq4) ); OSERDESE2 #( @@ -16730,17 +21301,17 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[5]), - .D2(soc_k7ddrphy_dfi_p0_address[5]), - .D3(soc_k7ddrphy_dfi_p1_address[5]), - .D4(soc_k7ddrphy_dfi_p1_address[5]), - .D5(soc_k7ddrphy_dfi_p2_address[5]), - .D6(soc_k7ddrphy_dfi_p2_address[5]), - .D7(soc_k7ddrphy_dfi_p3_address[5]), - .D8(soc_k7ddrphy_dfi_p3_address[5]), + .D1(main_k7ddrphy_dfi_p0_address[3]), + .D2(main_k7ddrphy_dfi_p0_address[3]), + .D3(main_k7ddrphy_dfi_p1_address[3]), + .D4(main_k7ddrphy_dfi_p1_address[3]), + .D5(main_k7ddrphy_dfi_p2_address[3]), + .D6(main_k7ddrphy_dfi_p2_address[3]), + .D7(main_k7ddrphy_dfi_p3_address[3]), + .D8(main_k7ddrphy_dfi_p3_address[3]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address5) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq5) ); ODELAYE2 #( @@ -16754,12 +21325,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_6 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[5]), - .ODATAIN(soc_k7ddrphy_address5) + .DATAOUT(ddram_a[3]), + .ODATAIN(main_k7ddrphy_oq5) ); OSERDESE2 #( @@ -16771,17 +21342,17 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[6]), - .D2(soc_k7ddrphy_dfi_p0_address[6]), - .D3(soc_k7ddrphy_dfi_p1_address[6]), - .D4(soc_k7ddrphy_dfi_p1_address[6]), - .D5(soc_k7ddrphy_dfi_p2_address[6]), - .D6(soc_k7ddrphy_dfi_p2_address[6]), - .D7(soc_k7ddrphy_dfi_p3_address[6]), - .D8(soc_k7ddrphy_dfi_p3_address[6]), + .D1(main_k7ddrphy_dfi_p0_address[4]), + .D2(main_k7ddrphy_dfi_p0_address[4]), + .D3(main_k7ddrphy_dfi_p1_address[4]), + .D4(main_k7ddrphy_dfi_p1_address[4]), + .D5(main_k7ddrphy_dfi_p2_address[4]), + .D6(main_k7ddrphy_dfi_p2_address[4]), + .D7(main_k7ddrphy_dfi_p3_address[4]), + .D8(main_k7ddrphy_dfi_p3_address[4]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address6) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq6) ); ODELAYE2 #( @@ -16795,12 +21366,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_7 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[6]), - .ODATAIN(soc_k7ddrphy_address6) + .DATAOUT(ddram_a[4]), + .ODATAIN(main_k7ddrphy_oq6) ); OSERDESE2 #( @@ -16812,17 +21383,17 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[7]), - .D2(soc_k7ddrphy_dfi_p0_address[7]), - .D3(soc_k7ddrphy_dfi_p1_address[7]), - .D4(soc_k7ddrphy_dfi_p1_address[7]), - .D5(soc_k7ddrphy_dfi_p2_address[7]), - .D6(soc_k7ddrphy_dfi_p2_address[7]), - .D7(soc_k7ddrphy_dfi_p3_address[7]), - .D8(soc_k7ddrphy_dfi_p3_address[7]), + .D1(main_k7ddrphy_dfi_p0_address[5]), + .D2(main_k7ddrphy_dfi_p0_address[5]), + .D3(main_k7ddrphy_dfi_p1_address[5]), + .D4(main_k7ddrphy_dfi_p1_address[5]), + .D5(main_k7ddrphy_dfi_p2_address[5]), + .D6(main_k7ddrphy_dfi_p2_address[5]), + .D7(main_k7ddrphy_dfi_p3_address[5]), + .D8(main_k7ddrphy_dfi_p3_address[5]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address7) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq7) ); ODELAYE2 #( @@ -16836,12 +21407,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_8 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[7]), - .ODATAIN(soc_k7ddrphy_address7) + .DATAOUT(ddram_a[5]), + .ODATAIN(main_k7ddrphy_oq7) ); OSERDESE2 #( @@ -16853,17 +21424,17 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[8]), - .D2(soc_k7ddrphy_dfi_p0_address[8]), - .D3(soc_k7ddrphy_dfi_p1_address[8]), - .D4(soc_k7ddrphy_dfi_p1_address[8]), - .D5(soc_k7ddrphy_dfi_p2_address[8]), - .D6(soc_k7ddrphy_dfi_p2_address[8]), - .D7(soc_k7ddrphy_dfi_p3_address[8]), - .D8(soc_k7ddrphy_dfi_p3_address[8]), + .D1(main_k7ddrphy_dfi_p0_address[6]), + .D2(main_k7ddrphy_dfi_p0_address[6]), + .D3(main_k7ddrphy_dfi_p1_address[6]), + .D4(main_k7ddrphy_dfi_p1_address[6]), + .D5(main_k7ddrphy_dfi_p2_address[6]), + .D6(main_k7ddrphy_dfi_p2_address[6]), + .D7(main_k7ddrphy_dfi_p3_address[6]), + .D8(main_k7ddrphy_dfi_p3_address[6]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address8) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq8) ); ODELAYE2 #( @@ -16877,12 +21448,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_9 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[8]), - .ODATAIN(soc_k7ddrphy_address8) + .DATAOUT(ddram_a[6]), + .ODATAIN(main_k7ddrphy_oq8) ); OSERDESE2 #( @@ -16894,17 +21465,17 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[9]), - .D2(soc_k7ddrphy_dfi_p0_address[9]), - .D3(soc_k7ddrphy_dfi_p1_address[9]), - .D4(soc_k7ddrphy_dfi_p1_address[9]), - .D5(soc_k7ddrphy_dfi_p2_address[9]), - .D6(soc_k7ddrphy_dfi_p2_address[9]), - .D7(soc_k7ddrphy_dfi_p3_address[9]), - .D8(soc_k7ddrphy_dfi_p3_address[9]), + .D1(main_k7ddrphy_dfi_p0_address[7]), + .D2(main_k7ddrphy_dfi_p0_address[7]), + .D3(main_k7ddrphy_dfi_p1_address[7]), + .D4(main_k7ddrphy_dfi_p1_address[7]), + .D5(main_k7ddrphy_dfi_p2_address[7]), + .D6(main_k7ddrphy_dfi_p2_address[7]), + .D7(main_k7ddrphy_dfi_p3_address[7]), + .D8(main_k7ddrphy_dfi_p3_address[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address9) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq9) ); ODELAYE2 #( @@ -16918,12 +21489,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_10 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[9]), - .ODATAIN(soc_k7ddrphy_address9) + .DATAOUT(ddram_a[7]), + .ODATAIN(main_k7ddrphy_oq9) ); OSERDESE2 #( @@ -16935,17 +21506,17 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[10]), - .D2(soc_k7ddrphy_dfi_p0_address[10]), - .D3(soc_k7ddrphy_dfi_p1_address[10]), - .D4(soc_k7ddrphy_dfi_p1_address[10]), - .D5(soc_k7ddrphy_dfi_p2_address[10]), - .D6(soc_k7ddrphy_dfi_p2_address[10]), - .D7(soc_k7ddrphy_dfi_p3_address[10]), - .D8(soc_k7ddrphy_dfi_p3_address[10]), + .D1(main_k7ddrphy_dfi_p0_address[8]), + .D2(main_k7ddrphy_dfi_p0_address[8]), + .D3(main_k7ddrphy_dfi_p1_address[8]), + .D4(main_k7ddrphy_dfi_p1_address[8]), + .D5(main_k7ddrphy_dfi_p2_address[8]), + .D6(main_k7ddrphy_dfi_p2_address[8]), + .D7(main_k7ddrphy_dfi_p3_address[8]), + .D8(main_k7ddrphy_dfi_p3_address[8]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address10) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq10) ); ODELAYE2 #( @@ -16959,12 +21530,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_11 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[10]), - .ODATAIN(soc_k7ddrphy_address10) + .DATAOUT(ddram_a[8]), + .ODATAIN(main_k7ddrphy_oq10) ); OSERDESE2 #( @@ -16976,17 +21547,17 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[11]), - .D2(soc_k7ddrphy_dfi_p0_address[11]), - .D3(soc_k7ddrphy_dfi_p1_address[11]), - .D4(soc_k7ddrphy_dfi_p1_address[11]), - .D5(soc_k7ddrphy_dfi_p2_address[11]), - .D6(soc_k7ddrphy_dfi_p2_address[11]), - .D7(soc_k7ddrphy_dfi_p3_address[11]), - .D8(soc_k7ddrphy_dfi_p3_address[11]), + .D1(main_k7ddrphy_dfi_p0_address[9]), + .D2(main_k7ddrphy_dfi_p0_address[9]), + .D3(main_k7ddrphy_dfi_p1_address[9]), + .D4(main_k7ddrphy_dfi_p1_address[9]), + .D5(main_k7ddrphy_dfi_p2_address[9]), + .D6(main_k7ddrphy_dfi_p2_address[9]), + .D7(main_k7ddrphy_dfi_p3_address[9]), + .D8(main_k7ddrphy_dfi_p3_address[9]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address11) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq11) ); ODELAYE2 #( @@ -17000,12 +21571,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_12 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[11]), - .ODATAIN(soc_k7ddrphy_address11) + .DATAOUT(ddram_a[9]), + .ODATAIN(main_k7ddrphy_oq11) ); OSERDESE2 #( @@ -17017,17 +21588,17 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[12]), - .D2(soc_k7ddrphy_dfi_p0_address[12]), - .D3(soc_k7ddrphy_dfi_p1_address[12]), - .D4(soc_k7ddrphy_dfi_p1_address[12]), - .D5(soc_k7ddrphy_dfi_p2_address[12]), - .D6(soc_k7ddrphy_dfi_p2_address[12]), - .D7(soc_k7ddrphy_dfi_p3_address[12]), - .D8(soc_k7ddrphy_dfi_p3_address[12]), + .D1(main_k7ddrphy_dfi_p0_address[10]), + .D2(main_k7ddrphy_dfi_p0_address[10]), + .D3(main_k7ddrphy_dfi_p1_address[10]), + .D4(main_k7ddrphy_dfi_p1_address[10]), + .D5(main_k7ddrphy_dfi_p2_address[10]), + .D6(main_k7ddrphy_dfi_p2_address[10]), + .D7(main_k7ddrphy_dfi_p3_address[10]), + .D8(main_k7ddrphy_dfi_p3_address[10]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address12) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq12) ); ODELAYE2 #( @@ -17041,12 +21612,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_13 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[12]), - .ODATAIN(soc_k7ddrphy_address12) + .DATAOUT(ddram_a[10]), + .ODATAIN(main_k7ddrphy_oq12) ); OSERDESE2 #( @@ -17058,17 +21629,17 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[13]), - .D2(soc_k7ddrphy_dfi_p0_address[13]), - .D3(soc_k7ddrphy_dfi_p1_address[13]), - .D4(soc_k7ddrphy_dfi_p1_address[13]), - .D5(soc_k7ddrphy_dfi_p2_address[13]), - .D6(soc_k7ddrphy_dfi_p2_address[13]), - .D7(soc_k7ddrphy_dfi_p3_address[13]), - .D8(soc_k7ddrphy_dfi_p3_address[13]), + .D1(main_k7ddrphy_dfi_p0_address[11]), + .D2(main_k7ddrphy_dfi_p0_address[11]), + .D3(main_k7ddrphy_dfi_p1_address[11]), + .D4(main_k7ddrphy_dfi_p1_address[11]), + .D5(main_k7ddrphy_dfi_p2_address[11]), + .D6(main_k7ddrphy_dfi_p2_address[11]), + .D7(main_k7ddrphy_dfi_p3_address[11]), + .D8(main_k7ddrphy_dfi_p3_address[11]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address13) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq13) ); ODELAYE2 #( @@ -17082,12 +21653,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_14 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[13]), - .ODATAIN(soc_k7ddrphy_address13) + .DATAOUT(ddram_a[11]), + .ODATAIN(main_k7ddrphy_oq13) ); OSERDESE2 #( @@ -17099,17 +21670,17 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_address[14]), - .D2(soc_k7ddrphy_dfi_p0_address[14]), - .D3(soc_k7ddrphy_dfi_p1_address[14]), - .D4(soc_k7ddrphy_dfi_p1_address[14]), - .D5(soc_k7ddrphy_dfi_p2_address[14]), - .D6(soc_k7ddrphy_dfi_p2_address[14]), - .D7(soc_k7ddrphy_dfi_p3_address[14]), - .D8(soc_k7ddrphy_dfi_p3_address[14]), + .D1(main_k7ddrphy_dfi_p0_address[12]), + .D2(main_k7ddrphy_dfi_p0_address[12]), + .D3(main_k7ddrphy_dfi_p1_address[12]), + .D4(main_k7ddrphy_dfi_p1_address[12]), + .D5(main_k7ddrphy_dfi_p2_address[12]), + .D6(main_k7ddrphy_dfi_p2_address[12]), + .D7(main_k7ddrphy_dfi_p3_address[12]), + .D8(main_k7ddrphy_dfi_p3_address[12]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_address14) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq14) ); ODELAYE2 #( @@ -17123,12 +21694,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_15 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[14]), - .ODATAIN(soc_k7ddrphy_address14) + .DATAOUT(ddram_a[12]), + .ODATAIN(main_k7ddrphy_oq14) ); OSERDESE2 #( @@ -17140,17 +21711,17 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_bank[0]), - .D2(soc_k7ddrphy_dfi_p0_bank[0]), - .D3(soc_k7ddrphy_dfi_p1_bank[0]), - .D4(soc_k7ddrphy_dfi_p1_bank[0]), - .D5(soc_k7ddrphy_dfi_p2_bank[0]), - .D6(soc_k7ddrphy_dfi_p2_bank[0]), - .D7(soc_k7ddrphy_dfi_p3_bank[0]), - .D8(soc_k7ddrphy_dfi_p3_bank[0]), + .D1(main_k7ddrphy_dfi_p0_address[13]), + .D2(main_k7ddrphy_dfi_p0_address[13]), + .D3(main_k7ddrphy_dfi_p1_address[13]), + .D4(main_k7ddrphy_dfi_p1_address[13]), + .D5(main_k7ddrphy_dfi_p2_address[13]), + .D6(main_k7ddrphy_dfi_p2_address[13]), + .D7(main_k7ddrphy_dfi_p3_address[13]), + .D8(main_k7ddrphy_dfi_p3_address[13]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_bank0) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq15) ); ODELAYE2 #( @@ -17164,12 +21735,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_16 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_ba[0]), - .ODATAIN(soc_k7ddrphy_bank0) + .DATAOUT(ddram_a[13]), + .ODATAIN(main_k7ddrphy_oq15) ); OSERDESE2 #( @@ -17181,17 +21752,17 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_bank[1]), - .D2(soc_k7ddrphy_dfi_p0_bank[1]), - .D3(soc_k7ddrphy_dfi_p1_bank[1]), - .D4(soc_k7ddrphy_dfi_p1_bank[1]), - .D5(soc_k7ddrphy_dfi_p2_bank[1]), - .D6(soc_k7ddrphy_dfi_p2_bank[1]), - .D7(soc_k7ddrphy_dfi_p3_bank[1]), - .D8(soc_k7ddrphy_dfi_p3_bank[1]), + .D1(main_k7ddrphy_dfi_p0_address[14]), + .D2(main_k7ddrphy_dfi_p0_address[14]), + .D3(main_k7ddrphy_dfi_p1_address[14]), + .D4(main_k7ddrphy_dfi_p1_address[14]), + .D5(main_k7ddrphy_dfi_p2_address[14]), + .D6(main_k7ddrphy_dfi_p2_address[14]), + .D7(main_k7ddrphy_dfi_p3_address[14]), + .D8(main_k7ddrphy_dfi_p3_address[14]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_bank1) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq16) ); ODELAYE2 #( @@ -17205,12 +21776,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_17 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_ba[1]), - .ODATAIN(soc_k7ddrphy_bank1) + .DATAOUT(ddram_a[14]), + .ODATAIN(main_k7ddrphy_oq16) ); OSERDESE2 #( @@ -17222,17 +21793,17 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_bank[2]), - .D2(soc_k7ddrphy_dfi_p0_bank[2]), - .D3(soc_k7ddrphy_dfi_p1_bank[2]), - .D4(soc_k7ddrphy_dfi_p1_bank[2]), - .D5(soc_k7ddrphy_dfi_p2_bank[2]), - .D6(soc_k7ddrphy_dfi_p2_bank[2]), - .D7(soc_k7ddrphy_dfi_p3_bank[2]), - .D8(soc_k7ddrphy_dfi_p3_bank[2]), + .D1(main_k7ddrphy_dfi_p0_bank[0]), + .D2(main_k7ddrphy_dfi_p0_bank[0]), + .D3(main_k7ddrphy_dfi_p1_bank[0]), + .D4(main_k7ddrphy_dfi_p1_bank[0]), + .D5(main_k7ddrphy_dfi_p2_bank[0]), + .D6(main_k7ddrphy_dfi_p2_bank[0]), + .D7(main_k7ddrphy_dfi_p3_bank[0]), + .D8(main_k7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_bank2) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq17) ); ODELAYE2 #( @@ -17246,12 +21817,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_18 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_ba[2]), - .ODATAIN(soc_k7ddrphy_bank2) + .DATAOUT(ddram_ba[0]), + .ODATAIN(main_k7ddrphy_oq17) ); OSERDESE2 #( @@ -17263,17 +21834,17 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_ras_n), - .D2(soc_k7ddrphy_dfi_p0_ras_n), - .D3(soc_k7ddrphy_dfi_p1_ras_n), - .D4(soc_k7ddrphy_dfi_p1_ras_n), - .D5(soc_k7ddrphy_dfi_p2_ras_n), - .D6(soc_k7ddrphy_dfi_p2_ras_n), - .D7(soc_k7ddrphy_dfi_p3_ras_n), - .D8(soc_k7ddrphy_dfi_p3_ras_n), + .D1(main_k7ddrphy_dfi_p0_bank[1]), + .D2(main_k7ddrphy_dfi_p0_bank[1]), + .D3(main_k7ddrphy_dfi_p1_bank[1]), + .D4(main_k7ddrphy_dfi_p1_bank[1]), + .D5(main_k7ddrphy_dfi_p2_bank[1]), + .D6(main_k7ddrphy_dfi_p2_bank[1]), + .D7(main_k7ddrphy_dfi_p3_bank[1]), + .D8(main_k7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd0) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq18) ); ODELAYE2 #( @@ -17287,12 +21858,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_19 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_ras_n), - .ODATAIN(soc_k7ddrphy_cmd0) + .DATAOUT(ddram_ba[1]), + .ODATAIN(main_k7ddrphy_oq18) ); OSERDESE2 #( @@ -17304,17 +21875,17 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_cas_n), - .D2(soc_k7ddrphy_dfi_p0_cas_n), - .D3(soc_k7ddrphy_dfi_p1_cas_n), - .D4(soc_k7ddrphy_dfi_p1_cas_n), - .D5(soc_k7ddrphy_dfi_p2_cas_n), - .D6(soc_k7ddrphy_dfi_p2_cas_n), - .D7(soc_k7ddrphy_dfi_p3_cas_n), - .D8(soc_k7ddrphy_dfi_p3_cas_n), + .D1(main_k7ddrphy_dfi_p0_bank[2]), + .D2(main_k7ddrphy_dfi_p0_bank[2]), + .D3(main_k7ddrphy_dfi_p1_bank[2]), + .D4(main_k7ddrphy_dfi_p1_bank[2]), + .D5(main_k7ddrphy_dfi_p2_bank[2]), + .D6(main_k7ddrphy_dfi_p2_bank[2]), + .D7(main_k7ddrphy_dfi_p3_bank[2]), + .D8(main_k7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd1) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq19) ); ODELAYE2 #( @@ -17328,12 +21899,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_20 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_cas_n), - .ODATAIN(soc_k7ddrphy_cmd1) + .DATAOUT(ddram_ba[2]), + .ODATAIN(main_k7ddrphy_oq19) ); OSERDESE2 #( @@ -17345,17 +21916,17 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_we_n), - .D2(soc_k7ddrphy_dfi_p0_we_n), - .D3(soc_k7ddrphy_dfi_p1_we_n), - .D4(soc_k7ddrphy_dfi_p1_we_n), - .D5(soc_k7ddrphy_dfi_p2_we_n), - .D6(soc_k7ddrphy_dfi_p2_we_n), - .D7(soc_k7ddrphy_dfi_p3_we_n), - .D8(soc_k7ddrphy_dfi_p3_we_n), + .D1(main_k7ddrphy_dfi_p0_ras_n), + .D2(main_k7ddrphy_dfi_p0_ras_n), + .D3(main_k7ddrphy_dfi_p1_ras_n), + .D4(main_k7ddrphy_dfi_p1_ras_n), + .D5(main_k7ddrphy_dfi_p2_ras_n), + .D6(main_k7ddrphy_dfi_p2_ras_n), + .D7(main_k7ddrphy_dfi_p3_ras_n), + .D8(main_k7ddrphy_dfi_p3_ras_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd2) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq20) ); ODELAYE2 #( @@ -17369,12 +21940,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_21 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_we_n), - .ODATAIN(soc_k7ddrphy_cmd2) + .DATAOUT(ddram_ras_n), + .ODATAIN(main_k7ddrphy_oq20) ); OSERDESE2 #( @@ -17386,17 +21957,17 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_cke), - .D2(soc_k7ddrphy_dfi_p0_cke), - .D3(soc_k7ddrphy_dfi_p1_cke), - .D4(soc_k7ddrphy_dfi_p1_cke), - .D5(soc_k7ddrphy_dfi_p2_cke), - .D6(soc_k7ddrphy_dfi_p2_cke), - .D7(soc_k7ddrphy_dfi_p3_cke), - .D8(soc_k7ddrphy_dfi_p3_cke), + .D1(main_k7ddrphy_dfi_p0_cas_n), + .D2(main_k7ddrphy_dfi_p0_cas_n), + .D3(main_k7ddrphy_dfi_p1_cas_n), + .D4(main_k7ddrphy_dfi_p1_cas_n), + .D5(main_k7ddrphy_dfi_p2_cas_n), + .D6(main_k7ddrphy_dfi_p2_cas_n), + .D7(main_k7ddrphy_dfi_p3_cas_n), + .D8(main_k7ddrphy_dfi_p3_cas_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd3) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq21) ); ODELAYE2 #( @@ -17410,12 +21981,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_22 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_cke), - .ODATAIN(soc_k7ddrphy_cmd3) + .DATAOUT(ddram_cas_n), + .ODATAIN(main_k7ddrphy_oq21) ); OSERDESE2 #( @@ -17427,17 +21998,17 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_odt), - .D2(soc_k7ddrphy_dfi_p0_odt), - .D3(soc_k7ddrphy_dfi_p1_odt), - .D4(soc_k7ddrphy_dfi_p1_odt), - .D5(soc_k7ddrphy_dfi_p2_odt), - .D6(soc_k7ddrphy_dfi_p2_odt), - .D7(soc_k7ddrphy_dfi_p3_odt), - .D8(soc_k7ddrphy_dfi_p3_odt), + .D1(main_k7ddrphy_dfi_p0_we_n), + .D2(main_k7ddrphy_dfi_p0_we_n), + .D3(main_k7ddrphy_dfi_p1_we_n), + .D4(main_k7ddrphy_dfi_p1_we_n), + .D5(main_k7ddrphy_dfi_p2_we_n), + .D6(main_k7ddrphy_dfi_p2_we_n), + .D7(main_k7ddrphy_dfi_p3_we_n), + .D8(main_k7ddrphy_dfi_p3_we_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd4) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq22) ); ODELAYE2 #( @@ -17451,12 +22022,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_23 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_odt), - .ODATAIN(soc_k7ddrphy_cmd4) + .DATAOUT(ddram_we_n), + .ODATAIN(main_k7ddrphy_oq22) ); OSERDESE2 #( @@ -17468,17 +22039,17 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_reset_n), - .D2(soc_k7ddrphy_dfi_p0_reset_n), - .D3(soc_k7ddrphy_dfi_p1_reset_n), - .D4(soc_k7ddrphy_dfi_p1_reset_n), - .D5(soc_k7ddrphy_dfi_p2_reset_n), - .D6(soc_k7ddrphy_dfi_p2_reset_n), - .D7(soc_k7ddrphy_dfi_p3_reset_n), - .D8(soc_k7ddrphy_dfi_p3_reset_n), + .D1(main_k7ddrphy_dfi_p0_cke), + .D2(main_k7ddrphy_dfi_p0_cke), + .D3(main_k7ddrphy_dfi_p1_cke), + .D4(main_k7ddrphy_dfi_p1_cke), + .D5(main_k7ddrphy_dfi_p2_cke), + .D6(main_k7ddrphy_dfi_p2_cke), + .D7(main_k7ddrphy_dfi_p3_cke), + .D8(main_k7ddrphy_dfi_p3_cke), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd5) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq23) ); ODELAYE2 #( @@ -17492,12 +22063,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_24 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_reset_n), - .ODATAIN(soc_k7ddrphy_cmd5) + .DATAOUT(ddram_cke), + .ODATAIN(main_k7ddrphy_oq23) ); OSERDESE2 #( @@ -17509,17 +22080,17 @@ OSERDESE2 #( ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_cs_n), - .D2(soc_k7ddrphy_dfi_p0_cs_n), - .D3(soc_k7ddrphy_dfi_p1_cs_n), - .D4(soc_k7ddrphy_dfi_p1_cs_n), - .D5(soc_k7ddrphy_dfi_p2_cs_n), - .D6(soc_k7ddrphy_dfi_p2_cs_n), - .D7(soc_k7ddrphy_dfi_p3_cs_n), - .D8(soc_k7ddrphy_dfi_p3_cs_n), + .D1(main_k7ddrphy_dfi_p0_odt), + .D2(main_k7ddrphy_dfi_p0_odt), + .D3(main_k7ddrphy_dfi_p1_odt), + .D4(main_k7ddrphy_dfi_p1_odt), + .D5(main_k7ddrphy_dfi_p2_odt), + .D6(main_k7ddrphy_dfi_p2_odt), + .D7(main_k7ddrphy_dfi_p3_odt), + .D8(main_k7ddrphy_dfi_p3_odt), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_cmd6) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_oq24) ); ODELAYE2 #( @@ -17533,12 +22104,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_25 ( .C(sys_clk), - .CE(soc_k7ddrphy_cdly_inc_re), + .CE(main_k7ddrphy_cdly_inc_re), .INC(1'd1), - .LD(soc_k7ddrphy_cdly_rst_re), + .LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_cs_n), - .ODATAIN(soc_k7ddrphy_cmd6) + .DATAOUT(ddram_odt), + .ODATAIN(main_k7ddrphy_oq24) ); OSERDESE2 #( @@ -17550,17 +22121,21 @@ OSERDESE2 #( ) OSERDESE2_26 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[4]), - .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[4]), - .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[4]), - .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[4]), + .D1(main_k7ddrphy_bitslip00[0]), + .D2(main_k7ddrphy_bitslip00[1]), + .D3(main_k7ddrphy_bitslip00[2]), + .D4(main_k7ddrphy_bitslip00[3]), + .D5(main_k7ddrphy_bitslip00[4]), + .D6(main_k7ddrphy_bitslip00[5]), + .D7(main_k7ddrphy_bitslip00[6]), + .D8(main_k7ddrphy_bitslip00[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_dm_o_nodelay0) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_k7ddrphy_dqs_o_no_delay0), + .OQ(main_k7ddrphy0), + .TQ(main_k7ddrphy_dqs_t0) ); ODELAYE2 #( @@ -17568,18 +22143,25 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), + .ODELAY_VALUE(4'd8), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_26 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[0]), - .ODATAIN(soc_k7ddrphy_dm_o_nodelay0) + .DATAOUT(main_k7ddrphy_dqs_o_delayed0), + .ODATAIN(main_k7ddrphy_dqs_o_no_delay0) +); + +IOBUFDS IOBUFDS( + .I(main_k7ddrphy_dqs_o_delayed0), + .T(main_k7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( @@ -17591,17 +22173,21 @@ OSERDESE2 #( ) OSERDESE2_27 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[5]), - .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[5]), - .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[5]), - .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[5]), + .D1(main_k7ddrphy_bitslip10[0]), + .D2(main_k7ddrphy_bitslip10[1]), + .D3(main_k7ddrphy_bitslip10[2]), + .D4(main_k7ddrphy_bitslip10[3]), + .D5(main_k7ddrphy_bitslip10[4]), + .D6(main_k7ddrphy_bitslip10[5]), + .D7(main_k7ddrphy_bitslip10[6]), + .D8(main_k7ddrphy_bitslip10[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_dm_o_nodelay1) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_k7ddrphy_dqs_o_no_delay1), + .OQ(main_k7ddrphy1), + .TQ(main_k7ddrphy_dqs_t1) ); ODELAYE2 #( @@ -17609,18 +22195,25 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), + .ODELAY_VALUE(4'd8), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_27 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[1]), - .ODATAIN(soc_k7ddrphy_dm_o_nodelay1) + .DATAOUT(main_k7ddrphy_dqs_o_delayed1), + .ODATAIN(main_k7ddrphy_dqs_o_no_delay1) +); + +IOBUFDS IOBUFDS_1( + .I(main_k7ddrphy_dqs_o_delayed1), + .T(main_k7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( @@ -17632,17 +22225,21 @@ OSERDESE2 #( ) OSERDESE2_28 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[2]), - .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[6]), - .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[2]), - .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[6]), - .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[2]), - .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[6]), - .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[2]), - .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[6]), + .D1(main_k7ddrphy_bitslip20[0]), + .D2(main_k7ddrphy_bitslip20[1]), + .D3(main_k7ddrphy_bitslip20[2]), + .D4(main_k7ddrphy_bitslip20[3]), + .D5(main_k7ddrphy_bitslip20[4]), + .D6(main_k7ddrphy_bitslip20[5]), + .D7(main_k7ddrphy_bitslip20[6]), + .D8(main_k7ddrphy_bitslip20[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_dm_o_nodelay2) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_k7ddrphy_dqs_o_no_delay2), + .OQ(main_k7ddrphy2), + .TQ(main_k7ddrphy_dqs_t2) ); ODELAYE2 #( @@ -17650,18 +22247,25 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), + .ODELAY_VALUE(4'd8), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_28 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[2]), - .ODATAIN(soc_k7ddrphy_dm_o_nodelay2) + .DATAOUT(main_k7ddrphy_dqs_o_delayed2), + .ODATAIN(main_k7ddrphy_dqs_o_no_delay2) +); + +IOBUFDS IOBUFDS_2( + .I(main_k7ddrphy_dqs_o_delayed2), + .T(main_k7ddrphy_dqs_t2), + .IO(ddram_dqs_p[2]), + .IOB(ddram_dqs_n[2]) ); OSERDESE2 #( @@ -17673,17 +22277,21 @@ OSERDESE2 #( ) OSERDESE2_29 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[3]), - .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[7]), - .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[3]), - .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[7]), - .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[3]), - .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[7]), - .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[3]), - .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[7]), + .D1(main_k7ddrphy_bitslip30[0]), + .D2(main_k7ddrphy_bitslip30[1]), + .D3(main_k7ddrphy_bitslip30[2]), + .D4(main_k7ddrphy_bitslip30[3]), + .D5(main_k7ddrphy_bitslip30[4]), + .D6(main_k7ddrphy_bitslip30[5]), + .D7(main_k7ddrphy_bitslip30[6]), + .D8(main_k7ddrphy_bitslip30[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_k7ddrphy_dm_o_nodelay3) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_k7ddrphy_dqs_o_no_delay3), + .OQ(main_k7ddrphy3), + .TQ(main_k7ddrphy_dqs_t3) ); ODELAYE2 #( @@ -17691,18 +22299,25 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), + .ODELAY_VALUE(4'd8), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_29 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[3]), - .ODATAIN(soc_k7ddrphy_dm_o_nodelay3) + .DATAOUT(main_k7ddrphy_dqs_o_delayed3), + .ODATAIN(main_k7ddrphy_dqs_o_no_delay3) +); + +IOBUFDS IOBUFDS_3( + .I(main_k7ddrphy_dqs_o_delayed3), + .T(main_k7ddrphy_dqs_t3), + .IO(ddram_dqs_p[3]), + .IOB(ddram_dqs_n[3]) ); OSERDESE2 #( @@ -17714,21 +22329,17 @@ OSERDESE2 #( ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dqspattern_o[0]), - .D2(soc_k7ddrphy_dqspattern_o[1]), - .D3(soc_k7ddrphy_dqspattern_o[2]), - .D4(soc_k7ddrphy_dqspattern_o[3]), - .D5(soc_k7ddrphy_dqspattern_o[4]), - .D6(soc_k7ddrphy_dqspattern_o[5]), - .D7(soc_k7ddrphy_dqspattern_o[6]), - .D8(soc_k7ddrphy_dqspattern_o[7]), + .D1(main_k7ddrphy_bitslip01[0]), + .D2(main_k7ddrphy_bitslip01[1]), + .D3(main_k7ddrphy_bitslip01[2]), + .D4(main_k7ddrphy_bitslip01[3]), + .D5(main_k7ddrphy_bitslip01[4]), + .D6(main_k7ddrphy_bitslip01[5]), + .D7(main_k7ddrphy_bitslip01[6]), + .D8(main_k7ddrphy_bitslip01[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_k7ddrphy_dqs_o_no_delay0), - .OQ(soc_k7ddrphy0), - .TQ(soc_k7ddrphy_dqs_t0) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_dm_o_nodelay0) ); ODELAYE2 #( @@ -17736,40 +22347,18 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), + .ODELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_30 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dqs_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dqs_o_delayed0), - .ODATAIN(soc_k7ddrphy_dqs_o_no_delay0) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2 ( - .IDATAIN(soc_k7ddrphy_dqs_i[0]), - .DATAOUT(soc_k7ddrphy_dqs_i_delayed[0]) -); - -IOBUFDS IOBUFDS( - .I(soc_k7ddrphy_dqs_o_delayed0), - .T(soc_k7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]), - .O(soc_k7ddrphy_dqs_i[0]) + .DATAOUT(ddram_dm[0]), + .ODATAIN(main_k7ddrphy_dm_o_nodelay0) ); OSERDESE2 #( @@ -17781,21 +22370,17 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dqspattern_o[0]), - .D2(soc_k7ddrphy_dqspattern_o[1]), - .D3(soc_k7ddrphy_dqspattern_o[2]), - .D4(soc_k7ddrphy_dqspattern_o[3]), - .D5(soc_k7ddrphy_dqspattern_o[4]), - .D6(soc_k7ddrphy_dqspattern_o[5]), - .D7(soc_k7ddrphy_dqspattern_o[6]), - .D8(soc_k7ddrphy_dqspattern_o[7]), + .D1(main_k7ddrphy_bitslip11[0]), + .D2(main_k7ddrphy_bitslip11[1]), + .D3(main_k7ddrphy_bitslip11[2]), + .D4(main_k7ddrphy_bitslip11[3]), + .D5(main_k7ddrphy_bitslip11[4]), + .D6(main_k7ddrphy_bitslip11[5]), + .D7(main_k7ddrphy_bitslip11[6]), + .D8(main_k7ddrphy_bitslip11[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_k7ddrphy_dqs_o_no_delay1), - .OQ(soc_k7ddrphy1), - .TQ(soc_k7ddrphy_dqs_t1) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_dm_o_nodelay1) ); ODELAYE2 #( @@ -17803,40 +22388,18 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), + .ODELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_31 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dqs_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dqs_o_delayed1), - .ODATAIN(soc_k7ddrphy_dqs_o_no_delay1) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_1 ( - .IDATAIN(soc_k7ddrphy_dqs_i[1]), - .DATAOUT(soc_k7ddrphy_dqs_i_delayed[1]) -); - -IOBUFDS IOBUFDS_1( - .I(soc_k7ddrphy_dqs_o_delayed1), - .T(soc_k7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]), - .O(soc_k7ddrphy_dqs_i[1]) + .DATAOUT(ddram_dm[1]), + .ODATAIN(main_k7ddrphy_dm_o_nodelay1) ); OSERDESE2 #( @@ -17848,21 +22411,17 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dqspattern_o[0]), - .D2(soc_k7ddrphy_dqspattern_o[1]), - .D3(soc_k7ddrphy_dqspattern_o[2]), - .D4(soc_k7ddrphy_dqspattern_o[3]), - .D5(soc_k7ddrphy_dqspattern_o[4]), - .D6(soc_k7ddrphy_dqspattern_o[5]), - .D7(soc_k7ddrphy_dqspattern_o[6]), - .D8(soc_k7ddrphy_dqspattern_o[7]), + .D1(main_k7ddrphy_bitslip21[0]), + .D2(main_k7ddrphy_bitslip21[1]), + .D3(main_k7ddrphy_bitslip21[2]), + .D4(main_k7ddrphy_bitslip21[3]), + .D5(main_k7ddrphy_bitslip21[4]), + .D6(main_k7ddrphy_bitslip21[5]), + .D7(main_k7ddrphy_bitslip21[6]), + .D8(main_k7ddrphy_bitslip21[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_k7ddrphy_dqs_o_no_delay2), - .OQ(soc_k7ddrphy2), - .TQ(soc_k7ddrphy_dqs_t2) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_dm_o_nodelay2) ); ODELAYE2 #( @@ -17870,40 +22429,18 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), + .ODELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_32 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dqs_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dqs_o_delayed2), - .ODATAIN(soc_k7ddrphy_dqs_o_no_delay2) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_2 ( - .IDATAIN(soc_k7ddrphy_dqs_i[2]), - .DATAOUT(soc_k7ddrphy_dqs_i_delayed[2]) -); - -IOBUFDS IOBUFDS_2( - .I(soc_k7ddrphy_dqs_o_delayed2), - .T(soc_k7ddrphy_dqs_t2), - .IO(ddram_dqs_p[2]), - .IOB(ddram_dqs_n[2]), - .O(soc_k7ddrphy_dqs_i[2]) + .DATAOUT(ddram_dm[2]), + .ODATAIN(main_k7ddrphy_dm_o_nodelay2) ); OSERDESE2 #( @@ -17915,21 +22452,17 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dqspattern_o[0]), - .D2(soc_k7ddrphy_dqspattern_o[1]), - .D3(soc_k7ddrphy_dqspattern_o[2]), - .D4(soc_k7ddrphy_dqspattern_o[3]), - .D5(soc_k7ddrphy_dqspattern_o[4]), - .D6(soc_k7ddrphy_dqspattern_o[5]), - .D7(soc_k7ddrphy_dqspattern_o[6]), - .D8(soc_k7ddrphy_dqspattern_o[7]), + .D1(main_k7ddrphy_bitslip31[0]), + .D2(main_k7ddrphy_bitslip31[1]), + .D3(main_k7ddrphy_bitslip31[2]), + .D4(main_k7ddrphy_bitslip31[3]), + .D5(main_k7ddrphy_bitslip31[4]), + .D6(main_k7ddrphy_bitslip31[5]), + .D7(main_k7ddrphy_bitslip31[6]), + .D8(main_k7ddrphy_bitslip31[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_k7ddrphy_dqs_o_no_delay3), - .OQ(soc_k7ddrphy3), - .TQ(soc_k7ddrphy_dqs_t3) + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .OQ(main_k7ddrphy_dm_o_nodelay3) ); ODELAYE2 #( @@ -17937,40 +22470,18 @@ ODELAYE2 #( .DELAY_SRC("ODATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), + .ODELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) ODELAYE2_33 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dqs_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dqs_o_delayed3), - .ODATAIN(soc_k7ddrphy_dqs_o_no_delay3) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_3 ( - .IDATAIN(soc_k7ddrphy_dqs_i[3]), - .DATAOUT(soc_k7ddrphy_dqs_i_delayed[3]) -); - -IOBUFDS IOBUFDS_3( - .I(soc_k7ddrphy_dqs_o_delayed3), - .T(soc_k7ddrphy_dqs_t3), - .IO(ddram_dqs_p[3]), - .IOB(ddram_dqs_n[3]), - .O(soc_k7ddrphy_dqs_i[3]) + .DATAOUT(ddram_dm[3]), + .ODATAIN(main_k7ddrphy_dm_o_nodelay3) ); OSERDESE2 #( @@ -17982,20 +22493,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[32]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[32]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[32]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[32]), + .D1(main_k7ddrphy_bitslip02[0]), + .D2(main_k7ddrphy_bitslip02[1]), + .D3(main_k7ddrphy_bitslip02[2]), + .D4(main_k7ddrphy_bitslip02[3]), + .D5(main_k7ddrphy_bitslip02[4]), + .D6(main_k7ddrphy_bitslip02[5]), + .D7(main_k7ddrphy_bitslip02[6]), + .D8(main_k7ddrphy_bitslip02[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay0), - .TQ(soc_k7ddrphy_dq_t0) + .OQ(main_k7ddrphy_dq_o_nodelay0), + .TQ(main_k7ddrphy_dq_t0) ); ISERDESE2 #( @@ -18011,16 +22522,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed0), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data0[7]), - .Q2(soc_k7ddrphy_dq_i_data0[6]), - .Q3(soc_k7ddrphy_dq_i_data0[5]), - .Q4(soc_k7ddrphy_dq_i_data0[4]), - .Q5(soc_k7ddrphy_dq_i_data0[3]), - .Q6(soc_k7ddrphy_dq_i_data0[2]), - .Q7(soc_k7ddrphy_dq_i_data0[1]), - .Q8(soc_k7ddrphy_dq_i_data0[0]) + .DDLY(main_k7ddrphy_dq_i_delayed0), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip03[7]), + .Q2(main_k7ddrphy_bitslip03[6]), + .Q3(main_k7ddrphy_bitslip03[5]), + .Q4(main_k7ddrphy_bitslip03[4]), + .Q5(main_k7ddrphy_bitslip03[3]), + .Q6(main_k7ddrphy_bitslip03[2]), + .Q7(main_k7ddrphy_bitslip03[1]), + .Q8(main_k7ddrphy_bitslip03[0]) ); ODELAYE2 #( @@ -18034,12 +22545,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_34 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed0), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay0) + .DATAOUT(main_k7ddrphy_dq_o_delayed0), + .ODATAIN(main_k7ddrphy_dq_o_nodelay0) ); IDELAYE2 #( @@ -18051,21 +22562,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_4 ( +) IDELAYE2 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay0), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed0) + .DATAOUT(main_k7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_k7ddrphy_dq_o_delayed0), - .T(soc_k7ddrphy_dq_t0), + .I(main_k7ddrphy_dq_o_delayed0), + .T(main_k7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_k7ddrphy_dq_i_nodelay0) + .O(main_k7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -18077,20 +22588,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[33]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[33]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[33]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[33]), + .D1(main_k7ddrphy_bitslip12[0]), + .D2(main_k7ddrphy_bitslip12[1]), + .D3(main_k7ddrphy_bitslip12[2]), + .D4(main_k7ddrphy_bitslip12[3]), + .D5(main_k7ddrphy_bitslip12[4]), + .D6(main_k7ddrphy_bitslip12[5]), + .D7(main_k7ddrphy_bitslip12[6]), + .D8(main_k7ddrphy_bitslip12[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay1), - .TQ(soc_k7ddrphy_dq_t1) + .OQ(main_k7ddrphy_dq_o_nodelay1), + .TQ(main_k7ddrphy_dq_t1) ); ISERDESE2 #( @@ -18106,16 +22617,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed1), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data1[7]), - .Q2(soc_k7ddrphy_dq_i_data1[6]), - .Q3(soc_k7ddrphy_dq_i_data1[5]), - .Q4(soc_k7ddrphy_dq_i_data1[4]), - .Q5(soc_k7ddrphy_dq_i_data1[3]), - .Q6(soc_k7ddrphy_dq_i_data1[2]), - .Q7(soc_k7ddrphy_dq_i_data1[1]), - .Q8(soc_k7ddrphy_dq_i_data1[0]) + .DDLY(main_k7ddrphy_dq_i_delayed1), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip13[7]), + .Q2(main_k7ddrphy_bitslip13[6]), + .Q3(main_k7ddrphy_bitslip13[5]), + .Q4(main_k7ddrphy_bitslip13[4]), + .Q5(main_k7ddrphy_bitslip13[3]), + .Q6(main_k7ddrphy_bitslip13[2]), + .Q7(main_k7ddrphy_bitslip13[1]), + .Q8(main_k7ddrphy_bitslip13[0]) ); ODELAYE2 #( @@ -18129,12 +22640,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_35 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed1), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay1) + .DATAOUT(main_k7ddrphy_dq_o_delayed1), + .ODATAIN(main_k7ddrphy_dq_o_nodelay1) ); IDELAYE2 #( @@ -18146,21 +22657,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_5 ( +) IDELAYE2_1 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay1), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed1) + .DATAOUT(main_k7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_k7ddrphy_dq_o_delayed1), - .T(soc_k7ddrphy_dq_t1), + .I(main_k7ddrphy_dq_o_delayed1), + .T(main_k7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_k7ddrphy_dq_i_nodelay1) + .O(main_k7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -18172,20 +22683,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[34]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[34]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[34]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[34]), + .D1(main_k7ddrphy_bitslip22[0]), + .D2(main_k7ddrphy_bitslip22[1]), + .D3(main_k7ddrphy_bitslip22[2]), + .D4(main_k7ddrphy_bitslip22[3]), + .D5(main_k7ddrphy_bitslip22[4]), + .D6(main_k7ddrphy_bitslip22[5]), + .D7(main_k7ddrphy_bitslip22[6]), + .D8(main_k7ddrphy_bitslip22[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay2), - .TQ(soc_k7ddrphy_dq_t2) + .OQ(main_k7ddrphy_dq_o_nodelay2), + .TQ(main_k7ddrphy_dq_t2) ); ISERDESE2 #( @@ -18201,16 +22712,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed2), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data2[7]), - .Q2(soc_k7ddrphy_dq_i_data2[6]), - .Q3(soc_k7ddrphy_dq_i_data2[5]), - .Q4(soc_k7ddrphy_dq_i_data2[4]), - .Q5(soc_k7ddrphy_dq_i_data2[3]), - .Q6(soc_k7ddrphy_dq_i_data2[2]), - .Q7(soc_k7ddrphy_dq_i_data2[1]), - .Q8(soc_k7ddrphy_dq_i_data2[0]) + .DDLY(main_k7ddrphy_dq_i_delayed2), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip23[7]), + .Q2(main_k7ddrphy_bitslip23[6]), + .Q3(main_k7ddrphy_bitslip23[5]), + .Q4(main_k7ddrphy_bitslip23[4]), + .Q5(main_k7ddrphy_bitslip23[3]), + .Q6(main_k7ddrphy_bitslip23[2]), + .Q7(main_k7ddrphy_bitslip23[1]), + .Q8(main_k7ddrphy_bitslip23[0]) ); ODELAYE2 #( @@ -18224,12 +22735,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_36 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed2), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay2) + .DATAOUT(main_k7ddrphy_dq_o_delayed2), + .ODATAIN(main_k7ddrphy_dq_o_nodelay2) ); IDELAYE2 #( @@ -18241,21 +22752,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_6 ( +) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay2), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed2) + .DATAOUT(main_k7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_k7ddrphy_dq_o_delayed2), - .T(soc_k7ddrphy_dq_t2), + .I(main_k7ddrphy_dq_o_delayed2), + .T(main_k7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_k7ddrphy_dq_i_nodelay2) + .O(main_k7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -18267,20 +22778,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[35]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[35]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[35]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[35]), + .D1(main_k7ddrphy_bitslip32[0]), + .D2(main_k7ddrphy_bitslip32[1]), + .D3(main_k7ddrphy_bitslip32[2]), + .D4(main_k7ddrphy_bitslip32[3]), + .D5(main_k7ddrphy_bitslip32[4]), + .D6(main_k7ddrphy_bitslip32[5]), + .D7(main_k7ddrphy_bitslip32[6]), + .D8(main_k7ddrphy_bitslip32[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay3), - .TQ(soc_k7ddrphy_dq_t3) + .OQ(main_k7ddrphy_dq_o_nodelay3), + .TQ(main_k7ddrphy_dq_t3) ); ISERDESE2 #( @@ -18296,16 +22807,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed3), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data3[7]), - .Q2(soc_k7ddrphy_dq_i_data3[6]), - .Q3(soc_k7ddrphy_dq_i_data3[5]), - .Q4(soc_k7ddrphy_dq_i_data3[4]), - .Q5(soc_k7ddrphy_dq_i_data3[3]), - .Q6(soc_k7ddrphy_dq_i_data3[2]), - .Q7(soc_k7ddrphy_dq_i_data3[1]), - .Q8(soc_k7ddrphy_dq_i_data3[0]) + .DDLY(main_k7ddrphy_dq_i_delayed3), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip33[7]), + .Q2(main_k7ddrphy_bitslip33[6]), + .Q3(main_k7ddrphy_bitslip33[5]), + .Q4(main_k7ddrphy_bitslip33[4]), + .Q5(main_k7ddrphy_bitslip33[3]), + .Q6(main_k7ddrphy_bitslip33[2]), + .Q7(main_k7ddrphy_bitslip33[1]), + .Q8(main_k7ddrphy_bitslip33[0]) ); ODELAYE2 #( @@ -18319,12 +22830,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_37 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed3), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay3) + .DATAOUT(main_k7ddrphy_dq_o_delayed3), + .ODATAIN(main_k7ddrphy_dq_o_nodelay3) ); IDELAYE2 #( @@ -18336,21 +22847,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_7 ( +) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay3), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed3) + .DATAOUT(main_k7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_k7ddrphy_dq_o_delayed3), - .T(soc_k7ddrphy_dq_t3), + .I(main_k7ddrphy_dq_o_delayed3), + .T(main_k7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_k7ddrphy_dq_i_nodelay3) + .O(main_k7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -18362,20 +22873,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[36]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[36]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[36]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[36]), + .D1(main_k7ddrphy_bitslip40[0]), + .D2(main_k7ddrphy_bitslip40[1]), + .D3(main_k7ddrphy_bitslip40[2]), + .D4(main_k7ddrphy_bitslip40[3]), + .D5(main_k7ddrphy_bitslip40[4]), + .D6(main_k7ddrphy_bitslip40[5]), + .D7(main_k7ddrphy_bitslip40[6]), + .D8(main_k7ddrphy_bitslip40[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay4), - .TQ(soc_k7ddrphy_dq_t4) + .OQ(main_k7ddrphy_dq_o_nodelay4), + .TQ(main_k7ddrphy_dq_t4) ); ISERDESE2 #( @@ -18391,16 +22902,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed4), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data4[7]), - .Q2(soc_k7ddrphy_dq_i_data4[6]), - .Q3(soc_k7ddrphy_dq_i_data4[5]), - .Q4(soc_k7ddrphy_dq_i_data4[4]), - .Q5(soc_k7ddrphy_dq_i_data4[3]), - .Q6(soc_k7ddrphy_dq_i_data4[2]), - .Q7(soc_k7ddrphy_dq_i_data4[1]), - .Q8(soc_k7ddrphy_dq_i_data4[0]) + .DDLY(main_k7ddrphy_dq_i_delayed4), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip41[7]), + .Q2(main_k7ddrphy_bitslip41[6]), + .Q3(main_k7ddrphy_bitslip41[5]), + .Q4(main_k7ddrphy_bitslip41[4]), + .Q5(main_k7ddrphy_bitslip41[3]), + .Q6(main_k7ddrphy_bitslip41[2]), + .Q7(main_k7ddrphy_bitslip41[1]), + .Q8(main_k7ddrphy_bitslip41[0]) ); ODELAYE2 #( @@ -18414,12 +22925,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_38 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed4), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay4) + .DATAOUT(main_k7ddrphy_dq_o_delayed4), + .ODATAIN(main_k7ddrphy_dq_o_nodelay4) ); IDELAYE2 #( @@ -18431,21 +22942,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_8 ( +) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay4), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed4) + .DATAOUT(main_k7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_k7ddrphy_dq_o_delayed4), - .T(soc_k7ddrphy_dq_t4), + .I(main_k7ddrphy_dq_o_delayed4), + .T(main_k7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_k7ddrphy_dq_i_nodelay4) + .O(main_k7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -18457,20 +22968,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[37]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[37]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[37]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[37]), + .D1(main_k7ddrphy_bitslip50[0]), + .D2(main_k7ddrphy_bitslip50[1]), + .D3(main_k7ddrphy_bitslip50[2]), + .D4(main_k7ddrphy_bitslip50[3]), + .D5(main_k7ddrphy_bitslip50[4]), + .D6(main_k7ddrphy_bitslip50[5]), + .D7(main_k7ddrphy_bitslip50[6]), + .D8(main_k7ddrphy_bitslip50[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay5), - .TQ(soc_k7ddrphy_dq_t5) + .OQ(main_k7ddrphy_dq_o_nodelay5), + .TQ(main_k7ddrphy_dq_t5) ); ISERDESE2 #( @@ -18486,16 +22997,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed5), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data5[7]), - .Q2(soc_k7ddrphy_dq_i_data5[6]), - .Q3(soc_k7ddrphy_dq_i_data5[5]), - .Q4(soc_k7ddrphy_dq_i_data5[4]), - .Q5(soc_k7ddrphy_dq_i_data5[3]), - .Q6(soc_k7ddrphy_dq_i_data5[2]), - .Q7(soc_k7ddrphy_dq_i_data5[1]), - .Q8(soc_k7ddrphy_dq_i_data5[0]) + .DDLY(main_k7ddrphy_dq_i_delayed5), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip51[7]), + .Q2(main_k7ddrphy_bitslip51[6]), + .Q3(main_k7ddrphy_bitslip51[5]), + .Q4(main_k7ddrphy_bitslip51[4]), + .Q5(main_k7ddrphy_bitslip51[3]), + .Q6(main_k7ddrphy_bitslip51[2]), + .Q7(main_k7ddrphy_bitslip51[1]), + .Q8(main_k7ddrphy_bitslip51[0]) ); ODELAYE2 #( @@ -18509,12 +23020,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_39 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed5), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay5) + .DATAOUT(main_k7ddrphy_dq_o_delayed5), + .ODATAIN(main_k7ddrphy_dq_o_nodelay5) ); IDELAYE2 #( @@ -18526,21 +23037,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_9 ( +) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay5), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed5) + .DATAOUT(main_k7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_k7ddrphy_dq_o_delayed5), - .T(soc_k7ddrphy_dq_t5), + .I(main_k7ddrphy_dq_o_delayed5), + .T(main_k7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_k7ddrphy_dq_i_nodelay5) + .O(main_k7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -18552,20 +23063,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[38]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[38]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[38]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[38]), + .D1(main_k7ddrphy_bitslip60[0]), + .D2(main_k7ddrphy_bitslip60[1]), + .D3(main_k7ddrphy_bitslip60[2]), + .D4(main_k7ddrphy_bitslip60[3]), + .D5(main_k7ddrphy_bitslip60[4]), + .D6(main_k7ddrphy_bitslip60[5]), + .D7(main_k7ddrphy_bitslip60[6]), + .D8(main_k7ddrphy_bitslip60[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay6), - .TQ(soc_k7ddrphy_dq_t6) + .OQ(main_k7ddrphy_dq_o_nodelay6), + .TQ(main_k7ddrphy_dq_t6) ); ISERDESE2 #( @@ -18581,16 +23092,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed6), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data6[7]), - .Q2(soc_k7ddrphy_dq_i_data6[6]), - .Q3(soc_k7ddrphy_dq_i_data6[5]), - .Q4(soc_k7ddrphy_dq_i_data6[4]), - .Q5(soc_k7ddrphy_dq_i_data6[3]), - .Q6(soc_k7ddrphy_dq_i_data6[2]), - .Q7(soc_k7ddrphy_dq_i_data6[1]), - .Q8(soc_k7ddrphy_dq_i_data6[0]) + .DDLY(main_k7ddrphy_dq_i_delayed6), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip61[7]), + .Q2(main_k7ddrphy_bitslip61[6]), + .Q3(main_k7ddrphy_bitslip61[5]), + .Q4(main_k7ddrphy_bitslip61[4]), + .Q5(main_k7ddrphy_bitslip61[3]), + .Q6(main_k7ddrphy_bitslip61[2]), + .Q7(main_k7ddrphy_bitslip61[1]), + .Q8(main_k7ddrphy_bitslip61[0]) ); ODELAYE2 #( @@ -18604,12 +23115,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_40 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed6), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay6) + .DATAOUT(main_k7ddrphy_dq_o_delayed6), + .ODATAIN(main_k7ddrphy_dq_o_nodelay6) ); IDELAYE2 #( @@ -18621,21 +23132,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_10 ( +) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay6), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed6) + .DATAOUT(main_k7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_k7ddrphy_dq_o_delayed6), - .T(soc_k7ddrphy_dq_t6), + .I(main_k7ddrphy_dq_o_delayed6), + .T(main_k7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_k7ddrphy_dq_i_nodelay6) + .O(main_k7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -18647,20 +23158,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[39]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[39]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[39]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[39]), + .D1(main_k7ddrphy_bitslip70[0]), + .D2(main_k7ddrphy_bitslip70[1]), + .D3(main_k7ddrphy_bitslip70[2]), + .D4(main_k7ddrphy_bitslip70[3]), + .D5(main_k7ddrphy_bitslip70[4]), + .D6(main_k7ddrphy_bitslip70[5]), + .D7(main_k7ddrphy_bitslip70[6]), + .D8(main_k7ddrphy_bitslip70[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay7), - .TQ(soc_k7ddrphy_dq_t7) + .OQ(main_k7ddrphy_dq_o_nodelay7), + .TQ(main_k7ddrphy_dq_t7) ); ISERDESE2 #( @@ -18676,16 +23187,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed7), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data7[7]), - .Q2(soc_k7ddrphy_dq_i_data7[6]), - .Q3(soc_k7ddrphy_dq_i_data7[5]), - .Q4(soc_k7ddrphy_dq_i_data7[4]), - .Q5(soc_k7ddrphy_dq_i_data7[3]), - .Q6(soc_k7ddrphy_dq_i_data7[2]), - .Q7(soc_k7ddrphy_dq_i_data7[1]), - .Q8(soc_k7ddrphy_dq_i_data7[0]) + .DDLY(main_k7ddrphy_dq_i_delayed7), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip71[7]), + .Q2(main_k7ddrphy_bitslip71[6]), + .Q3(main_k7ddrphy_bitslip71[5]), + .Q4(main_k7ddrphy_bitslip71[4]), + .Q5(main_k7ddrphy_bitslip71[3]), + .Q6(main_k7ddrphy_bitslip71[2]), + .Q7(main_k7ddrphy_bitslip71[1]), + .Q8(main_k7ddrphy_bitslip71[0]) ); ODELAYE2 #( @@ -18699,12 +23210,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_41 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed7), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay7) + .DATAOUT(main_k7ddrphy_dq_o_delayed7), + .ODATAIN(main_k7ddrphy_dq_o_nodelay7) ); IDELAYE2 #( @@ -18716,21 +23227,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_11 ( +) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay7), + .CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed7) + .DATAOUT(main_k7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_k7ddrphy_dq_o_delayed7), - .T(soc_k7ddrphy_dq_t7), + .I(main_k7ddrphy_dq_o_delayed7), + .T(main_k7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_k7ddrphy_dq_i_nodelay7) + .O(main_k7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -18742,20 +23253,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[40]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[40]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[40]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[40]), + .D1(main_k7ddrphy_bitslip80[0]), + .D2(main_k7ddrphy_bitslip80[1]), + .D3(main_k7ddrphy_bitslip80[2]), + .D4(main_k7ddrphy_bitslip80[3]), + .D5(main_k7ddrphy_bitslip80[4]), + .D6(main_k7ddrphy_bitslip80[5]), + .D7(main_k7ddrphy_bitslip80[6]), + .D8(main_k7ddrphy_bitslip80[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay8), - .TQ(soc_k7ddrphy_dq_t8) + .OQ(main_k7ddrphy_dq_o_nodelay8), + .TQ(main_k7ddrphy_dq_t8) ); ISERDESE2 #( @@ -18771,16 +23282,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed8), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data8[7]), - .Q2(soc_k7ddrphy_dq_i_data8[6]), - .Q3(soc_k7ddrphy_dq_i_data8[5]), - .Q4(soc_k7ddrphy_dq_i_data8[4]), - .Q5(soc_k7ddrphy_dq_i_data8[3]), - .Q6(soc_k7ddrphy_dq_i_data8[2]), - .Q7(soc_k7ddrphy_dq_i_data8[1]), - .Q8(soc_k7ddrphy_dq_i_data8[0]) + .DDLY(main_k7ddrphy_dq_i_delayed8), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip81[7]), + .Q2(main_k7ddrphy_bitslip81[6]), + .Q3(main_k7ddrphy_bitslip81[5]), + .Q4(main_k7ddrphy_bitslip81[4]), + .Q5(main_k7ddrphy_bitslip81[3]), + .Q6(main_k7ddrphy_bitslip81[2]), + .Q7(main_k7ddrphy_bitslip81[1]), + .Q8(main_k7ddrphy_bitslip81[0]) ); ODELAYE2 #( @@ -18794,12 +23305,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_42 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed8), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay8) + .DATAOUT(main_k7ddrphy_dq_o_delayed8), + .ODATAIN(main_k7ddrphy_dq_o_nodelay8) ); IDELAYE2 #( @@ -18811,21 +23322,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_12 ( +) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay8), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed8) + .DATAOUT(main_k7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_k7ddrphy_dq_o_delayed8), - .T(soc_k7ddrphy_dq_t8), + .I(main_k7ddrphy_dq_o_delayed8), + .T(main_k7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_k7ddrphy_dq_i_nodelay8) + .O(main_k7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -18837,20 +23348,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[41]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[41]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[41]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[41]), + .D1(main_k7ddrphy_bitslip90[0]), + .D2(main_k7ddrphy_bitslip90[1]), + .D3(main_k7ddrphy_bitslip90[2]), + .D4(main_k7ddrphy_bitslip90[3]), + .D5(main_k7ddrphy_bitslip90[4]), + .D6(main_k7ddrphy_bitslip90[5]), + .D7(main_k7ddrphy_bitslip90[6]), + .D8(main_k7ddrphy_bitslip90[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay9), - .TQ(soc_k7ddrphy_dq_t9) + .OQ(main_k7ddrphy_dq_o_nodelay9), + .TQ(main_k7ddrphy_dq_t9) ); ISERDESE2 #( @@ -18866,16 +23377,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed9), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data9[7]), - .Q2(soc_k7ddrphy_dq_i_data9[6]), - .Q3(soc_k7ddrphy_dq_i_data9[5]), - .Q4(soc_k7ddrphy_dq_i_data9[4]), - .Q5(soc_k7ddrphy_dq_i_data9[3]), - .Q6(soc_k7ddrphy_dq_i_data9[2]), - .Q7(soc_k7ddrphy_dq_i_data9[1]), - .Q8(soc_k7ddrphy_dq_i_data9[0]) + .DDLY(main_k7ddrphy_dq_i_delayed9), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip91[7]), + .Q2(main_k7ddrphy_bitslip91[6]), + .Q3(main_k7ddrphy_bitslip91[5]), + .Q4(main_k7ddrphy_bitslip91[4]), + .Q5(main_k7ddrphy_bitslip91[3]), + .Q6(main_k7ddrphy_bitslip91[2]), + .Q7(main_k7ddrphy_bitslip91[1]), + .Q8(main_k7ddrphy_bitslip91[0]) ); ODELAYE2 #( @@ -18889,12 +23400,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_43 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed9), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay9) + .DATAOUT(main_k7ddrphy_dq_o_delayed9), + .ODATAIN(main_k7ddrphy_dq_o_nodelay9) ); IDELAYE2 #( @@ -18906,21 +23417,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_13 ( +) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay9), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed9) + .DATAOUT(main_k7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_k7ddrphy_dq_o_delayed9), - .T(soc_k7ddrphy_dq_t9), + .I(main_k7ddrphy_dq_o_delayed9), + .T(main_k7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_k7ddrphy_dq_i_nodelay9) + .O(main_k7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -18932,20 +23443,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[42]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[42]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[42]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[42]), + .D1(main_k7ddrphy_bitslip100[0]), + .D2(main_k7ddrphy_bitslip100[1]), + .D3(main_k7ddrphy_bitslip100[2]), + .D4(main_k7ddrphy_bitslip100[3]), + .D5(main_k7ddrphy_bitslip100[4]), + .D6(main_k7ddrphy_bitslip100[5]), + .D7(main_k7ddrphy_bitslip100[6]), + .D8(main_k7ddrphy_bitslip100[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay10), - .TQ(soc_k7ddrphy_dq_t10) + .OQ(main_k7ddrphy_dq_o_nodelay10), + .TQ(main_k7ddrphy_dq_t10) ); ISERDESE2 #( @@ -18961,16 +23472,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed10), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data10[7]), - .Q2(soc_k7ddrphy_dq_i_data10[6]), - .Q3(soc_k7ddrphy_dq_i_data10[5]), - .Q4(soc_k7ddrphy_dq_i_data10[4]), - .Q5(soc_k7ddrphy_dq_i_data10[3]), - .Q6(soc_k7ddrphy_dq_i_data10[2]), - .Q7(soc_k7ddrphy_dq_i_data10[1]), - .Q8(soc_k7ddrphy_dq_i_data10[0]) + .DDLY(main_k7ddrphy_dq_i_delayed10), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip101[7]), + .Q2(main_k7ddrphy_bitslip101[6]), + .Q3(main_k7ddrphy_bitslip101[5]), + .Q4(main_k7ddrphy_bitslip101[4]), + .Q5(main_k7ddrphy_bitslip101[3]), + .Q6(main_k7ddrphy_bitslip101[2]), + .Q7(main_k7ddrphy_bitslip101[1]), + .Q8(main_k7ddrphy_bitslip101[0]) ); ODELAYE2 #( @@ -18984,12 +23495,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_44 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed10), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay10) + .DATAOUT(main_k7ddrphy_dq_o_delayed10), + .ODATAIN(main_k7ddrphy_dq_o_nodelay10) ); IDELAYE2 #( @@ -19001,21 +23512,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_14 ( +) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay10), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed10) + .DATAOUT(main_k7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_k7ddrphy_dq_o_delayed10), - .T(soc_k7ddrphy_dq_t10), + .I(main_k7ddrphy_dq_o_delayed10), + .T(main_k7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_k7ddrphy_dq_i_nodelay10) + .O(main_k7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -19027,20 +23538,20 @@ OSERDESE2 #( ) OSERDESE2_45 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[43]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[43]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[43]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[43]), + .D1(main_k7ddrphy_bitslip110[0]), + .D2(main_k7ddrphy_bitslip110[1]), + .D3(main_k7ddrphy_bitslip110[2]), + .D4(main_k7ddrphy_bitslip110[3]), + .D5(main_k7ddrphy_bitslip110[4]), + .D6(main_k7ddrphy_bitslip110[5]), + .D7(main_k7ddrphy_bitslip110[6]), + .D8(main_k7ddrphy_bitslip110[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay11), - .TQ(soc_k7ddrphy_dq_t11) + .OQ(main_k7ddrphy_dq_o_nodelay11), + .TQ(main_k7ddrphy_dq_t11) ); ISERDESE2 #( @@ -19056,16 +23567,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed11), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data11[7]), - .Q2(soc_k7ddrphy_dq_i_data11[6]), - .Q3(soc_k7ddrphy_dq_i_data11[5]), - .Q4(soc_k7ddrphy_dq_i_data11[4]), - .Q5(soc_k7ddrphy_dq_i_data11[3]), - .Q6(soc_k7ddrphy_dq_i_data11[2]), - .Q7(soc_k7ddrphy_dq_i_data11[1]), - .Q8(soc_k7ddrphy_dq_i_data11[0]) + .DDLY(main_k7ddrphy_dq_i_delayed11), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip111[7]), + .Q2(main_k7ddrphy_bitslip111[6]), + .Q3(main_k7ddrphy_bitslip111[5]), + .Q4(main_k7ddrphy_bitslip111[4]), + .Q5(main_k7ddrphy_bitslip111[3]), + .Q6(main_k7ddrphy_bitslip111[2]), + .Q7(main_k7ddrphy_bitslip111[1]), + .Q8(main_k7ddrphy_bitslip111[0]) ); ODELAYE2 #( @@ -19079,12 +23590,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_45 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed11), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay11) + .DATAOUT(main_k7ddrphy_dq_o_delayed11), + .ODATAIN(main_k7ddrphy_dq_o_nodelay11) ); IDELAYE2 #( @@ -19096,21 +23607,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_15 ( +) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay11), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed11) + .DATAOUT(main_k7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_k7ddrphy_dq_o_delayed11), - .T(soc_k7ddrphy_dq_t11), + .I(main_k7ddrphy_dq_o_delayed11), + .T(main_k7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_k7ddrphy_dq_i_nodelay11) + .O(main_k7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -19122,20 +23633,20 @@ OSERDESE2 #( ) OSERDESE2_46 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[44]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[44]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[44]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[44]), + .D1(main_k7ddrphy_bitslip120[0]), + .D2(main_k7ddrphy_bitslip120[1]), + .D3(main_k7ddrphy_bitslip120[2]), + .D4(main_k7ddrphy_bitslip120[3]), + .D5(main_k7ddrphy_bitslip120[4]), + .D6(main_k7ddrphy_bitslip120[5]), + .D7(main_k7ddrphy_bitslip120[6]), + .D8(main_k7ddrphy_bitslip120[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay12), - .TQ(soc_k7ddrphy_dq_t12) + .OQ(main_k7ddrphy_dq_o_nodelay12), + .TQ(main_k7ddrphy_dq_t12) ); ISERDESE2 #( @@ -19151,16 +23662,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed12), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data12[7]), - .Q2(soc_k7ddrphy_dq_i_data12[6]), - .Q3(soc_k7ddrphy_dq_i_data12[5]), - .Q4(soc_k7ddrphy_dq_i_data12[4]), - .Q5(soc_k7ddrphy_dq_i_data12[3]), - .Q6(soc_k7ddrphy_dq_i_data12[2]), - .Q7(soc_k7ddrphy_dq_i_data12[1]), - .Q8(soc_k7ddrphy_dq_i_data12[0]) + .DDLY(main_k7ddrphy_dq_i_delayed12), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip121[7]), + .Q2(main_k7ddrphy_bitslip121[6]), + .Q3(main_k7ddrphy_bitslip121[5]), + .Q4(main_k7ddrphy_bitslip121[4]), + .Q5(main_k7ddrphy_bitslip121[3]), + .Q6(main_k7ddrphy_bitslip121[2]), + .Q7(main_k7ddrphy_bitslip121[1]), + .Q8(main_k7ddrphy_bitslip121[0]) ); ODELAYE2 #( @@ -19174,12 +23685,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_46 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed12), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay12) + .DATAOUT(main_k7ddrphy_dq_o_delayed12), + .ODATAIN(main_k7ddrphy_dq_o_nodelay12) ); IDELAYE2 #( @@ -19191,21 +23702,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_16 ( +) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay12), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed12) + .DATAOUT(main_k7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_k7ddrphy_dq_o_delayed12), - .T(soc_k7ddrphy_dq_t12), + .I(main_k7ddrphy_dq_o_delayed12), + .T(main_k7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_k7ddrphy_dq_i_nodelay12) + .O(main_k7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -19217,20 +23728,20 @@ OSERDESE2 #( ) OSERDESE2_47 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[45]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[45]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[45]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[45]), + .D1(main_k7ddrphy_bitslip130[0]), + .D2(main_k7ddrphy_bitslip130[1]), + .D3(main_k7ddrphy_bitslip130[2]), + .D4(main_k7ddrphy_bitslip130[3]), + .D5(main_k7ddrphy_bitslip130[4]), + .D6(main_k7ddrphy_bitslip130[5]), + .D7(main_k7ddrphy_bitslip130[6]), + .D8(main_k7ddrphy_bitslip130[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay13), - .TQ(soc_k7ddrphy_dq_t13) + .OQ(main_k7ddrphy_dq_o_nodelay13), + .TQ(main_k7ddrphy_dq_t13) ); ISERDESE2 #( @@ -19246,16 +23757,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed13), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data13[7]), - .Q2(soc_k7ddrphy_dq_i_data13[6]), - .Q3(soc_k7ddrphy_dq_i_data13[5]), - .Q4(soc_k7ddrphy_dq_i_data13[4]), - .Q5(soc_k7ddrphy_dq_i_data13[3]), - .Q6(soc_k7ddrphy_dq_i_data13[2]), - .Q7(soc_k7ddrphy_dq_i_data13[1]), - .Q8(soc_k7ddrphy_dq_i_data13[0]) + .DDLY(main_k7ddrphy_dq_i_delayed13), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip131[7]), + .Q2(main_k7ddrphy_bitslip131[6]), + .Q3(main_k7ddrphy_bitslip131[5]), + .Q4(main_k7ddrphy_bitslip131[4]), + .Q5(main_k7ddrphy_bitslip131[3]), + .Q6(main_k7ddrphy_bitslip131[2]), + .Q7(main_k7ddrphy_bitslip131[1]), + .Q8(main_k7ddrphy_bitslip131[0]) ); ODELAYE2 #( @@ -19269,12 +23780,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_47 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed13), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay13) + .DATAOUT(main_k7ddrphy_dq_o_delayed13), + .ODATAIN(main_k7ddrphy_dq_o_nodelay13) ); IDELAYE2 #( @@ -19286,21 +23797,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_17 ( +) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay13), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed13) + .DATAOUT(main_k7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_k7ddrphy_dq_o_delayed13), - .T(soc_k7ddrphy_dq_t13), + .I(main_k7ddrphy_dq_o_delayed13), + .T(main_k7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_k7ddrphy_dq_i_nodelay13) + .O(main_k7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -19312,20 +23823,20 @@ OSERDESE2 #( ) OSERDESE2_48 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[46]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[46]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[46]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[46]), + .D1(main_k7ddrphy_bitslip140[0]), + .D2(main_k7ddrphy_bitslip140[1]), + .D3(main_k7ddrphy_bitslip140[2]), + .D4(main_k7ddrphy_bitslip140[3]), + .D5(main_k7ddrphy_bitslip140[4]), + .D6(main_k7ddrphy_bitslip140[5]), + .D7(main_k7ddrphy_bitslip140[6]), + .D8(main_k7ddrphy_bitslip140[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay14), - .TQ(soc_k7ddrphy_dq_t14) + .OQ(main_k7ddrphy_dq_o_nodelay14), + .TQ(main_k7ddrphy_dq_t14) ); ISERDESE2 #( @@ -19341,16 +23852,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed14), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data14[7]), - .Q2(soc_k7ddrphy_dq_i_data14[6]), - .Q3(soc_k7ddrphy_dq_i_data14[5]), - .Q4(soc_k7ddrphy_dq_i_data14[4]), - .Q5(soc_k7ddrphy_dq_i_data14[3]), - .Q6(soc_k7ddrphy_dq_i_data14[2]), - .Q7(soc_k7ddrphy_dq_i_data14[1]), - .Q8(soc_k7ddrphy_dq_i_data14[0]) + .DDLY(main_k7ddrphy_dq_i_delayed14), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip141[7]), + .Q2(main_k7ddrphy_bitslip141[6]), + .Q3(main_k7ddrphy_bitslip141[5]), + .Q4(main_k7ddrphy_bitslip141[4]), + .Q5(main_k7ddrphy_bitslip141[3]), + .Q6(main_k7ddrphy_bitslip141[2]), + .Q7(main_k7ddrphy_bitslip141[1]), + .Q8(main_k7ddrphy_bitslip141[0]) ); ODELAYE2 #( @@ -19364,12 +23875,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_48 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed14), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay14) + .DATAOUT(main_k7ddrphy_dq_o_delayed14), + .ODATAIN(main_k7ddrphy_dq_o_nodelay14) ); IDELAYE2 #( @@ -19381,21 +23892,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_18 ( +) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay14), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed14) + .DATAOUT(main_k7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_k7ddrphy_dq_o_delayed14), - .T(soc_k7ddrphy_dq_t14), + .I(main_k7ddrphy_dq_o_delayed14), + .T(main_k7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_k7ddrphy_dq_i_nodelay14) + .O(main_k7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -19407,20 +23918,20 @@ OSERDESE2 #( ) OSERDESE2_49 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[47]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[47]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[47]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[47]), + .D1(main_k7ddrphy_bitslip150[0]), + .D2(main_k7ddrphy_bitslip150[1]), + .D3(main_k7ddrphy_bitslip150[2]), + .D4(main_k7ddrphy_bitslip150[3]), + .D5(main_k7ddrphy_bitslip150[4]), + .D6(main_k7ddrphy_bitslip150[5]), + .D7(main_k7ddrphy_bitslip150[6]), + .D8(main_k7ddrphy_bitslip150[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay15), - .TQ(soc_k7ddrphy_dq_t15) + .OQ(main_k7ddrphy_dq_o_nodelay15), + .TQ(main_k7ddrphy_dq_t15) ); ISERDESE2 #( @@ -19436,16 +23947,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed15), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data15[7]), - .Q2(soc_k7ddrphy_dq_i_data15[6]), - .Q3(soc_k7ddrphy_dq_i_data15[5]), - .Q4(soc_k7ddrphy_dq_i_data15[4]), - .Q5(soc_k7ddrphy_dq_i_data15[3]), - .Q6(soc_k7ddrphy_dq_i_data15[2]), - .Q7(soc_k7ddrphy_dq_i_data15[1]), - .Q8(soc_k7ddrphy_dq_i_data15[0]) + .DDLY(main_k7ddrphy_dq_i_delayed15), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip151[7]), + .Q2(main_k7ddrphy_bitslip151[6]), + .Q3(main_k7ddrphy_bitslip151[5]), + .Q4(main_k7ddrphy_bitslip151[4]), + .Q5(main_k7ddrphy_bitslip151[3]), + .Q6(main_k7ddrphy_bitslip151[2]), + .Q7(main_k7ddrphy_bitslip151[1]), + .Q8(main_k7ddrphy_bitslip151[0]) ); ODELAYE2 #( @@ -19459,12 +23970,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_49 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed15), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay15) + .DATAOUT(main_k7ddrphy_dq_o_delayed15), + .ODATAIN(main_k7ddrphy_dq_o_nodelay15) ); IDELAYE2 #( @@ -19476,21 +23987,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_19 ( +) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay15), + .CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed15) + .DATAOUT(main_k7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_k7ddrphy_dq_o_delayed15), - .T(soc_k7ddrphy_dq_t15), + .I(main_k7ddrphy_dq_o_delayed15), + .T(main_k7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_k7ddrphy_dq_i_nodelay15) + .O(main_k7ddrphy_dq_i_nodelay15) ); OSERDESE2 #( @@ -19502,20 +24013,20 @@ OSERDESE2 #( ) OSERDESE2_50 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[16]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[48]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[16]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[48]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[16]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[48]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[16]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[48]), + .D1(main_k7ddrphy_bitslip160[0]), + .D2(main_k7ddrphy_bitslip160[1]), + .D3(main_k7ddrphy_bitslip160[2]), + .D4(main_k7ddrphy_bitslip160[3]), + .D5(main_k7ddrphy_bitslip160[4]), + .D6(main_k7ddrphy_bitslip160[5]), + .D7(main_k7ddrphy_bitslip160[6]), + .D8(main_k7ddrphy_bitslip160[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay16), - .TQ(soc_k7ddrphy_dq_t16) + .OQ(main_k7ddrphy_dq_o_nodelay16), + .TQ(main_k7ddrphy_dq_t16) ); ISERDESE2 #( @@ -19531,16 +24042,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed16), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data16[7]), - .Q2(soc_k7ddrphy_dq_i_data16[6]), - .Q3(soc_k7ddrphy_dq_i_data16[5]), - .Q4(soc_k7ddrphy_dq_i_data16[4]), - .Q5(soc_k7ddrphy_dq_i_data16[3]), - .Q6(soc_k7ddrphy_dq_i_data16[2]), - .Q7(soc_k7ddrphy_dq_i_data16[1]), - .Q8(soc_k7ddrphy_dq_i_data16[0]) + .DDLY(main_k7ddrphy_dq_i_delayed16), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip161[7]), + .Q2(main_k7ddrphy_bitslip161[6]), + .Q3(main_k7ddrphy_bitslip161[5]), + .Q4(main_k7ddrphy_bitslip161[4]), + .Q5(main_k7ddrphy_bitslip161[3]), + .Q6(main_k7ddrphy_bitslip161[2]), + .Q7(main_k7ddrphy_bitslip161[1]), + .Q8(main_k7ddrphy_bitslip161[0]) ); ODELAYE2 #( @@ -19554,12 +24065,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_50 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed16), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay16) + .DATAOUT(main_k7ddrphy_dq_o_delayed16), + .ODATAIN(main_k7ddrphy_dq_o_nodelay16) ); IDELAYE2 #( @@ -19571,21 +24082,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_20 ( +) IDELAYE2_16 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay16), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay16), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed16) + .DATAOUT(main_k7ddrphy_dq_i_delayed16) ); IOBUF IOBUF_16( - .I(soc_k7ddrphy_dq_o_delayed16), - .T(soc_k7ddrphy_dq_t16), + .I(main_k7ddrphy_dq_o_delayed16), + .T(main_k7ddrphy_dq_t16), .IO(ddram_dq[16]), - .O(soc_k7ddrphy_dq_i_nodelay16) + .O(main_k7ddrphy_dq_i_nodelay16) ); OSERDESE2 #( @@ -19597,20 +24108,20 @@ OSERDESE2 #( ) OSERDESE2_51 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[17]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[49]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[17]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[49]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[17]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[49]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[17]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[49]), + .D1(main_k7ddrphy_bitslip170[0]), + .D2(main_k7ddrphy_bitslip170[1]), + .D3(main_k7ddrphy_bitslip170[2]), + .D4(main_k7ddrphy_bitslip170[3]), + .D5(main_k7ddrphy_bitslip170[4]), + .D6(main_k7ddrphy_bitslip170[5]), + .D7(main_k7ddrphy_bitslip170[6]), + .D8(main_k7ddrphy_bitslip170[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay17), - .TQ(soc_k7ddrphy_dq_t17) + .OQ(main_k7ddrphy_dq_o_nodelay17), + .TQ(main_k7ddrphy_dq_t17) ); ISERDESE2 #( @@ -19626,16 +24137,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed17), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data17[7]), - .Q2(soc_k7ddrphy_dq_i_data17[6]), - .Q3(soc_k7ddrphy_dq_i_data17[5]), - .Q4(soc_k7ddrphy_dq_i_data17[4]), - .Q5(soc_k7ddrphy_dq_i_data17[3]), - .Q6(soc_k7ddrphy_dq_i_data17[2]), - .Q7(soc_k7ddrphy_dq_i_data17[1]), - .Q8(soc_k7ddrphy_dq_i_data17[0]) + .DDLY(main_k7ddrphy_dq_i_delayed17), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip171[7]), + .Q2(main_k7ddrphy_bitslip171[6]), + .Q3(main_k7ddrphy_bitslip171[5]), + .Q4(main_k7ddrphy_bitslip171[4]), + .Q5(main_k7ddrphy_bitslip171[3]), + .Q6(main_k7ddrphy_bitslip171[2]), + .Q7(main_k7ddrphy_bitslip171[1]), + .Q8(main_k7ddrphy_bitslip171[0]) ); ODELAYE2 #( @@ -19649,12 +24160,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_51 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed17), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay17) + .DATAOUT(main_k7ddrphy_dq_o_delayed17), + .ODATAIN(main_k7ddrphy_dq_o_nodelay17) ); IDELAYE2 #( @@ -19666,21 +24177,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_21 ( +) IDELAYE2_17 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay17), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay17), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed17) + .DATAOUT(main_k7ddrphy_dq_i_delayed17) ); IOBUF IOBUF_17( - .I(soc_k7ddrphy_dq_o_delayed17), - .T(soc_k7ddrphy_dq_t17), + .I(main_k7ddrphy_dq_o_delayed17), + .T(main_k7ddrphy_dq_t17), .IO(ddram_dq[17]), - .O(soc_k7ddrphy_dq_i_nodelay17) + .O(main_k7ddrphy_dq_i_nodelay17) ); OSERDESE2 #( @@ -19692,20 +24203,20 @@ OSERDESE2 #( ) OSERDESE2_52 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[18]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[50]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[18]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[50]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[18]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[50]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[18]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[50]), + .D1(main_k7ddrphy_bitslip180[0]), + .D2(main_k7ddrphy_bitslip180[1]), + .D3(main_k7ddrphy_bitslip180[2]), + .D4(main_k7ddrphy_bitslip180[3]), + .D5(main_k7ddrphy_bitslip180[4]), + .D6(main_k7ddrphy_bitslip180[5]), + .D7(main_k7ddrphy_bitslip180[6]), + .D8(main_k7ddrphy_bitslip180[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay18), - .TQ(soc_k7ddrphy_dq_t18) + .OQ(main_k7ddrphy_dq_o_nodelay18), + .TQ(main_k7ddrphy_dq_t18) ); ISERDESE2 #( @@ -19721,16 +24232,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed18), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data18[7]), - .Q2(soc_k7ddrphy_dq_i_data18[6]), - .Q3(soc_k7ddrphy_dq_i_data18[5]), - .Q4(soc_k7ddrphy_dq_i_data18[4]), - .Q5(soc_k7ddrphy_dq_i_data18[3]), - .Q6(soc_k7ddrphy_dq_i_data18[2]), - .Q7(soc_k7ddrphy_dq_i_data18[1]), - .Q8(soc_k7ddrphy_dq_i_data18[0]) + .DDLY(main_k7ddrphy_dq_i_delayed18), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip181[7]), + .Q2(main_k7ddrphy_bitslip181[6]), + .Q3(main_k7ddrphy_bitslip181[5]), + .Q4(main_k7ddrphy_bitslip181[4]), + .Q5(main_k7ddrphy_bitslip181[3]), + .Q6(main_k7ddrphy_bitslip181[2]), + .Q7(main_k7ddrphy_bitslip181[1]), + .Q8(main_k7ddrphy_bitslip181[0]) ); ODELAYE2 #( @@ -19744,12 +24255,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_52 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed18), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay18) + .DATAOUT(main_k7ddrphy_dq_o_delayed18), + .ODATAIN(main_k7ddrphy_dq_o_nodelay18) ); IDELAYE2 #( @@ -19761,21 +24272,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_22 ( +) IDELAYE2_18 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay18), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay18), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed18) + .DATAOUT(main_k7ddrphy_dq_i_delayed18) ); IOBUF IOBUF_18( - .I(soc_k7ddrphy_dq_o_delayed18), - .T(soc_k7ddrphy_dq_t18), + .I(main_k7ddrphy_dq_o_delayed18), + .T(main_k7ddrphy_dq_t18), .IO(ddram_dq[18]), - .O(soc_k7ddrphy_dq_i_nodelay18) + .O(main_k7ddrphy_dq_i_nodelay18) ); OSERDESE2 #( @@ -19787,20 +24298,20 @@ OSERDESE2 #( ) OSERDESE2_53 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[19]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[51]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[19]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[51]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[19]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[51]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[19]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[51]), + .D1(main_k7ddrphy_bitslip190[0]), + .D2(main_k7ddrphy_bitslip190[1]), + .D3(main_k7ddrphy_bitslip190[2]), + .D4(main_k7ddrphy_bitslip190[3]), + .D5(main_k7ddrphy_bitslip190[4]), + .D6(main_k7ddrphy_bitslip190[5]), + .D7(main_k7ddrphy_bitslip190[6]), + .D8(main_k7ddrphy_bitslip190[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay19), - .TQ(soc_k7ddrphy_dq_t19) + .OQ(main_k7ddrphy_dq_o_nodelay19), + .TQ(main_k7ddrphy_dq_t19) ); ISERDESE2 #( @@ -19816,16 +24327,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed19), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data19[7]), - .Q2(soc_k7ddrphy_dq_i_data19[6]), - .Q3(soc_k7ddrphy_dq_i_data19[5]), - .Q4(soc_k7ddrphy_dq_i_data19[4]), - .Q5(soc_k7ddrphy_dq_i_data19[3]), - .Q6(soc_k7ddrphy_dq_i_data19[2]), - .Q7(soc_k7ddrphy_dq_i_data19[1]), - .Q8(soc_k7ddrphy_dq_i_data19[0]) + .DDLY(main_k7ddrphy_dq_i_delayed19), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip191[7]), + .Q2(main_k7ddrphy_bitslip191[6]), + .Q3(main_k7ddrphy_bitslip191[5]), + .Q4(main_k7ddrphy_bitslip191[4]), + .Q5(main_k7ddrphy_bitslip191[3]), + .Q6(main_k7ddrphy_bitslip191[2]), + .Q7(main_k7ddrphy_bitslip191[1]), + .Q8(main_k7ddrphy_bitslip191[0]) ); ODELAYE2 #( @@ -19839,12 +24350,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_53 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed19), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay19) + .DATAOUT(main_k7ddrphy_dq_o_delayed19), + .ODATAIN(main_k7ddrphy_dq_o_nodelay19) ); IDELAYE2 #( @@ -19856,21 +24367,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_23 ( +) IDELAYE2_19 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay19), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay19), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed19) + .DATAOUT(main_k7ddrphy_dq_i_delayed19) ); IOBUF IOBUF_19( - .I(soc_k7ddrphy_dq_o_delayed19), - .T(soc_k7ddrphy_dq_t19), + .I(main_k7ddrphy_dq_o_delayed19), + .T(main_k7ddrphy_dq_t19), .IO(ddram_dq[19]), - .O(soc_k7ddrphy_dq_i_nodelay19) + .O(main_k7ddrphy_dq_i_nodelay19) ); OSERDESE2 #( @@ -19882,20 +24393,20 @@ OSERDESE2 #( ) OSERDESE2_54 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[20]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[52]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[20]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[52]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[20]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[52]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[20]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[52]), + .D1(main_k7ddrphy_bitslip200[0]), + .D2(main_k7ddrphy_bitslip200[1]), + .D3(main_k7ddrphy_bitslip200[2]), + .D4(main_k7ddrphy_bitslip200[3]), + .D5(main_k7ddrphy_bitslip200[4]), + .D6(main_k7ddrphy_bitslip200[5]), + .D7(main_k7ddrphy_bitslip200[6]), + .D8(main_k7ddrphy_bitslip200[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay20), - .TQ(soc_k7ddrphy_dq_t20) + .OQ(main_k7ddrphy_dq_o_nodelay20), + .TQ(main_k7ddrphy_dq_t20) ); ISERDESE2 #( @@ -19911,16 +24422,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed20), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data20[7]), - .Q2(soc_k7ddrphy_dq_i_data20[6]), - .Q3(soc_k7ddrphy_dq_i_data20[5]), - .Q4(soc_k7ddrphy_dq_i_data20[4]), - .Q5(soc_k7ddrphy_dq_i_data20[3]), - .Q6(soc_k7ddrphy_dq_i_data20[2]), - .Q7(soc_k7ddrphy_dq_i_data20[1]), - .Q8(soc_k7ddrphy_dq_i_data20[0]) + .DDLY(main_k7ddrphy_dq_i_delayed20), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip201[7]), + .Q2(main_k7ddrphy_bitslip201[6]), + .Q3(main_k7ddrphy_bitslip201[5]), + .Q4(main_k7ddrphy_bitslip201[4]), + .Q5(main_k7ddrphy_bitslip201[3]), + .Q6(main_k7ddrphy_bitslip201[2]), + .Q7(main_k7ddrphy_bitslip201[1]), + .Q8(main_k7ddrphy_bitslip201[0]) ); ODELAYE2 #( @@ -19934,12 +24445,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_54 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed20), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay20) + .DATAOUT(main_k7ddrphy_dq_o_delayed20), + .ODATAIN(main_k7ddrphy_dq_o_nodelay20) ); IDELAYE2 #( @@ -19951,21 +24462,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_24 ( +) IDELAYE2_20 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay20), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay20), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed20) + .DATAOUT(main_k7ddrphy_dq_i_delayed20) ); IOBUF IOBUF_20( - .I(soc_k7ddrphy_dq_o_delayed20), - .T(soc_k7ddrphy_dq_t20), + .I(main_k7ddrphy_dq_o_delayed20), + .T(main_k7ddrphy_dq_t20), .IO(ddram_dq[20]), - .O(soc_k7ddrphy_dq_i_nodelay20) + .O(main_k7ddrphy_dq_i_nodelay20) ); OSERDESE2 #( @@ -19977,20 +24488,20 @@ OSERDESE2 #( ) OSERDESE2_55 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[21]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[53]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[21]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[53]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[21]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[53]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[21]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[53]), + .D1(main_k7ddrphy_bitslip210[0]), + .D2(main_k7ddrphy_bitslip210[1]), + .D3(main_k7ddrphy_bitslip210[2]), + .D4(main_k7ddrphy_bitslip210[3]), + .D5(main_k7ddrphy_bitslip210[4]), + .D6(main_k7ddrphy_bitslip210[5]), + .D7(main_k7ddrphy_bitslip210[6]), + .D8(main_k7ddrphy_bitslip210[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay21), - .TQ(soc_k7ddrphy_dq_t21) + .OQ(main_k7ddrphy_dq_o_nodelay21), + .TQ(main_k7ddrphy_dq_t21) ); ISERDESE2 #( @@ -20006,16 +24517,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed21), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data21[7]), - .Q2(soc_k7ddrphy_dq_i_data21[6]), - .Q3(soc_k7ddrphy_dq_i_data21[5]), - .Q4(soc_k7ddrphy_dq_i_data21[4]), - .Q5(soc_k7ddrphy_dq_i_data21[3]), - .Q6(soc_k7ddrphy_dq_i_data21[2]), - .Q7(soc_k7ddrphy_dq_i_data21[1]), - .Q8(soc_k7ddrphy_dq_i_data21[0]) + .DDLY(main_k7ddrphy_dq_i_delayed21), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip211[7]), + .Q2(main_k7ddrphy_bitslip211[6]), + .Q3(main_k7ddrphy_bitslip211[5]), + .Q4(main_k7ddrphy_bitslip211[4]), + .Q5(main_k7ddrphy_bitslip211[3]), + .Q6(main_k7ddrphy_bitslip211[2]), + .Q7(main_k7ddrphy_bitslip211[1]), + .Q8(main_k7ddrphy_bitslip211[0]) ); ODELAYE2 #( @@ -20029,12 +24540,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_55 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed21), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay21) + .DATAOUT(main_k7ddrphy_dq_o_delayed21), + .ODATAIN(main_k7ddrphy_dq_o_nodelay21) ); IDELAYE2 #( @@ -20046,21 +24557,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_25 ( +) IDELAYE2_21 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay21), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay21), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed21) + .DATAOUT(main_k7ddrphy_dq_i_delayed21) ); IOBUF IOBUF_21( - .I(soc_k7ddrphy_dq_o_delayed21), - .T(soc_k7ddrphy_dq_t21), + .I(main_k7ddrphy_dq_o_delayed21), + .T(main_k7ddrphy_dq_t21), .IO(ddram_dq[21]), - .O(soc_k7ddrphy_dq_i_nodelay21) + .O(main_k7ddrphy_dq_i_nodelay21) ); OSERDESE2 #( @@ -20072,20 +24583,20 @@ OSERDESE2 #( ) OSERDESE2_56 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[22]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[54]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[22]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[54]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[22]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[54]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[22]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[54]), + .D1(main_k7ddrphy_bitslip220[0]), + .D2(main_k7ddrphy_bitslip220[1]), + .D3(main_k7ddrphy_bitslip220[2]), + .D4(main_k7ddrphy_bitslip220[3]), + .D5(main_k7ddrphy_bitslip220[4]), + .D6(main_k7ddrphy_bitslip220[5]), + .D7(main_k7ddrphy_bitslip220[6]), + .D8(main_k7ddrphy_bitslip220[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay22), - .TQ(soc_k7ddrphy_dq_t22) + .OQ(main_k7ddrphy_dq_o_nodelay22), + .TQ(main_k7ddrphy_dq_t22) ); ISERDESE2 #( @@ -20101,16 +24612,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed22), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data22[7]), - .Q2(soc_k7ddrphy_dq_i_data22[6]), - .Q3(soc_k7ddrphy_dq_i_data22[5]), - .Q4(soc_k7ddrphy_dq_i_data22[4]), - .Q5(soc_k7ddrphy_dq_i_data22[3]), - .Q6(soc_k7ddrphy_dq_i_data22[2]), - .Q7(soc_k7ddrphy_dq_i_data22[1]), - .Q8(soc_k7ddrphy_dq_i_data22[0]) + .DDLY(main_k7ddrphy_dq_i_delayed22), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip221[7]), + .Q2(main_k7ddrphy_bitslip221[6]), + .Q3(main_k7ddrphy_bitslip221[5]), + .Q4(main_k7ddrphy_bitslip221[4]), + .Q5(main_k7ddrphy_bitslip221[3]), + .Q6(main_k7ddrphy_bitslip221[2]), + .Q7(main_k7ddrphy_bitslip221[1]), + .Q8(main_k7ddrphy_bitslip221[0]) ); ODELAYE2 #( @@ -20124,12 +24635,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_56 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed22), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay22) + .DATAOUT(main_k7ddrphy_dq_o_delayed22), + .ODATAIN(main_k7ddrphy_dq_o_nodelay22) ); IDELAYE2 #( @@ -20141,21 +24652,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_26 ( +) IDELAYE2_22 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay22), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay22), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed22) + .DATAOUT(main_k7ddrphy_dq_i_delayed22) ); IOBUF IOBUF_22( - .I(soc_k7ddrphy_dq_o_delayed22), - .T(soc_k7ddrphy_dq_t22), + .I(main_k7ddrphy_dq_o_delayed22), + .T(main_k7ddrphy_dq_t22), .IO(ddram_dq[22]), - .O(soc_k7ddrphy_dq_i_nodelay22) + .O(main_k7ddrphy_dq_i_nodelay22) ); OSERDESE2 #( @@ -20167,20 +24678,20 @@ OSERDESE2 #( ) OSERDESE2_57 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[23]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[55]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[23]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[55]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[23]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[55]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[23]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[55]), + .D1(main_k7ddrphy_bitslip230[0]), + .D2(main_k7ddrphy_bitslip230[1]), + .D3(main_k7ddrphy_bitslip230[2]), + .D4(main_k7ddrphy_bitslip230[3]), + .D5(main_k7ddrphy_bitslip230[4]), + .D6(main_k7ddrphy_bitslip230[5]), + .D7(main_k7ddrphy_bitslip230[6]), + .D8(main_k7ddrphy_bitslip230[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay23), - .TQ(soc_k7ddrphy_dq_t23) + .OQ(main_k7ddrphy_dq_o_nodelay23), + .TQ(main_k7ddrphy_dq_t23) ); ISERDESE2 #( @@ -20196,16 +24707,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed23), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data23[7]), - .Q2(soc_k7ddrphy_dq_i_data23[6]), - .Q3(soc_k7ddrphy_dq_i_data23[5]), - .Q4(soc_k7ddrphy_dq_i_data23[4]), - .Q5(soc_k7ddrphy_dq_i_data23[3]), - .Q6(soc_k7ddrphy_dq_i_data23[2]), - .Q7(soc_k7ddrphy_dq_i_data23[1]), - .Q8(soc_k7ddrphy_dq_i_data23[0]) + .DDLY(main_k7ddrphy_dq_i_delayed23), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip231[7]), + .Q2(main_k7ddrphy_bitslip231[6]), + .Q3(main_k7ddrphy_bitslip231[5]), + .Q4(main_k7ddrphy_bitslip231[4]), + .Q5(main_k7ddrphy_bitslip231[3]), + .Q6(main_k7ddrphy_bitslip231[2]), + .Q7(main_k7ddrphy_bitslip231[1]), + .Q8(main_k7ddrphy_bitslip231[0]) ); ODELAYE2 #( @@ -20219,12 +24730,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_57 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed23), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay23) + .DATAOUT(main_k7ddrphy_dq_o_delayed23), + .ODATAIN(main_k7ddrphy_dq_o_nodelay23) ); IDELAYE2 #( @@ -20236,21 +24747,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_27 ( +) IDELAYE2_23 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay23), + .CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay23), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed23) + .DATAOUT(main_k7ddrphy_dq_i_delayed23) ); IOBUF IOBUF_23( - .I(soc_k7ddrphy_dq_o_delayed23), - .T(soc_k7ddrphy_dq_t23), + .I(main_k7ddrphy_dq_o_delayed23), + .T(main_k7ddrphy_dq_t23), .IO(ddram_dq[23]), - .O(soc_k7ddrphy_dq_i_nodelay23) + .O(main_k7ddrphy_dq_i_nodelay23) ); OSERDESE2 #( @@ -20262,20 +24773,20 @@ OSERDESE2 #( ) OSERDESE2_58 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[24]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[56]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[24]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[56]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[24]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[56]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[24]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[56]), + .D1(main_k7ddrphy_bitslip240[0]), + .D2(main_k7ddrphy_bitslip240[1]), + .D3(main_k7ddrphy_bitslip240[2]), + .D4(main_k7ddrphy_bitslip240[3]), + .D5(main_k7ddrphy_bitslip240[4]), + .D6(main_k7ddrphy_bitslip240[5]), + .D7(main_k7ddrphy_bitslip240[6]), + .D8(main_k7ddrphy_bitslip240[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay24), - .TQ(soc_k7ddrphy_dq_t24) + .OQ(main_k7ddrphy_dq_o_nodelay24), + .TQ(main_k7ddrphy_dq_t24) ); ISERDESE2 #( @@ -20291,16 +24802,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed24), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data24[7]), - .Q2(soc_k7ddrphy_dq_i_data24[6]), - .Q3(soc_k7ddrphy_dq_i_data24[5]), - .Q4(soc_k7ddrphy_dq_i_data24[4]), - .Q5(soc_k7ddrphy_dq_i_data24[3]), - .Q6(soc_k7ddrphy_dq_i_data24[2]), - .Q7(soc_k7ddrphy_dq_i_data24[1]), - .Q8(soc_k7ddrphy_dq_i_data24[0]) + .DDLY(main_k7ddrphy_dq_i_delayed24), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip241[7]), + .Q2(main_k7ddrphy_bitslip241[6]), + .Q3(main_k7ddrphy_bitslip241[5]), + .Q4(main_k7ddrphy_bitslip241[4]), + .Q5(main_k7ddrphy_bitslip241[3]), + .Q6(main_k7ddrphy_bitslip241[2]), + .Q7(main_k7ddrphy_bitslip241[1]), + .Q8(main_k7ddrphy_bitslip241[0]) ); ODELAYE2 #( @@ -20314,12 +24825,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_58 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed24), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay24) + .DATAOUT(main_k7ddrphy_dq_o_delayed24), + .ODATAIN(main_k7ddrphy_dq_o_nodelay24) ); IDELAYE2 #( @@ -20331,21 +24842,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_28 ( +) IDELAYE2_24 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay24), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay24), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed24) + .DATAOUT(main_k7ddrphy_dq_i_delayed24) ); IOBUF IOBUF_24( - .I(soc_k7ddrphy_dq_o_delayed24), - .T(soc_k7ddrphy_dq_t24), + .I(main_k7ddrphy_dq_o_delayed24), + .T(main_k7ddrphy_dq_t24), .IO(ddram_dq[24]), - .O(soc_k7ddrphy_dq_i_nodelay24) + .O(main_k7ddrphy_dq_i_nodelay24) ); OSERDESE2 #( @@ -20357,20 +24868,20 @@ OSERDESE2 #( ) OSERDESE2_59 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[25]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[57]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[25]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[57]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[25]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[57]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[25]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[57]), + .D1(main_k7ddrphy_bitslip250[0]), + .D2(main_k7ddrphy_bitslip250[1]), + .D3(main_k7ddrphy_bitslip250[2]), + .D4(main_k7ddrphy_bitslip250[3]), + .D5(main_k7ddrphy_bitslip250[4]), + .D6(main_k7ddrphy_bitslip250[5]), + .D7(main_k7ddrphy_bitslip250[6]), + .D8(main_k7ddrphy_bitslip250[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay25), - .TQ(soc_k7ddrphy_dq_t25) + .OQ(main_k7ddrphy_dq_o_nodelay25), + .TQ(main_k7ddrphy_dq_t25) ); ISERDESE2 #( @@ -20386,16 +24897,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed25), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data25[7]), - .Q2(soc_k7ddrphy_dq_i_data25[6]), - .Q3(soc_k7ddrphy_dq_i_data25[5]), - .Q4(soc_k7ddrphy_dq_i_data25[4]), - .Q5(soc_k7ddrphy_dq_i_data25[3]), - .Q6(soc_k7ddrphy_dq_i_data25[2]), - .Q7(soc_k7ddrphy_dq_i_data25[1]), - .Q8(soc_k7ddrphy_dq_i_data25[0]) + .DDLY(main_k7ddrphy_dq_i_delayed25), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip251[7]), + .Q2(main_k7ddrphy_bitslip251[6]), + .Q3(main_k7ddrphy_bitslip251[5]), + .Q4(main_k7ddrphy_bitslip251[4]), + .Q5(main_k7ddrphy_bitslip251[3]), + .Q6(main_k7ddrphy_bitslip251[2]), + .Q7(main_k7ddrphy_bitslip251[1]), + .Q8(main_k7ddrphy_bitslip251[0]) ); ODELAYE2 #( @@ -20409,12 +24920,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_59 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed25), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay25) + .DATAOUT(main_k7ddrphy_dq_o_delayed25), + .ODATAIN(main_k7ddrphy_dq_o_nodelay25) ); IDELAYE2 #( @@ -20426,21 +24937,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_29 ( +) IDELAYE2_25 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay25), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay25), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed25) + .DATAOUT(main_k7ddrphy_dq_i_delayed25) ); IOBUF IOBUF_25( - .I(soc_k7ddrphy_dq_o_delayed25), - .T(soc_k7ddrphy_dq_t25), + .I(main_k7ddrphy_dq_o_delayed25), + .T(main_k7ddrphy_dq_t25), .IO(ddram_dq[25]), - .O(soc_k7ddrphy_dq_i_nodelay25) + .O(main_k7ddrphy_dq_i_nodelay25) ); OSERDESE2 #( @@ -20452,20 +24963,20 @@ OSERDESE2 #( ) OSERDESE2_60 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[26]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[58]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[26]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[58]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[26]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[58]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[26]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[58]), + .D1(main_k7ddrphy_bitslip260[0]), + .D2(main_k7ddrphy_bitslip260[1]), + .D3(main_k7ddrphy_bitslip260[2]), + .D4(main_k7ddrphy_bitslip260[3]), + .D5(main_k7ddrphy_bitslip260[4]), + .D6(main_k7ddrphy_bitslip260[5]), + .D7(main_k7ddrphy_bitslip260[6]), + .D8(main_k7ddrphy_bitslip260[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay26), - .TQ(soc_k7ddrphy_dq_t26) + .OQ(main_k7ddrphy_dq_o_nodelay26), + .TQ(main_k7ddrphy_dq_t26) ); ISERDESE2 #( @@ -20481,16 +24992,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed26), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data26[7]), - .Q2(soc_k7ddrphy_dq_i_data26[6]), - .Q3(soc_k7ddrphy_dq_i_data26[5]), - .Q4(soc_k7ddrphy_dq_i_data26[4]), - .Q5(soc_k7ddrphy_dq_i_data26[3]), - .Q6(soc_k7ddrphy_dq_i_data26[2]), - .Q7(soc_k7ddrphy_dq_i_data26[1]), - .Q8(soc_k7ddrphy_dq_i_data26[0]) + .DDLY(main_k7ddrphy_dq_i_delayed26), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip261[7]), + .Q2(main_k7ddrphy_bitslip261[6]), + .Q3(main_k7ddrphy_bitslip261[5]), + .Q4(main_k7ddrphy_bitslip261[4]), + .Q5(main_k7ddrphy_bitslip261[3]), + .Q6(main_k7ddrphy_bitslip261[2]), + .Q7(main_k7ddrphy_bitslip261[1]), + .Q8(main_k7ddrphy_bitslip261[0]) ); ODELAYE2 #( @@ -20504,12 +25015,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_60 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed26), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay26) + .DATAOUT(main_k7ddrphy_dq_o_delayed26), + .ODATAIN(main_k7ddrphy_dq_o_nodelay26) ); IDELAYE2 #( @@ -20521,21 +25032,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_30 ( +) IDELAYE2_26 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay26), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay26), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed26) + .DATAOUT(main_k7ddrphy_dq_i_delayed26) ); IOBUF IOBUF_26( - .I(soc_k7ddrphy_dq_o_delayed26), - .T(soc_k7ddrphy_dq_t26), + .I(main_k7ddrphy_dq_o_delayed26), + .T(main_k7ddrphy_dq_t26), .IO(ddram_dq[26]), - .O(soc_k7ddrphy_dq_i_nodelay26) + .O(main_k7ddrphy_dq_i_nodelay26) ); OSERDESE2 #( @@ -20547,20 +25058,20 @@ OSERDESE2 #( ) OSERDESE2_61 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[27]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[59]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[27]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[59]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[27]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[59]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[27]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[59]), + .D1(main_k7ddrphy_bitslip270[0]), + .D2(main_k7ddrphy_bitslip270[1]), + .D3(main_k7ddrphy_bitslip270[2]), + .D4(main_k7ddrphy_bitslip270[3]), + .D5(main_k7ddrphy_bitslip270[4]), + .D6(main_k7ddrphy_bitslip270[5]), + .D7(main_k7ddrphy_bitslip270[6]), + .D8(main_k7ddrphy_bitslip270[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay27), - .TQ(soc_k7ddrphy_dq_t27) + .OQ(main_k7ddrphy_dq_o_nodelay27), + .TQ(main_k7ddrphy_dq_t27) ); ISERDESE2 #( @@ -20576,16 +25087,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed27), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data27[7]), - .Q2(soc_k7ddrphy_dq_i_data27[6]), - .Q3(soc_k7ddrphy_dq_i_data27[5]), - .Q4(soc_k7ddrphy_dq_i_data27[4]), - .Q5(soc_k7ddrphy_dq_i_data27[3]), - .Q6(soc_k7ddrphy_dq_i_data27[2]), - .Q7(soc_k7ddrphy_dq_i_data27[1]), - .Q8(soc_k7ddrphy_dq_i_data27[0]) + .DDLY(main_k7ddrphy_dq_i_delayed27), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip271[7]), + .Q2(main_k7ddrphy_bitslip271[6]), + .Q3(main_k7ddrphy_bitslip271[5]), + .Q4(main_k7ddrphy_bitslip271[4]), + .Q5(main_k7ddrphy_bitslip271[3]), + .Q6(main_k7ddrphy_bitslip271[2]), + .Q7(main_k7ddrphy_bitslip271[1]), + .Q8(main_k7ddrphy_bitslip271[0]) ); ODELAYE2 #( @@ -20599,12 +25110,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_61 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed27), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay27) + .DATAOUT(main_k7ddrphy_dq_o_delayed27), + .ODATAIN(main_k7ddrphy_dq_o_nodelay27) ); IDELAYE2 #( @@ -20616,21 +25127,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_31 ( +) IDELAYE2_27 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay27), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay27), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed27) + .DATAOUT(main_k7ddrphy_dq_i_delayed27) ); IOBUF IOBUF_27( - .I(soc_k7ddrphy_dq_o_delayed27), - .T(soc_k7ddrphy_dq_t27), + .I(main_k7ddrphy_dq_o_delayed27), + .T(main_k7ddrphy_dq_t27), .IO(ddram_dq[27]), - .O(soc_k7ddrphy_dq_i_nodelay27) + .O(main_k7ddrphy_dq_i_nodelay27) ); OSERDESE2 #( @@ -20642,20 +25153,20 @@ OSERDESE2 #( ) OSERDESE2_62 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[28]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[60]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[28]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[60]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[28]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[60]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[28]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[60]), + .D1(main_k7ddrphy_bitslip280[0]), + .D2(main_k7ddrphy_bitslip280[1]), + .D3(main_k7ddrphy_bitslip280[2]), + .D4(main_k7ddrphy_bitslip280[3]), + .D5(main_k7ddrphy_bitslip280[4]), + .D6(main_k7ddrphy_bitslip280[5]), + .D7(main_k7ddrphy_bitslip280[6]), + .D8(main_k7ddrphy_bitslip280[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay28), - .TQ(soc_k7ddrphy_dq_t28) + .OQ(main_k7ddrphy_dq_o_nodelay28), + .TQ(main_k7ddrphy_dq_t28) ); ISERDESE2 #( @@ -20671,16 +25182,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed28), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data28[7]), - .Q2(soc_k7ddrphy_dq_i_data28[6]), - .Q3(soc_k7ddrphy_dq_i_data28[5]), - .Q4(soc_k7ddrphy_dq_i_data28[4]), - .Q5(soc_k7ddrphy_dq_i_data28[3]), - .Q6(soc_k7ddrphy_dq_i_data28[2]), - .Q7(soc_k7ddrphy_dq_i_data28[1]), - .Q8(soc_k7ddrphy_dq_i_data28[0]) + .DDLY(main_k7ddrphy_dq_i_delayed28), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip281[7]), + .Q2(main_k7ddrphy_bitslip281[6]), + .Q3(main_k7ddrphy_bitslip281[5]), + .Q4(main_k7ddrphy_bitslip281[4]), + .Q5(main_k7ddrphy_bitslip281[3]), + .Q6(main_k7ddrphy_bitslip281[2]), + .Q7(main_k7ddrphy_bitslip281[1]), + .Q8(main_k7ddrphy_bitslip281[0]) ); ODELAYE2 #( @@ -20694,12 +25205,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_62 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed28), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay28) + .DATAOUT(main_k7ddrphy_dq_o_delayed28), + .ODATAIN(main_k7ddrphy_dq_o_nodelay28) ); IDELAYE2 #( @@ -20711,21 +25222,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_32 ( +) IDELAYE2_28 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay28), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay28), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed28) + .DATAOUT(main_k7ddrphy_dq_i_delayed28) ); IOBUF IOBUF_28( - .I(soc_k7ddrphy_dq_o_delayed28), - .T(soc_k7ddrphy_dq_t28), + .I(main_k7ddrphy_dq_o_delayed28), + .T(main_k7ddrphy_dq_t28), .IO(ddram_dq[28]), - .O(soc_k7ddrphy_dq_i_nodelay28) + .O(main_k7ddrphy_dq_i_nodelay28) ); OSERDESE2 #( @@ -20737,20 +25248,20 @@ OSERDESE2 #( ) OSERDESE2_63 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[29]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[61]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[29]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[61]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[29]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[61]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[29]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[61]), + .D1(main_k7ddrphy_bitslip290[0]), + .D2(main_k7ddrphy_bitslip290[1]), + .D3(main_k7ddrphy_bitslip290[2]), + .D4(main_k7ddrphy_bitslip290[3]), + .D5(main_k7ddrphy_bitslip290[4]), + .D6(main_k7ddrphy_bitslip290[5]), + .D7(main_k7ddrphy_bitslip290[6]), + .D8(main_k7ddrphy_bitslip290[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay29), - .TQ(soc_k7ddrphy_dq_t29) + .OQ(main_k7ddrphy_dq_o_nodelay29), + .TQ(main_k7ddrphy_dq_t29) ); ISERDESE2 #( @@ -20766,16 +25277,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed29), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data29[7]), - .Q2(soc_k7ddrphy_dq_i_data29[6]), - .Q3(soc_k7ddrphy_dq_i_data29[5]), - .Q4(soc_k7ddrphy_dq_i_data29[4]), - .Q5(soc_k7ddrphy_dq_i_data29[3]), - .Q6(soc_k7ddrphy_dq_i_data29[2]), - .Q7(soc_k7ddrphy_dq_i_data29[1]), - .Q8(soc_k7ddrphy_dq_i_data29[0]) + .DDLY(main_k7ddrphy_dq_i_delayed29), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip291[7]), + .Q2(main_k7ddrphy_bitslip291[6]), + .Q3(main_k7ddrphy_bitslip291[5]), + .Q4(main_k7ddrphy_bitslip291[4]), + .Q5(main_k7ddrphy_bitslip291[3]), + .Q6(main_k7ddrphy_bitslip291[2]), + .Q7(main_k7ddrphy_bitslip291[1]), + .Q8(main_k7ddrphy_bitslip291[0]) ); ODELAYE2 #( @@ -20789,12 +25300,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_63 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed29), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay29) + .DATAOUT(main_k7ddrphy_dq_o_delayed29), + .ODATAIN(main_k7ddrphy_dq_o_nodelay29) ); IDELAYE2 #( @@ -20806,21 +25317,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_33 ( +) IDELAYE2_29 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay29), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay29), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed29) + .DATAOUT(main_k7ddrphy_dq_i_delayed29) ); IOBUF IOBUF_29( - .I(soc_k7ddrphy_dq_o_delayed29), - .T(soc_k7ddrphy_dq_t29), + .I(main_k7ddrphy_dq_o_delayed29), + .T(main_k7ddrphy_dq_t29), .IO(ddram_dq[29]), - .O(soc_k7ddrphy_dq_i_nodelay29) + .O(main_k7ddrphy_dq_i_nodelay29) ); OSERDESE2 #( @@ -20832,20 +25343,20 @@ OSERDESE2 #( ) OSERDESE2_64 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[30]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[62]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[30]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[62]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[30]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[62]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[30]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[62]), + .D1(main_k7ddrphy_bitslip300[0]), + .D2(main_k7ddrphy_bitslip300[1]), + .D3(main_k7ddrphy_bitslip300[2]), + .D4(main_k7ddrphy_bitslip300[3]), + .D5(main_k7ddrphy_bitslip300[4]), + .D6(main_k7ddrphy_bitslip300[5]), + .D7(main_k7ddrphy_bitslip300[6]), + .D8(main_k7ddrphy_bitslip300[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay30), - .TQ(soc_k7ddrphy_dq_t30) + .OQ(main_k7ddrphy_dq_o_nodelay30), + .TQ(main_k7ddrphy_dq_t30) ); ISERDESE2 #( @@ -20861,16 +25372,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed30), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data30[7]), - .Q2(soc_k7ddrphy_dq_i_data30[6]), - .Q3(soc_k7ddrphy_dq_i_data30[5]), - .Q4(soc_k7ddrphy_dq_i_data30[4]), - .Q5(soc_k7ddrphy_dq_i_data30[3]), - .Q6(soc_k7ddrphy_dq_i_data30[2]), - .Q7(soc_k7ddrphy_dq_i_data30[1]), - .Q8(soc_k7ddrphy_dq_i_data30[0]) + .DDLY(main_k7ddrphy_dq_i_delayed30), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip301[7]), + .Q2(main_k7ddrphy_bitslip301[6]), + .Q3(main_k7ddrphy_bitslip301[5]), + .Q4(main_k7ddrphy_bitslip301[4]), + .Q5(main_k7ddrphy_bitslip301[3]), + .Q6(main_k7ddrphy_bitslip301[2]), + .Q7(main_k7ddrphy_bitslip301[1]), + .Q8(main_k7ddrphy_bitslip301[0]) ); ODELAYE2 #( @@ -20884,12 +25395,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_64 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed30), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay30) + .DATAOUT(main_k7ddrphy_dq_o_delayed30), + .ODATAIN(main_k7ddrphy_dq_o_nodelay30) ); IDELAYE2 #( @@ -20901,21 +25412,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_34 ( +) IDELAYE2_30 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay30), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay30), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed30) + .DATAOUT(main_k7ddrphy_dq_i_delayed30) ); IOBUF IOBUF_30( - .I(soc_k7ddrphy_dq_o_delayed30), - .T(soc_k7ddrphy_dq_t30), + .I(main_k7ddrphy_dq_o_delayed30), + .T(main_k7ddrphy_dq_t30), .IO(ddram_dq[30]), - .O(soc_k7ddrphy_dq_i_nodelay30) + .O(main_k7ddrphy_dq_i_nodelay30) ); OSERDESE2 #( @@ -20927,20 +25438,20 @@ OSERDESE2 #( ) OSERDESE2_65 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_k7ddrphy_dfi_p0_wrdata[31]), - .D2(soc_k7ddrphy_dfi_p0_wrdata[63]), - .D3(soc_k7ddrphy_dfi_p1_wrdata[31]), - .D4(soc_k7ddrphy_dfi_p1_wrdata[63]), - .D5(soc_k7ddrphy_dfi_p2_wrdata[31]), - .D6(soc_k7ddrphy_dfi_p2_wrdata[63]), - .D7(soc_k7ddrphy_dfi_p3_wrdata[31]), - .D8(soc_k7ddrphy_dfi_p3_wrdata[63]), + .D1(main_k7ddrphy_bitslip310[0]), + .D2(main_k7ddrphy_bitslip310[1]), + .D3(main_k7ddrphy_bitslip310[2]), + .D4(main_k7ddrphy_bitslip310[3]), + .D5(main_k7ddrphy_bitslip310[4]), + .D6(main_k7ddrphy_bitslip310[5]), + .D7(main_k7ddrphy_bitslip310[6]), + .D8(main_k7ddrphy_bitslip310[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_k7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_k7ddrphy_dq_o_nodelay31), - .TQ(soc_k7ddrphy_dq_t31) + .OQ(main_k7ddrphy_dq_o_nodelay31), + .TQ(main_k7ddrphy_dq_t31) ); ISERDESE2 #( @@ -20956,16 +25467,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_k7ddrphy_dq_i_delayed31), - .RST(sys_rst), - .Q1(soc_k7ddrphy_dq_i_data31[7]), - .Q2(soc_k7ddrphy_dq_i_data31[6]), - .Q3(soc_k7ddrphy_dq_i_data31[5]), - .Q4(soc_k7ddrphy_dq_i_data31[4]), - .Q5(soc_k7ddrphy_dq_i_data31[3]), - .Q6(soc_k7ddrphy_dq_i_data31[2]), - .Q7(soc_k7ddrphy_dq_i_data31[1]), - .Q8(soc_k7ddrphy_dq_i_data31[0]) + .DDLY(main_k7ddrphy_dq_i_delayed31), + .RST((sys_rst | main_k7ddrphy_rst_storage)), + .Q1(main_k7ddrphy_bitslip311[7]), + .Q2(main_k7ddrphy_bitslip311[6]), + .Q3(main_k7ddrphy_bitslip311[5]), + .Q4(main_k7ddrphy_bitslip311[4]), + .Q5(main_k7ddrphy_bitslip311[3]), + .Q6(main_k7ddrphy_bitslip311[2]), + .Q7(main_k7ddrphy_bitslip311[1]), + .Q8(main_k7ddrphy_bitslip311[0]) ); ODELAYE2 #( @@ -20979,12 +25490,12 @@ ODELAYE2 #( .SIGNAL_PATTERN("DATA") ) ODELAYE2_65 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_o_delayed31), - .ODATAIN(soc_k7ddrphy_dq_o_nodelay31) + .DATAOUT(main_k7ddrphy_dq_o_delayed31), + .ODATAIN(main_k7ddrphy_dq_o_nodelay31) ); IDELAYE2 #( @@ -20996,134 +25507,182 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_35 ( +) IDELAYE2_31 ( .C(sys_clk), - .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_k7ddrphy_dq_i_nodelay31), + .CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_k7ddrphy_dq_i_nodelay31), .INC(1'd1), - .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_k7ddrphy_dq_i_delayed31) + .DATAOUT(main_k7ddrphy_dq_i_delayed31) ); IOBUF IOBUF_31( - .I(soc_k7ddrphy_dq_o_delayed31), - .T(soc_k7ddrphy_dq_t31), + .I(main_k7ddrphy_dq_o_delayed31), + .T(main_k7ddrphy_dq_t31), .IO(ddram_dq[31]), - .O(soc_k7ddrphy_dq_i_nodelay31) + .O(main_k7ddrphy_dq_i_nodelay31) ); reg [24:0] storage[0:15]; reg [24:0] memdat; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_1[0:15]; reg [24:0] memdat_1; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_2[0:15]; reg [24:0] memdat_2; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_3[0:15]; reg [24:0] memdat_3; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_4[0:15]; reg [24:0] memdat_4; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_5[0:15]; reg [24:0] memdat_5; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_6[0:15]; reg [24:0] memdat_6; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_7[0:15]; reg [24:0] memdat_7; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +FD FD( + .C(main_clkin), + .D(main_reset), + .Q(builder_reset0) +); + +FD FD_1( + .C(main_clkin), + .D(builder_reset0), + .Q(builder_reset1) +); + +FD FD_2( + .C(main_clkin), + .D(builder_reset1), + .Q(builder_reset2) +); + +FD FD_3( + .C(main_clkin), + .D(builder_reset2), + .Q(builder_reset3) +); + +FD FD_4( + .C(main_clkin), + .D(builder_reset3), + .Q(builder_reset4) +); + +FD FD_5( + .C(main_clkin), + .D(builder_reset4), + .Q(builder_reset5) +); + +FD FD_6( + .C(main_clkin), + .D(builder_reset5), + .Q(builder_reset6) +); + +FD FD_7( + .C(main_clkin), + .D(builder_reset6), + .Q(builder_reset7) +); PLLE2_ADV #( .CLKFBOUT_MULT(4'd8), @@ -21140,15 +25699,16 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb), - .CLKIN1(soc_clkin), - .RST(soc_reset), - .CLKFBOUT(vns_pll_fb), - .CLKOUT0(soc_clkout0), - .CLKOUT1(soc_clkout1), - .CLKOUT2(soc_clkout2), - .CLKOUT3(soc_clkout3), - .LOCKED(soc_locked) + .CLKFBIN(builder_pll_fb), + .CLKIN1(main_clkin), + .PWRDWN(main_power_down), + .RST(builder_reset7), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout0), + .CLKOUT1(main_clkout1), + .CLKOUT2(main_clkout2), + .CLKOUT3(main_clkout3), + .LOCKED(main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -21157,8 +25717,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -21166,8 +25726,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(iodelay_rst) ); @@ -21177,8 +25737,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -21186,8 +25746,8 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), .Q(sys_rst) ); @@ -21197,8 +25757,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -21206,9 +25766,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -21217,8 +25777,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -21226,9 +25786,9 @@ PLLE2_ADV #( ) FDPE_7 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) + .D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 0f92f5b..af8cf09 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d8658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -518,79 +518,78 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842a9c4 -fbe1fff8fbc1fff0 -f821ff51f8010010 -f88100d83be10020 +7c0802a63842aec4 +f8010010fbe1fff8 +f88100d8f821ff51 38800080f8a100e0 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-39290001e9210060 -4bfffe6cf9210060 -38a0000a7d21e214 -f9410088f9010090 -7f43d37838800000 -4bfff73d9ae90020 -f861008060000000 -4bfff8617f63db78 -e921008060000000 -409d00407fa91840 -e94100887c634850 -2fa30000e9010090 -7d4af85039230001 -39200001409e0008 -e8c100602c290001 -418200103929ffff -7faa38407ce83050 -e8810060419d0020 -7fa3eb787f65db78 +e88100604bfffaad +38c000107ec7b378 +7c9e20507f85e378 +7d21ea144bfffed4 +38e0000a39000020 +9ae9002038c00001 +3920000038a10020 +386100607c8af850 +e92100604bfff96d +e92100609b890000 +f921006039290001 +7d21ea144bfffea0 +f901007838a0000a +38800000f9410070 +9ae9002038610020 +600000004bfff7e9 +7f83e378f8610068 +600000004bfff7b1 +7c291840e9210068 +7c6348514081004c +e9010078e9410070 +408200087d4af850 +e921006038600001 +7c2a38407ce84850 +38e0002040810024 +3863ffff2c230001 +e921006098e90000 +f921006039290001 +e88100604082ffd4 +386100607f85e378 7c84f8507c9e2050 -4bfffdd44bfff9cd -98e6000038e00020 -38e70001e8e10060 -4bffffb4f8e10060 -3b2000082b87006c -7cd83378409efdb0 -2b8700684bfffda8 -409efd9c3b200002 -3b2000017cd83378 -3b2000084bfffd90 -3a6000204bfffd88 -4bfffc603b010041 -7d455378993e0000 -39290001e9210060 -4bfffb24f9210060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -000000004e800020 +4bfffdfc4bfff9b5 +418200482805006c +4bfffdec3b600008 +3b60000228050068 +7cda33784082fde0 +4bfffdd43b600001 +554a063e3949ffd0 +4181fdc4280a0009 +7fa1ea14395d0001 +795d0020993d0020 +7cda33784bfffdb0 +993e00004bffffb8 +e92100607d455378 +f921006039290001 +000000004bfffaf0 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1715,6 +1883,7 @@ e8010010ebc1fff0 0000000000000020 54454e5245485445 0000000000000020 +000000000000000a 2020202020202020 203a4d4152422020 000a424b20646c25 @@ -1745,9 +1914,9 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -3830643432643338 +3133393063613937 0000000000000000 -0064623161656634 +0036643330323533 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1789,63 +1958,82 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d +62202c64256d2020 +007c203a64323025 +0000000000006425 +000000000000207c 203a7379616c6564 -0000000000000000 000000000000002d +203a7379616c6564 30252d2b64323025 0000000000006432 -00000000c8000818 -00000000c8000830 -00000000c8000848 -00000000c8000860 -6f6e204d41524453 -207265646e752077 -6572617764726168 -6c6f72746e6f6320 -000000000000000a -696c616974696e49 -41524420676e697a -383025783040204d -0000000a2e2e2e78 +6e69686374697753 +204d415244532067 +7774666f73206f74 +746e6f6320657261 +0000000a2e6c6f72 +6e69686374697753 +204d415244532067 +7764726168206f74 +746e6f6320657261 +0000000a2e6c6f72 +203a747365622020 +302562202c64256d +6000000000206432 +616c206574697257 +61632079636e6574 +6f6974617262696c +00000000000a3a6e +0000202d3a64256d +002064253a64256d 76656c2064616552 000a3a676e696c65 -302562202c64256d -0000007c203a6432 -0000000000006425 -000000000000207c -256d203a74736562 -6432302562202c64 -0000000000000020 -6f6e204d41524453 -207265646e752077 -6572617774666f73 -6c6f72746e6f6320 -000000000000000a +696c616974696e49 +52445320676e697a +3025783040204d41 +000a2e2e2e786c38 +0000000042756c25 +4b756c252e756c25 +0000000000004269 +4d756c252e756c25 +0000000000004269 +47756c252e756c25 +0000000000004269 +2d78257830207325 +0000002078257830 +000000000d202020 +3a65746972572020 +0000000000000000 +3a64616552202020 +0000000000000000 64656570736d654d -7025783020746120 -000000000a2e2e2e -203a736574697257 -7370624d20646c25 -000000000000000a -20203a7364616552 -7370624d20646c25 -000000000000000a +2820702520746120 +0000000000000000 +0000000a2e2e2e29 +2065746972572020 +00203a6465657073 +000000000000732f +2064616552202020 +00203a6465657073 20747365746d654d -2e70257830207461 -00000000000a2e2e -726520737562202d +0028207025207461 +7265207375622020 2520203a73726f72 00000a646c252f64 -652072646461202d +6520726464612020 25203a73726f7272 00000a646c252f64 -652061746164202d +6520617461642020 25203a73726f7272 00000a646c252f64 20747365746d654d 00000000000a4f4b 20747365746d654d -00000000000a4b4f +60000000000a4b4f +3736353433323130 +6665646362613938 +0000000000000000 +0000000000007830 0000000000000000 00000000000000ff 000000000000ffff @@ -1855,4 +2043,3 @@ e8010010ebc1fff0 0000ffffffffffff 00ffffffffffffff ffffffffffffffff -0000000000007830 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index a9b11c2..ae410c7 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:22 +// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:21 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -48,1806 +48,2039 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg [13:0] soc_litedramcore_adr = 14'd0; -reg soc_litedramcore_we = 1'd0; -wire [31:0] soc_litedramcore_dat_w; -wire [31:0] soc_litedramcore_dat_r; -wire [29:0] soc_litedramcore_wishbone_adr; -wire [31:0] soc_litedramcore_wishbone_dat_w; -wire [31:0] soc_litedramcore_wishbone_dat_r; -wire [3:0] soc_litedramcore_wishbone_sel; -wire soc_litedramcore_wishbone_cyc; -wire soc_litedramcore_wishbone_stb; -reg soc_litedramcore_wishbone_ack = 1'd0; -wire soc_litedramcore_wishbone_we; -wire [2:0] soc_litedramcore_wishbone_cti; -wire [1:0] soc_litedramcore_wishbone_bte; -reg soc_litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_reset; -wire soc_locked; -wire soc_clkin; -wire soc_clkout0; -wire soc_clkout_buf0; -wire soc_clkout1; -wire soc_clkout_buf1; -wire soc_clkout2; -wire soc_clkout_buf2; -wire soc_clkout3; -wire soc_clkout_buf3; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_a7ddrphy_wlevel_en_storage = 1'd0; -reg soc_a7ddrphy_wlevel_en_re = 1'd0; -wire soc_a7ddrphy_wlevel_strobe_re; -wire soc_a7ddrphy_wlevel_strobe_r; -wire soc_a7ddrphy_wlevel_strobe_we; -reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_a7ddrphy_cdly_rst_re; -wire soc_a7ddrphy_cdly_rst_r; -wire soc_a7ddrphy_cdly_rst_we; -reg soc_a7ddrphy_cdly_rst_w = 1'd0; -wire soc_a7ddrphy_cdly_inc_re; -wire soc_a7ddrphy_cdly_inc_r; -wire soc_a7ddrphy_cdly_inc_we; -reg soc_a7ddrphy_cdly_inc_w = 1'd0; -reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; -reg soc_a7ddrphy_dly_sel_re = 1'd0; -wire soc_a7ddrphy_rdly_dq_rst_re; -wire soc_a7ddrphy_rdly_dq_rst_r; -wire soc_a7ddrphy_rdly_dq_rst_we; -reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_inc_re; -wire soc_a7ddrphy_rdly_dq_inc_r; -wire soc_a7ddrphy_rdly_dq_inc_we; -reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_re; -wire soc_a7ddrphy_rdly_dq_bitslip_r; -wire soc_a7ddrphy_rdly_dq_bitslip_we; -reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p0_address; -wire [2:0] soc_a7ddrphy_dfi_p0_bank; -wire soc_a7ddrphy_dfi_p0_cas_n; -wire soc_a7ddrphy_dfi_p0_cs_n; -wire soc_a7ddrphy_dfi_p0_ras_n; -wire soc_a7ddrphy_dfi_p0_we_n; -wire soc_a7ddrphy_dfi_p0_cke; -wire soc_a7ddrphy_dfi_p0_odt; -wire soc_a7ddrphy_dfi_p0_reset_n; -wire soc_a7ddrphy_dfi_p0_act_n; -wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; -wire soc_a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; -wire soc_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p1_address; -wire [2:0] soc_a7ddrphy_dfi_p1_bank; -wire soc_a7ddrphy_dfi_p1_cas_n; -wire soc_a7ddrphy_dfi_p1_cs_n; -wire soc_a7ddrphy_dfi_p1_ras_n; -wire soc_a7ddrphy_dfi_p1_we_n; -wire soc_a7ddrphy_dfi_p1_cke; -wire soc_a7ddrphy_dfi_p1_odt; -wire soc_a7ddrphy_dfi_p1_reset_n; -wire soc_a7ddrphy_dfi_p1_act_n; -wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; -wire soc_a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; -wire soc_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p2_address; -wire [2:0] soc_a7ddrphy_dfi_p2_bank; -wire soc_a7ddrphy_dfi_p2_cas_n; -wire soc_a7ddrphy_dfi_p2_cs_n; -wire soc_a7ddrphy_dfi_p2_ras_n; -wire soc_a7ddrphy_dfi_p2_we_n; -wire soc_a7ddrphy_dfi_p2_cke; -wire soc_a7ddrphy_dfi_p2_odt; -wire soc_a7ddrphy_dfi_p2_reset_n; -wire soc_a7ddrphy_dfi_p2_act_n; -wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; -wire soc_a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; -wire soc_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p3_address; -wire [2:0] soc_a7ddrphy_dfi_p3_bank; -wire soc_a7ddrphy_dfi_p3_cas_n; -wire soc_a7ddrphy_dfi_p3_cs_n; -wire soc_a7ddrphy_dfi_p3_ras_n; -wire soc_a7ddrphy_dfi_p3_we_n; -wire soc_a7ddrphy_dfi_p3_cke; -wire soc_a7ddrphy_dfi_p3_odt; -wire soc_a7ddrphy_dfi_p3_reset_n; -wire soc_a7ddrphy_dfi_p3_act_n; -wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; -wire soc_a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; -wire soc_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_a7ddrphy_sd_clk_se_nodelay; -reg soc_a7ddrphy_dqs_oe = 1'd0; -reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_a7ddrphy_dqspattern0; -wire soc_a7ddrphy_dqspattern1; -reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; -wire [1:0] soc_a7ddrphy_dqs_i; -wire [1:0] soc_a7ddrphy_dqs_i_delayed; -wire soc_a7ddrphy_dqs_o_no_delay0; -wire soc_a7ddrphy_dqs_t0; -wire soc_a7ddrphy0; -wire soc_a7ddrphy_dqs_o_no_delay1; -wire soc_a7ddrphy_dqs_t1; -wire soc_a7ddrphy1; -wire soc_a7ddrphy_dq_oe; -reg soc_a7ddrphy_dq_oe_delayed = 1'd0; -wire soc_a7ddrphy_dq_o_nodelay0; -wire soc_a7ddrphy_dq_i_nodelay0; -wire soc_a7ddrphy_dq_i_delayed0; -wire soc_a7ddrphy_dq_t0; -wire [7:0] soc_a7ddrphy_dq_i_data0; -wire [7:0] soc_a7ddrphy_bitslip0_i; -reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay1; -wire soc_a7ddrphy_dq_i_nodelay1; -wire soc_a7ddrphy_dq_i_delayed1; -wire soc_a7ddrphy_dq_t1; -wire [7:0] soc_a7ddrphy_dq_i_data1; -wire [7:0] soc_a7ddrphy_bitslip1_i; -reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay2; -wire soc_a7ddrphy_dq_i_nodelay2; -wire soc_a7ddrphy_dq_i_delayed2; -wire soc_a7ddrphy_dq_t2; -wire [7:0] soc_a7ddrphy_dq_i_data2; -wire [7:0] soc_a7ddrphy_bitslip2_i; -reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay3; -wire soc_a7ddrphy_dq_i_nodelay3; -wire soc_a7ddrphy_dq_i_delayed3; -wire soc_a7ddrphy_dq_t3; -wire [7:0] soc_a7ddrphy_dq_i_data3; -wire [7:0] soc_a7ddrphy_bitslip3_i; -reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay4; -wire soc_a7ddrphy_dq_i_nodelay4; -wire soc_a7ddrphy_dq_i_delayed4; -wire soc_a7ddrphy_dq_t4; -wire [7:0] soc_a7ddrphy_dq_i_data4; -wire [7:0] soc_a7ddrphy_bitslip4_i; -reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay5; -wire soc_a7ddrphy_dq_i_nodelay5; -wire soc_a7ddrphy_dq_i_delayed5; -wire soc_a7ddrphy_dq_t5; -wire [7:0] soc_a7ddrphy_dq_i_data5; -wire [7:0] soc_a7ddrphy_bitslip5_i; -reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay6; -wire soc_a7ddrphy_dq_i_nodelay6; -wire soc_a7ddrphy_dq_i_delayed6; -wire soc_a7ddrphy_dq_t6; -wire [7:0] soc_a7ddrphy_dq_i_data6; -wire [7:0] soc_a7ddrphy_bitslip6_i; -reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay7; -wire soc_a7ddrphy_dq_i_nodelay7; -wire soc_a7ddrphy_dq_i_delayed7; -wire soc_a7ddrphy_dq_t7; -wire [7:0] soc_a7ddrphy_dq_i_data7; -wire [7:0] soc_a7ddrphy_bitslip7_i; -reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay8; -wire soc_a7ddrphy_dq_i_nodelay8; -wire soc_a7ddrphy_dq_i_delayed8; -wire soc_a7ddrphy_dq_t8; -wire [7:0] soc_a7ddrphy_dq_i_data8; -wire [7:0] soc_a7ddrphy_bitslip8_i; -reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay9; -wire soc_a7ddrphy_dq_i_nodelay9; -wire soc_a7ddrphy_dq_i_delayed9; -wire soc_a7ddrphy_dq_t9; -wire [7:0] soc_a7ddrphy_dq_i_data9; -wire [7:0] soc_a7ddrphy_bitslip9_i; -reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay10; -wire soc_a7ddrphy_dq_i_nodelay10; -wire soc_a7ddrphy_dq_i_delayed10; -wire soc_a7ddrphy_dq_t10; -wire [7:0] soc_a7ddrphy_dq_i_data10; -wire [7:0] soc_a7ddrphy_bitslip10_i; -reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay11; -wire soc_a7ddrphy_dq_i_nodelay11; -wire soc_a7ddrphy_dq_i_delayed11; -wire soc_a7ddrphy_dq_t11; -wire [7:0] soc_a7ddrphy_dq_i_data11; -wire [7:0] soc_a7ddrphy_bitslip11_i; -reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay12; -wire soc_a7ddrphy_dq_i_nodelay12; -wire soc_a7ddrphy_dq_i_delayed12; -wire soc_a7ddrphy_dq_t12; -wire [7:0] soc_a7ddrphy_dq_i_data12; -wire [7:0] soc_a7ddrphy_bitslip12_i; -reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay13; -wire soc_a7ddrphy_dq_i_nodelay13; -wire soc_a7ddrphy_dq_i_delayed13; -wire soc_a7ddrphy_dq_t13; -wire [7:0] soc_a7ddrphy_dq_i_data13; -wire [7:0] soc_a7ddrphy_bitslip13_i; -reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay14; -wire soc_a7ddrphy_dq_i_nodelay14; -wire soc_a7ddrphy_dq_i_delayed14; -wire soc_a7ddrphy_dq_t14; -wire [7:0] soc_a7ddrphy_dq_i_data14; -wire [7:0] soc_a7ddrphy_bitslip14_i; -reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0; -wire soc_a7ddrphy_dq_o_nodelay15; -wire soc_a7ddrphy_dq_i_nodelay15; -wire soc_a7ddrphy_dq_i_delayed15; -wire soc_a7ddrphy_dq_t15; -wire [7:0] soc_a7ddrphy_dq_i_data15; -wire [7:0] soc_a7ddrphy_bitslip15_i; -reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; -reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0; -reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0; -wire [7:0] soc_a7ddrphy_rddata_en; -reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_a7ddrphy_wrdata_en; -reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; -wire [14:0] soc_litedramcore_inti_p0_address; -wire [2:0] soc_litedramcore_inti_p0_bank; -reg soc_litedramcore_inti_p0_cas_n = 1'd1; -reg soc_litedramcore_inti_p0_cs_n = 1'd1; -reg soc_litedramcore_inti_p0_ras_n = 1'd1; -reg soc_litedramcore_inti_p0_we_n = 1'd1; -wire soc_litedramcore_inti_p0_cke; -wire soc_litedramcore_inti_p0_odt; -wire soc_litedramcore_inti_p0_reset_n; -reg soc_litedramcore_inti_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p0_wrdata; -wire soc_litedramcore_inti_p0_wrdata_en; -wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; -wire soc_litedramcore_inti_p0_rddata_en; -reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; -reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p1_address; -wire [2:0] soc_litedramcore_inti_p1_bank; -reg soc_litedramcore_inti_p1_cas_n = 1'd1; -reg soc_litedramcore_inti_p1_cs_n = 1'd1; -reg soc_litedramcore_inti_p1_ras_n = 1'd1; -reg soc_litedramcore_inti_p1_we_n = 1'd1; -wire soc_litedramcore_inti_p1_cke; -wire soc_litedramcore_inti_p1_odt; -wire soc_litedramcore_inti_p1_reset_n; -reg soc_litedramcore_inti_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p1_wrdata; -wire soc_litedramcore_inti_p1_wrdata_en; -wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; -wire soc_litedramcore_inti_p1_rddata_en; -reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; -reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p2_address; -wire [2:0] soc_litedramcore_inti_p2_bank; -reg soc_litedramcore_inti_p2_cas_n = 1'd1; -reg soc_litedramcore_inti_p2_cs_n = 1'd1; -reg soc_litedramcore_inti_p2_ras_n = 1'd1; -reg soc_litedramcore_inti_p2_we_n = 1'd1; -wire soc_litedramcore_inti_p2_cke; -wire soc_litedramcore_inti_p2_odt; -wire soc_litedramcore_inti_p2_reset_n; -reg soc_litedramcore_inti_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p2_wrdata; -wire soc_litedramcore_inti_p2_wrdata_en; -wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; -wire soc_litedramcore_inti_p2_rddata_en; -reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; -reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_inti_p3_address; -wire [2:0] soc_litedramcore_inti_p3_bank; -reg soc_litedramcore_inti_p3_cas_n = 1'd1; -reg soc_litedramcore_inti_p3_cs_n = 1'd1; -reg soc_litedramcore_inti_p3_ras_n = 1'd1; -reg soc_litedramcore_inti_p3_we_n = 1'd1; -wire soc_litedramcore_inti_p3_cke; -wire soc_litedramcore_inti_p3_odt; -wire soc_litedramcore_inti_p3_reset_n; -reg soc_litedramcore_inti_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_inti_p3_wrdata; -wire soc_litedramcore_inti_p3_wrdata_en; -wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; -wire soc_litedramcore_inti_p3_rddata_en; -reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; -reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [31:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [31:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [31:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [31:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] soc_litedramcore_master_p0_address = 15'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [14:0] soc_litedramcore_master_p1_address = 15'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [14:0] soc_litedramcore_master_p2_address = 15'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [14:0] soc_litedramcore_master_p3_address = 15'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_re; -wire soc_litedramcore_phaseinjector0_command_issue_r; -wire soc_litedramcore_phaseinjector0_command_issue_we; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector0_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0; -wire soc_litedramcore_phaseinjector0_we; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_re; -wire soc_litedramcore_phaseinjector1_command_issue_r; -wire soc_litedramcore_phaseinjector1_command_issue_we; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector1_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0; -wire soc_litedramcore_phaseinjector1_we; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_re; -wire soc_litedramcore_phaseinjector2_command_issue_r; -wire soc_litedramcore_phaseinjector2_command_issue_we; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector2_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0; -wire soc_litedramcore_phaseinjector2_we; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_re; -wire soc_litedramcore_phaseinjector3_command_issue_r; -wire soc_litedramcore_phaseinjector3_command_issue_we; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] soc_litedramcore_phaseinjector3_address_storage = 15'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0; -wire soc_litedramcore_phaseinjector3_we; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [21:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [21:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [21:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [21:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [21:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [21:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [21:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [21:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; -wire [127:0] soc_litedramcore_interface_rdata; -reg [14:0] soc_litedramcore_dfi_p0_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p1_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p2_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [14:0] soc_litedramcore_dfi_p3_address = 15'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [14:0] soc_litedramcore_cmd_payload_a = 15'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [21:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine0_row = 15'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [21:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine1_row = 15'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [21:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine2_row = 15'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [21:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine3_row = 15'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [21:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine4_row = 15'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [21:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine5_row = 15'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [21:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine6_row = 15'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [21:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_litedramcore_bankmachine7_row = 15'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; -wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] soc_litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; -wire soc_litedramcore_choose_cmd_cmd_payload_is_read; -wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] soc_litedramcore_choose_req_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_req_cmd_payload_is_cmd; -wire soc_litedramcore_choose_req_cmd_payload_is_read; -wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; -reg [14:0] soc_litedramcore_nop_a = 15'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; -wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; -wire [31:0] soc_wb_bus_dat_r; -wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; -wire soc_wb_bus_stb; -wire soc_wb_bus_ack; -wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [24:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [127:0] soc_user_port_wdata_payload_data; -wire [15:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [127:0] soc_user_port_rdata_payload_data; -reg vns_state = 1'd0; -reg vns_next_state = 1'd0; -wire vns_pll_fb; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire vns_roundrobin0_request; -wire vns_roundrobin0_grant; -wire vns_roundrobin0_ce; -wire vns_roundrobin1_request; -wire vns_roundrobin1_grant; -wire vns_roundrobin1_ce; -wire vns_roundrobin2_request; -wire vns_roundrobin2_grant; -wire vns_roundrobin2_ce; -wire vns_roundrobin3_request; -wire vns_roundrobin3_grant; -wire vns_roundrobin3_ce; -wire vns_roundrobin4_request; -wire vns_roundrobin4_grant; -wire vns_roundrobin4_ce; -wire vns_roundrobin5_request; -wire vns_roundrobin5_grant; -wire vns_roundrobin5_ce; -wire vns_roundrobin6_request; -wire vns_roundrobin6_grant; -wire vns_roundrobin6_ce; -wire vns_roundrobin7_request; -wire vns_roundrobin7_grant; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [31:0] vns_interface0_bank_bus_dat_w; -reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; -wire vns_csrbank0_init_done0_re; -wire vns_csrbank0_init_done0_r; -wire vns_csrbank0_init_done0_we; -wire vns_csrbank0_init_done0_w; -wire vns_csrbank0_init_error0_re; -wire vns_csrbank0_init_error0_r; -wire vns_csrbank0_init_error0_we; -wire vns_csrbank0_init_error0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [31:0] vns_interface1_bank_bus_dat_w; -reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; -wire vns_csrbank1_half_sys8x_taps0_re; -wire [4:0] vns_csrbank1_half_sys8x_taps0_r; -wire vns_csrbank1_half_sys8x_taps0_we; -wire [4:0] vns_csrbank1_half_sys8x_taps0_w; -wire vns_csrbank1_wlevel_en0_re; -wire vns_csrbank1_wlevel_en0_r; -wire vns_csrbank1_wlevel_en0_we; -wire vns_csrbank1_wlevel_en0_w; -wire vns_csrbank1_dly_sel0_re; -wire [1:0] vns_csrbank1_dly_sel0_r; -wire vns_csrbank1_dly_sel0_we; -wire [1:0] vns_csrbank1_dly_sel0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [31:0] vns_interface2_bank_bus_dat_w; -reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; -wire vns_csrbank2_dfii_control0_re; -wire [3:0] vns_csrbank2_dfii_control0_r; -wire vns_csrbank2_dfii_control0_we; -wire [3:0] vns_csrbank2_dfii_control0_w; -wire vns_csrbank2_dfii_pi0_command0_re; -wire [5:0] vns_csrbank2_dfii_pi0_command0_r; -wire vns_csrbank2_dfii_pi0_command0_we; -wire [5:0] vns_csrbank2_dfii_pi0_command0_w; -wire vns_csrbank2_dfii_pi0_address0_re; -wire [14:0] vns_csrbank2_dfii_pi0_address0_r; -wire vns_csrbank2_dfii_pi0_address0_we; -wire [14:0] vns_csrbank2_dfii_pi0_address0_w; -wire vns_csrbank2_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; -wire vns_csrbank2_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; -wire vns_csrbank2_dfii_pi0_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; -wire vns_csrbank2_dfii_pi0_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; -wire vns_csrbank2_dfii_pi0_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_r; -wire vns_csrbank2_dfii_pi0_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi0_rddata_w; -wire vns_csrbank2_dfii_pi1_command0_re; -wire [5:0] vns_csrbank2_dfii_pi1_command0_r; -wire vns_csrbank2_dfii_pi1_command0_we; -wire [5:0] vns_csrbank2_dfii_pi1_command0_w; -wire vns_csrbank2_dfii_pi1_address0_re; -wire [14:0] vns_csrbank2_dfii_pi1_address0_r; -wire vns_csrbank2_dfii_pi1_address0_we; -wire [14:0] vns_csrbank2_dfii_pi1_address0_w; -wire vns_csrbank2_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; -wire vns_csrbank2_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; -wire vns_csrbank2_dfii_pi1_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; -wire vns_csrbank2_dfii_pi1_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; -wire vns_csrbank2_dfii_pi1_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_r; -wire vns_csrbank2_dfii_pi1_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi1_rddata_w; -wire vns_csrbank2_dfii_pi2_command0_re; -wire [5:0] vns_csrbank2_dfii_pi2_command0_r; -wire vns_csrbank2_dfii_pi2_command0_we; -wire [5:0] vns_csrbank2_dfii_pi2_command0_w; -wire vns_csrbank2_dfii_pi2_address0_re; -wire [14:0] vns_csrbank2_dfii_pi2_address0_r; -wire vns_csrbank2_dfii_pi2_address0_we; -wire [14:0] vns_csrbank2_dfii_pi2_address0_w; -wire vns_csrbank2_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; -wire vns_csrbank2_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; -wire vns_csrbank2_dfii_pi2_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; -wire vns_csrbank2_dfii_pi2_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; -wire vns_csrbank2_dfii_pi2_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_r; -wire vns_csrbank2_dfii_pi2_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi2_rddata_w; -wire vns_csrbank2_dfii_pi3_command0_re; -wire [5:0] vns_csrbank2_dfii_pi3_command0_r; -wire vns_csrbank2_dfii_pi3_command0_we; -wire [5:0] vns_csrbank2_dfii_pi3_command0_w; -wire vns_csrbank2_dfii_pi3_address0_re; -wire [14:0] vns_csrbank2_dfii_pi3_address0_r; -wire vns_csrbank2_dfii_pi3_address0_we; -wire [14:0] vns_csrbank2_dfii_pi3_address0_w; -wire vns_csrbank2_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; -wire vns_csrbank2_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; -wire vns_csrbank2_dfii_pi3_wrdata0_re; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; -wire vns_csrbank2_dfii_pi3_wrdata0_we; -wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; -wire vns_csrbank2_dfii_pi3_rddata_re; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_r; -wire vns_csrbank2_dfii_pi3_rddata_we; -wire [31:0] vns_csrbank2_dfii_pi3_rddata_w; -wire vns_csrbank2_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [31:0] vns_dat_w; -wire [31:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [14:0] vns_rhs_array_muxed1 = 15'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [14:0] vns_rhs_array_muxed7 = 15'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [21:0] vns_rhs_array_muxed12 = 22'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [21:0] vns_rhs_array_muxed15 = 22'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [21:0] vns_rhs_array_muxed18 = 22'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [21:0] vns_rhs_array_muxed21 = 22'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [21:0] vns_rhs_array_muxed24 = 22'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [21:0] vns_rhs_array_muxed27 = 22'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [21:0] vns_rhs_array_muxed30 = 22'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [21:0] vns_rhs_array_muxed33 = 22'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [14:0] vns_array_muxed1 = 15'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [14:0] vns_array_muxed8 = 15'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [14:0] vns_array_muxed15 = 15'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [14:0] vns_array_muxed22 = 15'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl3_expr; +wire main_reset; +reg main_power_down = 1'd0; +wire main_locked; +wire main_clkin; +wire main_clkout0; +wire main_clkout_buf0; +wire main_clkout1; +wire main_clkout_buf1; +wire main_clkout2; +wire main_clkout_buf2; +wire main_clkout3; +wire main_clkout_buf3; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; +wire [14:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_ras_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_act_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire [14:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_ras_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_act_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire [14:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_ras_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_act_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire [14:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_ras_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_act_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +wire main_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_sd_clk_se_nodelay; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_t0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +wire main_a7ddrphy0; +wire main_a7ddrphy_dqs_o_no_delay1; +wire main_a7ddrphy_dqs_t1; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_t0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_t1; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_t2; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_t3; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_t4; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_t5; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_t6; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_t7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_t8; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_t9; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_t10; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_t11; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_t12; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_t13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_t14; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_t15; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [14:0] main_litedramcore_inti_p0_address; +wire [2:0] main_litedramcore_inti_p0_bank; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; +wire main_litedramcore_inti_p0_cke; +wire main_litedramcore_inti_p0_odt; +wire main_litedramcore_inti_p0_reset_n; +reg main_litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p0_wrdata; +wire main_litedramcore_inti_p0_wrdata_en; +wire [3:0] main_litedramcore_inti_p0_wrdata_mask; +wire main_litedramcore_inti_p0_rddata_en; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p1_address; +wire [2:0] main_litedramcore_inti_p1_bank; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; +wire main_litedramcore_inti_p1_cke; +wire main_litedramcore_inti_p1_odt; +wire main_litedramcore_inti_p1_reset_n; +reg main_litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p1_wrdata; +wire main_litedramcore_inti_p1_wrdata_en; +wire [3:0] main_litedramcore_inti_p1_wrdata_mask; +wire main_litedramcore_inti_p1_rddata_en; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p2_address; +wire [2:0] main_litedramcore_inti_p2_bank; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; +wire main_litedramcore_inti_p2_cke; +wire main_litedramcore_inti_p2_odt; +wire main_litedramcore_inti_p2_reset_n; +reg main_litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p2_wrdata; +wire main_litedramcore_inti_p2_wrdata_en; +wire [3:0] main_litedramcore_inti_p2_wrdata_mask; +wire main_litedramcore_inti_p2_rddata_en; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_inti_p3_address; +wire [2:0] main_litedramcore_inti_p3_bank; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; +wire main_litedramcore_inti_p3_cke; +wire main_litedramcore_inti_p3_odt; +wire main_litedramcore_inti_p3_reset_n; +reg main_litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_inti_p3_wrdata; +wire main_litedramcore_inti_p3_wrdata_en; +wire [3:0] main_litedramcore_inti_p3_wrdata_mask; +wire main_litedramcore_inti_p3_rddata_en; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_ras_n; +wire main_litedramcore_slave_p0_we_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_act_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p0_rddata_en; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_ras_n; +wire main_litedramcore_slave_p1_we_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_act_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p1_rddata_en; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_ras_n; +wire main_litedramcore_slave_p2_we_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_act_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p2_rddata_en; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_ras_n; +wire main_litedramcore_slave_p3_we_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_act_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +wire main_litedramcore_slave_p3_rddata_en; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p0_rddata; +wire main_litedramcore_master_p0_rddata_valid; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p1_rddata; +wire main_litedramcore_master_p1_rddata_valid; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p2_rddata; +wire main_litedramcore_master_p2_rddata_valid; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_master_p3_rddata; +wire main_litedramcore_master_p3_rddata_valid; +wire main_litedramcore_sel; +wire main_litedramcore_cke; +wire main_litedramcore_odt; +wire main_litedramcore_reset_n; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_we; +wire [21:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_we; +wire [21:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_we; +wire [21:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_we; +wire [21:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_we; +wire [21:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_we; +wire [21:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_we; +wire [21:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_we; +wire [21:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_rdata_valid; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] main_litedramcore_interface_rdata; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +wire main_litedramcore_dfi_p0_odt; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p0_rddata; +wire main_litedramcore_dfi_p0_rddata_valid; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +wire main_litedramcore_dfi_p1_odt; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p1_rddata; +wire main_litedramcore_dfi_p1_rddata_valid; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +wire main_litedramcore_dfi_p2_odt; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p2_rddata; +wire main_litedramcore_dfi_p2_rddata_valid; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +wire main_litedramcore_dfi_p3_odt; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] main_litedramcore_dfi_p3_rddata; +wire main_litedramcore_dfi_p3_rddata_valid; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_timer_wait; +wire main_litedramcore_timer_done0; +wire [9:0] main_litedramcore_timer_count0; +wire main_litedramcore_timer_done1; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_done0; +wire main_litedramcore_sequencer_start1; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_zqcs_timer_wait; +wire main_litedramcore_zqcs_timer_done0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +wire main_litedramcore_zqcs_timer_done1; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +wire main_litedramcore_bankmachine0_req_valid; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_we; +wire [21:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +wire main_litedramcore_bankmachine1_req_valid; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_we; +wire [21:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +wire main_litedramcore_bankmachine2_req_valid; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_we; +wire [21:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +wire main_litedramcore_bankmachine3_req_valid; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_we; +wire [21:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +wire main_litedramcore_bankmachine4_req_valid; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_we; +wire [21:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +wire main_litedramcore_bankmachine5_req_valid; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_we; +wire [21:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +wire main_litedramcore_bankmachine6_req_valid; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_we; +wire [21:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +wire main_litedramcore_bankmachine7_req_valid; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_we; +wire [21:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +wire main_litedramcore_ras_allowed; +wire main_litedramcore_cas_allowed; +wire [1:0] main_litedramcore_rdcmdphase; +wire [1:0] main_litedramcore_wrcmdphase; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire main_litedramcore_choose_cmd_ce; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire main_litedramcore_choose_req_ce; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +wire main_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; +wire main_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] main_litedramcore_tfawcon_count; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +wire main_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; +wire main_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_write_available; +reg main_litedramcore_en0 = 1'd0; +wire main_litedramcore_max_time0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; +wire main_litedramcore_max_time1; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire main_litedramcore_go_to_refresh; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; +wire [29:0] main_wb_bus_adr; +wire [31:0] main_wb_bus_dat_w; +wire [31:0] main_wb_bus_dat_r; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_cyc; +wire main_wb_bus_stb; +wire main_wb_bus_ack; +wire main_wb_bus_we; +wire [2:0] main_wb_bus_cti; +wire [1:0] main_wb_bus_bte; +wire main_wb_bus_err; +wire main_user_port_cmd_valid; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_payload_we; +wire [24:0] main_user_port_cmd_payload_addr; +wire main_user_port_wdata_valid; +wire main_user_port_wdata_ready; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_rdata_valid; +wire main_user_port_rdata_ready; +wire [127:0] main_user_port_rdata_payload_data; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +wire builder_pll_fb; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +wire builder_roundrobin0_request; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_ce; +wire builder_roundrobin1_request; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_ce; +wire builder_roundrobin2_request; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_ce; +wire builder_roundrobin3_request; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_ce; +wire builder_roundrobin4_request; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_ce; +wire builder_roundrobin5_request; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_ce; +wire builder_roundrobin6_request; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_ce; +wire builder_roundrobin7_request; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_ce; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [7:0] builder_litedramcore_dat_w = 8'd0; +wire [7:0] builder_litedramcore_dat_r; +wire [29:0] builder_litedramcore_wishbone_adr; +wire [31:0] builder_litedramcore_wishbone_dat_w; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] builder_litedramcore_wishbone_sel; +wire builder_litedramcore_wishbone_cyc; +wire builder_litedramcore_wishbone_stb; +reg builder_litedramcore_wishbone_ack = 1'd0; +wire builder_litedramcore_wishbone_we; +wire [2:0] builder_litedramcore_wishbone_cti; +wire [1:0] builder_litedramcore_wishbone_bte; +reg builder_litedramcore_wishbone_err = 1'd0; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [7:0] builder_interface0_bank_bus_dat_w; +reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_init_error0_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [7:0] builder_interface1_bank_bus_dat_w; +reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [7:0] builder_interface2_bank_bus_dat_w; +reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi0_address1_r; +reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi0_address1_w; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; +reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; +reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; +reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; +reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; +reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; +reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi1_address1_r; +reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi1_address1_w; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; +reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; +reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; +reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; +reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; +reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; +reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi2_address1_r; +reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi2_address1_w; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; +reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; +reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; +reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; +reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; +reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; +reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi3_address1_r; +reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; +wire [6:0] builder_csrbank2_dfii_pi3_address1_w; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; +reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; +reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; +reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; +reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; +reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; +reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +wire builder_csrbank2_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [7:0] builder_csr_interconnect_dat_w; +wire [7:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [14:0] builder_rhs_array_muxed1 = 15'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [14:0] builder_rhs_array_muxed7 = 15'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [21:0] builder_rhs_array_muxed12 = 22'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [21:0] builder_rhs_array_muxed15 = 22'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [21:0] builder_rhs_array_muxed18 = 22'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [21:0] builder_rhs_array_muxed21 = 22'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [21:0] builder_rhs_array_muxed24 = 22'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [21:0] builder_rhs_array_muxed27 = 22'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [21:0] builder_rhs_array_muxed30 = 22'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [21:0] builder_rhs_array_muxed33 = 22'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [14:0] builder_array_muxed1 = 15'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [14:0] builder_array_muxed8 = 15'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [14:0] builder_array_muxed15 = 15'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [14:0] builder_array_muxed22 = 15'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl3; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; -assign soc_wb_bus_adr = wb_ctrl_adr; -assign soc_wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = soc_wb_bus_dat_r; -assign soc_wb_bus_sel = wb_ctrl_sel; -assign soc_wb_bus_cyc = wb_ctrl_cyc; -assign soc_wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = soc_wb_bus_ack; -assign soc_wb_bus_we = wb_ctrl_we; -assign soc_wb_bus_cti = wb_ctrl_cti; -assign soc_wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = soc_wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; -assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; -assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; -assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; -assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; -assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; +assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; +assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign main_reset = rst; +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - vns_next_state <= 1'd0; - vns_next_state <= vns_state; - case (vns_state) - 1'd1: begin - vns_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - vns_next_state <= 1'd1; - end - end - endcase + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on @@ -1857,16 +2090,39 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_adr <= 14'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; - end - end - endcase + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on @@ -1876,16 +2132,39 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_we <= 1'd0; - case (vns_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); - end - end - endcase + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -1895,106 +2174,84 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_wishbone_ack <= 1'd0; - case (vns_state) - 1'd1: begin - soc_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end -assign soc_reset = rst; -assign pll_locked = soc_locked; -assign soc_clkin = clk; -assign iodelay_clk = soc_clkout_buf0; -assign sys_clk = soc_clkout_buf1; -assign sys4x_clk = soc_clkout_buf2; -assign sys4x_dqs_clk = soc_clkout_buf3; -assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p0_rddata <= 32'd0; - soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; - soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; - soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; - soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; - soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; - soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; - soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; - soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; - soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; - soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; - soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; - soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; - soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; - soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; - soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; - soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; - soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; - soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; - soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; - soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; - soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; - soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; - soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; - soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; - soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; - soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; - soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; - soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; - soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; - soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; - soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; - soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end // synthesis translate_off dummy_d_4 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); // synthesis translate_off reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p1_rddata <= 32'd0; - soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; - soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; - soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; - soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; - soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; - soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; - soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; - soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; - soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; - soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; - soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; - soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; - soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; - soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; - soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; - soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; - soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; - soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; - soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; - soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; - soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; - soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; - soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; - soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; - soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; - soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; - soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; - soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; - soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; - soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; - soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; - soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end // synthesis translate_off dummy_d_5 = dummy_s; // synthesis translate_on @@ -2004,39 +2261,33 @@ end reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p2_rddata <= 32'd0; - soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; - soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; - soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; - soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; - soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; - soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; - soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; - soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; - soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; - soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; - soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; - soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; - soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; - soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; - soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; - soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; - soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; - soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; - soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; - soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; - soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; - soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; - soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; - soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; - soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; - soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; - soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; - soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; - soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; - soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; - soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; - soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) + 1'd0: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_6 = dummy_s; // synthesis translate_on @@ -2046,97 +2297,105 @@ end reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dfi_p3_rddata <= 32'd0; - soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; - soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; - soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; - soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; - soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; - soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; - soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; - soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; - soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; - soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; - soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; - soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; - soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; - soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; - soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; - soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; - soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; - soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; - soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; - soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; - soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; - soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; - soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; - soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; - soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; - soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; - soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; - soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; - soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; - soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; - soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; - soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) + 1'd0: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_7 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; -assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; -assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; -assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; -assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; -assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; -assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; -assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; -assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; -assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; -assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; -assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; -assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; -assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; -assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; -assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; -assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; -assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqs_oe <= 1'd0; - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqs_oe <= 1'd1; - end else begin - soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; - end + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) + 1'd0: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_8 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); -assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); // synthesis translate_off reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqspattern_o0 <= 8'd0; - soc_a7ddrphy_dqspattern_o0 <= 7'd85; - if (soc_a7ddrphy_dqspattern0) begin - soc_a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (soc_a7ddrphy_dqspattern1) begin - soc_a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd0; - if (soc_a7ddrphy_wlevel_strobe_re) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd1; + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) + 1'd0: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end - end + 1'd1: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_9 = dummy_s; // synthesis translate_on @@ -2146,55 +2405,31 @@ end reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip0_o <= 8'd0; - case (soc_a7ddrphy_bitslip0_value) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase // synthesis translate_off @@ -2206,55 +2441,31 @@ end reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip1_o <= 8'd0; - case (soc_a7ddrphy_bitslip1_value) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase // synthesis translate_off @@ -2266,55 +2477,31 @@ end reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip2_o <= 8'd0; - case (soc_a7ddrphy_bitslip2_value) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase // synthesis translate_off @@ -2326,55 +2513,31 @@ end reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip3_o <= 8'd0; - case (soc_a7ddrphy_bitslip3_value) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase // synthesis translate_off @@ -2386,55 +2549,31 @@ end reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip4_o <= 8'd0; - case (soc_a7ddrphy_bitslip4_value) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase // synthesis translate_off @@ -2446,55 +2585,31 @@ end reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip5_o <= 8'd0; - case (soc_a7ddrphy_bitslip5_value) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase // synthesis translate_off @@ -2506,55 +2621,31 @@ end reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip6_o <= 8'd0; - case (soc_a7ddrphy_bitslip6_value) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase // synthesis translate_off @@ -2566,55 +2657,31 @@ end reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip7_o <= 8'd0; - case (soc_a7ddrphy_bitslip7_value) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase // synthesis translate_off @@ -2626,55 +2693,31 @@ end reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip8_o <= 8'd0; - case (soc_a7ddrphy_bitslip8_value) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase // synthesis translate_off @@ -2686,55 +2729,31 @@ end reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip9_o <= 8'd0; - case (soc_a7ddrphy_bitslip9_value) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase // synthesis translate_off @@ -2746,55 +2765,31 @@ end reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip10_o <= 8'd0; - case (soc_a7ddrphy_bitslip10_value) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase // synthesis translate_off @@ -2806,55 +2801,31 @@ end reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip11_o <= 8'd0; - case (soc_a7ddrphy_bitslip11_value) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase // synthesis translate_off @@ -2866,55 +2837,31 @@ end reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip12_o <= 8'd0; - case (soc_a7ddrphy_bitslip12_value) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase // synthesis translate_off @@ -2926,55 +2873,31 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip13_o <= 8'd0; - case (soc_a7ddrphy_bitslip13_value) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase // synthesis translate_off @@ -2986,55 +2909,31 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip14_o <= 8'd0; - case (soc_a7ddrphy_bitslip14_value) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase // synthesis translate_off @@ -3046,200 +2945,69 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip15_o <= 8'd0; - case (soc_a7ddrphy_bitslip15_value) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; - end - 4'd8: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8]; - end - 4'd9: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9]; - end - 4'd10: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10]; - end - 4'd11: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11]; - end - 4'd12: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12]; - end - 4'd13: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13]; - end - 4'd14: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14]; - end - 4'd15: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase // synthesis translate_off dummy_d_25 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; -assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; -assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; -assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; -assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; -assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; -assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; -assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; -assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; -assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; -assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; -assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; -assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; -assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; -assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; -assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; -assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; -assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; -assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; -assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; -assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; -assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; -assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; -assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; -assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; -assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; -assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; -assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; -assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; -assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; -assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; -assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; -assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; -assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; -assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; -assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; -assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; -assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; -assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; -assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; -assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; -assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; -assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; -assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; -assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; -assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; -assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; -assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; -assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; -assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; -assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; -assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; -assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; -assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; -assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; -assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; -assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; -assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; -assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; -assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; -assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; -assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; -assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; -assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; -assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; -assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; -assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; -assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; -assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; -assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; -assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; -assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; -assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; -assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; -assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; -assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; -assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; -assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; -assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; -assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; -assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; -assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; -assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; -assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; -assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; -assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; -assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; -assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; -assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; -assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; -assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; -assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; -assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; -assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; -assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; -assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; -assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; -assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; -assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; -assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; -assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; -assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; -assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; -assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; -assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; -assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; -assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; -assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; -assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; -assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; -assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; -assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; -assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; -assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; -assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; -assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; -assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; -assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; -assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; -assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; -assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; -assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; -assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; -assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; -assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; -assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; -assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; -assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; - end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; - end + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) + 1'd0: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_26 = dummy_s; // synthesis translate_on @@ -3249,11 +3017,33 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end else begin - end + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) + 1'd0: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_27 = dummy_s; // synthesis translate_on @@ -3263,12 +3053,33 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; - end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; - end + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) + 1'd0: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_28 = dummy_s; // synthesis translate_on @@ -3278,12 +3089,33 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; - end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; - end + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) + 1'd0: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_29 = dummy_s; // synthesis translate_on @@ -3293,12 +3125,33 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; - end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; - end + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) + 1'd0: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_30 = dummy_s; // synthesis translate_on @@ -3308,12 +3161,33 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; - end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; - end + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) + 1'd0: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_31 = dummy_s; // synthesis translate_on @@ -3323,12 +3197,33 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; - end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; - end + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) + 1'd0: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_32 = dummy_s; // synthesis translate_on @@ -3338,11 +3233,33 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; - end + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) + 1'd0: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_33 = dummy_s; // synthesis translate_on @@ -3352,12 +3269,33 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; - end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; - end + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) + 1'd0: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_34 = dummy_s; // synthesis translate_on @@ -3367,11 +3305,33 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) + 1'd0: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_35 = dummy_s; // synthesis translate_on @@ -3381,12 +3341,33 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; - end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; - end + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) + 1'd0: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_36 = dummy_s; // synthesis translate_on @@ -3396,12 +3377,33 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; - end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; - end + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) + 1'd0: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_37 = dummy_s; // synthesis translate_on @@ -3411,26 +3413,69 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; - end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; - end -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on -end - + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) + 1'd0: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; + end + endcase +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + // synthesis translate_off reg dummy_d_39; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; - end else begin - end + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) + 1'd0: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_39 = dummy_s; // synthesis translate_on @@ -3440,12 +3485,33 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; - end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; - end + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) + 1'd0: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; + end + endcase // synthesis translate_off dummy_d_40 = dummy_s; // synthesis translate_on @@ -3455,26 +3521,175 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; - end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; - end + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) + 1'd0: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase // synthesis translate_off dummy_d_41 = dummy_s; // synthesis translate_on end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_42; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3485,9 +3700,9 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end // synthesis translate_off @@ -3499,11 +3714,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3514,11 +3729,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3529,10 +3744,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end else begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3543,11 +3759,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3558,11 +3774,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3573,11 +3789,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + main_litedramcore_inti_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3588,11 +3803,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3603,11 +3818,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3618,10 +3832,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end else begin - soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3632,11 +3847,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3647,10 +3862,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p0_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end else begin - soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3661,11 +3877,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3676,11 +3892,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3691,11 +3907,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3706,11 +3922,10 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3721,11 +3936,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3736,11 +3951,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3751,11 +3966,10 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3766,10 +3980,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end else begin + main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3780,11 +3995,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3795,10 +4010,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end else begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3809,11 +4025,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; + main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3824,11 +4040,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; + main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3839,11 +4055,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + main_litedramcore_inti_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; + main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3854,11 +4069,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3869,11 +4084,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + main_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; + main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3884,10 +4098,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end else begin - soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3898,11 +4113,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3913,10 +4128,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p1_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end else begin - soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3927,11 +4143,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3942,11 +4158,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3957,11 +4173,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3972,11 +4188,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3987,11 +4203,10 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -4002,11 +4217,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -4017,11 +4232,10 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -4032,10 +4246,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end else begin + main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -4046,11 +4261,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -4061,10 +4276,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end else begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -4075,11 +4291,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -4090,11 +4306,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -4105,11 +4321,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + main_litedramcore_inti_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; + main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -4120,11 +4335,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -4135,11 +4350,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + main_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; + main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -4150,10 +4364,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -4164,11 +4379,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -4179,10 +4394,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin + main_litedramcore_master_p2_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end else begin - soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -4193,11 +4409,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -4208,11 +4424,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -4223,11 +4439,11 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_address <= 15'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4238,11 +4454,11 @@ end reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -4253,11 +4469,10 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -4268,11 +4483,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -4283,38 +4498,25 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; -assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; -assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; -assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; // synthesis translate_off reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4325,11 +4527,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end else begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4340,11 +4542,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4355,32 +4557,26 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_101 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; -assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; -assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); -assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); -assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; -assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_inti_p1_we_n <= 1'd1; + main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4391,11 +4587,10 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + main_litedramcore_inti_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4406,11 +4601,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4421,32 +4616,25 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + main_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_105 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; -assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; -assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); -assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); -assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; -assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4457,11 +4645,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end else begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4472,11 +4660,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + main_litedramcore_master_p3_address <= 15'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end else begin - soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4487,32 +4675,25 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; -assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; -assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); -assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); -assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; -assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4523,11 +4704,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4538,11 +4719,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4553,126 +4734,39 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; -assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; -assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); -assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); -assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; -assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; -assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; -assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; -assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; -assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; -assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; -assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; -assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; -assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; -assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; -assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; -assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; -assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; -assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; -assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; -assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; -assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; -assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; -assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; -assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; -assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; -assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; -assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; -assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; -assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; -assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; -assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; -assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; -assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; -assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; -assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; -assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; -assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; -assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; -assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; -assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; -assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; -assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; -assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; -assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; -assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; -assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; -assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; -assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; -assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; -assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; -assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; -assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; -assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; -assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; -assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; -assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; -assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; -assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; -assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; -assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; -assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; -assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); -assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; -assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; -assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; -assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); -assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); -assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; -assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; -assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); -assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); -assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); -assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; -assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; +assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p2_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p3_cke = main_litedramcore_cke; +assign main_litedramcore_inti_p0_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p1_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p2_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p3_odt = main_litedramcore_odt; +assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; // synthesis translate_off reg dummy_d_114; // synthesis translate_on always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (soc_litedramcore_wants_refresh) begin - vns_refresher_next_state <= 1'd1; - end - end - end - endcase + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; + end // synthesis translate_off dummy_d_114 = dummy_s; // synthesis translate_on @@ -4682,29 +4776,12 @@ end reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase + main_litedramcore_inti_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + end else begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_115 = dummy_s; // synthesis translate_on @@ -4714,23 +4791,12 @@ end reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_116 = dummy_s; // synthesis translate_on @@ -4740,204 +4806,99 @@ end reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase + main_litedramcore_inti_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); + end else begin + main_litedramcore_inti_p0_ras_n <= 1'd1; + end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end +assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]); +assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); +assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + end else begin + main_litedramcore_inti_p1_we_n <= 1'd1; + end // synthesis translate_off dummy_d_118 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; -assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); -assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + main_litedramcore_inti_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + main_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_119 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); -assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); -assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); - end + main_litedramcore_inti_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_120 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + main_litedramcore_inti_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + main_litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_121 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); +assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]); +assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); +assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_122; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end - end else begin - vns_bankmachine0_next_state <= 1'd1; - end - end else begin - vns_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end // synthesis translate_off dummy_d_122 = dummy_s; // synthesis translate_on @@ -4947,42 +4908,12 @@ end reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); + end else begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + end // synthesis translate_off dummy_d_123 = dummy_s; // synthesis translate_on @@ -4992,42 +4923,12 @@ end reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_inti_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end // synthesis translate_off dummy_d_124 = dummy_s; // synthesis translate_on @@ -5037,156 +4938,472 @@ end reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]); +assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); +assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + end else begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + end else begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]); +assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]); +assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; end end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; + end else begin + builder_refresher_next_state <= 1'd0; + end + end end - 4'd8: begin + 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; + end end default: begin + if (1'd1) begin + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; + end + end end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin end - 3'd5: begin + default: begin end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) + 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end - 3'd7: begin + 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end - 4'd8: begin + 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_133; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end end end - 3'd4: begin + 2'd3: begin end - 3'd5: begin + default: begin end - 3'd6: begin + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) + 1'd1: begin end - 3'd7: begin + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end - 4'd8: begin + 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_128; +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_138; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; + end + end end 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; + end + end end 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine0_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; + end + end else begin + builder_bankmachine0_next_state <= 1'd1; + end + end else begin + builder_bankmachine0_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5203,12 +5420,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -5218,26 +5438,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5254,26 +5471,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5284,42 +5505,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5332,33 +5535,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5369,19 +5580,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5399,14 +5625,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5417,16 +5643,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5444,14 +5670,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5462,176 +5688,105 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; -assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); -assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); -assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); -assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_137; +reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin end - end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_139; +reg dummy_d_147; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin - vns_bankmachine1_next_state <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5644,34 +5799,52 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5689,15 +5862,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; - end + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5707,23 +5877,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5740,60 +5913,179 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_143; +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_155; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; + end + end end 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; end end 3'd5: begin + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine1_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; + end + end else begin + builder_bankmachine1_next_state <= 1'd1; + end + end else begin + builder_bankmachine1_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5806,12 +6098,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -5821,23 +6116,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5854,26 +6149,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5887,16 +6186,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5914,12 +6213,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -5929,27 +6231,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -5962,23 +6258,35 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5995,13 +6303,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; end else begin end end else begin @@ -6013,30 +6321,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6047,19 +6348,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6067,6 +6383,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6077,39 +6396,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6122,15 +6432,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -6140,178 +6447,59 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); -assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_154; +reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on -always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; - end - end + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin end 2'd2: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; - end - end else begin - vns_bankmachine2_next_state <= 1'd1; - end - end else begin - vns_bankmachine2_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_166; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6322,34 +6510,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_167; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6367,15 +6540,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; - end + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6385,26 +6555,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6418,72 +6591,179 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_160; +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; + end end else begin + builder_bankmachine2_next_state <= 1'd1; end end else begin + builder_bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6496,26 +6776,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6532,26 +6827,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6565,16 +6864,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6592,12 +6891,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -6607,27 +6909,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6640,23 +6936,35 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6673,13 +6981,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6691,30 +6999,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6725,19 +7026,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_180; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6745,6 +7061,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6755,39 +7074,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6800,15 +7110,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6818,178 +7125,59 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; -assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); -assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); -assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); -assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_173; +reg dummy_d_182; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; - end - end else begin - vns_bankmachine3_next_state <= 1'd1; - end - end else begin - vns_bankmachine3_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -7000,34 +7188,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7045,15 +7218,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; - end + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7063,26 +7233,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_185; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7096,131 +7269,175 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_177; +reg dummy_d_186; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_178; +reg dummy_d_187; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end - endcase + end // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_179; +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_189; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end + end end 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -7237,12 +7454,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -7252,23 +7472,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7285,29 +7505,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7321,20 +7542,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7351,14 +7569,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7369,30 +7587,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7403,19 +7614,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7433,14 +7659,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7451,16 +7677,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7478,14 +7704,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7496,176 +7722,60 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); -assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); -assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_190; +reg dummy_d_197; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; - end - end else begin - vns_bankmachine4_next_state <= 1'd1; - end - end else begin - vns_bankmachine4_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7678,15 +7788,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; - end else begin - end + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -7696,21 +7803,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -7723,44 +7833,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7774,27 +7869,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7807,12 +7896,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7822,23 +7911,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7855,102 +7947,179 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_196; +reg dummy_d_203; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) - 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_197; +reg dummy_d_204; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_206; +// synthesis translate_on +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end end else begin + builder_bankmachine4_next_state <= 1'd1; end end else begin + builder_bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7963,27 +8132,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7996,48 +8180,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8051,16 +8220,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8078,14 +8247,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8096,24 +8265,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8126,19 +8292,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8156,13 +8337,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; end else begin end end else begin @@ -8174,171 +8355,61 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; -assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); -assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); -assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); -assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_207; +reg dummy_d_213; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin - vns_bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_214; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8346,6 +8417,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8356,39 +8430,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8401,15 +8466,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; - end + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -8419,23 +8481,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -8452,26 +8514,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8485,27 +8547,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8518,12 +8574,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8533,23 +8589,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8566,50 +8625,175 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_214; +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_221 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_223; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; + end + end else begin + builder_bankmachine5_next_state <= 1'd1; + end + end else begin + builder_bankmachine5_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8626,12 +8810,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8641,26 +8828,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8677,26 +8861,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8707,48 +8895,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8759,19 +8925,34 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_218 = dummy_s; + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8789,14 +8970,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8807,16 +8988,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8834,13 +9015,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -8852,176 +9033,105 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); -assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); -assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_222; +reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin end - end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_224; +reg dummy_d_231; // synthesis translate_on always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; - end - end else begin - vns_bankmachine6_next_state <= 1'd1; - end - end else begin - vns_bankmachine6_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9034,15 +9144,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; - end else begin - end + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -9052,21 +9159,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin end @@ -9079,44 +9189,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -9130,27 +9225,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9163,12 +9252,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9178,23 +9267,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9211,59 +9303,181 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_230; +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_240; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end + end else begin + builder_bankmachine6_next_state <= 1'd1; + end + end else begin + builder_bankmachine6_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9274,24 +9488,42 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9304,44 +9536,33 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9355,20 +9576,17 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9385,14 +9603,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9403,30 +9621,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9437,19 +9648,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9467,14 +9693,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9485,16 +9711,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9512,14 +9738,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9530,176 +9756,105 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; -assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); -assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); -assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); -assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); -assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_239; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin end - end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_241; +reg dummy_d_249; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin - vns_bankmachine7_next_state <= 1'd1; end end else begin - vns_bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -9712,34 +9867,52 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_251; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9757,15 +9930,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9775,26 +9945,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9808,72 +9981,179 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_245; +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_257; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end end else begin + builder_bankmachine7_next_state <= 1'd1; end end else begin + builder_bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end end 3'd4: begin end @@ -9886,29 +10166,44 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_259; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9922,23 +10217,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_260; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9949,42 +10251,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_261; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9997,23 +10281,35 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10030,13 +10326,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10048,30 +10344,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10082,19 +10371,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10112,14 +10416,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10130,26 +10434,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10163,21 +10467,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -10190,15 +10500,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -10208,386 +10515,571 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); -assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); -assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); -assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; -assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); -assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); -assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); -assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); -assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); -assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; -assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); -assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); -assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_255; +reg dummy_d_267; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_valids <= 8'd0; - soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; -assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; // synthesis translate_off -reg dummy_d_256; +reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; - end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_272; +// synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_273; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; + end +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_276; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_277; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_278; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_279; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_264; +reg dummy_d_280; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_281; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_282; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_283; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_valids <= 8'd0; - soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; -assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; // synthesis translate_off -reg dummy_d_268; +reg dummy_d_284; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_285; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_286; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); -assign soc_litedramcore_dfi_p0_reset_n = 1'd1; -assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; -assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; -assign soc_litedramcore_dfi_p1_reset_n = 1'd1; -assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; -assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; -assign soc_litedramcore_dfi_p2_reset_n = 1'd1; -assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; -assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; -assign soc_litedramcore_dfi_p3_reset_n = 1'd1; -assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; -assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; -assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_271; +reg dummy_d_287; // synthesis translate_on always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (soc_litedramcore_read_available) begin - if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (soc_litedramcore_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (soc_litedramcore_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - vns_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - vns_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - vns_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - vns_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - vns_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - vns_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - vns_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (soc_litedramcore_write_available) begin - if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (soc_litedramcore_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_288; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + main_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel0 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; end end 2'd2: begin + main_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10606,25 +11098,34 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; end end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_290; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end 2'd2: begin end @@ -10645,23 +11146,30 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_291; // synthesis translate_on always @(*) begin - soc_litedramcore_en0 <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10680,24 +11188,29 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_292; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10716,23 +11229,30 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_293; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end 2'd2: begin @@ -10756,22 +11276,29 @@ always @(*) begin default: begin if (1'd0) begin end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_294; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_steerer_sel3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end end 2'd2: begin end @@ -10792,22 +11319,27 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; + end end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_295; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10828,24 +11360,24 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_296; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end 2'd2: begin @@ -10868,2999 +11400,5058 @@ always @(*) begin end default: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12; +assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15; +assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18; +assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21; +assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24; +assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27; +assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30; +assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33; +assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + end + default: begin + main_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + end + default: begin + main_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_next_state <= 2'd2; + end + 2'd2: begin + builder_next_state <= 1'd0; + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_dat_r <= 32'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value0 <= 8'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; + end + endcase +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value1 <= 14'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + builder_litedramcore_we_next_value2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end +assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; +assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r; +assign builder_litedramcore_wishbone_sel = main_wb_bus_sel; +assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc; +assign builder_litedramcore_wishbone_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_litedramcore_wishbone_ack; +assign builder_litedramcore_wishbone_we = main_wb_bus_we; +assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; +assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_litedramcore_wishbone_err; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + end +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + end +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + end +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + end +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin + builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin + builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_416; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin + builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_416 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_417; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_417 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_418; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin + builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_418 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_419; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_419 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_420; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin + builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_420 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; + +// synthesis translate_off +reg dummy_d_421; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_421 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_422; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_422 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; + +// synthesis translate_off +reg dummy_d_423; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_423 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_424; +// synthesis translate_on +always @(*) begin + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_424 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0]; + +// synthesis translate_off +reg dummy_d_425; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_425 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_426; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin + builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_426 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_427; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_427 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_428; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_428 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; + +// synthesis translate_off +reg dummy_d_429; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_429 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_430; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_430 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_431; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_431 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_432; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin + builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_432 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_433; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_433 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_434; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin + builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_434 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_435; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_435 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_436; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_436 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_437; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + end +// synthesis translate_off + dummy_d_437 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_438; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_438 = dummy_s; +// synthesis translate_on +end +assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; + +// synthesis translate_off +reg dummy_d_439; +// synthesis translate_on +always @(*) begin + builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_439 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_280; +reg dummy_d_440; // synthesis translate_on always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin + builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_440 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_281; +reg dummy_d_441; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_441 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_282; +reg dummy_d_442; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - endcase + builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin + builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_442 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_443; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - endcase + builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_443 = dummy_s; // synthesis translate_on end -assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); -assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); -assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); -assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); -assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); -assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); -assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); -assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); -assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); -assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_444; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; - end - default: begin - soc_litedramcore_interface_wdata <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin + builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_444 = dummy_s; // synthesis translate_on end +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; // synthesis translate_off -reg dummy_d_285; +reg dummy_d_445; // synthesis translate_on always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; - case ({vns_new_master_wdata_ready2}) - 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; - end - default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; - end - endcase + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + end // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_445 = dummy_s; // synthesis translate_on end -assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; -assign vns_roundrobin0_grant = 1'd0; -assign vns_roundrobin1_grant = 1'd0; -assign vns_roundrobin2_grant = 1'd0; -assign vns_roundrobin3_grant = 1'd0; -assign vns_roundrobin4_grant = 1'd0; -assign vns_roundrobin5_grant = 1'd0; -assign vns_roundrobin6_grant = 1'd0; -assign vns_roundrobin7_grant = 1'd0; -assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; -assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; -assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; -assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; -assign soc_litedramcore_wishbone_we = soc_wb_bus_we; -assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; -assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = soc_litedramcore_wishbone_err; -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank0_init_done0_w = soc_init_done_storage; -assign vns_csrbank0_init_error0_w = soc_init_error_storage; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; -assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); -assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0]; -assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); -assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); -assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; -assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); -assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; -assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); -assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); -assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); -assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); -assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); -assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); -assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; -assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); -assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); -assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[14:0]; -assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); -assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; -assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); -assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); -assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); -assign soc_litedramcore_sel = soc_litedramcore_storage[0]; -assign soc_litedramcore_cke = soc_litedramcore_storage[1]; -assign soc_litedramcore_odt = soc_litedramcore_storage[2]; -assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; -assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; -assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; -assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[14:0]; -assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0]; -assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we; -assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; -assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[14:0]; -assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0]; -assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we; -assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; -assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[14:0]; -assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0]; -assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we; -assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; -assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[14:0]; -assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0]; -assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we; -assign vns_adr = soc_litedramcore_adr; -assign vns_we = soc_litedramcore_we; -assign vns_dat_w = soc_litedramcore_dat_w; -assign soc_litedramcore_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_286; +reg dummy_d_446; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin + builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + end +// synthesis translate_off + dummy_d_446 = dummy_s; +// synthesis translate_on +end +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; +assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; +assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; +assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; +assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; +assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csr_interconnect_adr = builder_litedramcore_adr; +assign builder_csr_interconnect_we = builder_litedramcore_we; +assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; +assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r; +assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_447; +// synthesis translate_on +always @(*) begin + builder_rhs_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_447 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_448; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 15'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed1 <= 15'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_448 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_449; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_449 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_450; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_450 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_451; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_451 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_452; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_rhs_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_452 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_453; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_453 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_454; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_454 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_455; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) + builder_t_array_muxed2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_455 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_456; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6]; end default: begin - vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_456 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_457; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 15'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed7 <= 15'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_457 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_458; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_458 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_459; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_459 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_460; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_460 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_461; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_rhs_array_muxed11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_461 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_462; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_462 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_463; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_463 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_464; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_req_grant) + builder_t_array_muxed5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_464 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_465; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 22'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed12 <= 22'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_465 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_466; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_466 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_467; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + builder_rhs_array_muxed14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_467 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_468; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 22'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed15 <= 22'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_468 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_469; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_469 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_470; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + builder_rhs_array_muxed17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_470 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_471; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 22'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed18 <= 22'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_471 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_472; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_472 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_473; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) + builder_rhs_array_muxed20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_473 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_474; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 22'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed21 <= 22'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_474 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_475; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_475 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_476; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) + builder_rhs_array_muxed23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_476 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_477; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 22'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed24 <= 22'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_477 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_478; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_478 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_479; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) + builder_rhs_array_muxed26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_479 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_480; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 22'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed27 <= 22'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_480 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_481; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_481 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_482; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) + builder_rhs_array_muxed29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_482 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_483; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 22'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed30 <= 22'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_483 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_484; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_484 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_485; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) + builder_rhs_array_muxed32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_485 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_486; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 22'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed33 <= 22'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_486 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_487; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_487 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_488; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) + builder_rhs_array_muxed35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_488 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_489; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed0 <= 3'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_489 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_490; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 15'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed1 <= 15'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_litedramcore_nop_a; + builder_array_muxed1 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_490 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_491; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed2 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + builder_array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_491 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_492; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed3 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + builder_array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_492 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_493; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed4 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + builder_array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_493 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_494; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed5 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + builder_array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_494 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_495; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + builder_array_muxed6 <= 1'd0; + case (main_litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + builder_array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_495 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_496; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed7 <= 3'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_496 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_497; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 15'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed8 <= 15'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_litedramcore_nop_a; + builder_array_muxed8 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_497 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_498; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed9 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + builder_array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_498 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_499; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed10 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + builder_array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_499 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_500; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed11 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + builder_array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_500 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_501; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed12 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + builder_array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_501 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_502; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + builder_array_muxed13 <= 1'd0; + case (main_litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + builder_array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_502 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_503; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed14 <= 3'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_503 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_504; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 15'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed15 <= 15'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_litedramcore_nop_a; + builder_array_muxed15 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_504 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_505; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed16 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + builder_array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_505 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_506; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed17 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + builder_array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_506 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_507; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed18 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + builder_array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_507 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_508; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed19 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + builder_array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_508 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_509; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + builder_array_muxed20 <= 1'd0; + case (main_litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + builder_array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_509 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_510; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed21 <= 3'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_510 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_511; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 15'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed22 <= 15'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_litedramcore_nop_a; + builder_array_muxed22 <= main_litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_511 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_512; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed23 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + builder_array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_512 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_513; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed24 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + builder_array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_513 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_514; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed25 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + builder_array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_514 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_515; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed26 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + builder_array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_515 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_516; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + builder_array_muxed27 <= 1'd0; + case (main_litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + builder_array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_516 = dummy_s; // synthesis translate_on end -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - soc_ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - vns_state <= vns_next_state; - soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; - soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; - soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; + end + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; + end + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; + end + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; + end + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; + end + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; + end + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; + end + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; + end + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip0_value <= 1'd0; + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip1_value <= 1'd0; + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip2_value <= 1'd0; + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip3_value <= 1'd0; + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip4_value <= 1'd0; + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip5_value <= 1'd0; + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip6_value <= 1'd0; + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip7_value <= 1'd0; + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip8_value <= 1'd0; + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip9_value <= 1'd0; + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip10_value <= 1'd0; + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip11_value <= 1'd0; + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip12_value <= 1'd0; + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip13_value <= 1'd0; + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip14_value <= 1'd0; + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip15_value <= 1'd0; + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]}; - if (soc_litedramcore_inti_p0_rddata_valid) begin - soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - if (soc_litedramcore_inti_p1_rddata_valid) begin - soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if (soc_litedramcore_inti_p2_rddata_valid) begin - soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - if (soc_litedramcore_inti_p3_rddata_valid) begin - soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin - soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; + end + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; + end + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; + end + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; + end + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; + end + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; + end + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; + end + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; + end + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; + end + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; + end + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_inti_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata; + end + if (main_litedramcore_inti_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata; + end + if (main_litedramcore_inti_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata; + end + if (main_litedramcore_inti_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - soc_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - soc_litedramcore_postponer_req_o <= 1'd0; - if (soc_litedramcore_postponer_req_i) begin - soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); - if ((soc_litedramcore_postponer_count == 1'd0)) begin - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (soc_litedramcore_sequencer_start0) begin - soc_litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_litedramcore_sequencer_done1) begin - if ((soc_litedramcore_sequencer_count != 1'd0)) begin - soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); - end - end - end - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd1; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd0; - end - if ((soc_litedramcore_sequencer_counter == 6'd55)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 6'd55)) begin - soc_litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_counter == 6'd55)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_counter == 6'd55)) begin + main_litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_counter != 1'd0)) begin + main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin - soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_zqcs_executer_done <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin + main_litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin + main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_litedramcore_bankmachine0_row_close) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine0_row_open) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd1; - soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; - soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid; + main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first; + main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine0_twtpcon_valid) begin - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin - soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trccon_valid) begin - soc_litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin - soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine0_trascon_valid) begin - soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_litedramcore_bankmachine1_row_close) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine1_row_open) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd1; - soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; - soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid; + main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first; + main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine1_twtpcon_valid) begin - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin - soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trccon_valid) begin - soc_litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin - soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine1_trascon_valid) begin - soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_litedramcore_bankmachine2_row_close) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine2_row_open) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd1; - soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; - soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid; + main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first; + main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine2_twtpcon_valid) begin - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin - soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trccon_valid) begin - soc_litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin - soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine2_trascon_valid) begin - soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_litedramcore_bankmachine3_row_close) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine3_row_open) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd1; - soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; - soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid; + main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first; + main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine3_twtpcon_valid) begin - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin - soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trccon_valid) begin - soc_litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin - soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine3_trascon_valid) begin - soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_litedramcore_bankmachine4_row_close) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine4_row_open) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd1; - soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; - soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid; + main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first; + main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine4_twtpcon_valid) begin - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin - soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trccon_valid) begin - soc_litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin - soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine4_trascon_valid) begin - soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_litedramcore_bankmachine5_row_close) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine5_row_open) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd1; - soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; - soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid; + main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first; + main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine5_twtpcon_valid) begin - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin - soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trccon_valid) begin - soc_litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin - soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine5_trascon_valid) begin - soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_litedramcore_bankmachine6_row_close) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine6_row_open) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd1; - soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; - soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid; + main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first; + main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine6_twtpcon_valid) begin - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin - soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trccon_valid) begin - soc_litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin - soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine6_trascon_valid) begin - soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_litedramcore_bankmachine7_row_close) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_litedramcore_bankmachine7_row_open) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd1; - soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; - soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid; + main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first; + main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_litedramcore_bankmachine7_twtpcon_valid) begin - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin - soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trccon_valid) begin - soc_litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin - soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_litedramcore_bankmachine7_trascon_valid) begin - soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_litedramcore_en0)) begin - soc_litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~soc_litedramcore_max_time0)) begin - soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~soc_litedramcore_en1)) begin - soc_litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~soc_litedramcore_max_time1)) begin - soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (soc_litedramcore_choose_cmd_ce) begin - case (soc_litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13870,26 +16461,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13899,26 +16490,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13928,26 +16519,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13957,26 +16548,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13986,26 +16577,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -14015,26 +16606,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -14044,26 +16635,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -14074,29 +16665,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_litedramcore_choose_req_ce) begin - case (soc_litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -14106,26 +16697,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -14135,26 +16726,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -14164,26 +16755,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -14193,26 +16784,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -14222,26 +16813,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -14251,26 +16842,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -14280,26 +16871,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -14310,578 +16901,802 @@ always @(posedge sys_clk) begin end endcase end - soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; - soc_litedramcore_dfi_p0_address <= vns_array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; - soc_litedramcore_dfi_p1_address <= vns_array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; - soc_litedramcore_dfi_p2_address <= vns_array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; - soc_litedramcore_dfi_p3_address <= vns_array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_litedramcore_trrdcon_valid) begin - soc_litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_array_muxed0; + main_litedramcore_dfi_p0_address <= builder_array_muxed1; + main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2); + main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3); + main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4); + main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5; + main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_array_muxed7; + main_litedramcore_dfi_p1_address <= builder_array_muxed8; + main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9); + main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10); + main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11); + main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12; + main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_array_muxed14; + main_litedramcore_dfi_p2_address <= builder_array_muxed15; + main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16); + main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17); + main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18); + main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19; + main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_array_muxed21; + main_litedramcore_dfi_p3_address <= builder_array_muxed22; + main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23); + main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24); + main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25); + main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26; + main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_trrdcon_ready)) begin - soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); - if ((soc_litedramcore_trrdcon_count == 1'd1)) begin - soc_litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; - if ((soc_litedramcore_tfawcon_count < 3'd4)) begin - if ((soc_litedramcore_tfawcon_count == 2'd3)) begin - soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - soc_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_litedramcore_tccdcon_valid) begin - soc_litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_tccdcon_ready)) begin - soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); - if ((soc_litedramcore_tccdcon_count == 1'd1)) begin - soc_litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_litedramcore_twtrcon_valid) begin - soc_litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~soc_litedramcore_twtrcon_ready)) begin - soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); - if ((soc_litedramcore_twtrcon_count == 1'd1)) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_litedramcore_dat_w_next_value_ce0) begin + builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0; + end + if (builder_litedramcore_adr_next_value_ce1) begin + builder_litedramcore_adr <= builder_litedramcore_adr_next_value1; + end + if (builder_litedramcore_we_next_value_ce2) begin + builder_litedramcore_we <= builder_litedramcore_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (vns_csrbank0_init_done0_re) begin - soc_init_done_storage <= vns_csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank0_init_done0_re; - if (vns_csrbank0_init_error0_re) begin - soc_init_error_storage <= vns_csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank0_init_error0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[3:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd2: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 2'd3: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd4: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 3'd5: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (vns_csrbank1_half_sys8x_taps0_re) begin - soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; + end + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + end + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; + end + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; - if (vns_csrbank1_wlevel_en0_re) begin - soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; - if (vns_csrbank1_dly_sel0_re) begin - soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r; + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[4:0]) + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 4'd10: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; end 4'd11: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; end 4'd12: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end 4'd13: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end 4'd14: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd15: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; end 5'd17: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 5'd18: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 5'd19: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; end 5'd20: begin - vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; end 5'd21: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; end 5'd22: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 5'd23: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; end 5'd24: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; + end + 5'd25: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; + end + 5'd26: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; + end + 5'd27: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; + end + 5'd28: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; + end + 5'd29: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; + end + 5'd30: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; + end + 5'd31: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; + end + 6'd32: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; + end + 6'd33: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; + end + 6'd34: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; + end + 6'd35: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; + end + 6'd36: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; + end + 6'd37: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; + end + 6'd38: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; + end + 6'd39: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; + end + 6'd40: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; + end + 6'd41: begin + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; + end + 6'd42: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; + end + 6'd43: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; + end + 6'd44: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; + end + 6'd45: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; + end + 6'd46: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; + end + 6'd47: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; + end + 6'd48: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; + end + 6'd49: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; + end + 6'd50: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; + end + 6'd51: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; + end + 6'd52: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank2_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + end + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; + end + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address1_re) begin + main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r; + end + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + end + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; - if (vns_csrbank2_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata3_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; end - soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; - if (vns_csrbank2_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[14:0] <= vns_csrbank2_dfii_pi0_address0_r; + if (builder_csrbank2_dfii_pi0_wrdata2_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; end - soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; - if (vns_csrbank2_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + if (builder_csrbank2_dfii_pi0_wrdata1_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; end - soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; - if (vns_csrbank2_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; - if (vns_csrbank2_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end - soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; - if (vns_csrbank2_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[14:0] <= vns_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address1_re) begin + main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r; end - soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; - if (vns_csrbank2_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; end - soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; - if (vns_csrbank2_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; - if (vns_csrbank2_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata3_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; end - soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; - if (vns_csrbank2_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[14:0] <= vns_csrbank2_dfii_pi2_address0_r; + if (builder_csrbank2_dfii_pi1_wrdata2_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; end - soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; - if (vns_csrbank2_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + if (builder_csrbank2_dfii_pi1_wrdata1_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; end - soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; - if (vns_csrbank2_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; - if (vns_csrbank2_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end - soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; - if (vns_csrbank2_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[14:0] <= vns_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address1_re) begin + main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r; end - soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; - if (vns_csrbank2_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; end - soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; - if (vns_csrbank2_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata3_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; + end + if (builder_csrbank2_dfii_pi2_wrdata2_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; + end + if (builder_csrbank2_dfii_pi2_wrdata1_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; + end + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + end + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; + end + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address1_re) begin + main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r; + end + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + end + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + end + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata3_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; + end + if (builder_csrbank2_dfii_pi3_wrdata2_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; + end + if (builder_csrbank2_dfii_pi3_wrdata1_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; + end + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + end + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; if (sys_rst) begin - soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_a7ddrphy_wlevel_en_storage <= 1'd0; - soc_a7ddrphy_wlevel_en_re <= 1'd0; - soc_a7ddrphy_dly_sel_storage <= 2'd0; - soc_a7ddrphy_dly_sel_re <= 1'd0; - soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_a7ddrphy_dqs_oe_delayed <= 1'd0; - soc_a7ddrphy_dqspattern_o1 <= 8'd0; - soc_a7ddrphy_dq_oe_delayed <= 1'd0; - soc_a7ddrphy_bitslip0_value <= 4'd0; - soc_a7ddrphy_bitslip1_value <= 4'd0; - soc_a7ddrphy_bitslip2_value <= 4'd0; - soc_a7ddrphy_bitslip3_value <= 4'd0; - soc_a7ddrphy_bitslip4_value <= 4'd0; - soc_a7ddrphy_bitslip5_value <= 4'd0; - soc_a7ddrphy_bitslip6_value <= 4'd0; - soc_a7ddrphy_bitslip7_value <= 4'd0; - soc_a7ddrphy_bitslip8_value <= 4'd0; - soc_a7ddrphy_bitslip9_value <= 4'd0; - soc_a7ddrphy_bitslip10_value <= 4'd0; - soc_a7ddrphy_bitslip11_value <= 4'd0; - soc_a7ddrphy_bitslip12_value <= 4'd0; - soc_a7ddrphy_bitslip13_value <= 4'd0; - soc_a7ddrphy_bitslip14_value <= 4'd0; - soc_a7ddrphy_bitslip15_value <= 4'd0; - soc_a7ddrphy_rddata_en_last <= 8'd0; - soc_a7ddrphy_wrdata_en_last <= 4'd0; - soc_litedramcore_storage <= 4'd1; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; - soc_litedramcore_phaseinjector0_command_re <= 1'd0; - soc_litedramcore_phaseinjector0_address_re <= 1'd0; - soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector0_status <= 32'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; - soc_litedramcore_phaseinjector1_command_re <= 1'd0; - soc_litedramcore_phaseinjector1_address_re <= 1'd0; - soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector1_status <= 32'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; - soc_litedramcore_phaseinjector2_command_re <= 1'd0; - soc_litedramcore_phaseinjector2_address_re <= 1'd0; - soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector2_status <= 32'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; - soc_litedramcore_phaseinjector3_command_re <= 1'd0; - soc_litedramcore_phaseinjector3_address_re <= 1'd0; - soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector3_status <= 32'd0; - soc_litedramcore_dfi_p0_address <= 15'd0; - soc_litedramcore_dfi_p0_bank <= 3'd0; - soc_litedramcore_dfi_p0_cas_n <= 1'd1; - soc_litedramcore_dfi_p0_cs_n <= 1'd1; - soc_litedramcore_dfi_p0_ras_n <= 1'd1; - soc_litedramcore_dfi_p0_we_n <= 1'd1; - soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p0_rddata_en <= 1'd0; - soc_litedramcore_dfi_p1_address <= 15'd0; - soc_litedramcore_dfi_p1_bank <= 3'd0; - soc_litedramcore_dfi_p1_cas_n <= 1'd1; - soc_litedramcore_dfi_p1_cs_n <= 1'd1; - soc_litedramcore_dfi_p1_ras_n <= 1'd1; - soc_litedramcore_dfi_p1_we_n <= 1'd1; - soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p1_rddata_en <= 1'd0; - soc_litedramcore_dfi_p2_address <= 15'd0; - soc_litedramcore_dfi_p2_bank <= 3'd0; - soc_litedramcore_dfi_p2_cas_n <= 1'd1; - soc_litedramcore_dfi_p2_cs_n <= 1'd1; - soc_litedramcore_dfi_p2_ras_n <= 1'd1; - soc_litedramcore_dfi_p2_we_n <= 1'd1; - soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p2_rddata_en <= 1'd0; - soc_litedramcore_dfi_p3_address <= 15'd0; - soc_litedramcore_dfi_p3_bank <= 3'd0; - soc_litedramcore_dfi_p3_cas_n <= 1'd1; - soc_litedramcore_dfi_p3_cs_n <= 1'd1; - soc_litedramcore_dfi_p3_ras_n <= 1'd1; - soc_litedramcore_dfi_p3_we_n <= 1'd1; - soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p3_rddata_en <= 1'd0; - soc_litedramcore_timer_count1 <= 10'd781; - soc_litedramcore_postponer_req_o <= 1'd0; - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 6'd0; - soc_litedramcore_sequencer_count <= 1'd0; - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine0_row <= 15'd0; - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trccon_count <= 3'd0; - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trascon_count <= 3'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine1_row <= 15'd0; - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trccon_count <= 3'd0; - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trascon_count <= 3'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine2_row <= 15'd0; - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trccon_count <= 3'd0; - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trascon_count <= 3'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine3_row <= 15'd0; - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trccon_count <= 3'd0; - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trascon_count <= 3'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine4_row <= 15'd0; - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trccon_count <= 3'd0; - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trascon_count <= 3'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine5_row <= 15'd0; - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trccon_count <= 3'd0; - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trascon_count <= 3'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine6_row <= 15'd0; - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trccon_count <= 3'd0; - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trascon_count <= 3'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine7_row <= 15'd0; - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trccon_count <= 3'd0; - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trascon_count <= 3'd0; - soc_litedramcore_choose_cmd_grant <= 3'd0; - soc_litedramcore_choose_req_grant <= 3'd0; - soc_litedramcore_trrdcon_ready <= 1'd0; - soc_litedramcore_trrdcon_count <= 1'd0; - soc_litedramcore_tfawcon_ready <= 1'd1; - soc_litedramcore_tfawcon_window <= 5'd0; - soc_litedramcore_tccdcon_ready <= 1'd0; - soc_litedramcore_tccdcon_count <= 1'd0; - soc_litedramcore_twtrcon_ready <= 1'd0; - soc_litedramcore_twtrcon_count <= 3'd0; - soc_litedramcore_time0 <= 5'd0; - soc_litedramcore_time1 <= 4'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 6'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 6'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 6'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 6'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 15'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 15'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 15'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 15'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 15'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_counter <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_counter <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine0_row <= 15'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine1_row <= 15'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine2_row <= 15'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine3_row <= 15'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine4_row <= 15'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine5_row <= 15'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine6_row <= 15'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine7_row <= 15'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_litedramcore_we <= 1'd0; + builder_state <= 2'd0; end end BUFG BUFG( - .I(soc_clkout0), - .O(soc_clkout_buf0) + .I(main_clkout0), + .O(main_clkout_buf0) ); BUFG BUFG_1( - .I(soc_clkout1), - .O(soc_clkout_buf1) + .I(main_clkout1), + .O(main_clkout_buf1) ); BUFG BUFG_2( - .I(soc_clkout2), - .O(soc_clkout_buf2) + .I(main_clkout2), + .O(main_clkout_buf2) ); BUFG BUFG_3( - .I(soc_clkout3), - .O(soc_clkout_buf3) + .I(main_clkout3), + .O(main_clkout_buf3) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(main_ic_reset) ); OSERDESE2 #( @@ -14902,12 +17717,12 @@ OSERDESE2 #( .D7(1'd0), .D8(1'd1), .OCE(1'd1), - .RST(sys_rst), - .OQ(soc_a7ddrphy_sd_clk_se_nodelay) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(main_a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_a7ddrphy_sd_clk_se_nodelay), + .I(main_a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -14921,17 +17736,17 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[0]), - .D2(soc_a7ddrphy_dfi_p0_address[0]), - .D3(soc_a7ddrphy_dfi_p1_address[0]), - .D4(soc_a7ddrphy_dfi_p1_address[0]), - .D5(soc_a7ddrphy_dfi_p2_address[0]), - .D6(soc_a7ddrphy_dfi_p2_address[0]), - .D7(soc_a7ddrphy_dfi_p3_address[0]), - .D8(soc_a7ddrphy_dfi_p3_address[0]), + .D1(main_a7ddrphy_dfi_p0_reset_n), + .D2(main_a7ddrphy_dfi_p0_reset_n), + .D3(main_a7ddrphy_dfi_p1_reset_n), + .D4(main_a7ddrphy_dfi_p1_reset_n), + .D5(main_a7ddrphy_dfi_p2_reset_n), + .D6(main_a7ddrphy_dfi_p2_reset_n), + .D7(main_a7ddrphy_dfi_p3_reset_n), + .D8(main_a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_reset_n) ); OSERDESE2 #( @@ -14943,17 +17758,17 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[1]), - .D2(soc_a7ddrphy_dfi_p0_address[1]), - .D3(soc_a7ddrphy_dfi_p1_address[1]), - .D4(soc_a7ddrphy_dfi_p1_address[1]), - .D5(soc_a7ddrphy_dfi_p2_address[1]), - .D6(soc_a7ddrphy_dfi_p2_address[1]), - .D7(soc_a7ddrphy_dfi_p3_address[1]), - .D8(soc_a7ddrphy_dfi_p3_address[1]), + .D1(main_a7ddrphy_dfi_p0_cs_n), + .D2(main_a7ddrphy_dfi_p0_cs_n), + .D3(main_a7ddrphy_dfi_p1_cs_n), + .D4(main_a7ddrphy_dfi_p1_cs_n), + .D5(main_a7ddrphy_dfi_p2_cs_n), + .D6(main_a7ddrphy_dfi_p2_cs_n), + .D7(main_a7ddrphy_dfi_p3_cs_n), + .D8(main_a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cs_n) ); OSERDESE2 #( @@ -14965,17 +17780,17 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[2]), - .D2(soc_a7ddrphy_dfi_p0_address[2]), - .D3(soc_a7ddrphy_dfi_p1_address[2]), - .D4(soc_a7ddrphy_dfi_p1_address[2]), - .D5(soc_a7ddrphy_dfi_p2_address[2]), - .D6(soc_a7ddrphy_dfi_p2_address[2]), - .D7(soc_a7ddrphy_dfi_p3_address[2]), - .D8(soc_a7ddrphy_dfi_p3_address[2]), + .D1(main_a7ddrphy_dfi_p0_address[0]), + .D2(main_a7ddrphy_dfi_p0_address[0]), + .D3(main_a7ddrphy_dfi_p1_address[0]), + .D4(main_a7ddrphy_dfi_p1_address[0]), + .D5(main_a7ddrphy_dfi_p2_address[0]), + .D6(main_a7ddrphy_dfi_p2_address[0]), + .D7(main_a7ddrphy_dfi_p3_address[0]), + .D8(main_a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[0]) ); OSERDESE2 #( @@ -14987,17 +17802,17 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[3]), - .D2(soc_a7ddrphy_dfi_p0_address[3]), - .D3(soc_a7ddrphy_dfi_p1_address[3]), - .D4(soc_a7ddrphy_dfi_p1_address[3]), - .D5(soc_a7ddrphy_dfi_p2_address[3]), - .D6(soc_a7ddrphy_dfi_p2_address[3]), - .D7(soc_a7ddrphy_dfi_p3_address[3]), - .D8(soc_a7ddrphy_dfi_p3_address[3]), + .D1(main_a7ddrphy_dfi_p0_address[1]), + .D2(main_a7ddrphy_dfi_p0_address[1]), + .D3(main_a7ddrphy_dfi_p1_address[1]), + .D4(main_a7ddrphy_dfi_p1_address[1]), + .D5(main_a7ddrphy_dfi_p2_address[1]), + .D6(main_a7ddrphy_dfi_p2_address[1]), + .D7(main_a7ddrphy_dfi_p3_address[1]), + .D8(main_a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[3]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[1]) ); OSERDESE2 #( @@ -15009,17 +17824,17 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[4]), - .D2(soc_a7ddrphy_dfi_p0_address[4]), - .D3(soc_a7ddrphy_dfi_p1_address[4]), - .D4(soc_a7ddrphy_dfi_p1_address[4]), - .D5(soc_a7ddrphy_dfi_p2_address[4]), - .D6(soc_a7ddrphy_dfi_p2_address[4]), - .D7(soc_a7ddrphy_dfi_p3_address[4]), - .D8(soc_a7ddrphy_dfi_p3_address[4]), + .D1(main_a7ddrphy_dfi_p0_address[2]), + .D2(main_a7ddrphy_dfi_p0_address[2]), + .D3(main_a7ddrphy_dfi_p1_address[2]), + .D4(main_a7ddrphy_dfi_p1_address[2]), + .D5(main_a7ddrphy_dfi_p2_address[2]), + .D6(main_a7ddrphy_dfi_p2_address[2]), + .D7(main_a7ddrphy_dfi_p3_address[2]), + .D8(main_a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[4]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[2]) ); OSERDESE2 #( @@ -15031,17 +17846,17 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[5]), - .D2(soc_a7ddrphy_dfi_p0_address[5]), - .D3(soc_a7ddrphy_dfi_p1_address[5]), - .D4(soc_a7ddrphy_dfi_p1_address[5]), - .D5(soc_a7ddrphy_dfi_p2_address[5]), - .D6(soc_a7ddrphy_dfi_p2_address[5]), - .D7(soc_a7ddrphy_dfi_p3_address[5]), - .D8(soc_a7ddrphy_dfi_p3_address[5]), + .D1(main_a7ddrphy_dfi_p0_address[3]), + .D2(main_a7ddrphy_dfi_p0_address[3]), + .D3(main_a7ddrphy_dfi_p1_address[3]), + .D4(main_a7ddrphy_dfi_p1_address[3]), + .D5(main_a7ddrphy_dfi_p2_address[3]), + .D6(main_a7ddrphy_dfi_p2_address[3]), + .D7(main_a7ddrphy_dfi_p3_address[3]), + .D8(main_a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[5]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[3]) ); OSERDESE2 #( @@ -15053,17 +17868,17 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[6]), - .D2(soc_a7ddrphy_dfi_p0_address[6]), - .D3(soc_a7ddrphy_dfi_p1_address[6]), - .D4(soc_a7ddrphy_dfi_p1_address[6]), - .D5(soc_a7ddrphy_dfi_p2_address[6]), - .D6(soc_a7ddrphy_dfi_p2_address[6]), - .D7(soc_a7ddrphy_dfi_p3_address[6]), - .D8(soc_a7ddrphy_dfi_p3_address[6]), + .D1(main_a7ddrphy_dfi_p0_address[4]), + .D2(main_a7ddrphy_dfi_p0_address[4]), + .D3(main_a7ddrphy_dfi_p1_address[4]), + .D4(main_a7ddrphy_dfi_p1_address[4]), + .D5(main_a7ddrphy_dfi_p2_address[4]), + .D6(main_a7ddrphy_dfi_p2_address[4]), + .D7(main_a7ddrphy_dfi_p3_address[4]), + .D8(main_a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[6]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[4]) ); OSERDESE2 #( @@ -15075,17 +17890,17 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[7]), - .D2(soc_a7ddrphy_dfi_p0_address[7]), - .D3(soc_a7ddrphy_dfi_p1_address[7]), - .D4(soc_a7ddrphy_dfi_p1_address[7]), - .D5(soc_a7ddrphy_dfi_p2_address[7]), - .D6(soc_a7ddrphy_dfi_p2_address[7]), - .D7(soc_a7ddrphy_dfi_p3_address[7]), - .D8(soc_a7ddrphy_dfi_p3_address[7]), + .D1(main_a7ddrphy_dfi_p0_address[5]), + .D2(main_a7ddrphy_dfi_p0_address[5]), + .D3(main_a7ddrphy_dfi_p1_address[5]), + .D4(main_a7ddrphy_dfi_p1_address[5]), + .D5(main_a7ddrphy_dfi_p2_address[5]), + .D6(main_a7ddrphy_dfi_p2_address[5]), + .D7(main_a7ddrphy_dfi_p3_address[5]), + .D8(main_a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[7]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[5]) ); OSERDESE2 #( @@ -15097,17 +17912,17 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[8]), - .D2(soc_a7ddrphy_dfi_p0_address[8]), - .D3(soc_a7ddrphy_dfi_p1_address[8]), - .D4(soc_a7ddrphy_dfi_p1_address[8]), - .D5(soc_a7ddrphy_dfi_p2_address[8]), - .D6(soc_a7ddrphy_dfi_p2_address[8]), - .D7(soc_a7ddrphy_dfi_p3_address[8]), - .D8(soc_a7ddrphy_dfi_p3_address[8]), + .D1(main_a7ddrphy_dfi_p0_address[6]), + .D2(main_a7ddrphy_dfi_p0_address[6]), + .D3(main_a7ddrphy_dfi_p1_address[6]), + .D4(main_a7ddrphy_dfi_p1_address[6]), + .D5(main_a7ddrphy_dfi_p2_address[6]), + .D6(main_a7ddrphy_dfi_p2_address[6]), + .D7(main_a7ddrphy_dfi_p3_address[6]), + .D8(main_a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[8]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[6]) ); OSERDESE2 #( @@ -15119,17 +17934,17 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[9]), - .D2(soc_a7ddrphy_dfi_p0_address[9]), - .D3(soc_a7ddrphy_dfi_p1_address[9]), - .D4(soc_a7ddrphy_dfi_p1_address[9]), - .D5(soc_a7ddrphy_dfi_p2_address[9]), - .D6(soc_a7ddrphy_dfi_p2_address[9]), - .D7(soc_a7ddrphy_dfi_p3_address[9]), - .D8(soc_a7ddrphy_dfi_p3_address[9]), + .D1(main_a7ddrphy_dfi_p0_address[7]), + .D2(main_a7ddrphy_dfi_p0_address[7]), + .D3(main_a7ddrphy_dfi_p1_address[7]), + .D4(main_a7ddrphy_dfi_p1_address[7]), + .D5(main_a7ddrphy_dfi_p2_address[7]), + .D6(main_a7ddrphy_dfi_p2_address[7]), + .D7(main_a7ddrphy_dfi_p3_address[7]), + .D8(main_a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[9]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[7]) ); OSERDESE2 #( @@ -15141,17 +17956,17 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[10]), - .D2(soc_a7ddrphy_dfi_p0_address[10]), - .D3(soc_a7ddrphy_dfi_p1_address[10]), - .D4(soc_a7ddrphy_dfi_p1_address[10]), - .D5(soc_a7ddrphy_dfi_p2_address[10]), - .D6(soc_a7ddrphy_dfi_p2_address[10]), - .D7(soc_a7ddrphy_dfi_p3_address[10]), - .D8(soc_a7ddrphy_dfi_p3_address[10]), + .D1(main_a7ddrphy_dfi_p0_address[8]), + .D2(main_a7ddrphy_dfi_p0_address[8]), + .D3(main_a7ddrphy_dfi_p1_address[8]), + .D4(main_a7ddrphy_dfi_p1_address[8]), + .D5(main_a7ddrphy_dfi_p2_address[8]), + .D6(main_a7ddrphy_dfi_p2_address[8]), + .D7(main_a7ddrphy_dfi_p3_address[8]), + .D8(main_a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[10]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[8]) ); OSERDESE2 #( @@ -15163,17 +17978,17 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[11]), - .D2(soc_a7ddrphy_dfi_p0_address[11]), - .D3(soc_a7ddrphy_dfi_p1_address[11]), - .D4(soc_a7ddrphy_dfi_p1_address[11]), - .D5(soc_a7ddrphy_dfi_p2_address[11]), - .D6(soc_a7ddrphy_dfi_p2_address[11]), - .D7(soc_a7ddrphy_dfi_p3_address[11]), - .D8(soc_a7ddrphy_dfi_p3_address[11]), + .D1(main_a7ddrphy_dfi_p0_address[9]), + .D2(main_a7ddrphy_dfi_p0_address[9]), + .D3(main_a7ddrphy_dfi_p1_address[9]), + .D4(main_a7ddrphy_dfi_p1_address[9]), + .D5(main_a7ddrphy_dfi_p2_address[9]), + .D6(main_a7ddrphy_dfi_p2_address[9]), + .D7(main_a7ddrphy_dfi_p3_address[9]), + .D8(main_a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[11]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[9]) ); OSERDESE2 #( @@ -15185,17 +18000,17 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[12]), - .D2(soc_a7ddrphy_dfi_p0_address[12]), - .D3(soc_a7ddrphy_dfi_p1_address[12]), - .D4(soc_a7ddrphy_dfi_p1_address[12]), - .D5(soc_a7ddrphy_dfi_p2_address[12]), - .D6(soc_a7ddrphy_dfi_p2_address[12]), - .D7(soc_a7ddrphy_dfi_p3_address[12]), - .D8(soc_a7ddrphy_dfi_p3_address[12]), + .D1(main_a7ddrphy_dfi_p0_address[10]), + .D2(main_a7ddrphy_dfi_p0_address[10]), + .D3(main_a7ddrphy_dfi_p1_address[10]), + .D4(main_a7ddrphy_dfi_p1_address[10]), + .D5(main_a7ddrphy_dfi_p2_address[10]), + .D6(main_a7ddrphy_dfi_p2_address[10]), + .D7(main_a7ddrphy_dfi_p3_address[10]), + .D8(main_a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[12]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[10]) ); OSERDESE2 #( @@ -15207,17 +18022,17 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[13]), - .D2(soc_a7ddrphy_dfi_p0_address[13]), - .D3(soc_a7ddrphy_dfi_p1_address[13]), - .D4(soc_a7ddrphy_dfi_p1_address[13]), - .D5(soc_a7ddrphy_dfi_p2_address[13]), - .D6(soc_a7ddrphy_dfi_p2_address[13]), - .D7(soc_a7ddrphy_dfi_p3_address[13]), - .D8(soc_a7ddrphy_dfi_p3_address[13]), + .D1(main_a7ddrphy_dfi_p0_address[11]), + .D2(main_a7ddrphy_dfi_p0_address[11]), + .D3(main_a7ddrphy_dfi_p1_address[11]), + .D4(main_a7ddrphy_dfi_p1_address[11]), + .D5(main_a7ddrphy_dfi_p2_address[11]), + .D6(main_a7ddrphy_dfi_p2_address[11]), + .D7(main_a7ddrphy_dfi_p3_address[11]), + .D8(main_a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[13]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[11]) ); OSERDESE2 #( @@ -15229,17 +18044,17 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[14]), - .D2(soc_a7ddrphy_dfi_p0_address[14]), - .D3(soc_a7ddrphy_dfi_p1_address[14]), - .D4(soc_a7ddrphy_dfi_p1_address[14]), - .D5(soc_a7ddrphy_dfi_p2_address[14]), - .D6(soc_a7ddrphy_dfi_p2_address[14]), - .D7(soc_a7ddrphy_dfi_p3_address[14]), - .D8(soc_a7ddrphy_dfi_p3_address[14]), + .D1(main_a7ddrphy_dfi_p0_address[12]), + .D2(main_a7ddrphy_dfi_p0_address[12]), + .D3(main_a7ddrphy_dfi_p1_address[12]), + .D4(main_a7ddrphy_dfi_p1_address[12]), + .D5(main_a7ddrphy_dfi_p2_address[12]), + .D6(main_a7ddrphy_dfi_p2_address[12]), + .D7(main_a7ddrphy_dfi_p3_address[12]), + .D8(main_a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_a[14]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[12]) ); OSERDESE2 #( @@ -15251,17 +18066,17 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[0]), - .D2(soc_a7ddrphy_dfi_p0_bank[0]), - .D3(soc_a7ddrphy_dfi_p1_bank[0]), - .D4(soc_a7ddrphy_dfi_p1_bank[0]), - .D5(soc_a7ddrphy_dfi_p2_bank[0]), - .D6(soc_a7ddrphy_dfi_p2_bank[0]), - .D7(soc_a7ddrphy_dfi_p3_bank[0]), - .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .D1(main_a7ddrphy_dfi_p0_address[13]), + .D2(main_a7ddrphy_dfi_p0_address[13]), + .D3(main_a7ddrphy_dfi_p1_address[13]), + .D4(main_a7ddrphy_dfi_p1_address[13]), + .D5(main_a7ddrphy_dfi_p2_address[13]), + .D6(main_a7ddrphy_dfi_p2_address[13]), + .D7(main_a7ddrphy_dfi_p3_address[13]), + .D8(main_a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[13]) ); OSERDESE2 #( @@ -15273,17 +18088,17 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[1]), - .D2(soc_a7ddrphy_dfi_p0_bank[1]), - .D3(soc_a7ddrphy_dfi_p1_bank[1]), - .D4(soc_a7ddrphy_dfi_p1_bank[1]), - .D5(soc_a7ddrphy_dfi_p2_bank[1]), - .D6(soc_a7ddrphy_dfi_p2_bank[1]), - .D7(soc_a7ddrphy_dfi_p3_bank[1]), - .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .D1(main_a7ddrphy_dfi_p0_address[14]), + .D2(main_a7ddrphy_dfi_p0_address[14]), + .D3(main_a7ddrphy_dfi_p1_address[14]), + .D4(main_a7ddrphy_dfi_p1_address[14]), + .D5(main_a7ddrphy_dfi_p2_address[14]), + .D6(main_a7ddrphy_dfi_p2_address[14]), + .D7(main_a7ddrphy_dfi_p3_address[14]), + .D8(main_a7ddrphy_dfi_p3_address[14]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_a[14]) ); OSERDESE2 #( @@ -15295,17 +18110,17 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[2]), - .D2(soc_a7ddrphy_dfi_p0_bank[2]), - .D3(soc_a7ddrphy_dfi_p1_bank[2]), - .D4(soc_a7ddrphy_dfi_p1_bank[2]), - .D5(soc_a7ddrphy_dfi_p2_bank[2]), - .D6(soc_a7ddrphy_dfi_p2_bank[2]), - .D7(soc_a7ddrphy_dfi_p3_bank[2]), - .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .D1(main_a7ddrphy_dfi_p0_bank[0]), + .D2(main_a7ddrphy_dfi_p0_bank[0]), + .D3(main_a7ddrphy_dfi_p1_bank[0]), + .D4(main_a7ddrphy_dfi_p1_bank[0]), + .D5(main_a7ddrphy_dfi_p2_bank[0]), + .D6(main_a7ddrphy_dfi_p2_bank[0]), + .D7(main_a7ddrphy_dfi_p3_bank[0]), + .D8(main_a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ba[2]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[0]) ); OSERDESE2 #( @@ -15317,17 +18132,17 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_ras_n), - .D2(soc_a7ddrphy_dfi_p0_ras_n), - .D3(soc_a7ddrphy_dfi_p1_ras_n), - .D4(soc_a7ddrphy_dfi_p1_ras_n), - .D5(soc_a7ddrphy_dfi_p2_ras_n), - .D6(soc_a7ddrphy_dfi_p2_ras_n), - .D7(soc_a7ddrphy_dfi_p3_ras_n), - .D8(soc_a7ddrphy_dfi_p3_ras_n), + .D1(main_a7ddrphy_dfi_p0_bank[1]), + .D2(main_a7ddrphy_dfi_p0_bank[1]), + .D3(main_a7ddrphy_dfi_p1_bank[1]), + .D4(main_a7ddrphy_dfi_p1_bank[1]), + .D5(main_a7ddrphy_dfi_p2_bank[1]), + .D6(main_a7ddrphy_dfi_p2_bank[1]), + .D7(main_a7ddrphy_dfi_p3_bank[1]), + .D8(main_a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_ras_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[1]) ); OSERDESE2 #( @@ -15339,17 +18154,17 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cas_n), - .D2(soc_a7ddrphy_dfi_p0_cas_n), - .D3(soc_a7ddrphy_dfi_p1_cas_n), - .D4(soc_a7ddrphy_dfi_p1_cas_n), - .D5(soc_a7ddrphy_dfi_p2_cas_n), - .D6(soc_a7ddrphy_dfi_p2_cas_n), - .D7(soc_a7ddrphy_dfi_p3_cas_n), - .D8(soc_a7ddrphy_dfi_p3_cas_n), + .D1(main_a7ddrphy_dfi_p0_bank[2]), + .D2(main_a7ddrphy_dfi_p0_bank[2]), + .D3(main_a7ddrphy_dfi_p1_bank[2]), + .D4(main_a7ddrphy_dfi_p1_bank[2]), + .D5(main_a7ddrphy_dfi_p2_bank[2]), + .D6(main_a7ddrphy_dfi_p2_bank[2]), + .D7(main_a7ddrphy_dfi_p3_bank[2]), + .D8(main_a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cas_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ba[2]) ); OSERDESE2 #( @@ -15361,17 +18176,17 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_we_n), - .D2(soc_a7ddrphy_dfi_p0_we_n), - .D3(soc_a7ddrphy_dfi_p1_we_n), - .D4(soc_a7ddrphy_dfi_p1_we_n), - .D5(soc_a7ddrphy_dfi_p2_we_n), - .D6(soc_a7ddrphy_dfi_p2_we_n), - .D7(soc_a7ddrphy_dfi_p3_we_n), - .D8(soc_a7ddrphy_dfi_p3_we_n), + .D1(main_a7ddrphy_dfi_p0_ras_n), + .D2(main_a7ddrphy_dfi_p0_ras_n), + .D3(main_a7ddrphy_dfi_p1_ras_n), + .D4(main_a7ddrphy_dfi_p1_ras_n), + .D5(main_a7ddrphy_dfi_p2_ras_n), + .D6(main_a7ddrphy_dfi_p2_ras_n), + .D7(main_a7ddrphy_dfi_p3_ras_n), + .D8(main_a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_we_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_ras_n) ); OSERDESE2 #( @@ -15383,17 +18198,17 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cke), - .D2(soc_a7ddrphy_dfi_p0_cke), - .D3(soc_a7ddrphy_dfi_p1_cke), - .D4(soc_a7ddrphy_dfi_p1_cke), - .D5(soc_a7ddrphy_dfi_p2_cke), - .D6(soc_a7ddrphy_dfi_p2_cke), - .D7(soc_a7ddrphy_dfi_p3_cke), - .D8(soc_a7ddrphy_dfi_p3_cke), + .D1(main_a7ddrphy_dfi_p0_cas_n), + .D2(main_a7ddrphy_dfi_p0_cas_n), + .D3(main_a7ddrphy_dfi_p1_cas_n), + .D4(main_a7ddrphy_dfi_p1_cas_n), + .D5(main_a7ddrphy_dfi_p2_cas_n), + .D6(main_a7ddrphy_dfi_p2_cas_n), + .D7(main_a7ddrphy_dfi_p3_cas_n), + .D8(main_a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cke) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cas_n) ); OSERDESE2 #( @@ -15405,17 +18220,17 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_odt), - .D2(soc_a7ddrphy_dfi_p0_odt), - .D3(soc_a7ddrphy_dfi_p1_odt), - .D4(soc_a7ddrphy_dfi_p1_odt), - .D5(soc_a7ddrphy_dfi_p2_odt), - .D6(soc_a7ddrphy_dfi_p2_odt), - .D7(soc_a7ddrphy_dfi_p3_odt), - .D8(soc_a7ddrphy_dfi_p3_odt), + .D1(main_a7ddrphy_dfi_p0_we_n), + .D2(main_a7ddrphy_dfi_p0_we_n), + .D3(main_a7ddrphy_dfi_p1_we_n), + .D4(main_a7ddrphy_dfi_p1_we_n), + .D5(main_a7ddrphy_dfi_p2_we_n), + .D6(main_a7ddrphy_dfi_p2_we_n), + .D7(main_a7ddrphy_dfi_p3_we_n), + .D8(main_a7ddrphy_dfi_p3_we_n), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_odt) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_we_n) ); OSERDESE2 #( @@ -15427,17 +18242,17 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_reset_n), - .D2(soc_a7ddrphy_dfi_p0_reset_n), - .D3(soc_a7ddrphy_dfi_p1_reset_n), - .D4(soc_a7ddrphy_dfi_p1_reset_n), - .D5(soc_a7ddrphy_dfi_p2_reset_n), - .D6(soc_a7ddrphy_dfi_p2_reset_n), - .D7(soc_a7ddrphy_dfi_p3_reset_n), - .D8(soc_a7ddrphy_dfi_p3_reset_n), + .D1(main_a7ddrphy_dfi_p0_cke), + .D2(main_a7ddrphy_dfi_p0_cke), + .D3(main_a7ddrphy_dfi_p1_cke), + .D4(main_a7ddrphy_dfi_p1_cke), + .D5(main_a7ddrphy_dfi_p2_cke), + .D6(main_a7ddrphy_dfi_p2_cke), + .D7(main_a7ddrphy_dfi_p3_cke), + .D8(main_a7ddrphy_dfi_p3_cke), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_reset_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_cke) ); OSERDESE2 #( @@ -15449,17 +18264,17 @@ OSERDESE2 #( ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cs_n), - .D2(soc_a7ddrphy_dfi_p0_cs_n), - .D3(soc_a7ddrphy_dfi_p1_cs_n), - .D4(soc_a7ddrphy_dfi_p1_cs_n), - .D5(soc_a7ddrphy_dfi_p2_cs_n), - .D6(soc_a7ddrphy_dfi_p2_cs_n), - .D7(soc_a7ddrphy_dfi_p3_cs_n), - .D8(soc_a7ddrphy_dfi_p3_cs_n), + .D1(main_a7ddrphy_dfi_p0_odt), + .D2(main_a7ddrphy_dfi_p0_odt), + .D3(main_a7ddrphy_dfi_p1_odt), + .D4(main_a7ddrphy_dfi_p1_odt), + .D5(main_a7ddrphy_dfi_p2_odt), + .D6(main_a7ddrphy_dfi_p2_odt), + .D7(main_a7ddrphy_dfi_p3_odt), + .D8(main_a7ddrphy_dfi_p3_odt), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_cs_n) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_odt) ); OSERDESE2 #( @@ -15469,19 +18284,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .D1(main_a7ddrphy_bitslip00[0]), + .D2(main_a7ddrphy_bitslip00[1]), + .D3(main_a7ddrphy_bitslip00[2]), + .D4(main_a7ddrphy_bitslip00[3]), + .D5(main_a7ddrphy_bitslip00[4]), + .D6(main_a7ddrphy_bitslip00[5]), + .D7(main_a7ddrphy_bitslip00[6]), + .D8(main_a7ddrphy_bitslip00[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy0), + .OQ(main_a7ddrphy_dqs_o_no_delay0), + .TQ(main_a7ddrphy_dqs_t0) +); + +IOBUFDS IOBUFDS( + .I(main_a7ddrphy_dqs_o_no_delay0), + .T(main_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( @@ -15491,19 +18317,30 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_clk), + .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .D1(main_a7ddrphy_bitslip10[0]), + .D2(main_a7ddrphy_bitslip10[1]), + .D3(main_a7ddrphy_bitslip10[2]), + .D4(main_a7ddrphy_bitslip10[3]), + .D5(main_a7ddrphy_bitslip10[4]), + .D6(main_a7ddrphy_bitslip10[5]), + .D7(main_a7ddrphy_bitslip10[6]), + .D8(main_a7ddrphy_bitslip10[7]), .OCE(1'd1), - .RST(sys_rst), - .OQ(ddram_dm[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(main_a7ddrphy1), + .OQ(main_a7ddrphy_dqs_o_no_delay1), + .TQ(main_a7ddrphy_dqs_t1) +); + +IOBUFDS IOBUFDS_1( + .I(main_a7ddrphy_dqs_o_no_delay1), + .T(main_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( @@ -15513,45 +18350,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip01[0]), + .D2(main_a7ddrphy_bitslip01[1]), + .D3(main_a7ddrphy_bitslip01[2]), + .D4(main_a7ddrphy_bitslip01[3]), + .D5(main_a7ddrphy_bitslip01[4]), + .D6(main_a7ddrphy_bitslip01[5]), + .D7(main_a7ddrphy_bitslip01[6]), + .D8(main_a7ddrphy_bitslip01[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy0), - .OQ(soc_a7ddrphy_dqs_o_no_delay0), - .TQ(soc_a7ddrphy_dqs_t0) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2 ( - .IDATAIN(soc_a7ddrphy_dqs_i[0]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) -); - -IOBUFDS IOBUFDS( - .I(soc_a7ddrphy_dqs_o_no_delay0), - .T(soc_a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]), - .O(soc_a7ddrphy_dqs_i[0]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[0]) ); OSERDESE2 #( @@ -15561,45 +18372,19 @@ OSERDESE2 #( .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_dqs_clk), + .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(main_a7ddrphy_bitslip11[0]), + .D2(main_a7ddrphy_bitslip11[1]), + .D3(main_a7ddrphy_bitslip11[2]), + .D4(main_a7ddrphy_bitslip11[3]), + .D5(main_a7ddrphy_bitslip11[4]), + .D6(main_a7ddrphy_bitslip11[5]), + .D7(main_a7ddrphy_bitslip11[6]), + .D8(main_a7ddrphy_bitslip11[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), - .TCE(1'd1), - .OFB(soc_a7ddrphy1), - .OQ(soc_a7ddrphy_dqs_o_no_delay1), - .TQ(soc_a7ddrphy_dqs_t1) -); - -IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") -) IDELAYE2_1 ( - .IDATAIN(soc_a7ddrphy_dqs_i[1]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) -); - -IOBUFDS IOBUFDS_1( - .I(soc_a7ddrphy_dqs_o_no_delay1), - .T(soc_a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]), - .O(soc_a7ddrphy_dqs_i[1]) + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .OQ(ddram_dm[1]) ); OSERDESE2 #( @@ -15611,20 +18396,20 @@ OSERDESE2 #( ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .D1(main_a7ddrphy_bitslip02[0]), + .D2(main_a7ddrphy_bitslip02[1]), + .D3(main_a7ddrphy_bitslip02[2]), + .D4(main_a7ddrphy_bitslip02[3]), + .D5(main_a7ddrphy_bitslip02[4]), + .D6(main_a7ddrphy_bitslip02[5]), + .D7(main_a7ddrphy_bitslip02[6]), + .D8(main_a7ddrphy_bitslip02[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay0), - .TQ(soc_a7ddrphy_dq_t0) + .OQ(main_a7ddrphy_dq_o_nodelay0), + .TQ(main_a7ddrphy_dq_t0) ); ISERDESE2 #( @@ -15640,16 +18425,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed0), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data0[7]), - .Q2(soc_a7ddrphy_dq_i_data0[6]), - .Q3(soc_a7ddrphy_dq_i_data0[5]), - .Q4(soc_a7ddrphy_dq_i_data0[4]), - .Q5(soc_a7ddrphy_dq_i_data0[3]), - .Q6(soc_a7ddrphy_dq_i_data0[2]), - .Q7(soc_a7ddrphy_dq_i_data0[1]), - .Q8(soc_a7ddrphy_dq_i_data0[0]) + .DDLY(main_a7ddrphy_dq_i_delayed0), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip03[7]), + .Q2(main_a7ddrphy_bitslip03[6]), + .Q3(main_a7ddrphy_bitslip03[5]), + .Q4(main_a7ddrphy_bitslip03[4]), + .Q5(main_a7ddrphy_bitslip03[3]), + .Q6(main_a7ddrphy_bitslip03[2]), + .Q7(main_a7ddrphy_bitslip03[1]), + .Q8(main_a7ddrphy_bitslip03[0]) ); IDELAYE2 #( @@ -15661,21 +18446,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_2 ( +) IDELAYE2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed0) + .DATAOUT(main_a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_a7ddrphy_dq_o_nodelay0), - .T(soc_a7ddrphy_dq_t0), + .I(main_a7ddrphy_dq_o_nodelay0), + .T(main_a7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_a7ddrphy_dq_i_nodelay0) + .O(main_a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -15687,20 +18472,20 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .D1(main_a7ddrphy_bitslip12[0]), + .D2(main_a7ddrphy_bitslip12[1]), + .D3(main_a7ddrphy_bitslip12[2]), + .D4(main_a7ddrphy_bitslip12[3]), + .D5(main_a7ddrphy_bitslip12[4]), + .D6(main_a7ddrphy_bitslip12[5]), + .D7(main_a7ddrphy_bitslip12[6]), + .D8(main_a7ddrphy_bitslip12[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay1), - .TQ(soc_a7ddrphy_dq_t1) + .OQ(main_a7ddrphy_dq_o_nodelay1), + .TQ(main_a7ddrphy_dq_t1) ); ISERDESE2 #( @@ -15716,16 +18501,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed1), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data1[7]), - .Q2(soc_a7ddrphy_dq_i_data1[6]), - .Q3(soc_a7ddrphy_dq_i_data1[5]), - .Q4(soc_a7ddrphy_dq_i_data1[4]), - .Q5(soc_a7ddrphy_dq_i_data1[3]), - .Q6(soc_a7ddrphy_dq_i_data1[2]), - .Q7(soc_a7ddrphy_dq_i_data1[1]), - .Q8(soc_a7ddrphy_dq_i_data1[0]) + .DDLY(main_a7ddrphy_dq_i_delayed1), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip13[7]), + .Q2(main_a7ddrphy_bitslip13[6]), + .Q3(main_a7ddrphy_bitslip13[5]), + .Q4(main_a7ddrphy_bitslip13[4]), + .Q5(main_a7ddrphy_bitslip13[3]), + .Q6(main_a7ddrphy_bitslip13[2]), + .Q7(main_a7ddrphy_bitslip13[1]), + .Q8(main_a7ddrphy_bitslip13[0]) ); IDELAYE2 #( @@ -15737,21 +18522,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_3 ( +) IDELAYE2_1 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed1) + .DATAOUT(main_a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_a7ddrphy_dq_o_nodelay1), - .T(soc_a7ddrphy_dq_t1), + .I(main_a7ddrphy_dq_o_nodelay1), + .T(main_a7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_a7ddrphy_dq_i_nodelay1) + .O(main_a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -15763,20 +18548,20 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .D1(main_a7ddrphy_bitslip20[0]), + .D2(main_a7ddrphy_bitslip20[1]), + .D3(main_a7ddrphy_bitslip20[2]), + .D4(main_a7ddrphy_bitslip20[3]), + .D5(main_a7ddrphy_bitslip20[4]), + .D6(main_a7ddrphy_bitslip20[5]), + .D7(main_a7ddrphy_bitslip20[6]), + .D8(main_a7ddrphy_bitslip20[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay2), - .TQ(soc_a7ddrphy_dq_t2) + .OQ(main_a7ddrphy_dq_o_nodelay2), + .TQ(main_a7ddrphy_dq_t2) ); ISERDESE2 #( @@ -15792,16 +18577,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed2), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data2[7]), - .Q2(soc_a7ddrphy_dq_i_data2[6]), - .Q3(soc_a7ddrphy_dq_i_data2[5]), - .Q4(soc_a7ddrphy_dq_i_data2[4]), - .Q5(soc_a7ddrphy_dq_i_data2[3]), - .Q6(soc_a7ddrphy_dq_i_data2[2]), - .Q7(soc_a7ddrphy_dq_i_data2[1]), - .Q8(soc_a7ddrphy_dq_i_data2[0]) + .DDLY(main_a7ddrphy_dq_i_delayed2), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip21[7]), + .Q2(main_a7ddrphy_bitslip21[6]), + .Q3(main_a7ddrphy_bitslip21[5]), + .Q4(main_a7ddrphy_bitslip21[4]), + .Q5(main_a7ddrphy_bitslip21[3]), + .Q6(main_a7ddrphy_bitslip21[2]), + .Q7(main_a7ddrphy_bitslip21[1]), + .Q8(main_a7ddrphy_bitslip21[0]) ); IDELAYE2 #( @@ -15813,21 +18598,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_4 ( +) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed2) + .DATAOUT(main_a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_a7ddrphy_dq_o_nodelay2), - .T(soc_a7ddrphy_dq_t2), + .I(main_a7ddrphy_dq_o_nodelay2), + .T(main_a7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_a7ddrphy_dq_i_nodelay2) + .O(main_a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -15839,20 +18624,20 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .D1(main_a7ddrphy_bitslip30[0]), + .D2(main_a7ddrphy_bitslip30[1]), + .D3(main_a7ddrphy_bitslip30[2]), + .D4(main_a7ddrphy_bitslip30[3]), + .D5(main_a7ddrphy_bitslip30[4]), + .D6(main_a7ddrphy_bitslip30[5]), + .D7(main_a7ddrphy_bitslip30[6]), + .D8(main_a7ddrphy_bitslip30[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay3), - .TQ(soc_a7ddrphy_dq_t3) + .OQ(main_a7ddrphy_dq_o_nodelay3), + .TQ(main_a7ddrphy_dq_t3) ); ISERDESE2 #( @@ -15868,16 +18653,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed3), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data3[7]), - .Q2(soc_a7ddrphy_dq_i_data3[6]), - .Q3(soc_a7ddrphy_dq_i_data3[5]), - .Q4(soc_a7ddrphy_dq_i_data3[4]), - .Q5(soc_a7ddrphy_dq_i_data3[3]), - .Q6(soc_a7ddrphy_dq_i_data3[2]), - .Q7(soc_a7ddrphy_dq_i_data3[1]), - .Q8(soc_a7ddrphy_dq_i_data3[0]) + .DDLY(main_a7ddrphy_dq_i_delayed3), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip31[7]), + .Q2(main_a7ddrphy_bitslip31[6]), + .Q3(main_a7ddrphy_bitslip31[5]), + .Q4(main_a7ddrphy_bitslip31[4]), + .Q5(main_a7ddrphy_bitslip31[3]), + .Q6(main_a7ddrphy_bitslip31[2]), + .Q7(main_a7ddrphy_bitslip31[1]), + .Q8(main_a7ddrphy_bitslip31[0]) ); IDELAYE2 #( @@ -15889,21 +18674,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_5 ( +) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed3) + .DATAOUT(main_a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_a7ddrphy_dq_o_nodelay3), - .T(soc_a7ddrphy_dq_t3), + .I(main_a7ddrphy_dq_o_nodelay3), + .T(main_a7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_a7ddrphy_dq_i_nodelay3) + .O(main_a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -15915,20 +18700,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .D1(main_a7ddrphy_bitslip40[0]), + .D2(main_a7ddrphy_bitslip40[1]), + .D3(main_a7ddrphy_bitslip40[2]), + .D4(main_a7ddrphy_bitslip40[3]), + .D5(main_a7ddrphy_bitslip40[4]), + .D6(main_a7ddrphy_bitslip40[5]), + .D7(main_a7ddrphy_bitslip40[6]), + .D8(main_a7ddrphy_bitslip40[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay4), - .TQ(soc_a7ddrphy_dq_t4) + .OQ(main_a7ddrphy_dq_o_nodelay4), + .TQ(main_a7ddrphy_dq_t4) ); ISERDESE2 #( @@ -15944,16 +18729,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed4), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data4[7]), - .Q2(soc_a7ddrphy_dq_i_data4[6]), - .Q3(soc_a7ddrphy_dq_i_data4[5]), - .Q4(soc_a7ddrphy_dq_i_data4[4]), - .Q5(soc_a7ddrphy_dq_i_data4[3]), - .Q6(soc_a7ddrphy_dq_i_data4[2]), - .Q7(soc_a7ddrphy_dq_i_data4[1]), - .Q8(soc_a7ddrphy_dq_i_data4[0]) + .DDLY(main_a7ddrphy_dq_i_delayed4), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip41[7]), + .Q2(main_a7ddrphy_bitslip41[6]), + .Q3(main_a7ddrphy_bitslip41[5]), + .Q4(main_a7ddrphy_bitslip41[4]), + .Q5(main_a7ddrphy_bitslip41[3]), + .Q6(main_a7ddrphy_bitslip41[2]), + .Q7(main_a7ddrphy_bitslip41[1]), + .Q8(main_a7ddrphy_bitslip41[0]) ); IDELAYE2 #( @@ -15965,21 +18750,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_6 ( +) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed4) + .DATAOUT(main_a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_a7ddrphy_dq_o_nodelay4), - .T(soc_a7ddrphy_dq_t4), + .I(main_a7ddrphy_dq_o_nodelay4), + .T(main_a7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_a7ddrphy_dq_i_nodelay4) + .O(main_a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -15991,20 +18776,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .D1(main_a7ddrphy_bitslip50[0]), + .D2(main_a7ddrphy_bitslip50[1]), + .D3(main_a7ddrphy_bitslip50[2]), + .D4(main_a7ddrphy_bitslip50[3]), + .D5(main_a7ddrphy_bitslip50[4]), + .D6(main_a7ddrphy_bitslip50[5]), + .D7(main_a7ddrphy_bitslip50[6]), + .D8(main_a7ddrphy_bitslip50[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay5), - .TQ(soc_a7ddrphy_dq_t5) + .OQ(main_a7ddrphy_dq_o_nodelay5), + .TQ(main_a7ddrphy_dq_t5) ); ISERDESE2 #( @@ -16020,16 +18805,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed5), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data5[7]), - .Q2(soc_a7ddrphy_dq_i_data5[6]), - .Q3(soc_a7ddrphy_dq_i_data5[5]), - .Q4(soc_a7ddrphy_dq_i_data5[4]), - .Q5(soc_a7ddrphy_dq_i_data5[3]), - .Q6(soc_a7ddrphy_dq_i_data5[2]), - .Q7(soc_a7ddrphy_dq_i_data5[1]), - .Q8(soc_a7ddrphy_dq_i_data5[0]) + .DDLY(main_a7ddrphy_dq_i_delayed5), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip51[7]), + .Q2(main_a7ddrphy_bitslip51[6]), + .Q3(main_a7ddrphy_bitslip51[5]), + .Q4(main_a7ddrphy_bitslip51[4]), + .Q5(main_a7ddrphy_bitslip51[3]), + .Q6(main_a7ddrphy_bitslip51[2]), + .Q7(main_a7ddrphy_bitslip51[1]), + .Q8(main_a7ddrphy_bitslip51[0]) ); IDELAYE2 #( @@ -16041,21 +18826,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_7 ( +) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed5) + .DATAOUT(main_a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_a7ddrphy_dq_o_nodelay5), - .T(soc_a7ddrphy_dq_t5), + .I(main_a7ddrphy_dq_o_nodelay5), + .T(main_a7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_a7ddrphy_dq_i_nodelay5) + .O(main_a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -16067,20 +18852,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .D1(main_a7ddrphy_bitslip60[0]), + .D2(main_a7ddrphy_bitslip60[1]), + .D3(main_a7ddrphy_bitslip60[2]), + .D4(main_a7ddrphy_bitslip60[3]), + .D5(main_a7ddrphy_bitslip60[4]), + .D6(main_a7ddrphy_bitslip60[5]), + .D7(main_a7ddrphy_bitslip60[6]), + .D8(main_a7ddrphy_bitslip60[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay6), - .TQ(soc_a7ddrphy_dq_t6) + .OQ(main_a7ddrphy_dq_o_nodelay6), + .TQ(main_a7ddrphy_dq_t6) ); ISERDESE2 #( @@ -16096,16 +18881,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed6), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data6[7]), - .Q2(soc_a7ddrphy_dq_i_data6[6]), - .Q3(soc_a7ddrphy_dq_i_data6[5]), - .Q4(soc_a7ddrphy_dq_i_data6[4]), - .Q5(soc_a7ddrphy_dq_i_data6[3]), - .Q6(soc_a7ddrphy_dq_i_data6[2]), - .Q7(soc_a7ddrphy_dq_i_data6[1]), - .Q8(soc_a7ddrphy_dq_i_data6[0]) + .DDLY(main_a7ddrphy_dq_i_delayed6), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip61[7]), + .Q2(main_a7ddrphy_bitslip61[6]), + .Q3(main_a7ddrphy_bitslip61[5]), + .Q4(main_a7ddrphy_bitslip61[4]), + .Q5(main_a7ddrphy_bitslip61[3]), + .Q6(main_a7ddrphy_bitslip61[2]), + .Q7(main_a7ddrphy_bitslip61[1]), + .Q8(main_a7ddrphy_bitslip61[0]) ); IDELAYE2 #( @@ -16117,21 +18902,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_8 ( +) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed6) + .DATAOUT(main_a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_a7ddrphy_dq_o_nodelay6), - .T(soc_a7ddrphy_dq_t6), + .I(main_a7ddrphy_dq_o_nodelay6), + .T(main_a7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_a7ddrphy_dq_i_nodelay6) + .O(main_a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -16143,20 +18928,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .D1(main_a7ddrphy_bitslip70[0]), + .D2(main_a7ddrphy_bitslip70[1]), + .D3(main_a7ddrphy_bitslip70[2]), + .D4(main_a7ddrphy_bitslip70[3]), + .D5(main_a7ddrphy_bitslip70[4]), + .D6(main_a7ddrphy_bitslip70[5]), + .D7(main_a7ddrphy_bitslip70[6]), + .D8(main_a7ddrphy_bitslip70[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay7), - .TQ(soc_a7ddrphy_dq_t7) + .OQ(main_a7ddrphy_dq_o_nodelay7), + .TQ(main_a7ddrphy_dq_t7) ); ISERDESE2 #( @@ -16172,16 +18957,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed7), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data7[7]), - .Q2(soc_a7ddrphy_dq_i_data7[6]), - .Q3(soc_a7ddrphy_dq_i_data7[5]), - .Q4(soc_a7ddrphy_dq_i_data7[4]), - .Q5(soc_a7ddrphy_dq_i_data7[3]), - .Q6(soc_a7ddrphy_dq_i_data7[2]), - .Q7(soc_a7ddrphy_dq_i_data7[1]), - .Q8(soc_a7ddrphy_dq_i_data7[0]) + .DDLY(main_a7ddrphy_dq_i_delayed7), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip71[7]), + .Q2(main_a7ddrphy_bitslip71[6]), + .Q3(main_a7ddrphy_bitslip71[5]), + .Q4(main_a7ddrphy_bitslip71[4]), + .Q5(main_a7ddrphy_bitslip71[3]), + .Q6(main_a7ddrphy_bitslip71[2]), + .Q7(main_a7ddrphy_bitslip71[1]), + .Q8(main_a7ddrphy_bitslip71[0]) ); IDELAYE2 #( @@ -16193,21 +18978,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_9 ( +) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed7) + .DATAOUT(main_a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_a7ddrphy_dq_o_nodelay7), - .T(soc_a7ddrphy_dq_t7), + .I(main_a7ddrphy_dq_o_nodelay7), + .T(main_a7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_a7ddrphy_dq_i_nodelay7) + .O(main_a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -16219,20 +19004,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .D1(main_a7ddrphy_bitslip80[0]), + .D2(main_a7ddrphy_bitslip80[1]), + .D3(main_a7ddrphy_bitslip80[2]), + .D4(main_a7ddrphy_bitslip80[3]), + .D5(main_a7ddrphy_bitslip80[4]), + .D6(main_a7ddrphy_bitslip80[5]), + .D7(main_a7ddrphy_bitslip80[6]), + .D8(main_a7ddrphy_bitslip80[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay8), - .TQ(soc_a7ddrphy_dq_t8) + .OQ(main_a7ddrphy_dq_o_nodelay8), + .TQ(main_a7ddrphy_dq_t8) ); ISERDESE2 #( @@ -16248,16 +19033,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed8), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data8[7]), - .Q2(soc_a7ddrphy_dq_i_data8[6]), - .Q3(soc_a7ddrphy_dq_i_data8[5]), - .Q4(soc_a7ddrphy_dq_i_data8[4]), - .Q5(soc_a7ddrphy_dq_i_data8[3]), - .Q6(soc_a7ddrphy_dq_i_data8[2]), - .Q7(soc_a7ddrphy_dq_i_data8[1]), - .Q8(soc_a7ddrphy_dq_i_data8[0]) + .DDLY(main_a7ddrphy_dq_i_delayed8), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip81[7]), + .Q2(main_a7ddrphy_bitslip81[6]), + .Q3(main_a7ddrphy_bitslip81[5]), + .Q4(main_a7ddrphy_bitslip81[4]), + .Q5(main_a7ddrphy_bitslip81[3]), + .Q6(main_a7ddrphy_bitslip81[2]), + .Q7(main_a7ddrphy_bitslip81[1]), + .Q8(main_a7ddrphy_bitslip81[0]) ); IDELAYE2 #( @@ -16269,21 +19054,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_10 ( +) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed8) + .DATAOUT(main_a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_a7ddrphy_dq_o_nodelay8), - .T(soc_a7ddrphy_dq_t8), + .I(main_a7ddrphy_dq_o_nodelay8), + .T(main_a7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_a7ddrphy_dq_i_nodelay8) + .O(main_a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -16295,20 +19080,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .D1(main_a7ddrphy_bitslip90[0]), + .D2(main_a7ddrphy_bitslip90[1]), + .D3(main_a7ddrphy_bitslip90[2]), + .D4(main_a7ddrphy_bitslip90[3]), + .D5(main_a7ddrphy_bitslip90[4]), + .D6(main_a7ddrphy_bitslip90[5]), + .D7(main_a7ddrphy_bitslip90[6]), + .D8(main_a7ddrphy_bitslip90[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay9), - .TQ(soc_a7ddrphy_dq_t9) + .OQ(main_a7ddrphy_dq_o_nodelay9), + .TQ(main_a7ddrphy_dq_t9) ); ISERDESE2 #( @@ -16324,16 +19109,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed9), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data9[7]), - .Q2(soc_a7ddrphy_dq_i_data9[6]), - .Q3(soc_a7ddrphy_dq_i_data9[5]), - .Q4(soc_a7ddrphy_dq_i_data9[4]), - .Q5(soc_a7ddrphy_dq_i_data9[3]), - .Q6(soc_a7ddrphy_dq_i_data9[2]), - .Q7(soc_a7ddrphy_dq_i_data9[1]), - .Q8(soc_a7ddrphy_dq_i_data9[0]) + .DDLY(main_a7ddrphy_dq_i_delayed9), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip91[7]), + .Q2(main_a7ddrphy_bitslip91[6]), + .Q3(main_a7ddrphy_bitslip91[5]), + .Q4(main_a7ddrphy_bitslip91[4]), + .Q5(main_a7ddrphy_bitslip91[3]), + .Q6(main_a7ddrphy_bitslip91[2]), + .Q7(main_a7ddrphy_bitslip91[1]), + .Q8(main_a7ddrphy_bitslip91[0]) ); IDELAYE2 #( @@ -16345,21 +19130,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_11 ( +) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed9) + .DATAOUT(main_a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_a7ddrphy_dq_o_nodelay9), - .T(soc_a7ddrphy_dq_t9), + .I(main_a7ddrphy_dq_o_nodelay9), + .T(main_a7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_a7ddrphy_dq_i_nodelay9) + .O(main_a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -16371,20 +19156,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .D1(main_a7ddrphy_bitslip100[0]), + .D2(main_a7ddrphy_bitslip100[1]), + .D3(main_a7ddrphy_bitslip100[2]), + .D4(main_a7ddrphy_bitslip100[3]), + .D5(main_a7ddrphy_bitslip100[4]), + .D6(main_a7ddrphy_bitslip100[5]), + .D7(main_a7ddrphy_bitslip100[6]), + .D8(main_a7ddrphy_bitslip100[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay10), - .TQ(soc_a7ddrphy_dq_t10) + .OQ(main_a7ddrphy_dq_o_nodelay10), + .TQ(main_a7ddrphy_dq_t10) ); ISERDESE2 #( @@ -16400,16 +19185,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed10), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data10[7]), - .Q2(soc_a7ddrphy_dq_i_data10[6]), - .Q3(soc_a7ddrphy_dq_i_data10[5]), - .Q4(soc_a7ddrphy_dq_i_data10[4]), - .Q5(soc_a7ddrphy_dq_i_data10[3]), - .Q6(soc_a7ddrphy_dq_i_data10[2]), - .Q7(soc_a7ddrphy_dq_i_data10[1]), - .Q8(soc_a7ddrphy_dq_i_data10[0]) + .DDLY(main_a7ddrphy_dq_i_delayed10), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip101[7]), + .Q2(main_a7ddrphy_bitslip101[6]), + .Q3(main_a7ddrphy_bitslip101[5]), + .Q4(main_a7ddrphy_bitslip101[4]), + .Q5(main_a7ddrphy_bitslip101[3]), + .Q6(main_a7ddrphy_bitslip101[2]), + .Q7(main_a7ddrphy_bitslip101[1]), + .Q8(main_a7ddrphy_bitslip101[0]) ); IDELAYE2 #( @@ -16421,21 +19206,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_12 ( +) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed10) + .DATAOUT(main_a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_a7ddrphy_dq_o_nodelay10), - .T(soc_a7ddrphy_dq_t10), + .I(main_a7ddrphy_dq_o_nodelay10), + .T(main_a7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_a7ddrphy_dq_i_nodelay10) + .O(main_a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -16447,20 +19232,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .D1(main_a7ddrphy_bitslip110[0]), + .D2(main_a7ddrphy_bitslip110[1]), + .D3(main_a7ddrphy_bitslip110[2]), + .D4(main_a7ddrphy_bitslip110[3]), + .D5(main_a7ddrphy_bitslip110[4]), + .D6(main_a7ddrphy_bitslip110[5]), + .D7(main_a7ddrphy_bitslip110[6]), + .D8(main_a7ddrphy_bitslip110[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay11), - .TQ(soc_a7ddrphy_dq_t11) + .OQ(main_a7ddrphy_dq_o_nodelay11), + .TQ(main_a7ddrphy_dq_t11) ); ISERDESE2 #( @@ -16476,16 +19261,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed11), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data11[7]), - .Q2(soc_a7ddrphy_dq_i_data11[6]), - .Q3(soc_a7ddrphy_dq_i_data11[5]), - .Q4(soc_a7ddrphy_dq_i_data11[4]), - .Q5(soc_a7ddrphy_dq_i_data11[3]), - .Q6(soc_a7ddrphy_dq_i_data11[2]), - .Q7(soc_a7ddrphy_dq_i_data11[1]), - .Q8(soc_a7ddrphy_dq_i_data11[0]) + .DDLY(main_a7ddrphy_dq_i_delayed11), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip111[7]), + .Q2(main_a7ddrphy_bitslip111[6]), + .Q3(main_a7ddrphy_bitslip111[5]), + .Q4(main_a7ddrphy_bitslip111[4]), + .Q5(main_a7ddrphy_bitslip111[3]), + .Q6(main_a7ddrphy_bitslip111[2]), + .Q7(main_a7ddrphy_bitslip111[1]), + .Q8(main_a7ddrphy_bitslip111[0]) ); IDELAYE2 #( @@ -16497,21 +19282,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_13 ( +) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed11) + .DATAOUT(main_a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_a7ddrphy_dq_o_nodelay11), - .T(soc_a7ddrphy_dq_t11), + .I(main_a7ddrphy_dq_o_nodelay11), + .T(main_a7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_a7ddrphy_dq_i_nodelay11) + .O(main_a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -16523,20 +19308,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .D1(main_a7ddrphy_bitslip120[0]), + .D2(main_a7ddrphy_bitslip120[1]), + .D3(main_a7ddrphy_bitslip120[2]), + .D4(main_a7ddrphy_bitslip120[3]), + .D5(main_a7ddrphy_bitslip120[4]), + .D6(main_a7ddrphy_bitslip120[5]), + .D7(main_a7ddrphy_bitslip120[6]), + .D8(main_a7ddrphy_bitslip120[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay12), - .TQ(soc_a7ddrphy_dq_t12) + .OQ(main_a7ddrphy_dq_o_nodelay12), + .TQ(main_a7ddrphy_dq_t12) ); ISERDESE2 #( @@ -16552,16 +19337,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed12), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data12[7]), - .Q2(soc_a7ddrphy_dq_i_data12[6]), - .Q3(soc_a7ddrphy_dq_i_data12[5]), - .Q4(soc_a7ddrphy_dq_i_data12[4]), - .Q5(soc_a7ddrphy_dq_i_data12[3]), - .Q6(soc_a7ddrphy_dq_i_data12[2]), - .Q7(soc_a7ddrphy_dq_i_data12[1]), - .Q8(soc_a7ddrphy_dq_i_data12[0]) + .DDLY(main_a7ddrphy_dq_i_delayed12), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip121[7]), + .Q2(main_a7ddrphy_bitslip121[6]), + .Q3(main_a7ddrphy_bitslip121[5]), + .Q4(main_a7ddrphy_bitslip121[4]), + .Q5(main_a7ddrphy_bitslip121[3]), + .Q6(main_a7ddrphy_bitslip121[2]), + .Q7(main_a7ddrphy_bitslip121[1]), + .Q8(main_a7ddrphy_bitslip121[0]) ); IDELAYE2 #( @@ -16573,21 +19358,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_14 ( +) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed12) + .DATAOUT(main_a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_a7ddrphy_dq_o_nodelay12), - .T(soc_a7ddrphy_dq_t12), + .I(main_a7ddrphy_dq_o_nodelay12), + .T(main_a7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_a7ddrphy_dq_i_nodelay12) + .O(main_a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -16599,20 +19384,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .D1(main_a7ddrphy_bitslip130[0]), + .D2(main_a7ddrphy_bitslip130[1]), + .D3(main_a7ddrphy_bitslip130[2]), + .D4(main_a7ddrphy_bitslip130[3]), + .D5(main_a7ddrphy_bitslip130[4]), + .D6(main_a7ddrphy_bitslip130[5]), + .D7(main_a7ddrphy_bitslip130[6]), + .D8(main_a7ddrphy_bitslip130[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay13), - .TQ(soc_a7ddrphy_dq_t13) + .OQ(main_a7ddrphy_dq_o_nodelay13), + .TQ(main_a7ddrphy_dq_t13) ); ISERDESE2 #( @@ -16628,16 +19413,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed13), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data13[7]), - .Q2(soc_a7ddrphy_dq_i_data13[6]), - .Q3(soc_a7ddrphy_dq_i_data13[5]), - .Q4(soc_a7ddrphy_dq_i_data13[4]), - .Q5(soc_a7ddrphy_dq_i_data13[3]), - .Q6(soc_a7ddrphy_dq_i_data13[2]), - .Q7(soc_a7ddrphy_dq_i_data13[1]), - .Q8(soc_a7ddrphy_dq_i_data13[0]) + .DDLY(main_a7ddrphy_dq_i_delayed13), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip131[7]), + .Q2(main_a7ddrphy_bitslip131[6]), + .Q3(main_a7ddrphy_bitslip131[5]), + .Q4(main_a7ddrphy_bitslip131[4]), + .Q5(main_a7ddrphy_bitslip131[3]), + .Q6(main_a7ddrphy_bitslip131[2]), + .Q7(main_a7ddrphy_bitslip131[1]), + .Q8(main_a7ddrphy_bitslip131[0]) ); IDELAYE2 #( @@ -16649,21 +19434,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_15 ( +) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed13) + .DATAOUT(main_a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_a7ddrphy_dq_o_nodelay13), - .T(soc_a7ddrphy_dq_t13), + .I(main_a7ddrphy_dq_o_nodelay13), + .T(main_a7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_a7ddrphy_dq_i_nodelay13) + .O(main_a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -16675,20 +19460,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .D1(main_a7ddrphy_bitslip140[0]), + .D2(main_a7ddrphy_bitslip140[1]), + .D3(main_a7ddrphy_bitslip140[2]), + .D4(main_a7ddrphy_bitslip140[3]), + .D5(main_a7ddrphy_bitslip140[4]), + .D6(main_a7ddrphy_bitslip140[5]), + .D7(main_a7ddrphy_bitslip140[6]), + .D8(main_a7ddrphy_bitslip140[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay14), - .TQ(soc_a7ddrphy_dq_t14) + .OQ(main_a7ddrphy_dq_o_nodelay14), + .TQ(main_a7ddrphy_dq_t14) ); ISERDESE2 #( @@ -16704,16 +19489,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed14), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data14[7]), - .Q2(soc_a7ddrphy_dq_i_data14[6]), - .Q3(soc_a7ddrphy_dq_i_data14[5]), - .Q4(soc_a7ddrphy_dq_i_data14[4]), - .Q5(soc_a7ddrphy_dq_i_data14[3]), - .Q6(soc_a7ddrphy_dq_i_data14[2]), - .Q7(soc_a7ddrphy_dq_i_data14[1]), - .Q8(soc_a7ddrphy_dq_i_data14[0]) + .DDLY(main_a7ddrphy_dq_i_delayed14), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip141[7]), + .Q2(main_a7ddrphy_bitslip141[6]), + .Q3(main_a7ddrphy_bitslip141[5]), + .Q4(main_a7ddrphy_bitslip141[4]), + .Q5(main_a7ddrphy_bitslip141[3]), + .Q6(main_a7ddrphy_bitslip141[2]), + .Q7(main_a7ddrphy_bitslip141[1]), + .Q8(main_a7ddrphy_bitslip141[0]) ); IDELAYE2 #( @@ -16725,21 +19510,21 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_16 ( +) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed14) + .DATAOUT(main_a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_a7ddrphy_dq_o_nodelay14), - .T(soc_a7ddrphy_dq_t14), + .I(main_a7ddrphy_dq_o_nodelay14), + .T(main_a7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_a7ddrphy_dq_i_nodelay14) + .O(main_a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -16751,20 +19536,20 @@ OSERDESE2 #( ) OSERDESE2_45 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .D1(main_a7ddrphy_bitslip150[0]), + .D2(main_a7ddrphy_bitslip150[1]), + .D3(main_a7ddrphy_bitslip150[2]), + .D4(main_a7ddrphy_bitslip150[3]), + .D5(main_a7ddrphy_bitslip150[4]), + .D6(main_a7ddrphy_bitslip150[5]), + .D7(main_a7ddrphy_bitslip150[6]), + .D8(main_a7ddrphy_bitslip150[7]), .OCE(1'd1), - .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay15), - .TQ(soc_a7ddrphy_dq_t15) + .OQ(main_a7ddrphy_dq_o_nodelay15), + .TQ(main_a7ddrphy_dq_t15) ); ISERDESE2 #( @@ -16780,16 +19565,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed15), - .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data15[7]), - .Q2(soc_a7ddrphy_dq_i_data15[6]), - .Q3(soc_a7ddrphy_dq_i_data15[5]), - .Q4(soc_a7ddrphy_dq_i_data15[4]), - .Q5(soc_a7ddrphy_dq_i_data15[3]), - .Q6(soc_a7ddrphy_dq_i_data15[2]), - .Q7(soc_a7ddrphy_dq_i_data15[1]), - .Q8(soc_a7ddrphy_dq_i_data15[0]) + .DDLY(main_a7ddrphy_dq_i_delayed15), + .RST((sys_rst | main_a7ddrphy_rst_storage)), + .Q1(main_a7ddrphy_bitslip151[7]), + .Q2(main_a7ddrphy_bitslip151[6]), + .Q3(main_a7ddrphy_bitslip151[5]), + .Q4(main_a7ddrphy_bitslip151[4]), + .Q5(main_a7ddrphy_bitslip151[3]), + .Q6(main_a7ddrphy_bitslip151[2]), + .Q7(main_a7ddrphy_bitslip151[1]), + .Q8(main_a7ddrphy_bitslip151[0]) ); IDELAYE2 #( @@ -16801,134 +19586,182 @@ IDELAYE2 #( .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") -) IDELAYE2_17 ( +) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed15) + .DATAOUT(main_a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_a7ddrphy_dq_o_nodelay15), - .T(soc_a7ddrphy_dq_t15), + .I(main_a7ddrphy_dq_o_nodelay15), + .T(main_a7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_a7ddrphy_dq_i_nodelay15) + .O(main_a7ddrphy_dq_i_nodelay15) ); reg [24:0] storage[0:15]; reg [24:0] memdat; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_1[0:15]; reg [24:0] memdat_1; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_2[0:15]; reg [24:0] memdat_2; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_3[0:15]; reg [24:0] memdat_3; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_4[0:15]; reg [24:0] memdat_4; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_5[0:15]; reg [24:0] memdat_5; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_6[0:15]; reg [24:0] memdat_6; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_7[0:15]; reg [24:0] memdat_7; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +FD FD( + .C(main_clkin), + .D(main_reset), + .Q(builder_reset0) +); + +FD FD_1( + .C(main_clkin), + .D(builder_reset0), + .Q(builder_reset1) +); + +FD FD_2( + .C(main_clkin), + .D(builder_reset1), + .Q(builder_reset2) +); + +FD FD_3( + .C(main_clkin), + .D(builder_reset2), + .Q(builder_reset3) +); + +FD FD_4( + .C(main_clkin), + .D(builder_reset3), + .Q(builder_reset4) +); + +FD FD_5( + .C(main_clkin), + .D(builder_reset4), + .Q(builder_reset5) +); + +FD FD_6( + .C(main_clkin), + .D(builder_reset5), + .Q(builder_reset6) +); + +FD FD_7( + .C(main_clkin), + .D(builder_reset6), + .Q(builder_reset7) +); PLLE2_ADV #( .CLKFBOUT_MULT(5'd16), @@ -16945,15 +19778,16 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb), - .CLKIN1(soc_clkin), - .RST(soc_reset), - .CLKFBOUT(vns_pll_fb), - .CLKOUT0(soc_clkout0), - .CLKOUT1(soc_clkout1), - .CLKOUT2(soc_clkout2), - .CLKOUT3(soc_clkout3), - .LOCKED(soc_locked) + .CLKFBIN(builder_pll_fb), + .CLKIN1(main_clkin), + .PWRDWN(main_power_down), + .RST(builder_reset7), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout0), + .CLKOUT1(main_clkout1), + .CLKOUT2(main_clkout2), + .CLKOUT3(main_clkout3), + .LOCKED(main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -16962,8 +19796,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16971,8 +19805,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(iodelay_rst) ); @@ -16982,8 +19816,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -16991,8 +19825,8 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), .Q(sys_rst) ); @@ -17002,8 +19836,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17011,9 +19845,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -17022,8 +19856,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -17031,9 +19865,9 @@ PLLE2_ADV #( ) FDPE_7 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) + .D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index d486310..aa94e4b 100644 --- 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-4bfffb24f9210060 +4bfffaf0f9210060 0100000000000000 f9c1ff7000001280 fa01ff80f9e1ff78 @@ -1378,7 +1482,7 @@ ebc1fff07c0803a6 4e800020ebe1fff8 e8010010ebc1fff0 7c0803a6ebe1fff8 -000000004e800020 +600000004e800020 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1397,6 +1501,7 @@ e8010010ebc1fff0 0000000000000020 54454e5245485445 0000000000000020 +000000000000000a 2020202020202020 203a4d4152422020 000a424b20646c25 @@ -1427,9 +1532,9 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -3830643432643338 +3133393063613937 0000000000000000 -0064623161656634 +0036643330323533 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1471,45 +1576,62 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -6f6e204d41524453 -207265646e752077 -6572617764726168 -6c6f72746e6f6320 -000000000000000a +6e69686374697753 +204d415244532067 +7774666f73206f74 +746e6f6320657261 +0000000a2e6c6f72 +6e69686374697753 +204d415244532067 +7764726168206f74 +746e6f6320657261 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-652061746164202d +6520617461642020 25203a73726f7272 00000a646c252f64 20747365746d654d 00000000000a4f4b 20747365746d654d -00000000000a4b4f +60000000000a4b4f +3736353433323130 +6665646362613938 +0000000000000000 +0000000000007830 0000000000000000 00000000000000ff 000000000000ffff @@ -1519,4 +1641,3 @@ e8010010ebc1fff0 0000ffffffffffff 00ffffffffffffff ffffffffffffffff -0000000000007830 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index 85d1ee1..e5617fa 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,7 +1,8 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:26 +// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:25 //-------------------------------------------------------------------------------- module litedram_core( + input wire sim_trace, input wire clk, output wire init_done, output wire init_error, @@ -31,1550 +32,1519 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -wire [31:0] litedramcore_dat_w; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -wire [31:0] litedramcore_wishbone_dat_r; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire por_clk; -reg int_rst = 1'd1; -wire [13:0] ddrphy_dfi_p0_address; -wire [2:0] ddrphy_dfi_p0_bank; -wire ddrphy_dfi_p0_cas_n; -wire ddrphy_dfi_p0_cs_n; -wire ddrphy_dfi_p0_ras_n; -wire ddrphy_dfi_p0_we_n; -wire ddrphy_dfi_p0_cke; -wire ddrphy_dfi_p0_odt; -wire ddrphy_dfi_p0_reset_n; -wire ddrphy_dfi_p0_act_n; -wire [31:0] ddrphy_dfi_p0_wrdata; -wire ddrphy_dfi_p0_wrdata_en; -wire [3:0] ddrphy_dfi_p0_wrdata_mask; -wire ddrphy_dfi_p0_rddata_en; -wire [31:0] ddrphy_dfi_p0_rddata; -wire ddrphy_dfi_p0_rddata_valid; -wire [13:0] ddrphy_dfi_p1_address; -wire [2:0] ddrphy_dfi_p1_bank; -wire ddrphy_dfi_p1_cas_n; -wire ddrphy_dfi_p1_cs_n; -wire ddrphy_dfi_p1_ras_n; -wire ddrphy_dfi_p1_we_n; -wire ddrphy_dfi_p1_cke; -wire ddrphy_dfi_p1_odt; -wire ddrphy_dfi_p1_reset_n; -wire ddrphy_dfi_p1_act_n; -wire [31:0] ddrphy_dfi_p1_wrdata; -wire ddrphy_dfi_p1_wrdata_en; -wire [3:0] ddrphy_dfi_p1_wrdata_mask; -wire ddrphy_dfi_p1_rddata_en; -wire [31:0] ddrphy_dfi_p1_rddata; -wire ddrphy_dfi_p1_rddata_valid; -wire [13:0] ddrphy_dfi_p2_address; -wire [2:0] ddrphy_dfi_p2_bank; -wire ddrphy_dfi_p2_cas_n; -wire ddrphy_dfi_p2_cs_n; -wire ddrphy_dfi_p2_ras_n; -wire ddrphy_dfi_p2_we_n; -wire ddrphy_dfi_p2_cke; -wire ddrphy_dfi_p2_odt; -wire ddrphy_dfi_p2_reset_n; -wire ddrphy_dfi_p2_act_n; -wire [31:0] ddrphy_dfi_p2_wrdata; -wire ddrphy_dfi_p2_wrdata_en; -wire [3:0] ddrphy_dfi_p2_wrdata_mask; -wire ddrphy_dfi_p2_rddata_en; -wire [31:0] ddrphy_dfi_p2_rddata; -wire ddrphy_dfi_p2_rddata_valid; -wire [13:0] ddrphy_dfi_p3_address; -wire [2:0] ddrphy_dfi_p3_bank; -wire ddrphy_dfi_p3_cas_n; -wire ddrphy_dfi_p3_cs_n; -wire ddrphy_dfi_p3_ras_n; -wire ddrphy_dfi_p3_we_n; -wire ddrphy_dfi_p3_cke; -wire ddrphy_dfi_p3_odt; -wire ddrphy_dfi_p3_reset_n; -wire ddrphy_dfi_p3_act_n; -wire [31:0] ddrphy_dfi_p3_wrdata; -wire ddrphy_dfi_p3_wrdata_en; -wire [3:0] ddrphy_dfi_p3_wrdata_mask; -wire ddrphy_dfi_p3_rddata_en; -wire [31:0] ddrphy_dfi_p3_rddata; -wire ddrphy_dfi_p3_rddata_valid; -reg ddrphy_dfiphasemodel0_activate = 1'd0; -reg ddrphy_dfiphasemodel0_precharge = 1'd0; -reg ddrphy_dfiphasemodel0_write = 1'd0; -reg ddrphy_dfiphasemodel0_read = 1'd0; -reg ddrphy_dfiphasemodel1_activate = 1'd0; -reg ddrphy_dfiphasemodel1_precharge = 1'd0; -reg ddrphy_dfiphasemodel1_write = 1'd0; -reg ddrphy_dfiphasemodel1_read = 1'd0; -reg ddrphy_dfiphasemodel2_activate = 1'd0; -reg ddrphy_dfiphasemodel2_precharge = 1'd0; -reg ddrphy_dfiphasemodel2_write = 1'd0; -reg ddrphy_dfiphasemodel2_read = 1'd0; -reg ddrphy_dfiphasemodel3_activate = 1'd0; -reg ddrphy_dfiphasemodel3_precharge = 1'd0; -reg ddrphy_dfiphasemodel3_write = 1'd0; -reg ddrphy_dfiphasemodel3_read = 1'd0; -reg ddrphy_bankmodel0_activate = 1'd0; -reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0; -reg ddrphy_bankmodel0_precharge = 1'd0; -wire ddrphy_bankmodel0_write; -wire [9:0] ddrphy_bankmodel0_write_col; -wire [127:0] ddrphy_bankmodel0_write_data; -wire [15:0] ddrphy_bankmodel0_write_mask; -reg ddrphy_bankmodel0_read = 1'd0; -reg [9:0] ddrphy_bankmodel0_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel0_read_data = 128'd0; -reg ddrphy_bankmodel0_active = 1'd0; -reg [13:0] ddrphy_bankmodel0_row = 14'd0; -reg [20:0] ddrphy_bankmodel0_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel0_write_port_dat_r; -reg [15:0] ddrphy_bankmodel0_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel0_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel0_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel0_read_port_dat_r; -wire [20:0] ddrphy_bankmodel0_wraddr; -wire [20:0] ddrphy_bankmodel0_rdaddr; -reg ddrphy_bankmodel1_activate = 1'd0; -reg [13:0] ddrphy_bankmodel1_activate_row = 14'd0; -reg ddrphy_bankmodel1_precharge = 1'd0; -wire ddrphy_bankmodel1_write; -wire [9:0] ddrphy_bankmodel1_write_col; -wire [127:0] ddrphy_bankmodel1_write_data; -wire [15:0] ddrphy_bankmodel1_write_mask; -reg ddrphy_bankmodel1_read = 1'd0; -reg [9:0] ddrphy_bankmodel1_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel1_read_data = 128'd0; -reg ddrphy_bankmodel1_active = 1'd0; -reg [13:0] ddrphy_bankmodel1_row = 14'd0; -reg [20:0] ddrphy_bankmodel1_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel1_write_port_dat_r; -reg [15:0] ddrphy_bankmodel1_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel1_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel1_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel1_read_port_dat_r; -wire [20:0] ddrphy_bankmodel1_wraddr; -wire [20:0] ddrphy_bankmodel1_rdaddr; -reg ddrphy_bankmodel2_activate = 1'd0; -reg [13:0] ddrphy_bankmodel2_activate_row = 14'd0; -reg ddrphy_bankmodel2_precharge = 1'd0; -wire ddrphy_bankmodel2_write; -wire [9:0] ddrphy_bankmodel2_write_col; -wire [127:0] ddrphy_bankmodel2_write_data; -wire [15:0] ddrphy_bankmodel2_write_mask; -reg ddrphy_bankmodel2_read = 1'd0; -reg [9:0] ddrphy_bankmodel2_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel2_read_data = 128'd0; -reg ddrphy_bankmodel2_active = 1'd0; -reg [13:0] ddrphy_bankmodel2_row = 14'd0; -reg [20:0] ddrphy_bankmodel2_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel2_write_port_dat_r; -reg [15:0] ddrphy_bankmodel2_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel2_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel2_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel2_read_port_dat_r; -wire [20:0] ddrphy_bankmodel2_wraddr; -wire [20:0] ddrphy_bankmodel2_rdaddr; -reg ddrphy_bankmodel3_activate = 1'd0; -reg [13:0] ddrphy_bankmodel3_activate_row = 14'd0; -reg ddrphy_bankmodel3_precharge = 1'd0; -wire ddrphy_bankmodel3_write; -wire [9:0] ddrphy_bankmodel3_write_col; -wire [127:0] ddrphy_bankmodel3_write_data; -wire [15:0] ddrphy_bankmodel3_write_mask; -reg ddrphy_bankmodel3_read = 1'd0; -reg [9:0] ddrphy_bankmodel3_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel3_read_data = 128'd0; -reg ddrphy_bankmodel3_active = 1'd0; -reg [13:0] ddrphy_bankmodel3_row = 14'd0; -reg [20:0] ddrphy_bankmodel3_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel3_write_port_dat_r; -reg [15:0] ddrphy_bankmodel3_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel3_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel3_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel3_read_port_dat_r; -wire [20:0] ddrphy_bankmodel3_wraddr; -wire [20:0] ddrphy_bankmodel3_rdaddr; -reg ddrphy_bankmodel4_activate = 1'd0; -reg [13:0] ddrphy_bankmodel4_activate_row = 14'd0; -reg ddrphy_bankmodel4_precharge = 1'd0; -wire ddrphy_bankmodel4_write; -wire [9:0] ddrphy_bankmodel4_write_col; -wire [127:0] ddrphy_bankmodel4_write_data; -wire [15:0] ddrphy_bankmodel4_write_mask; -reg ddrphy_bankmodel4_read = 1'd0; -reg [9:0] ddrphy_bankmodel4_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel4_read_data = 128'd0; -reg ddrphy_bankmodel4_active = 1'd0; -reg [13:0] ddrphy_bankmodel4_row = 14'd0; -reg [20:0] ddrphy_bankmodel4_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel4_write_port_dat_r; -reg [15:0] ddrphy_bankmodel4_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel4_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel4_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel4_read_port_dat_r; -wire [20:0] ddrphy_bankmodel4_wraddr; -wire [20:0] ddrphy_bankmodel4_rdaddr; -reg ddrphy_bankmodel5_activate = 1'd0; -reg [13:0] ddrphy_bankmodel5_activate_row = 14'd0; -reg ddrphy_bankmodel5_precharge = 1'd0; -wire ddrphy_bankmodel5_write; -wire [9:0] ddrphy_bankmodel5_write_col; -wire [127:0] ddrphy_bankmodel5_write_data; -wire [15:0] ddrphy_bankmodel5_write_mask; -reg ddrphy_bankmodel5_read = 1'd0; -reg [9:0] ddrphy_bankmodel5_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel5_read_data = 128'd0; -reg ddrphy_bankmodel5_active = 1'd0; -reg [13:0] ddrphy_bankmodel5_row = 14'd0; -reg [20:0] ddrphy_bankmodel5_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel5_write_port_dat_r; -reg [15:0] ddrphy_bankmodel5_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel5_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel5_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel5_read_port_dat_r; -wire [20:0] ddrphy_bankmodel5_wraddr; -wire [20:0] ddrphy_bankmodel5_rdaddr; -reg ddrphy_bankmodel6_activate = 1'd0; -reg [13:0] ddrphy_bankmodel6_activate_row = 14'd0; -reg ddrphy_bankmodel6_precharge = 1'd0; -wire ddrphy_bankmodel6_write; -wire [9:0] ddrphy_bankmodel6_write_col; -wire [127:0] ddrphy_bankmodel6_write_data; -wire [15:0] ddrphy_bankmodel6_write_mask; -reg ddrphy_bankmodel6_read = 1'd0; -reg [9:0] ddrphy_bankmodel6_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel6_read_data = 128'd0; -reg ddrphy_bankmodel6_active = 1'd0; -reg [13:0] ddrphy_bankmodel6_row = 14'd0; -reg [20:0] ddrphy_bankmodel6_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel6_write_port_dat_r; -reg [15:0] ddrphy_bankmodel6_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel6_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel6_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel6_read_port_dat_r; -wire [20:0] ddrphy_bankmodel6_wraddr; -wire [20:0] ddrphy_bankmodel6_rdaddr; -reg ddrphy_bankmodel7_activate = 1'd0; -reg [13:0] ddrphy_bankmodel7_activate_row = 14'd0; -reg ddrphy_bankmodel7_precharge = 1'd0; -wire ddrphy_bankmodel7_write; -wire [9:0] ddrphy_bankmodel7_write_col; -wire [127:0] ddrphy_bankmodel7_write_data; -wire [15:0] ddrphy_bankmodel7_write_mask; -reg ddrphy_bankmodel7_read = 1'd0; -reg [9:0] ddrphy_bankmodel7_read_col = 10'd0; -reg [127:0] ddrphy_bankmodel7_read_data = 128'd0; -reg ddrphy_bankmodel7_active = 1'd0; -reg [13:0] ddrphy_bankmodel7_row = 14'd0; -reg [20:0] ddrphy_bankmodel7_write_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel7_write_port_dat_r; -reg [15:0] ddrphy_bankmodel7_write_port_we = 16'd0; -reg [127:0] ddrphy_bankmodel7_write_port_dat_w = 128'd0; -reg [20:0] ddrphy_bankmodel7_read_port_adr = 21'd0; -wire [127:0] ddrphy_bankmodel7_read_port_dat_r; -wire [20:0] ddrphy_bankmodel7_wraddr; -wire [20:0] ddrphy_bankmodel7_rdaddr; -reg [3:0] ddrphy_activates0 = 4'd0; -reg [3:0] ddrphy_precharges0 = 4'd0; -reg ddrphy_bank_write0 = 1'd0; -reg [9:0] ddrphy_bank_write_col0 = 10'd0; -reg [3:0] ddrphy_writes0 = 4'd0; -reg ddrphy_new_bank_write0 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col0 = 10'd0; -reg ddrphy_new_bank_write1 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col1 = 10'd0; -reg [3:0] ddrphy_reads0 = 4'd0; -reg [3:0] ddrphy_activates1 = 4'd0; -reg [3:0] ddrphy_precharges1 = 4'd0; -reg ddrphy_bank_write1 = 1'd0; -reg [9:0] ddrphy_bank_write_col1 = 10'd0; -reg [3:0] ddrphy_writes1 = 4'd0; -reg ddrphy_new_bank_write2 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col2 = 10'd0; -reg ddrphy_new_bank_write3 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col3 = 10'd0; -reg [3:0] ddrphy_reads1 = 4'd0; -reg [3:0] ddrphy_activates2 = 4'd0; -reg [3:0] ddrphy_precharges2 = 4'd0; -reg ddrphy_bank_write2 = 1'd0; -reg [9:0] ddrphy_bank_write_col2 = 10'd0; -reg [3:0] ddrphy_writes2 = 4'd0; -reg ddrphy_new_bank_write4 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col4 = 10'd0; -reg ddrphy_new_bank_write5 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col5 = 10'd0; -reg [3:0] ddrphy_reads2 = 4'd0; -reg [3:0] ddrphy_activates3 = 4'd0; -reg [3:0] ddrphy_precharges3 = 4'd0; -reg ddrphy_bank_write3 = 1'd0; -reg [9:0] ddrphy_bank_write_col3 = 10'd0; -reg [3:0] ddrphy_writes3 = 4'd0; -reg ddrphy_new_bank_write6 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col6 = 10'd0; -reg ddrphy_new_bank_write7 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col7 = 10'd0; -reg [3:0] ddrphy_reads3 = 4'd0; -reg [3:0] ddrphy_activates4 = 4'd0; -reg [3:0] ddrphy_precharges4 = 4'd0; -reg ddrphy_bank_write4 = 1'd0; -reg [9:0] ddrphy_bank_write_col4 = 10'd0; -reg [3:0] ddrphy_writes4 = 4'd0; -reg ddrphy_new_bank_write8 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col8 = 10'd0; -reg ddrphy_new_bank_write9 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col9 = 10'd0; -reg [3:0] ddrphy_reads4 = 4'd0; -reg [3:0] ddrphy_activates5 = 4'd0; -reg [3:0] ddrphy_precharges5 = 4'd0; -reg ddrphy_bank_write5 = 1'd0; -reg [9:0] ddrphy_bank_write_col5 = 10'd0; -reg [3:0] ddrphy_writes5 = 4'd0; -reg ddrphy_new_bank_write10 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col10 = 10'd0; -reg ddrphy_new_bank_write11 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col11 = 10'd0; -reg [3:0] ddrphy_reads5 = 4'd0; -reg [3:0] ddrphy_activates6 = 4'd0; -reg [3:0] ddrphy_precharges6 = 4'd0; -reg ddrphy_bank_write6 = 1'd0; -reg [9:0] ddrphy_bank_write_col6 = 10'd0; -reg [3:0] ddrphy_writes6 = 4'd0; -reg ddrphy_new_bank_write12 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col12 = 10'd0; -reg ddrphy_new_bank_write13 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col13 = 10'd0; -reg [3:0] ddrphy_reads6 = 4'd0; -reg [3:0] ddrphy_activates7 = 4'd0; -reg [3:0] ddrphy_precharges7 = 4'd0; -reg ddrphy_bank_write7 = 1'd0; -reg [9:0] ddrphy_bank_write_col7 = 10'd0; -reg [3:0] ddrphy_writes7 = 4'd0; -reg ddrphy_new_bank_write14 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col14 = 10'd0; -reg ddrphy_new_bank_write15 = 1'd0; -reg [9:0] ddrphy_new_bank_write_col15 = 10'd0; -reg [3:0] ddrphy_reads7 = 4'd0; -wire ddrphy_banks_read; -wire [127:0] ddrphy_banks_read_data; -reg ddrphy_new_banks_read0 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data0 = 128'd0; -reg ddrphy_new_banks_read1 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data1 = 128'd0; -reg ddrphy_new_banks_read2 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data2 = 128'd0; -reg ddrphy_new_banks_read3 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data3 = 128'd0; -reg ddrphy_new_banks_read4 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data4 = 128'd0; -reg ddrphy_new_banks_read5 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data5 = 128'd0; -reg ddrphy_new_banks_read6 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data6 = 128'd0; -reg ddrphy_new_banks_read7 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data7 = 128'd0; -reg ddrphy_new_banks_read8 = 1'd0; -reg [127:0] ddrphy_new_banks_read_data8 = 128'd0; -wire [13:0] litedramcore_inti_p0_address; -wire [2:0] litedramcore_inti_p0_bank; -reg litedramcore_inti_p0_cas_n = 1'd1; -reg litedramcore_inti_p0_cs_n = 1'd1; -reg litedramcore_inti_p0_ras_n = 1'd1; -reg litedramcore_inti_p0_we_n = 1'd1; -wire litedramcore_inti_p0_cke; -wire litedramcore_inti_p0_odt; -wire litedramcore_inti_p0_reset_n; -reg litedramcore_inti_p0_act_n = 1'd1; -wire [31:0] litedramcore_inti_p0_wrdata; -wire litedramcore_inti_p0_wrdata_en; -wire [3:0] litedramcore_inti_p0_wrdata_mask; -wire litedramcore_inti_p0_rddata_en; -reg [31:0] litedramcore_inti_p0_rddata = 32'd0; -reg litedramcore_inti_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_inti_p1_address; -wire [2:0] litedramcore_inti_p1_bank; -reg litedramcore_inti_p1_cas_n = 1'd1; -reg litedramcore_inti_p1_cs_n = 1'd1; -reg litedramcore_inti_p1_ras_n = 1'd1; -reg litedramcore_inti_p1_we_n = 1'd1; -wire litedramcore_inti_p1_cke; -wire litedramcore_inti_p1_odt; -wire litedramcore_inti_p1_reset_n; -reg litedramcore_inti_p1_act_n = 1'd1; -wire [31:0] litedramcore_inti_p1_wrdata; -wire litedramcore_inti_p1_wrdata_en; -wire [3:0] litedramcore_inti_p1_wrdata_mask; -wire litedramcore_inti_p1_rddata_en; -reg [31:0] litedramcore_inti_p1_rddata = 32'd0; -reg litedramcore_inti_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_inti_p2_address; -wire [2:0] litedramcore_inti_p2_bank; -reg litedramcore_inti_p2_cas_n = 1'd1; -reg litedramcore_inti_p2_cs_n = 1'd1; -reg litedramcore_inti_p2_ras_n = 1'd1; -reg litedramcore_inti_p2_we_n = 1'd1; -wire litedramcore_inti_p2_cke; -wire litedramcore_inti_p2_odt; -wire litedramcore_inti_p2_reset_n; -reg litedramcore_inti_p2_act_n = 1'd1; -wire [31:0] litedramcore_inti_p2_wrdata; -wire litedramcore_inti_p2_wrdata_en; -wire [3:0] litedramcore_inti_p2_wrdata_mask; -wire litedramcore_inti_p2_rddata_en; -reg [31:0] litedramcore_inti_p2_rddata = 32'd0; -reg litedramcore_inti_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_inti_p3_address; -wire [2:0] litedramcore_inti_p3_bank; -reg litedramcore_inti_p3_cas_n = 1'd1; -reg litedramcore_inti_p3_cs_n = 1'd1; -reg litedramcore_inti_p3_ras_n = 1'd1; -reg litedramcore_inti_p3_we_n = 1'd1; -wire litedramcore_inti_p3_cke; -wire litedramcore_inti_p3_odt; -wire litedramcore_inti_p3_reset_n; -reg litedramcore_inti_p3_act_n = 1'd1; -wire [31:0] litedramcore_inti_p3_wrdata; -wire litedramcore_inti_p3_wrdata_en; -wire [3:0] litedramcore_inti_p3_wrdata_mask; -wire litedramcore_inti_p3_rddata_en; -reg [31:0] litedramcore_inti_p3_rddata = 32'd0; -reg litedramcore_inti_p3_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_master_p0_address = 14'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [13:0] litedramcore_master_p1_address = 14'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [13:0] litedramcore_master_p2_address = 14'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [13:0] litedramcore_master_p3_address = 14'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_re; -wire litedramcore_phaseinjector0_command_issue_r; -wire litedramcore_phaseinjector0_command_issue_we; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_status = 32'd0; -wire litedramcore_phaseinjector0_we; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_re; -wire litedramcore_phaseinjector1_command_issue_r; -wire litedramcore_phaseinjector1_command_issue_we; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_status = 32'd0; -wire litedramcore_phaseinjector1_we; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_re; -wire litedramcore_phaseinjector2_command_issue_r; -wire litedramcore_phaseinjector2_command_issue_we; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_status = 32'd0; -wire litedramcore_phaseinjector2_we; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_re; -wire litedramcore_phaseinjector3_command_issue_r; -wire litedramcore_phaseinjector3_command_issue_we; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_status = 32'd0; -wire litedramcore_phaseinjector3_we; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [20:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [20:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [20:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [20:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [20:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [20:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [20:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [20:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [13:0] litedramcore_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [13:0] litedramcore_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [13:0] litedramcore_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [13:0] litedramcore_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [13:0] litedramcore_cmd_payload_a = 14'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [20:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine0_row = 14'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [20:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine1_row = 14'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [20:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine2_row = 14'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [20:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine3_row = 14'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [20:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine4_row = 14'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [20:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine5_row = 14'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [20:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine6_row = 14'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [20:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine7_row = 14'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* no_retiming = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [13:0] litedramcore_nop_a = 14'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* no_retiming = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* no_retiming = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* no_retiming = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* no_retiming = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [23:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg state = 1'd0; -reg next_state = 1'd0; +reg soc_int_rst = 1'd1; +wire [13:0] soc_ddrphy_dfi_p0_address; +wire [2:0] soc_ddrphy_dfi_p0_bank; +wire soc_ddrphy_dfi_p0_cas_n; +wire soc_ddrphy_dfi_p0_cs_n; +wire soc_ddrphy_dfi_p0_ras_n; +wire soc_ddrphy_dfi_p0_we_n; +wire soc_ddrphy_dfi_p0_cke; +wire soc_ddrphy_dfi_p0_odt; +wire soc_ddrphy_dfi_p0_reset_n; +wire soc_ddrphy_dfi_p0_act_n; +wire [31:0] soc_ddrphy_dfi_p0_wrdata; +wire soc_ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; +wire soc_ddrphy_dfi_p0_rddata_en; +wire [31:0] soc_ddrphy_dfi_p0_rddata; +wire soc_ddrphy_dfi_p0_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p1_address; +wire [2:0] soc_ddrphy_dfi_p1_bank; +wire soc_ddrphy_dfi_p1_cas_n; +wire soc_ddrphy_dfi_p1_cs_n; +wire soc_ddrphy_dfi_p1_ras_n; +wire soc_ddrphy_dfi_p1_we_n; +wire soc_ddrphy_dfi_p1_cke; +wire soc_ddrphy_dfi_p1_odt; +wire soc_ddrphy_dfi_p1_reset_n; +wire soc_ddrphy_dfi_p1_act_n; +wire [31:0] soc_ddrphy_dfi_p1_wrdata; +wire soc_ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; +wire soc_ddrphy_dfi_p1_rddata_en; +wire [31:0] soc_ddrphy_dfi_p1_rddata; +wire soc_ddrphy_dfi_p1_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p2_address; +wire [2:0] soc_ddrphy_dfi_p2_bank; +wire soc_ddrphy_dfi_p2_cas_n; +wire soc_ddrphy_dfi_p2_cs_n; +wire soc_ddrphy_dfi_p2_ras_n; +wire soc_ddrphy_dfi_p2_we_n; +wire soc_ddrphy_dfi_p2_cke; +wire soc_ddrphy_dfi_p2_odt; +wire soc_ddrphy_dfi_p2_reset_n; +wire soc_ddrphy_dfi_p2_act_n; +wire [31:0] soc_ddrphy_dfi_p2_wrdata; +wire soc_ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; +wire soc_ddrphy_dfi_p2_rddata_en; +wire [31:0] soc_ddrphy_dfi_p2_rddata; +wire soc_ddrphy_dfi_p2_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p3_address; +wire [2:0] soc_ddrphy_dfi_p3_bank; +wire soc_ddrphy_dfi_p3_cas_n; +wire soc_ddrphy_dfi_p3_cs_n; +wire soc_ddrphy_dfi_p3_ras_n; +wire soc_ddrphy_dfi_p3_we_n; +wire soc_ddrphy_dfi_p3_cke; +wire soc_ddrphy_dfi_p3_odt; +wire soc_ddrphy_dfi_p3_reset_n; +wire soc_ddrphy_dfi_p3_act_n; +wire [31:0] soc_ddrphy_dfi_p3_wrdata; +wire soc_ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; +wire soc_ddrphy_dfi_p3_rddata_en; +wire [31:0] soc_ddrphy_dfi_p3_rddata; +wire soc_ddrphy_dfi_p3_rddata_valid; +reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_write = 1'd0; +reg soc_ddrphy_dfiphasemodel0_read = 1'd0; +reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel1_write = 1'd0; +reg soc_ddrphy_dfiphasemodel1_read = 1'd0; +reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel2_write = 1'd0; +reg soc_ddrphy_dfiphasemodel2_read = 1'd0; +reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel3_write = 1'd0; +reg soc_ddrphy_dfiphasemodel3_read = 1'd0; +reg soc_ddrphy_bankmodel0_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; +reg soc_ddrphy_bankmodel0_precharge = 1'd0; +wire soc_ddrphy_bankmodel0_write; +wire [9:0] soc_ddrphy_bankmodel0_write_col; +wire [127:0] soc_ddrphy_bankmodel0_write_data; +wire [15:0] soc_ddrphy_bankmodel0_write_mask; +reg soc_ddrphy_bankmodel0_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; +reg soc_ddrphy_bankmodel0_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel0_wraddr; +wire [20:0] soc_ddrphy_bankmodel0_rdaddr; +reg soc_ddrphy_bankmodel1_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; +reg soc_ddrphy_bankmodel1_precharge = 1'd0; +wire soc_ddrphy_bankmodel1_write; +wire [9:0] soc_ddrphy_bankmodel1_write_col; +wire [127:0] soc_ddrphy_bankmodel1_write_data; +wire [15:0] soc_ddrphy_bankmodel1_write_mask; +reg soc_ddrphy_bankmodel1_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; +reg soc_ddrphy_bankmodel1_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel1_wraddr; +wire [20:0] soc_ddrphy_bankmodel1_rdaddr; +reg soc_ddrphy_bankmodel2_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; +reg soc_ddrphy_bankmodel2_precharge = 1'd0; +wire soc_ddrphy_bankmodel2_write; +wire [9:0] soc_ddrphy_bankmodel2_write_col; +wire [127:0] soc_ddrphy_bankmodel2_write_data; +wire [15:0] soc_ddrphy_bankmodel2_write_mask; +reg soc_ddrphy_bankmodel2_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; +reg soc_ddrphy_bankmodel2_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel2_wraddr; +wire [20:0] soc_ddrphy_bankmodel2_rdaddr; +reg soc_ddrphy_bankmodel3_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; +reg soc_ddrphy_bankmodel3_precharge = 1'd0; +wire soc_ddrphy_bankmodel3_write; +wire [9:0] soc_ddrphy_bankmodel3_write_col; +wire [127:0] soc_ddrphy_bankmodel3_write_data; +wire [15:0] soc_ddrphy_bankmodel3_write_mask; +reg soc_ddrphy_bankmodel3_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; +reg soc_ddrphy_bankmodel3_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel3_wraddr; +wire [20:0] soc_ddrphy_bankmodel3_rdaddr; +reg soc_ddrphy_bankmodel4_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; +reg soc_ddrphy_bankmodel4_precharge = 1'd0; +wire soc_ddrphy_bankmodel4_write; +wire [9:0] soc_ddrphy_bankmodel4_write_col; +wire [127:0] soc_ddrphy_bankmodel4_write_data; +wire [15:0] soc_ddrphy_bankmodel4_write_mask; +reg soc_ddrphy_bankmodel4_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; +reg soc_ddrphy_bankmodel4_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel4_wraddr; +wire [20:0] soc_ddrphy_bankmodel4_rdaddr; +reg soc_ddrphy_bankmodel5_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; +reg soc_ddrphy_bankmodel5_precharge = 1'd0; +wire soc_ddrphy_bankmodel5_write; +wire [9:0] soc_ddrphy_bankmodel5_write_col; +wire [127:0] soc_ddrphy_bankmodel5_write_data; +wire [15:0] soc_ddrphy_bankmodel5_write_mask; +reg soc_ddrphy_bankmodel5_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; +reg soc_ddrphy_bankmodel5_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel5_wraddr; +wire [20:0] soc_ddrphy_bankmodel5_rdaddr; +reg soc_ddrphy_bankmodel6_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; +reg soc_ddrphy_bankmodel6_precharge = 1'd0; +wire soc_ddrphy_bankmodel6_write; +wire [9:0] soc_ddrphy_bankmodel6_write_col; +wire [127:0] soc_ddrphy_bankmodel6_write_data; +wire [15:0] soc_ddrphy_bankmodel6_write_mask; +reg soc_ddrphy_bankmodel6_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; +reg soc_ddrphy_bankmodel6_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel6_wraddr; +wire [20:0] soc_ddrphy_bankmodel6_rdaddr; +reg soc_ddrphy_bankmodel7_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; +reg soc_ddrphy_bankmodel7_precharge = 1'd0; +wire soc_ddrphy_bankmodel7_write; +wire [9:0] soc_ddrphy_bankmodel7_write_col; +wire [127:0] soc_ddrphy_bankmodel7_write_data; +wire [15:0] soc_ddrphy_bankmodel7_write_mask; +reg soc_ddrphy_bankmodel7_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; +reg soc_ddrphy_bankmodel7_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel7_wraddr; +wire [20:0] soc_ddrphy_bankmodel7_rdaddr; +reg [3:0] soc_ddrphy_activates0 = 4'd0; +reg [3:0] soc_ddrphy_precharges0 = 4'd0; +reg soc_ddrphy_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_writes0 = 4'd0; +reg soc_ddrphy_new_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_reads0 = 4'd0; +reg [3:0] soc_ddrphy_activates1 = 4'd0; +reg [3:0] soc_ddrphy_precharges1 = 4'd0; +reg soc_ddrphy_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_writes1 = 4'd0; +reg soc_ddrphy_new_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_reads1 = 4'd0; +reg [3:0] soc_ddrphy_activates2 = 4'd0; +reg [3:0] soc_ddrphy_precharges2 = 4'd0; +reg soc_ddrphy_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_writes2 = 4'd0; +reg soc_ddrphy_new_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_reads2 = 4'd0; +reg [3:0] soc_ddrphy_activates3 = 4'd0; +reg [3:0] soc_ddrphy_precharges3 = 4'd0; +reg soc_ddrphy_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_writes3 = 4'd0; +reg soc_ddrphy_new_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_reads3 = 4'd0; +reg [3:0] soc_ddrphy_activates4 = 4'd0; +reg [3:0] soc_ddrphy_precharges4 = 4'd0; +reg soc_ddrphy_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_writes4 = 4'd0; +reg soc_ddrphy_new_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_reads4 = 4'd0; +reg [3:0] soc_ddrphy_activates5 = 4'd0; +reg [3:0] soc_ddrphy_precharges5 = 4'd0; +reg soc_ddrphy_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_writes5 = 4'd0; +reg soc_ddrphy_new_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_reads5 = 4'd0; +reg [3:0] soc_ddrphy_activates6 = 4'd0; +reg [3:0] soc_ddrphy_precharges6 = 4'd0; +reg soc_ddrphy_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_writes6 = 4'd0; +reg soc_ddrphy_new_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_reads6 = 4'd0; +reg [3:0] soc_ddrphy_activates7 = 4'd0; +reg [3:0] soc_ddrphy_precharges7 = 4'd0; +reg soc_ddrphy_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_writes7 = 4'd0; +reg soc_ddrphy_new_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_reads7 = 4'd0; +wire soc_ddrphy_banks_read; +wire [127:0] soc_ddrphy_banks_read_data; +reg soc_ddrphy_new_banks_read0 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; +reg soc_ddrphy_new_banks_read1 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; +reg soc_ddrphy_new_banks_read2 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; +reg soc_ddrphy_new_banks_read3 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; +reg soc_ddrphy_new_banks_read4 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; +reg soc_ddrphy_new_banks_read5 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; +reg soc_ddrphy_new_banks_read6 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; +reg soc_ddrphy_new_banks_read7 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; +wire [13:0] soc_litedramcore_inti_p0_address; +wire [2:0] soc_litedramcore_inti_p0_bank; +reg soc_litedramcore_inti_p0_cas_n = 1'd1; +reg soc_litedramcore_inti_p0_cs_n = 1'd1; +reg soc_litedramcore_inti_p0_ras_n = 1'd1; +reg soc_litedramcore_inti_p0_we_n = 1'd1; +wire soc_litedramcore_inti_p0_cke; +wire soc_litedramcore_inti_p0_odt; +wire soc_litedramcore_inti_p0_reset_n; +reg soc_litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p0_wrdata; +wire soc_litedramcore_inti_p0_wrdata_en; +wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; +wire soc_litedramcore_inti_p0_rddata_en; +reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; +reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_inti_p1_address; +wire [2:0] soc_litedramcore_inti_p1_bank; +reg soc_litedramcore_inti_p1_cas_n = 1'd1; +reg soc_litedramcore_inti_p1_cs_n = 1'd1; +reg soc_litedramcore_inti_p1_ras_n = 1'd1; +reg soc_litedramcore_inti_p1_we_n = 1'd1; +wire soc_litedramcore_inti_p1_cke; +wire soc_litedramcore_inti_p1_odt; +wire soc_litedramcore_inti_p1_reset_n; +reg soc_litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p1_wrdata; +wire soc_litedramcore_inti_p1_wrdata_en; +wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; +wire soc_litedramcore_inti_p1_rddata_en; +reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; +reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_inti_p2_address; +wire [2:0] soc_litedramcore_inti_p2_bank; +reg soc_litedramcore_inti_p2_cas_n = 1'd1; +reg soc_litedramcore_inti_p2_cs_n = 1'd1; +reg soc_litedramcore_inti_p2_ras_n = 1'd1; +reg soc_litedramcore_inti_p2_we_n = 1'd1; +wire soc_litedramcore_inti_p2_cke; +wire soc_litedramcore_inti_p2_odt; +wire soc_litedramcore_inti_p2_reset_n; +reg soc_litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p2_wrdata; +wire soc_litedramcore_inti_p2_wrdata_en; +wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; +wire soc_litedramcore_inti_p2_rddata_en; +reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; +reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_inti_p3_address; +wire [2:0] soc_litedramcore_inti_p3_bank; +reg soc_litedramcore_inti_p3_cas_n = 1'd1; +reg soc_litedramcore_inti_p3_cs_n = 1'd1; +reg soc_litedramcore_inti_p3_ras_n = 1'd1; +reg soc_litedramcore_inti_p3_we_n = 1'd1; +wire soc_litedramcore_inti_p3_cke; +wire soc_litedramcore_inti_p3_odt; +wire soc_litedramcore_inti_p3_reset_n; +reg soc_litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p3_wrdata; +wire soc_litedramcore_inti_p3_wrdata_en; +wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; +wire soc_litedramcore_inti_p3_rddata_en; +reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; +reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_ras_n; +wire soc_litedramcore_slave_p0_we_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_act_n; +wire [31:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p0_rddata_en; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_ras_n; +wire soc_litedramcore_slave_p1_we_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_act_n; +wire [31:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p1_rddata_en; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_ras_n; +wire soc_litedramcore_slave_p2_we_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_act_n; +wire [31:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p2_rddata_en; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_ras_n; +wire soc_litedramcore_slave_p3_we_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_act_n; +wire [31:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; +wire soc_litedramcore_slave_p3_rddata_en; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_master_p0_address = 14'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p0_rddata; +wire soc_litedramcore_master_p0_rddata_valid; +reg [13:0] soc_litedramcore_master_p1_address = 14'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p1_rddata; +wire soc_litedramcore_master_p1_rddata_valid; +reg [13:0] soc_litedramcore_master_p2_address = 14'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p2_rddata; +wire soc_litedramcore_master_p2_rddata_valid; +reg [13:0] soc_litedramcore_master_p3_address = 14'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p3_rddata; +wire soc_litedramcore_master_p3_rddata_valid; +wire soc_litedramcore_sel; +wire soc_litedramcore_cke; +wire soc_litedramcore_odt; +wire soc_litedramcore_reset_n; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector0_command_issue_r; +reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector0_rddata_we; +reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector1_command_issue_r; +reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector1_rddata_we; +reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector2_command_issue_r; +reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector2_rddata_we; +reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector3_command_issue_r; +reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector3_rddata_we; +reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_we; +wire [20:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_we; +wire [20:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_we; +wire [20:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_we; +wire [20:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_we; +wire [20:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_we; +wire [20:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_we; +wire [20:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_we; +wire [20:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_rdata_valid; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] soc_litedramcore_interface_rdata; +reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +wire soc_litedramcore_dfi_p0_odt; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p0_rddata; +wire soc_litedramcore_dfi_p0_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +wire soc_litedramcore_dfi_p1_odt; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p1_rddata; +wire soc_litedramcore_dfi_p1_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +wire soc_litedramcore_dfi_p2_odt; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p2_rddata; +wire soc_litedramcore_dfi_p2_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +wire soc_litedramcore_dfi_p3_odt; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p3_rddata; +wire soc_litedramcore_dfi_p3_rddata_valid; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_last = 1'd0; +reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +wire soc_litedramcore_timer_wait; +wire soc_litedramcore_timer_done0; +wire [9:0] soc_litedramcore_timer_count0; +wire soc_litedramcore_timer_done1; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +reg soc_litedramcore_postponer_count = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_done0; +wire soc_litedramcore_sequencer_start1; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_zqcs_timer_wait; +wire soc_litedramcore_zqcs_timer_done0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +wire soc_litedramcore_zqcs_timer_done1; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; +wire soc_litedramcore_bankmachine0_req_valid; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_we; +wire [20:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine1_req_valid; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_we; +wire [20:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine2_req_valid; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_we; +wire [20:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine3_req_valid; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_we; +wire [20:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine4_req_valid; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_we; +wire [20:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine5_req_valid; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_we; +wire [20:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine6_req_valid; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_we; +wire [20:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine7_req_valid; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_we; +wire [20:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; +wire soc_litedramcore_ras_allowed; +wire soc_litedramcore_cas_allowed; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire soc_litedramcore_choose_cmd_cmd_payload_is_read; +wire soc_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +wire soc_litedramcore_choose_cmd_ce; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_req_cmd_payload_is_cmd; +wire soc_litedramcore_choose_req_cmd_payload_is_read; +wire soc_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_req_request; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +wire soc_litedramcore_choose_req_ce; +reg [13:0] soc_litedramcore_nop_a = 14'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; +wire soc_litedramcore_trrdcon_valid; +reg soc_litedramcore_trrdcon_ready = 1'd0; +reg soc_litedramcore_trrdcon_count = 1'd0; +wire soc_litedramcore_tfawcon_valid; +reg soc_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] soc_litedramcore_tfawcon_count; +reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; +wire soc_litedramcore_tccdcon_valid; +reg soc_litedramcore_tccdcon_ready = 1'd0; +reg soc_litedramcore_tccdcon_count = 1'd0; +wire soc_litedramcore_twtrcon_valid; +reg soc_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +wire soc_litedramcore_read_available; +wire soc_litedramcore_write_available; +reg soc_litedramcore_en0 = 1'd0; +wire soc_litedramcore_max_time0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg soc_litedramcore_en1 = 1'd0; +wire soc_litedramcore_max_time1; +reg [3:0] soc_litedramcore_time1 = 4'd0; +wire soc_litedramcore_go_to_refresh; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire [29:0] soc_wb_bus_adr; +wire [31:0] soc_wb_bus_dat_w; +wire [31:0] soc_wb_bus_dat_r; +wire [3:0] soc_wb_bus_sel; +wire soc_wb_bus_cyc; +wire soc_wb_bus_stb; +wire soc_wb_bus_ack; +wire soc_wb_bus_we; +wire [2:0] soc_wb_bus_cti; +wire [1:0] soc_wb_bus_bte; +wire soc_wb_bus_err; +wire soc_user_port_cmd_valid; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_payload_we; +wire [23:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_wdata_valid; +wire soc_user_port_wdata_ready; +wire [127:0] soc_user_port_wdata_payload_data; +wire [15:0] soc_user_port_wdata_payload_we; +wire soc_user_port_rdata_valid; +wire soc_user_port_rdata_ready; +wire [127:0] soc_user_port_rdata_payload_data; reg [1:0] refresher_state = 2'd0; reg [1:0] refresher_next_state = 2'd0; reg [3:0] bankmachine0_state = 4'd0; @@ -1629,7 +1599,6 @@ reg locked6 = 1'd0; reg locked7 = 1'd0; reg new_master_wdata_ready0 = 1'd0; reg new_master_wdata_ready1 = 1'd0; -reg new_master_wdata_ready2 = 1'd0; reg new_master_rdata_valid0 = 1'd0; reg new_master_rdata_valid1 = 1'd0; reg new_master_rdata_valid2 = 1'd0; @@ -1639,113 +1608,247 @@ reg new_master_rdata_valid5 = 1'd0; reg new_master_rdata_valid6 = 1'd0; reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; -reg new_master_rdata_valid9 = 1'd0; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [7:0] litedramcore_dat_w = 8'd0; +wire [7:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -wire csrbank0_init_done0_re; +wire [7:0] interface0_bank_bus_dat_w; +reg [7:0] interface0_bank_bus_dat_r = 8'd0; +reg csrbank0_init_done0_re = 1'd0; wire csrbank0_init_done0_r; -wire csrbank0_init_done0_we; +reg csrbank0_init_done0_we = 1'd0; wire csrbank0_init_done0_w; -wire csrbank0_init_error0_re; +reg csrbank0_init_error0_re = 1'd0; wire csrbank0_init_error0_r; -wire csrbank0_init_error0_we; +reg csrbank0_init_error0_we = 1'd0; wire csrbank0_init_error0_w; wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -wire csrbank1_dfii_control0_re; +wire [7:0] interface1_bank_bus_dat_w; +reg [7:0] interface1_bank_bus_dat_r = 8'd0; +reg csrbank1_dfii_control0_re = 1'd0; wire [3:0] csrbank1_dfii_control0_r; -wire csrbank1_dfii_control0_we; +reg csrbank1_dfii_control0_we = 1'd0; wire [3:0] csrbank1_dfii_control0_w; -wire csrbank1_dfii_pi0_command0_re; +reg csrbank1_dfii_pi0_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi0_command0_r; -wire csrbank1_dfii_pi0_command0_we; +reg csrbank1_dfii_pi0_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi0_command0_w; -wire csrbank1_dfii_pi0_address0_re; -wire [13:0] csrbank1_dfii_pi0_address0_r; -wire csrbank1_dfii_pi0_address0_we; -wire [13:0] csrbank1_dfii_pi0_address0_w; -wire csrbank1_dfii_pi0_baddress0_re; +reg csrbank1_dfii_pi0_address1_re = 1'd0; +wire [5:0] csrbank1_dfii_pi0_address1_r; +reg csrbank1_dfii_pi0_address1_we = 1'd0; +wire [5:0] csrbank1_dfii_pi0_address1_w; +reg csrbank1_dfii_pi0_address0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_address0_r; +reg csrbank1_dfii_pi0_address0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_address0_w; +reg csrbank1_dfii_pi0_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi0_baddress0_r; -wire csrbank1_dfii_pi0_baddress0_we; +reg csrbank1_dfii_pi0_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi0_baddress0_w; -wire csrbank1_dfii_pi0_wrdata0_re; -wire [31:0] csrbank1_dfii_pi0_wrdata0_r; -wire csrbank1_dfii_pi0_wrdata0_we; -wire [31:0] csrbank1_dfii_pi0_wrdata0_w; -wire csrbank1_dfii_pi0_rddata_re; -wire [31:0] csrbank1_dfii_pi0_rddata_r; -wire csrbank1_dfii_pi0_rddata_we; -wire [31:0] csrbank1_dfii_pi0_rddata_w; -wire csrbank1_dfii_pi1_command0_re; +reg csrbank1_dfii_pi0_wrdata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata3_r; +reg csrbank1_dfii_pi0_wrdata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata3_w; +reg csrbank1_dfii_pi0_wrdata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata2_r; +reg csrbank1_dfii_pi0_wrdata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata2_w; +reg csrbank1_dfii_pi0_wrdata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata1_r; +reg csrbank1_dfii_pi0_wrdata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata1_w; +reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata0_r; +reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_wrdata0_w; +reg csrbank1_dfii_pi0_rddata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata3_r; +reg csrbank1_dfii_pi0_rddata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata3_w; +reg csrbank1_dfii_pi0_rddata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata2_r; +reg csrbank1_dfii_pi0_rddata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata2_w; +reg csrbank1_dfii_pi0_rddata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata1_r; +reg csrbank1_dfii_pi0_rddata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata1_w; +reg csrbank1_dfii_pi0_rddata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata0_r; +reg csrbank1_dfii_pi0_rddata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_rddata0_w; +reg csrbank1_dfii_pi1_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi1_command0_r; -wire csrbank1_dfii_pi1_command0_we; +reg csrbank1_dfii_pi1_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi1_command0_w; -wire csrbank1_dfii_pi1_address0_re; -wire [13:0] csrbank1_dfii_pi1_address0_r; -wire csrbank1_dfii_pi1_address0_we; -wire [13:0] csrbank1_dfii_pi1_address0_w; -wire csrbank1_dfii_pi1_baddress0_re; +reg csrbank1_dfii_pi1_address1_re = 1'd0; +wire [5:0] csrbank1_dfii_pi1_address1_r; +reg csrbank1_dfii_pi1_address1_we = 1'd0; +wire [5:0] csrbank1_dfii_pi1_address1_w; +reg csrbank1_dfii_pi1_address0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_address0_r; +reg csrbank1_dfii_pi1_address0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_address0_w; +reg csrbank1_dfii_pi1_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi1_baddress0_r; -wire csrbank1_dfii_pi1_baddress0_we; +reg csrbank1_dfii_pi1_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi1_baddress0_w; -wire csrbank1_dfii_pi1_wrdata0_re; -wire [31:0] csrbank1_dfii_pi1_wrdata0_r; -wire csrbank1_dfii_pi1_wrdata0_we; -wire [31:0] csrbank1_dfii_pi1_wrdata0_w; -wire csrbank1_dfii_pi1_rddata_re; -wire [31:0] csrbank1_dfii_pi1_rddata_r; -wire csrbank1_dfii_pi1_rddata_we; -wire [31:0] csrbank1_dfii_pi1_rddata_w; -wire csrbank1_dfii_pi2_command0_re; +reg csrbank1_dfii_pi1_wrdata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata3_r; +reg csrbank1_dfii_pi1_wrdata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata3_w; +reg csrbank1_dfii_pi1_wrdata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata2_r; +reg csrbank1_dfii_pi1_wrdata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata2_w; +reg csrbank1_dfii_pi1_wrdata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata1_r; +reg csrbank1_dfii_pi1_wrdata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata1_w; +reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata0_r; +reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_wrdata0_w; +reg csrbank1_dfii_pi1_rddata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata3_r; +reg csrbank1_dfii_pi1_rddata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata3_w; +reg csrbank1_dfii_pi1_rddata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata2_r; +reg csrbank1_dfii_pi1_rddata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata2_w; +reg csrbank1_dfii_pi1_rddata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata1_r; +reg csrbank1_dfii_pi1_rddata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata1_w; +reg csrbank1_dfii_pi1_rddata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata0_r; +reg csrbank1_dfii_pi1_rddata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_rddata0_w; +reg csrbank1_dfii_pi2_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi2_command0_r; -wire csrbank1_dfii_pi2_command0_we; +reg csrbank1_dfii_pi2_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi2_command0_w; -wire csrbank1_dfii_pi2_address0_re; -wire [13:0] csrbank1_dfii_pi2_address0_r; -wire csrbank1_dfii_pi2_address0_we; -wire [13:0] csrbank1_dfii_pi2_address0_w; -wire csrbank1_dfii_pi2_baddress0_re; +reg csrbank1_dfii_pi2_address1_re = 1'd0; +wire [5:0] csrbank1_dfii_pi2_address1_r; +reg csrbank1_dfii_pi2_address1_we = 1'd0; +wire [5:0] csrbank1_dfii_pi2_address1_w; +reg csrbank1_dfii_pi2_address0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_address0_r; +reg csrbank1_dfii_pi2_address0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_address0_w; +reg csrbank1_dfii_pi2_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi2_baddress0_r; -wire csrbank1_dfii_pi2_baddress0_we; +reg csrbank1_dfii_pi2_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi2_baddress0_w; -wire csrbank1_dfii_pi2_wrdata0_re; -wire [31:0] csrbank1_dfii_pi2_wrdata0_r; -wire csrbank1_dfii_pi2_wrdata0_we; -wire [31:0] csrbank1_dfii_pi2_wrdata0_w; -wire csrbank1_dfii_pi2_rddata_re; -wire [31:0] csrbank1_dfii_pi2_rddata_r; -wire csrbank1_dfii_pi2_rddata_we; -wire [31:0] csrbank1_dfii_pi2_rddata_w; -wire csrbank1_dfii_pi3_command0_re; +reg csrbank1_dfii_pi2_wrdata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata3_r; +reg csrbank1_dfii_pi2_wrdata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata3_w; +reg csrbank1_dfii_pi2_wrdata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata2_r; +reg csrbank1_dfii_pi2_wrdata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata2_w; +reg csrbank1_dfii_pi2_wrdata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata1_r; +reg csrbank1_dfii_pi2_wrdata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata1_w; +reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata0_r; +reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_wrdata0_w; +reg csrbank1_dfii_pi2_rddata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata3_r; +reg csrbank1_dfii_pi2_rddata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata3_w; +reg csrbank1_dfii_pi2_rddata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata2_r; +reg csrbank1_dfii_pi2_rddata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata2_w; +reg csrbank1_dfii_pi2_rddata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata1_r; +reg csrbank1_dfii_pi2_rddata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata1_w; +reg csrbank1_dfii_pi2_rddata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata0_r; +reg csrbank1_dfii_pi2_rddata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_rddata0_w; +reg csrbank1_dfii_pi3_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi3_command0_r; -wire csrbank1_dfii_pi3_command0_we; +reg csrbank1_dfii_pi3_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi3_command0_w; -wire csrbank1_dfii_pi3_address0_re; -wire [13:0] csrbank1_dfii_pi3_address0_r; -wire csrbank1_dfii_pi3_address0_we; -wire [13:0] csrbank1_dfii_pi3_address0_w; -wire csrbank1_dfii_pi3_baddress0_re; +reg csrbank1_dfii_pi3_address1_re = 1'd0; +wire [5:0] csrbank1_dfii_pi3_address1_r; +reg csrbank1_dfii_pi3_address1_we = 1'd0; +wire [5:0] csrbank1_dfii_pi3_address1_w; +reg csrbank1_dfii_pi3_address0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_address0_r; +reg csrbank1_dfii_pi3_address0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_address0_w; +reg csrbank1_dfii_pi3_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi3_baddress0_r; -wire csrbank1_dfii_pi3_baddress0_we; +reg csrbank1_dfii_pi3_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi3_baddress0_w; -wire csrbank1_dfii_pi3_wrdata0_re; -wire [31:0] csrbank1_dfii_pi3_wrdata0_r; -wire csrbank1_dfii_pi3_wrdata0_we; -wire [31:0] csrbank1_dfii_pi3_wrdata0_w; -wire csrbank1_dfii_pi3_rddata_re; -wire [31:0] csrbank1_dfii_pi3_rddata_r; -wire csrbank1_dfii_pi3_rddata_we; -wire [31:0] csrbank1_dfii_pi3_rddata_w; +reg csrbank1_dfii_pi3_wrdata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata3_r; +reg csrbank1_dfii_pi3_wrdata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata3_w; +reg csrbank1_dfii_pi3_wrdata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata2_r; +reg csrbank1_dfii_pi3_wrdata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata2_w; +reg csrbank1_dfii_pi3_wrdata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata1_r; +reg csrbank1_dfii_pi3_wrdata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata1_w; +reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata0_r; +reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata0_w; +reg csrbank1_dfii_pi3_rddata3_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata3_r; +reg csrbank1_dfii_pi3_rddata3_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata3_w; +reg csrbank1_dfii_pi3_rddata2_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata2_r; +reg csrbank1_dfii_pi3_rddata2_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata2_w; +reg csrbank1_dfii_pi3_rddata1_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata1_r; +reg csrbank1_dfii_pi3_rddata1_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata1_w; +reg csrbank1_dfii_pi3_rddata0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata0_r; +reg csrbank1_dfii_pi3_rddata0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_rddata0_w; wire csrbank1_sel; -wire [13:0] adr; -wire we; -wire [31:0] dat_w; -wire [31:0] dat_r; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [7:0] csr_interconnect_dat_w; +wire [7:0] csr_interconnect_dat_r; +reg [1:0] state = 2'd0; +reg [1:0] next_state = 2'd0; +reg [7:0] litedramcore_dat_w_next_value0 = 8'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; wire [24:0] slice_proxy0; wire [24:0] slice_proxy1; wire [24:0] slice_proxy2; @@ -1833,2652 +1936,2602 @@ reg array_muxed25 = 1'd0; reg array_muxed26 = 1'd0; reg array_muxed27 = 1'd0; -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign soc_wb_bus_adr = wb_ctrl_adr; +assign soc_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = soc_wb_bus_dat_r; +assign soc_wb_bus_sel = wb_ctrl_sel; +assign soc_wb_bus_cyc = wb_ctrl_cyc; +assign soc_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = soc_wb_bus_ack; +assign soc_wb_bus_we = wb_ctrl_we; +assign soc_wb_bus_cti = wb_ctrl_cti; +assign soc_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = soc_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = user_port_cmd_ready; -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = user_port_wdata_ready; -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = user_port_rdata_valid; -assign user_port_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign litedramcore_dat_w = litedramcore_wishbone_dat_w; -assign litedramcore_wishbone_dat_r = litedramcore_dat_r; -always @(*) begin - next_state = 1'd0; - next_state = state; - case (state) - 1'd1: begin - next_state = 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - next_state = 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack = 1'd0; - case (state) - 1'd1: begin - litedramcore_wishbone_ack = 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_adr = 14'd0; - case (state) - 1'd1: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr = litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_we = 1'd0; - case (state) - 1'd1: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end +assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; +assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; +assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; +assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; assign sys_clk = clk; assign por_clk = clk; -assign sys_rst = int_rst; +assign sys_rst = soc_int_rst; always @(*) begin - ddrphy_activates0 = 4'd0; - ddrphy_activates0[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates0[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates0[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates0[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates0 = 4'd0; + soc_ddrphy_activates0[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates0[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates0[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates0[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel0_activate_row = 14'd0; - case (ddrphy_activates0) + soc_ddrphy_bankmodel0_activate = 1'd0; + case (soc_ddrphy_activates0) 1'd1: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - ddrphy_bankmodel0_activate = 1'd0; - case (ddrphy_activates0) + soc_ddrphy_bankmodel0_activate_row = 14'd0; + case (soc_ddrphy_activates0) 1'd1: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges0 = 4'd0; - ddrphy_precharges0[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges0[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges0[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges0[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges0 = 4'd0; + soc_ddrphy_precharges0[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges0[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges0[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges0[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel0_precharge = 1'd0; - case (ddrphy_precharges0) + soc_ddrphy_bankmodel0_precharge = 1'd0; + case (soc_ddrphy_precharges0) 1'd1: begin - ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes0 = 4'd0; - ddrphy_writes0[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes0[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes0[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes0 = 4'd0; + soc_ddrphy_writes0[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes0[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes0[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes0[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write0 = 1'd0; - case (ddrphy_writes0) + soc_ddrphy_bank_write_col0 = 10'd0; + case (soc_ddrphy_writes0) 1'd1: begin - ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col0 = 10'd0; - case (ddrphy_writes0) + soc_ddrphy_bank_write0 = 1'd0; + case (soc_ddrphy_writes0) 1'd1: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end -assign ddrphy_bankmodel0_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel0_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel0_write = ddrphy_new_bank_write1; -assign ddrphy_bankmodel0_write_col = ddrphy_new_bank_write_col1; +assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0; +assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0; always @(*) begin - ddrphy_reads0 = 4'd0; - ddrphy_reads0[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads0[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads0[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads0 = 4'd0; + soc_ddrphy_reads0[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads0[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads0[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads0[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel0_read = 1'd0; - case (ddrphy_reads0) + soc_ddrphy_bankmodel0_read = 1'd0; + case (soc_ddrphy_reads0) 1'd1: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - ddrphy_bankmodel0_read_col = 10'd0; - case (ddrphy_reads0) + soc_ddrphy_bankmodel0_read_col = 10'd0; + case (soc_ddrphy_reads0) 1'd1: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_activates1 = 4'd0; - ddrphy_activates1[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates1[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates1[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates1 = 4'd0; + soc_ddrphy_activates1[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates1[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates1[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel1_activate = 1'd0; - case (ddrphy_activates1) + soc_ddrphy_bankmodel1_activate = 1'd0; + case (soc_ddrphy_activates1) 1'd1: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - ddrphy_bankmodel1_activate_row = 14'd0; - case (ddrphy_activates1) + soc_ddrphy_bankmodel1_activate_row = 14'd0; + case (soc_ddrphy_activates1) 1'd1: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges1 = 4'd0; - ddrphy_precharges1[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges1[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges1[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges1[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges1 = 4'd0; + soc_ddrphy_precharges1[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges1[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges1[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges1[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel1_precharge = 1'd0; - case (ddrphy_precharges1) + soc_ddrphy_bankmodel1_precharge = 1'd0; + case (soc_ddrphy_precharges1) 1'd1: begin - ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes1 = 4'd0; - ddrphy_writes1[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes1[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes1[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes1 = 4'd0; + soc_ddrphy_writes1[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes1[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes1[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes1[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write1 = 1'd0; - case (ddrphy_writes1) + soc_ddrphy_bank_write1 = 1'd0; + case (soc_ddrphy_writes1) 1'd1: begin - ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - ddrphy_bank_write_col1 = 10'd0; - case (ddrphy_writes1) + soc_ddrphy_bank_write_col1 = 10'd0; + case (soc_ddrphy_writes1) 1'd1: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel1_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel1_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel1_write = ddrphy_new_bank_write3; -assign ddrphy_bankmodel1_write_col = ddrphy_new_bank_write_col3; +assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1; +assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1; always @(*) begin - ddrphy_reads1 = 4'd0; - ddrphy_reads1[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads1[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads1[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads1[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads1 = 4'd0; + soc_ddrphy_reads1[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads1[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads1[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads1[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel1_read = 1'd0; - case (ddrphy_reads1) + soc_ddrphy_bankmodel1_read = 1'd0; + case (soc_ddrphy_reads1) 1'd1: begin - ddrphy_bankmodel1_read = (ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - ddrphy_bankmodel1_read = (ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - ddrphy_bankmodel1_read = (ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - ddrphy_bankmodel1_read = (ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - ddrphy_bankmodel1_read_col = 10'd0; - case (ddrphy_reads1) + soc_ddrphy_bankmodel1_read_col = 10'd0; + case (soc_ddrphy_reads1) 1'd1: begin - ddrphy_bankmodel1_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel1_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel1_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel1_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_activates2 = 4'd0; - ddrphy_activates2[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates2[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates2[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates2 = 4'd0; + soc_ddrphy_activates2[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates2[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates2[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates2[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel2_activate = 1'd0; - case (ddrphy_activates2) + soc_ddrphy_bankmodel2_activate = 1'd0; + case (soc_ddrphy_activates2) 1'd1: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - ddrphy_bankmodel2_activate_row = 14'd0; - case (ddrphy_activates2) + soc_ddrphy_bankmodel2_activate_row = 14'd0; + case (soc_ddrphy_activates2) 1'd1: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges2 = 4'd0; - ddrphy_precharges2[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges2[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges2[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges2[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges2 = 4'd0; + soc_ddrphy_precharges2[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges2[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges2[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges2[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel2_precharge = 1'd0; - case (ddrphy_precharges2) + soc_ddrphy_bankmodel2_precharge = 1'd0; + case (soc_ddrphy_precharges2) 1'd1: begin - ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes2 = 4'd0; - ddrphy_writes2[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes2[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes2[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes2[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes2 = 4'd0; + soc_ddrphy_writes2[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes2[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes2[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes2[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col2 = 10'd0; - case (ddrphy_writes2) + soc_ddrphy_bank_write2 = 1'd0; + case (soc_ddrphy_writes2) 1'd1: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - ddrphy_bank_write2 = 1'd0; - case (ddrphy_writes2) + soc_ddrphy_bank_write_col2 = 10'd0; + case (soc_ddrphy_writes2) 1'd1: begin - ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel2_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel2_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel2_write = ddrphy_new_bank_write5; -assign ddrphy_bankmodel2_write_col = ddrphy_new_bank_write_col5; +assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2; +assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2; always @(*) begin - ddrphy_reads2 = 4'd0; - ddrphy_reads2[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads2[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads2[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads2 = 4'd0; + soc_ddrphy_reads2[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads2[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads2[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads2[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel2_read = 1'd0; - case (ddrphy_reads2) + soc_ddrphy_bankmodel2_read_col = 10'd0; + case (soc_ddrphy_reads2) 1'd1: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel2_read_col = 10'd0; - case (ddrphy_reads2) + soc_ddrphy_bankmodel2_read = 1'd0; + case (soc_ddrphy_reads2) 1'd1: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - ddrphy_activates3 = 4'd0; - ddrphy_activates3[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates3[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates3[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates3[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates3 = 4'd0; + soc_ddrphy_activates3[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates3[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates3[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates3[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel3_activate = 1'd0; - case (ddrphy_activates3) + soc_ddrphy_bankmodel3_activate = 1'd0; + case (soc_ddrphy_activates3) 1'd1: begin - ddrphy_bankmodel3_activate = (ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - ddrphy_bankmodel3_activate = (ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - ddrphy_bankmodel3_activate = (ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - ddrphy_bankmodel3_activate = (ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - ddrphy_bankmodel3_activate_row = 14'd0; - case (ddrphy_activates3) + soc_ddrphy_bankmodel3_activate_row = 14'd0; + case (soc_ddrphy_activates3) 1'd1: begin - ddrphy_bankmodel3_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel3_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel3_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel3_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges3 = 4'd0; - ddrphy_precharges3[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges3[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges3[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges3[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges3 = 4'd0; + soc_ddrphy_precharges3[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges3[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges3[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges3[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel3_precharge = 1'd0; - case (ddrphy_precharges3) + soc_ddrphy_bankmodel3_precharge = 1'd0; + case (soc_ddrphy_precharges3) 1'd1: begin - ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes3 = 4'd0; - ddrphy_writes3[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes3[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes3[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes3 = 4'd0; + soc_ddrphy_writes3[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes3[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes3[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes3[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write3 = 1'd0; - case (ddrphy_writes3) + soc_ddrphy_bank_write3 = 1'd0; + case (soc_ddrphy_writes3) 1'd1: begin - ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - ddrphy_bank_write_col3 = 10'd0; - case (ddrphy_writes3) + soc_ddrphy_bank_write_col3 = 10'd0; + case (soc_ddrphy_writes3) 1'd1: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel3_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel3_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel3_write = ddrphy_new_bank_write7; -assign ddrphy_bankmodel3_write_col = ddrphy_new_bank_write_col7; +assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3; +assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3; always @(*) begin - ddrphy_reads3 = 4'd0; - ddrphy_reads3[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads3[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads3[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads3[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads3 = 4'd0; + soc_ddrphy_reads3[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads3[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads3[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads3[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel3_read_col = 10'd0; - case (ddrphy_reads3) + soc_ddrphy_bankmodel3_read = 1'd0; + case (soc_ddrphy_reads3) 1'd1: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - ddrphy_bankmodel3_read = 1'd0; - case (ddrphy_reads3) + soc_ddrphy_bankmodel3_read_col = 10'd0; + case (soc_ddrphy_reads3) 1'd1: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_activates4 = 4'd0; - ddrphy_activates4[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates4[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates4[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates4 = 4'd0; + soc_ddrphy_activates4[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates4[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates4[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates4[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel4_activate = 1'd0; - case (ddrphy_activates4) + soc_ddrphy_bankmodel4_activate_row = 14'd0; + case (soc_ddrphy_activates4) 1'd1: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel4_activate_row = 14'd0; - case (ddrphy_activates4) + soc_ddrphy_bankmodel4_activate = 1'd0; + case (soc_ddrphy_activates4) 1'd1: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - ddrphy_precharges4 = 4'd0; - ddrphy_precharges4[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges4[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges4[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges4[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges4 = 4'd0; + soc_ddrphy_precharges4[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges4[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges4[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges4[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel4_precharge = 1'd0; - case (ddrphy_precharges4) + soc_ddrphy_bankmodel4_precharge = 1'd0; + case (soc_ddrphy_precharges4) 1'd1: begin - ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes4 = 4'd0; - ddrphy_writes4[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes4[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes4[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes4 = 4'd0; + soc_ddrphy_writes4[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes4[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes4[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes4[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write4 = 1'd0; - case (ddrphy_writes4) + soc_ddrphy_bank_write_col4 = 10'd0; + case (soc_ddrphy_writes4) 1'd1: begin - ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col4 = 10'd0; - case (ddrphy_writes4) + soc_ddrphy_bank_write4 = 1'd0; + case (soc_ddrphy_writes4) 1'd1: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end -assign ddrphy_bankmodel4_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel4_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel4_write = ddrphy_new_bank_write9; -assign ddrphy_bankmodel4_write_col = ddrphy_new_bank_write_col9; +assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4; +assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4; always @(*) begin - ddrphy_reads4 = 4'd0; - ddrphy_reads4[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads4[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads4[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads4 = 4'd0; + soc_ddrphy_reads4[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads4[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads4[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads4[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel4_read = 1'd0; - case (ddrphy_reads4) + soc_ddrphy_bankmodel4_read = 1'd0; + case (soc_ddrphy_reads4) 1'd1: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - ddrphy_bankmodel4_read_col = 10'd0; - case (ddrphy_reads4) + soc_ddrphy_bankmodel4_read_col = 10'd0; + case (soc_ddrphy_reads4) 1'd1: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_activates5 = 4'd0; - ddrphy_activates5[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates5[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates5[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates5[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates5 = 4'd0; + soc_ddrphy_activates5[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates5[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates5[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates5[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel5_activate_row = 14'd0; - case (ddrphy_activates5) + soc_ddrphy_bankmodel5_activate = 1'd0; + case (soc_ddrphy_activates5) 1'd1: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - ddrphy_bankmodel5_activate = 1'd0; - case (ddrphy_activates5) + soc_ddrphy_bankmodel5_activate_row = 14'd0; + case (soc_ddrphy_activates5) 1'd1: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges5 = 4'd0; - ddrphy_precharges5[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges5[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges5[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges5[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges5 = 4'd0; + soc_ddrphy_precharges5[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges5[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges5[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges5[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel5_precharge = 1'd0; - case (ddrphy_precharges5) + soc_ddrphy_bankmodel5_precharge = 1'd0; + case (soc_ddrphy_precharges5) 1'd1: begin - ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes5 = 4'd0; - ddrphy_writes5[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes5[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes5[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes5 = 4'd0; + soc_ddrphy_writes5[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes5[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes5[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes5[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write5 = 1'd0; - case (ddrphy_writes5) + soc_ddrphy_bank_write5 = 1'd0; + case (soc_ddrphy_writes5) 1'd1: begin - ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - ddrphy_bank_write_col5 = 10'd0; - case (ddrphy_writes5) + soc_ddrphy_bank_write_col5 = 10'd0; + case (soc_ddrphy_writes5) 1'd1: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel5_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel5_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel5_write = ddrphy_new_bank_write11; -assign ddrphy_bankmodel5_write_col = ddrphy_new_bank_write_col11; +assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5; +assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5; always @(*) begin - ddrphy_reads5 = 4'd0; - ddrphy_reads5[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads5[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads5[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads5[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads5 = 4'd0; + soc_ddrphy_reads5[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads5[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads5[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel5_read = 1'd0; - case (ddrphy_reads5) + soc_ddrphy_bankmodel5_read_col = 10'd0; + case (soc_ddrphy_reads5) 1'd1: begin - ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel5_read_col = 10'd0; - case (ddrphy_reads5) + soc_ddrphy_bankmodel5_read = 1'd0; + case (soc_ddrphy_reads5) 1'd1: begin - ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - ddrphy_activates6 = 4'd0; - ddrphy_activates6[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates6[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates6[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates6 = 4'd0; + soc_ddrphy_activates6[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates6[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates6[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates6[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel6_activate = 1'd0; - case (ddrphy_activates6) + soc_ddrphy_bankmodel6_activate = 1'd0; + case (soc_ddrphy_activates6) 1'd1: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - ddrphy_bankmodel6_activate_row = 14'd0; - case (ddrphy_activates6) + soc_ddrphy_bankmodel6_activate_row = 14'd0; + case (soc_ddrphy_activates6) 1'd1: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_precharges6 = 4'd0; - ddrphy_precharges6[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges6[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges6[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges6[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges6 = 4'd0; + soc_ddrphy_precharges6[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges6[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges6[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges6[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel6_precharge = 1'd0; - case (ddrphy_precharges6) + soc_ddrphy_bankmodel6_precharge = 1'd0; + case (soc_ddrphy_precharges6) 1'd1: begin - ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes6 = 4'd0; - ddrphy_writes6[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes6[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes6[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes6[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes6 = 4'd0; + soc_ddrphy_writes6[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes6[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes6[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes6[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col6 = 10'd0; - case (ddrphy_writes6) + soc_ddrphy_bank_write6 = 1'd0; + case (soc_ddrphy_writes6) 1'd1: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - ddrphy_bank_write6 = 1'd0; - case (ddrphy_writes6) + soc_ddrphy_bank_write_col6 = 10'd0; + case (soc_ddrphy_writes6) 1'd1: begin - ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel6_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel6_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel6_write = ddrphy_new_bank_write13; -assign ddrphy_bankmodel6_write_col = ddrphy_new_bank_write_col13; +assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6; +assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6; always @(*) begin - ddrphy_reads6 = 4'd0; - ddrphy_reads6[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads6[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads6[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads6[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads6 = 4'd0; + soc_ddrphy_reads6[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads6[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads6[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads6[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel6_read_col = 10'd0; - case (ddrphy_reads6) + soc_ddrphy_bankmodel6_read = 1'd0; + case (soc_ddrphy_reads6) 1'd1: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - ddrphy_bankmodel6_read = 1'd0; - case (ddrphy_reads6) + soc_ddrphy_bankmodel6_read_col = 10'd0; + case (soc_ddrphy_reads6) 1'd1: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_activates7 = 4'd0; - ddrphy_activates7[0] = ddrphy_dfiphasemodel0_activate; - ddrphy_activates7[1] = ddrphy_dfiphasemodel1_activate; - ddrphy_activates7[2] = ddrphy_dfiphasemodel2_activate; - ddrphy_activates7[3] = ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates7 = 4'd0; + soc_ddrphy_activates7[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates7[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates7[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel7_activate = 1'd0; - case (ddrphy_activates7) + soc_ddrphy_bankmodel7_activate_row = 14'd0; + case (soc_ddrphy_activates7) 1'd1: begin - ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel7_activate_row = 14'd0; - case (ddrphy_activates7) + soc_ddrphy_bankmodel7_activate = 1'd0; + case (soc_ddrphy_activates7) 1'd1: begin - ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - ddrphy_precharges7 = 4'd0; - ddrphy_precharges7[0] = ddrphy_dfiphasemodel0_precharge; - ddrphy_precharges7[1] = ddrphy_dfiphasemodel1_precharge; - ddrphy_precharges7[2] = ddrphy_dfiphasemodel2_precharge; - ddrphy_precharges7[3] = ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges7 = 4'd0; + soc_ddrphy_precharges7[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges7[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges7[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges7[3] = soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - ddrphy_bankmodel7_precharge = 1'd0; - case (ddrphy_precharges7) + soc_ddrphy_bankmodel7_precharge = 1'd0; + case (soc_ddrphy_precharges7) 1'd1: begin - ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - ddrphy_writes7 = 4'd0; - ddrphy_writes7[0] = ddrphy_dfiphasemodel0_write; - ddrphy_writes7[1] = ddrphy_dfiphasemodel1_write; - ddrphy_writes7[2] = ddrphy_dfiphasemodel2_write; - ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes7 = 4'd0; + soc_ddrphy_writes7[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes7[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes7[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes7[3] = soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write7 = 1'd0; - case (ddrphy_writes7) + soc_ddrphy_bank_write7 = 1'd0; + case (soc_ddrphy_writes7) 1'd1: begin - ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - ddrphy_bank_write_col7 = 10'd0; - case (ddrphy_writes7) + soc_ddrphy_bank_write_col7 = 10'd0; + case (soc_ddrphy_writes7) 1'd1: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_bankmodel7_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; -assign ddrphy_bankmodel7_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; -assign ddrphy_bankmodel7_write = ddrphy_new_bank_write15; -assign ddrphy_bankmodel7_write_col = ddrphy_new_bank_write_col15; +assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7; +assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7; always @(*) begin - ddrphy_reads7 = 4'd0; - ddrphy_reads7[0] = ddrphy_dfiphasemodel0_read; - ddrphy_reads7[1] = ddrphy_dfiphasemodel1_read; - ddrphy_reads7[2] = ddrphy_dfiphasemodel2_read; - ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads7 = 4'd0; + soc_ddrphy_reads7[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads7[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads7[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel7_read = 1'd0; - case (ddrphy_reads7) + soc_ddrphy_bankmodel7_read = 1'd0; + case (soc_ddrphy_reads7) 1'd1: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - ddrphy_bankmodel7_read_col = 10'd0; - case (ddrphy_reads7) + soc_ddrphy_bankmodel7_read_col = 10'd0; + case (soc_ddrphy_reads7) 1'd1: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address; end endcase end -assign ddrphy_banks_read = (((((((ddrphy_bankmodel0_read | ddrphy_bankmodel1_read) | ddrphy_bankmodel2_read) | ddrphy_bankmodel3_read) | ddrphy_bankmodel4_read) | ddrphy_bankmodel5_read) | ddrphy_bankmodel6_read) | ddrphy_bankmodel7_read); -assign ddrphy_banks_read_data = (((((((ddrphy_bankmodel0_read_data | ddrphy_bankmodel1_read_data) | ddrphy_bankmodel2_read_data) | ddrphy_bankmodel3_read_data) | ddrphy_bankmodel4_read_data) | ddrphy_bankmodel5_read_data) | ddrphy_bankmodel6_read_data) | ddrphy_bankmodel7_read_data); -assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; -assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; -assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; -assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; -assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; -assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; -assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; -assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; +assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read); +assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data); +assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7; +assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7; +assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7; +assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7; +assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; +assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; +assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; +assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; always @(*) begin - ddrphy_dfiphasemodel0_precharge = 1'd0; - if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin - ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_activate = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin + soc_ddrphy_dfiphasemodel0_activate = soc_ddrphy_dfi_p0_we_n; end end always @(*) begin - ddrphy_dfiphasemodel0_activate = 1'd0; - if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin - ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin + soc_ddrphy_dfiphasemodel0_precharge = (~soc_ddrphy_dfi_p0_we_n); end end always @(*) begin - ddrphy_dfiphasemodel0_write = 1'd0; - if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin - ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_read = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin + soc_ddrphy_dfiphasemodel0_read = soc_ddrphy_dfi_p0_we_n; end end always @(*) begin - ddrphy_dfiphasemodel0_read = 1'd0; - if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin - ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_write = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin + soc_ddrphy_dfiphasemodel0_write = (~soc_ddrphy_dfi_p0_we_n); end end always @(*) begin - ddrphy_dfiphasemodel1_activate = 1'd0; - if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin - ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_activate = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin + soc_ddrphy_dfiphasemodel1_activate = soc_ddrphy_dfi_p1_we_n; end end always @(*) begin - ddrphy_dfiphasemodel1_precharge = 1'd0; - if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin - ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin + soc_ddrphy_dfiphasemodel1_precharge = (~soc_ddrphy_dfi_p1_we_n); end end always @(*) begin - ddrphy_dfiphasemodel1_write = 1'd0; - if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin - ddrphy_dfiphasemodel1_write = (~ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_write = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin + soc_ddrphy_dfiphasemodel1_write = (~soc_ddrphy_dfi_p1_we_n); end end always @(*) begin - ddrphy_dfiphasemodel1_read = 1'd0; - if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin - ddrphy_dfiphasemodel1_read = ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_read = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin + soc_ddrphy_dfiphasemodel1_read = soc_ddrphy_dfi_p1_we_n; end end always @(*) begin - ddrphy_dfiphasemodel2_activate = 1'd0; - if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin - ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin + soc_ddrphy_dfiphasemodel2_precharge = (~soc_ddrphy_dfi_p2_we_n); end end always @(*) begin - ddrphy_dfiphasemodel2_precharge = 1'd0; - if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin - ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_activate = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin + soc_ddrphy_dfiphasemodel2_activate = soc_ddrphy_dfi_p2_we_n; end end always @(*) begin - ddrphy_dfiphasemodel2_read = 1'd0; - if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin - ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_write = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin + soc_ddrphy_dfiphasemodel2_write = (~soc_ddrphy_dfi_p2_we_n); end end always @(*) begin - ddrphy_dfiphasemodel2_write = 1'd0; - if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin - ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_read = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin + soc_ddrphy_dfiphasemodel2_read = soc_ddrphy_dfi_p2_we_n; end end always @(*) begin - ddrphy_dfiphasemodel3_activate = 1'd0; - if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin - ddrphy_dfiphasemodel3_activate = ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_activate = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin + soc_ddrphy_dfiphasemodel3_activate = soc_ddrphy_dfi_p3_we_n; end end always @(*) begin - ddrphy_dfiphasemodel3_precharge = 1'd0; - if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin - ddrphy_dfiphasemodel3_precharge = (~ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin + soc_ddrphy_dfiphasemodel3_precharge = (~soc_ddrphy_dfi_p3_we_n); end end always @(*) begin - ddrphy_dfiphasemodel3_write = 1'd0; - if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin - ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_write = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin + soc_ddrphy_dfiphasemodel3_write = (~soc_ddrphy_dfi_p3_we_n); end end always @(*) begin - ddrphy_dfiphasemodel3_read = 1'd0; - if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin - ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_read = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin + soc_ddrphy_dfiphasemodel3_read = soc_ddrphy_dfi_p3_we_n; end end -assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; -assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; +assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; +assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; always @(*) begin - ddrphy_bankmodel0_read_data = 128'd0; - if (ddrphy_bankmodel0_active) begin - if (ddrphy_bankmodel0_read) begin - ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r; + soc_ddrphy_bankmodel0_read_data = 128'd0; + if (soc_ddrphy_bankmodel0_active) begin + if (soc_ddrphy_bankmodel0_read) begin + soc_ddrphy_bankmodel0_read_data = soc_ddrphy_bankmodel0_read_port_dat_r; end end end always @(*) begin - ddrphy_bankmodel0_write_port_adr = 21'd0; - if (ddrphy_bankmodel0_active) begin - ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr; + soc_ddrphy_bankmodel0_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_adr = soc_ddrphy_bankmodel0_wraddr; end end always @(*) begin - ddrphy_bankmodel0_write_port_we = 16'd0; - if (ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel0_active) begin if (4'd8) begin - ddrphy_bankmodel0_write_port_we = ({16{ddrphy_bankmodel0_write}} & (~ddrphy_bankmodel0_write_mask)); + soc_ddrphy_bankmodel0_write_port_we = ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); end else begin - ddrphy_bankmodel0_write_port_we = ddrphy_bankmodel0_write; + soc_ddrphy_bankmodel0_write_port_we = soc_ddrphy_bankmodel0_write; end end end always @(*) begin - ddrphy_bankmodel0_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel0_active) begin - ddrphy_bankmodel0_write_port_dat_w = ddrphy_bankmodel0_write_data; + soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_dat_w = soc_ddrphy_bankmodel0_write_data; end end always @(*) begin - ddrphy_bankmodel0_read_port_adr = 21'd0; - if (ddrphy_bankmodel0_active) begin - if (ddrphy_bankmodel0_read) begin - ddrphy_bankmodel0_read_port_adr = ddrphy_bankmodel0_rdaddr; + soc_ddrphy_bankmodel0_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel0_active) begin + if (soc_ddrphy_bankmodel0_read) begin + soc_ddrphy_bankmodel0_read_port_adr = soc_ddrphy_bankmodel0_rdaddr; end end end -assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; -assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; +assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; +assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; always @(*) begin - ddrphy_bankmodel1_write_port_adr = 21'd0; - if (ddrphy_bankmodel1_active) begin - ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr; + soc_ddrphy_bankmodel1_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_adr = soc_ddrphy_bankmodel1_wraddr; end end always @(*) begin - ddrphy_bankmodel1_write_port_we = 16'd0; - if (ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel1_active) begin if (4'd8) begin - ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask)); + soc_ddrphy_bankmodel1_write_port_we = ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); end else begin - ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write; + soc_ddrphy_bankmodel1_write_port_we = soc_ddrphy_bankmodel1_write; end end end always @(*) begin - ddrphy_bankmodel1_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel1_active) begin - ddrphy_bankmodel1_write_port_dat_w = ddrphy_bankmodel1_write_data; + soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_dat_w = soc_ddrphy_bankmodel1_write_data; end end always @(*) begin - ddrphy_bankmodel1_read_port_adr = 21'd0; - if (ddrphy_bankmodel1_active) begin - if (ddrphy_bankmodel1_read) begin - ddrphy_bankmodel1_read_port_adr = ddrphy_bankmodel1_rdaddr; + soc_ddrphy_bankmodel1_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_port_adr = soc_ddrphy_bankmodel1_rdaddr; end end end always @(*) begin - ddrphy_bankmodel1_read_data = 128'd0; - if (ddrphy_bankmodel1_active) begin - if (ddrphy_bankmodel1_read) begin - ddrphy_bankmodel1_read_data = ddrphy_bankmodel1_read_port_dat_r; + soc_ddrphy_bankmodel1_read_data = 128'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r; end end end -assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; -assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; +assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; +assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; always @(*) begin - ddrphy_bankmodel2_write_port_adr = 21'd0; - if (ddrphy_bankmodel2_active) begin - ddrphy_bankmodel2_write_port_adr = ddrphy_bankmodel2_wraddr; + soc_ddrphy_bankmodel2_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_adr = soc_ddrphy_bankmodel2_wraddr; end end always @(*) begin - ddrphy_bankmodel2_write_port_we = 16'd0; - if (ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel2_active) begin if (4'd8) begin - ddrphy_bankmodel2_write_port_we = ({16{ddrphy_bankmodel2_write}} & (~ddrphy_bankmodel2_write_mask)); + soc_ddrphy_bankmodel2_write_port_we = ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); end else begin - ddrphy_bankmodel2_write_port_we = ddrphy_bankmodel2_write; + soc_ddrphy_bankmodel2_write_port_we = soc_ddrphy_bankmodel2_write; end end end always @(*) begin - ddrphy_bankmodel2_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel2_active) begin - ddrphy_bankmodel2_write_port_dat_w = ddrphy_bankmodel2_write_data; + soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_dat_w = soc_ddrphy_bankmodel2_write_data; end end always @(*) begin - ddrphy_bankmodel2_read_port_adr = 21'd0; - if (ddrphy_bankmodel2_active) begin - if (ddrphy_bankmodel2_read) begin - ddrphy_bankmodel2_read_port_adr = ddrphy_bankmodel2_rdaddr; + soc_ddrphy_bankmodel2_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel2_active) begin + if (soc_ddrphy_bankmodel2_read) begin + soc_ddrphy_bankmodel2_read_port_adr = soc_ddrphy_bankmodel2_rdaddr; end end end always @(*) begin - ddrphy_bankmodel2_read_data = 128'd0; - if (ddrphy_bankmodel2_active) begin - if (ddrphy_bankmodel2_read) begin - ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r; + soc_ddrphy_bankmodel2_read_data = 128'd0; + if (soc_ddrphy_bankmodel2_active) begin + if (soc_ddrphy_bankmodel2_read) begin + soc_ddrphy_bankmodel2_read_data = soc_ddrphy_bankmodel2_read_port_dat_r; end end end -assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; -assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; +assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; +assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; always @(*) begin - ddrphy_bankmodel3_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel3_active) begin - ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data; + soc_ddrphy_bankmodel3_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel3_write_port_we = ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); + end else begin + soc_ddrphy_bankmodel3_write_port_we = soc_ddrphy_bankmodel3_write; + end end end always @(*) begin - ddrphy_bankmodel3_read_port_adr = 21'd0; - if (ddrphy_bankmodel3_active) begin - if (ddrphy_bankmodel3_read) begin - ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr; - end + soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_dat_w = soc_ddrphy_bankmodel3_write_data; end end always @(*) begin - ddrphy_bankmodel3_read_data = 128'd0; - if (ddrphy_bankmodel3_active) begin - if (ddrphy_bankmodel3_read) begin - ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r; + soc_ddrphy_bankmodel3_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (soc_ddrphy_bankmodel3_read) begin + soc_ddrphy_bankmodel3_read_port_adr = soc_ddrphy_bankmodel3_rdaddr; end end end always @(*) begin - ddrphy_bankmodel3_write_port_adr = 21'd0; - if (ddrphy_bankmodel3_active) begin - ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr; + soc_ddrphy_bankmodel3_read_data = 128'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (soc_ddrphy_bankmodel3_read) begin + soc_ddrphy_bankmodel3_read_data = soc_ddrphy_bankmodel3_read_port_dat_r; + end end end always @(*) begin - ddrphy_bankmodel3_write_port_we = 16'd0; - if (ddrphy_bankmodel3_active) begin - if (4'd8) begin - ddrphy_bankmodel3_write_port_we = ({16{ddrphy_bankmodel3_write}} & (~ddrphy_bankmodel3_write_mask)); - end else begin - ddrphy_bankmodel3_write_port_we = ddrphy_bankmodel3_write; - end + soc_ddrphy_bankmodel3_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_adr = soc_ddrphy_bankmodel3_wraddr; end end -assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; -assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; +assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; +assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin - ddrphy_bankmodel4_read_port_adr = 21'd0; - if (ddrphy_bankmodel4_active) begin - if (ddrphy_bankmodel4_read) begin - ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr; + soc_ddrphy_bankmodel4_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_port_adr = soc_ddrphy_bankmodel4_rdaddr; end end end always @(*) begin - ddrphy_bankmodel4_read_data = 128'd0; - if (ddrphy_bankmodel4_active) begin - if (ddrphy_bankmodel4_read) begin - ddrphy_bankmodel4_read_data = ddrphy_bankmodel4_read_port_dat_r; + soc_ddrphy_bankmodel4_read_data = 128'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_data = soc_ddrphy_bankmodel4_read_port_dat_r; end end end always @(*) begin - ddrphy_bankmodel4_write_port_adr = 21'd0; - if (ddrphy_bankmodel4_active) begin - ddrphy_bankmodel4_write_port_adr = ddrphy_bankmodel4_wraddr; + soc_ddrphy_bankmodel4_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_adr = soc_ddrphy_bankmodel4_wraddr; end end always @(*) begin - ddrphy_bankmodel4_write_port_we = 16'd0; - if (ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel4_active) begin if (4'd8) begin - ddrphy_bankmodel4_write_port_we = ({16{ddrphy_bankmodel4_write}} & (~ddrphy_bankmodel4_write_mask)); + soc_ddrphy_bankmodel4_write_port_we = ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); end else begin - ddrphy_bankmodel4_write_port_we = ddrphy_bankmodel4_write; + soc_ddrphy_bankmodel4_write_port_we = soc_ddrphy_bankmodel4_write; end end end always @(*) begin - ddrphy_bankmodel4_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel4_active) begin - ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data; + soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data; end end -assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; -assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; +assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; +assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin - ddrphy_bankmodel5_read_data = 128'd0; - if (ddrphy_bankmodel5_active) begin - if (ddrphy_bankmodel5_read) begin - ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r; + soc_ddrphy_bankmodel5_read_data = 128'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_data = soc_ddrphy_bankmodel5_read_port_dat_r; end end end always @(*) begin - ddrphy_bankmodel5_write_port_adr = 21'd0; - if (ddrphy_bankmodel5_active) begin - ddrphy_bankmodel5_write_port_adr = ddrphy_bankmodel5_wraddr; + soc_ddrphy_bankmodel5_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_adr = soc_ddrphy_bankmodel5_wraddr; end end always @(*) begin - ddrphy_bankmodel5_write_port_we = 16'd0; - if (ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel5_active) begin if (4'd8) begin - ddrphy_bankmodel5_write_port_we = ({16{ddrphy_bankmodel5_write}} & (~ddrphy_bankmodel5_write_mask)); + soc_ddrphy_bankmodel5_write_port_we = ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); end else begin - ddrphy_bankmodel5_write_port_we = ddrphy_bankmodel5_write; + soc_ddrphy_bankmodel5_write_port_we = soc_ddrphy_bankmodel5_write; end end end always @(*) begin - ddrphy_bankmodel5_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel5_active) begin - ddrphy_bankmodel5_write_port_dat_w = ddrphy_bankmodel5_write_data; + soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_dat_w = soc_ddrphy_bankmodel5_write_data; end end always @(*) begin - ddrphy_bankmodel5_read_port_adr = 21'd0; - if (ddrphy_bankmodel5_active) begin - if (ddrphy_bankmodel5_read) begin - ddrphy_bankmodel5_read_port_adr = ddrphy_bankmodel5_rdaddr; + soc_ddrphy_bankmodel5_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_port_adr = soc_ddrphy_bankmodel5_rdaddr; end end end -assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; -assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; +assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; +assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin - ddrphy_bankmodel6_read_data = 128'd0; - if (ddrphy_bankmodel6_active) begin - if (ddrphy_bankmodel6_read) begin - ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r; + soc_ddrphy_bankmodel6_read_data = 128'd0; + if (soc_ddrphy_bankmodel6_active) begin + if (soc_ddrphy_bankmodel6_read) begin + soc_ddrphy_bankmodel6_read_data = soc_ddrphy_bankmodel6_read_port_dat_r; end end end always @(*) begin - ddrphy_bankmodel6_write_port_adr = 21'd0; - if (ddrphy_bankmodel6_active) begin - ddrphy_bankmodel6_write_port_adr = ddrphy_bankmodel6_wraddr; + soc_ddrphy_bankmodel6_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_adr = soc_ddrphy_bankmodel6_wraddr; end end always @(*) begin - ddrphy_bankmodel6_write_port_we = 16'd0; - if (ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel6_active) begin if (4'd8) begin - ddrphy_bankmodel6_write_port_we = ({16{ddrphy_bankmodel6_write}} & (~ddrphy_bankmodel6_write_mask)); + soc_ddrphy_bankmodel6_write_port_we = ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); end else begin - ddrphy_bankmodel6_write_port_we = ddrphy_bankmodel6_write; + soc_ddrphy_bankmodel6_write_port_we = soc_ddrphy_bankmodel6_write; end end end always @(*) begin - ddrphy_bankmodel6_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel6_active) begin - ddrphy_bankmodel6_write_port_dat_w = ddrphy_bankmodel6_write_data; + soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_dat_w = soc_ddrphy_bankmodel6_write_data; + end +end +always @(*) begin + soc_ddrphy_bankmodel6_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel6_active) begin + if (soc_ddrphy_bankmodel6_read) begin + soc_ddrphy_bankmodel6_read_port_adr = soc_ddrphy_bankmodel6_rdaddr; + end end end +assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; +assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin - ddrphy_bankmodel6_read_port_adr = 21'd0; - if (ddrphy_bankmodel6_active) begin - if (ddrphy_bankmodel6_read) begin - ddrphy_bankmodel6_read_port_adr = ddrphy_bankmodel6_rdaddr; + soc_ddrphy_bankmodel7_read_data = 128'd0; + if (soc_ddrphy_bankmodel7_active) begin + if (soc_ddrphy_bankmodel7_read) begin + soc_ddrphy_bankmodel7_read_data = soc_ddrphy_bankmodel7_read_port_dat_r; end end end -assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; -assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin - ddrphy_bankmodel7_write_port_adr = 21'd0; - if (ddrphy_bankmodel7_active) begin - ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr; + soc_ddrphy_bankmodel7_write_port_adr = 21'd0; + if (soc_ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_adr = soc_ddrphy_bankmodel7_wraddr; end end always @(*) begin - ddrphy_bankmodel7_write_port_we = 16'd0; - if (ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel7_active) begin if (4'd8) begin - ddrphy_bankmodel7_write_port_we = ({16{ddrphy_bankmodel7_write}} & (~ddrphy_bankmodel7_write_mask)); + soc_ddrphy_bankmodel7_write_port_we = ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); end else begin - ddrphy_bankmodel7_write_port_we = ddrphy_bankmodel7_write; - end - end -end -always @(*) begin - ddrphy_bankmodel7_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel7_active) begin - ddrphy_bankmodel7_write_port_dat_w = ddrphy_bankmodel7_write_data; - end -end -always @(*) begin - ddrphy_bankmodel7_read_port_adr = 21'd0; - if (ddrphy_bankmodel7_active) begin - if (ddrphy_bankmodel7_read) begin - ddrphy_bankmodel7_read_port_adr = ddrphy_bankmodel7_rdaddr; - end - end -end -always @(*) begin - ddrphy_bankmodel7_read_data = 128'd0; - if (ddrphy_bankmodel7_active) begin - if (ddrphy_bankmodel7_read) begin - ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r; - end - end -end -assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid; -assign ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid; -assign ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = ddrphy_dfi_p2_rddata_valid; -assign ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; + soc_ddrphy_bankmodel7_write_port_we = soc_ddrphy_bankmodel7_write; + end + end +end +always @(*) begin + soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; + if (soc_ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_dat_w = soc_ddrphy_bankmodel7_write_data; + end +end +always @(*) begin + soc_ddrphy_bankmodel7_read_port_adr = 21'd0; + if (soc_ddrphy_bankmodel7_active) begin + if (soc_ddrphy_bankmodel7_read) begin + soc_ddrphy_bankmodel7_read_port_adr = soc_ddrphy_bankmodel7_rdaddr; + end + end +end +assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; +assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; +assign soc_ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; +assign soc_ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; +assign soc_ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; +assign soc_ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; +assign soc_ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; +assign soc_ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; +assign soc_ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; +assign soc_ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; +assign soc_ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; +assign soc_ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; +assign soc_ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; +assign soc_ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; +assign soc_litedramcore_master_p0_rddata = soc_ddrphy_dfi_p0_rddata; +assign soc_litedramcore_master_p0_rddata_valid = soc_ddrphy_dfi_p0_rddata_valid; +assign soc_ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; +assign soc_ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; +assign soc_ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; +assign soc_ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; +assign soc_ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; +assign soc_ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; +assign soc_ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; +assign soc_ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; +assign soc_ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; +assign soc_ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; +assign soc_ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; +assign soc_ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; +assign soc_ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; +assign soc_ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; +assign soc_litedramcore_master_p1_rddata = soc_ddrphy_dfi_p1_rddata; +assign soc_litedramcore_master_p1_rddata_valid = soc_ddrphy_dfi_p1_rddata_valid; +assign soc_ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; +assign soc_ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; +assign soc_ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; +assign soc_ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; +assign soc_ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; +assign soc_ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; +assign soc_ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; +assign soc_ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; +assign soc_ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; +assign soc_ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; +assign soc_ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; +assign soc_ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; +assign soc_ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; +assign soc_ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; +assign soc_litedramcore_master_p2_rddata = soc_ddrphy_dfi_p2_rddata; +assign soc_litedramcore_master_p2_rddata_valid = soc_ddrphy_dfi_p2_rddata_valid; +assign soc_ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; +assign soc_ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; +assign soc_ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; +assign soc_ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; +assign soc_ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; +assign soc_ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; +assign soc_ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; +assign soc_ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; +assign soc_ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; +assign soc_ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; +assign soc_ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; +assign soc_ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; +assign soc_ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; +assign soc_ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; +assign soc_litedramcore_master_p3_rddata = soc_ddrphy_dfi_p3_rddata; +assign soc_litedramcore_master_p3_rddata_valid = soc_ddrphy_dfi_p3_rddata_valid; +assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; +assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; +assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; +assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; +assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; +assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; +assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; +assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; +assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; +assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; +assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; +assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; +assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; +assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; +assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; +assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; +assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; +assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; +assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; +assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; +assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; +assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; +assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; +assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; +assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; +assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; +assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; +assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; +assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; +assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; +assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; +assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; +assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; +assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; +assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; +assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; +assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; +assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; +assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; +assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; +assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; +assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; +assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; +assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; +assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; +assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; +assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; +assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; +assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; +assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; +assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; +assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; +assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; +assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; +assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; +assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; +assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; +assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; +assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; +assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; +assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; +assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; +assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; +assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_master_p2_we_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; + soc_litedramcore_master_p0_we_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_we_n = soc_litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; + soc_litedramcore_master_p0_we_n = soc_litedramcore_inti_p0_we_n; end end always @(*) begin - litedramcore_slave_p2_rddata_valid = 1'd0; - if (litedramcore_sel) begin - litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + soc_litedramcore_slave_p0_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; end else begin end end always @(*) begin - litedramcore_master_p2_cke = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_cke = litedramcore_slave_p2_cke; + soc_litedramcore_master_p0_cke = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cke = soc_litedramcore_slave_p0_cke; end else begin - litedramcore_master_p2_cke = litedramcore_inti_p2_cke; + soc_litedramcore_master_p0_cke = soc_litedramcore_inti_p0_cke; end end always @(*) begin - litedramcore_master_p2_odt = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_odt = litedramcore_slave_p2_odt; + soc_litedramcore_master_p0_odt = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_odt = soc_litedramcore_slave_p0_odt; end else begin - litedramcore_master_p2_odt = litedramcore_inti_p2_odt; + soc_litedramcore_master_p0_odt = soc_litedramcore_inti_p0_odt; end end always @(*) begin - litedramcore_master_p2_reset_n = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; + soc_litedramcore_master_p0_reset_n = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_reset_n = soc_litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; + soc_litedramcore_master_p0_reset_n = soc_litedramcore_inti_p0_reset_n; end end always @(*) begin - litedramcore_master_p2_act_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; + soc_litedramcore_master_p0_act_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_act_n = soc_litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; + soc_litedramcore_master_p0_act_n = soc_litedramcore_inti_p0_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata = 32'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; + soc_litedramcore_master_p0_wrdata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata = soc_litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; + soc_litedramcore_master_p0_wrdata = soc_litedramcore_inti_p0_wrdata; end end always @(*) begin - litedramcore_inti_p3_rddata = 32'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p1_rddata = 32'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; + soc_litedramcore_inti_p1_rddata = soc_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_master_p2_wrdata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; + soc_litedramcore_master_p0_wrdata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; + soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_inti_p0_wrdata_en; end end always @(*) begin - litedramcore_inti_p3_rddata_valid = 1'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p1_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + soc_litedramcore_inti_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_master_p2_wrdata_mask = 4'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; + soc_litedramcore_master_p0_wrdata_mask = 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; + soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_inti_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_rddata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; + soc_litedramcore_master_p0_rddata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_rddata_en = soc_litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; + soc_litedramcore_master_p0_rddata_en = soc_litedramcore_inti_p0_rddata_en; end end always @(*) begin - litedramcore_master_p3_address = 14'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_address = litedramcore_slave_p3_address; + soc_litedramcore_master_p1_address = 14'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_address = soc_litedramcore_slave_p1_address; end else begin - litedramcore_master_p3_address = litedramcore_inti_p3_address; + soc_litedramcore_master_p1_address = soc_litedramcore_inti_p1_address; end end always @(*) begin - litedramcore_master_p3_bank = 3'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_bank = litedramcore_slave_p3_bank; + soc_litedramcore_master_p1_bank = 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_bank = soc_litedramcore_slave_p1_bank; end else begin - litedramcore_master_p3_bank = litedramcore_inti_p3_bank; + soc_litedramcore_master_p1_bank = soc_litedramcore_inti_p1_bank; end end always @(*) begin - litedramcore_master_p3_cas_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n; + soc_litedramcore_master_p1_cas_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cas_n = soc_litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n; + soc_litedramcore_master_p1_cas_n = soc_litedramcore_inti_p1_cas_n; end end always @(*) begin - litedramcore_master_p3_cs_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n; + soc_litedramcore_master_p1_cs_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cs_n = soc_litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n; + soc_litedramcore_master_p1_cs_n = soc_litedramcore_inti_p1_cs_n; end end always @(*) begin - litedramcore_master_p3_ras_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n; + soc_litedramcore_master_p1_ras_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_ras_n = soc_litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n; + soc_litedramcore_master_p1_ras_n = soc_litedramcore_inti_p1_ras_n; end end always @(*) begin - litedramcore_slave_p3_rddata = 32'd0; - if (litedramcore_sel) begin - litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata; + soc_litedramcore_slave_p1_rddata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata = soc_litedramcore_master_p1_rddata; end else begin end end always @(*) begin - litedramcore_master_p3_we_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n; + soc_litedramcore_master_p1_we_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_we_n = soc_litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n; + soc_litedramcore_master_p1_we_n = soc_litedramcore_inti_p1_we_n; end end always @(*) begin - litedramcore_slave_p3_rddata_valid = 1'd0; - if (litedramcore_sel) begin - litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + soc_litedramcore_slave_p1_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; end else begin end end always @(*) begin - litedramcore_master_p3_cke = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_cke = litedramcore_slave_p3_cke; + soc_litedramcore_master_p1_cke = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cke = soc_litedramcore_slave_p1_cke; end else begin - litedramcore_master_p3_cke = litedramcore_inti_p3_cke; + soc_litedramcore_master_p1_cke = soc_litedramcore_inti_p1_cke; end end always @(*) begin - litedramcore_master_p3_odt = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_odt = litedramcore_slave_p3_odt; + soc_litedramcore_master_p1_odt = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_odt = soc_litedramcore_slave_p1_odt; end else begin - litedramcore_master_p3_odt = litedramcore_inti_p3_odt; + soc_litedramcore_master_p1_odt = soc_litedramcore_inti_p1_odt; end end always @(*) begin - litedramcore_master_p3_reset_n = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n; + soc_litedramcore_master_p1_reset_n = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_reset_n = soc_litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n; + soc_litedramcore_master_p1_reset_n = soc_litedramcore_inti_p1_reset_n; end end always @(*) begin - litedramcore_master_p3_act_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n; + soc_litedramcore_master_p1_act_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_act_n = soc_litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n; + soc_litedramcore_master_p1_act_n = soc_litedramcore_inti_p1_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata = 32'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata; + soc_litedramcore_master_p1_wrdata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata = soc_litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata; + soc_litedramcore_master_p1_wrdata = soc_litedramcore_inti_p1_wrdata; end end always @(*) begin - litedramcore_inti_p0_rddata = 32'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p2_rddata = 32'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata; + soc_litedramcore_inti_p2_rddata = soc_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_master_p3_wrdata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en; + soc_litedramcore_master_p1_wrdata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en; + soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_inti_p1_wrdata_en; end end always @(*) begin - litedramcore_inti_p0_rddata_valid = 1'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p2_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; end end always @(*) begin - litedramcore_slave_p2_rddata = 32'd0; - if (litedramcore_sel) begin - litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; + soc_litedramcore_master_p0_ras_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n; end else begin + soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n; end end always @(*) begin - litedramcore_master_p3_wrdata_mask = 4'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask; + soc_litedramcore_master_p1_wrdata_mask = 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask; + soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_inti_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_rddata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en; + soc_litedramcore_master_p1_rddata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_rddata_en = soc_litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en; + soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en; end end always @(*) begin - litedramcore_master_p0_address = 14'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_address = litedramcore_slave_p0_address; + soc_litedramcore_master_p2_address = 14'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_address = soc_litedramcore_slave_p2_address; end else begin - litedramcore_master_p0_address = litedramcore_inti_p0_address; + soc_litedramcore_master_p2_address = soc_litedramcore_inti_p2_address; end end always @(*) begin - litedramcore_master_p0_bank = 3'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_bank = litedramcore_slave_p0_bank; + soc_litedramcore_master_p2_bank = 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_bank = soc_litedramcore_slave_p2_bank; end else begin - litedramcore_master_p0_bank = litedramcore_inti_p0_bank; + soc_litedramcore_master_p2_bank = soc_litedramcore_inti_p2_bank; end end always @(*) begin - litedramcore_master_p0_cas_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n; + soc_litedramcore_master_p2_cas_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cas_n = soc_litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n; + soc_litedramcore_master_p2_cas_n = soc_litedramcore_inti_p2_cas_n; end end always @(*) begin - litedramcore_master_p0_cs_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n; + soc_litedramcore_master_p2_cs_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cs_n = soc_litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n; + soc_litedramcore_master_p2_cs_n = soc_litedramcore_inti_p2_cs_n; end end always @(*) begin - litedramcore_slave_p0_rddata = 32'd0; - if (litedramcore_sel) begin - litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata; + soc_litedramcore_master_p2_ras_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_ras_n = soc_litedramcore_slave_p2_ras_n; end else begin + soc_litedramcore_master_p2_ras_n = soc_litedramcore_inti_p2_ras_n; end end always @(*) begin - litedramcore_master_p0_ras_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n; + soc_litedramcore_slave_p2_rddata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata = soc_litedramcore_master_p2_rddata; end else begin - litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_we_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n; + soc_litedramcore_master_p2_we_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_we_n = soc_litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n; + soc_litedramcore_master_p2_we_n = soc_litedramcore_inti_p2_we_n; end end always @(*) begin - litedramcore_slave_p0_rddata_valid = 1'd0; - if (litedramcore_sel) begin - litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + soc_litedramcore_slave_p2_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; end else begin end end always @(*) begin - litedramcore_master_p0_cke = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_cke = litedramcore_slave_p0_cke; + soc_litedramcore_master_p2_cke = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cke = soc_litedramcore_slave_p2_cke; end else begin - litedramcore_master_p0_cke = litedramcore_inti_p0_cke; + soc_litedramcore_master_p2_cke = soc_litedramcore_inti_p2_cke; end end always @(*) begin - litedramcore_master_p0_odt = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_odt = litedramcore_slave_p0_odt; + soc_litedramcore_master_p2_odt = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_odt = soc_litedramcore_slave_p2_odt; end else begin - litedramcore_master_p0_odt = litedramcore_inti_p0_odt; + soc_litedramcore_master_p2_odt = soc_litedramcore_inti_p2_odt; end end always @(*) begin - litedramcore_master_p0_reset_n = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n; + soc_litedramcore_master_p2_reset_n = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_reset_n = soc_litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n; + soc_litedramcore_master_p2_reset_n = soc_litedramcore_inti_p2_reset_n; end end always @(*) begin - litedramcore_master_p0_act_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n; + soc_litedramcore_master_p2_act_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_act_n = soc_litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n; + soc_litedramcore_master_p2_act_n = soc_litedramcore_inti_p2_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata = 32'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata; + soc_litedramcore_master_p2_wrdata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata = soc_litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata; + soc_litedramcore_master_p2_wrdata = soc_litedramcore_inti_p2_wrdata; end end always @(*) begin - litedramcore_inti_p1_rddata = 32'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p3_rddata = 32'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata; + soc_litedramcore_inti_p3_rddata = soc_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_master_p0_wrdata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en; + soc_litedramcore_master_p2_wrdata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en; + soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_inti_p2_wrdata_en; end end always @(*) begin - litedramcore_inti_p1_rddata_valid = 1'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p3_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + soc_litedramcore_inti_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; end end always @(*) begin - litedramcore_master_p0_wrdata_mask = 4'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask; + soc_litedramcore_master_p2_wrdata_mask = 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask; + soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_inti_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p0_rddata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en; + soc_litedramcore_master_p2_rddata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_rddata_en = soc_litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en; + soc_litedramcore_master_p2_rddata_en = soc_litedramcore_inti_p2_rddata_en; end end always @(*) begin - litedramcore_master_p1_address = 14'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_address = litedramcore_slave_p1_address; + soc_litedramcore_master_p3_address = 14'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_address = soc_litedramcore_slave_p3_address; end else begin - litedramcore_master_p1_address = litedramcore_inti_p1_address; + soc_litedramcore_master_p3_address = soc_litedramcore_inti_p3_address; end end always @(*) begin - litedramcore_master_p1_bank = 3'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_bank = litedramcore_slave_p1_bank; + soc_litedramcore_master_p3_bank = 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_bank = soc_litedramcore_slave_p3_bank; end else begin - litedramcore_master_p1_bank = litedramcore_inti_p1_bank; + soc_litedramcore_master_p3_bank = soc_litedramcore_inti_p3_bank; end end always @(*) begin - litedramcore_master_p1_cas_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n; + soc_litedramcore_master_p3_cas_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cas_n = soc_litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n; + soc_litedramcore_master_p3_cas_n = soc_litedramcore_inti_p3_cas_n; end end always @(*) begin - litedramcore_master_p1_cs_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; + soc_litedramcore_master_p3_cs_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cs_n = soc_litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; + soc_litedramcore_master_p3_cs_n = soc_litedramcore_inti_p3_cs_n; end end always @(*) begin - litedramcore_master_p1_ras_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; + soc_litedramcore_master_p3_ras_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_ras_n = soc_litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; + soc_litedramcore_master_p3_ras_n = soc_litedramcore_inti_p3_ras_n; end end always @(*) begin - litedramcore_slave_p1_rddata = 32'd0; - if (litedramcore_sel) begin - litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; + soc_litedramcore_slave_p3_rddata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata = soc_litedramcore_master_p3_rddata; end else begin end end always @(*) begin - litedramcore_master_p1_we_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; + soc_litedramcore_master_p3_we_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_we_n = soc_litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; + soc_litedramcore_master_p3_we_n = soc_litedramcore_inti_p3_we_n; end end always @(*) begin - litedramcore_slave_p1_rddata_valid = 1'd0; - if (litedramcore_sel) begin - litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + soc_litedramcore_slave_p3_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; end else begin end end always @(*) begin - litedramcore_master_p1_cke = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_cke = litedramcore_slave_p1_cke; + soc_litedramcore_master_p3_cke = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cke = soc_litedramcore_slave_p3_cke; end else begin - litedramcore_master_p1_cke = litedramcore_inti_p1_cke; + soc_litedramcore_master_p3_cke = soc_litedramcore_inti_p3_cke; end end always @(*) begin - litedramcore_master_p1_odt = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_odt = litedramcore_slave_p1_odt; + soc_litedramcore_master_p3_odt = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_odt = soc_litedramcore_slave_p3_odt; end else begin - litedramcore_master_p1_odt = litedramcore_inti_p1_odt; + soc_litedramcore_master_p3_odt = soc_litedramcore_inti_p3_odt; end end always @(*) begin - litedramcore_master_p1_reset_n = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; + soc_litedramcore_master_p3_reset_n = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_reset_n = soc_litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; + soc_litedramcore_master_p3_reset_n = soc_litedramcore_inti_p3_reset_n; end end always @(*) begin - litedramcore_master_p1_act_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; + soc_litedramcore_master_p3_act_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_act_n = soc_litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; + soc_litedramcore_master_p3_act_n = soc_litedramcore_inti_p3_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata = 32'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; + soc_litedramcore_master_p3_wrdata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata = soc_litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; + soc_litedramcore_master_p3_wrdata = soc_litedramcore_inti_p3_wrdata; end end always @(*) begin - litedramcore_inti_p2_rddata = 32'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p0_rddata = 32'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; + soc_litedramcore_inti_p0_rddata = soc_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_master_p1_wrdata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; + soc_litedramcore_master_p3_wrdata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; + soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_inti_p3_wrdata_en; end end always @(*) begin - litedramcore_inti_p2_rddata_valid = 1'd0; - if (litedramcore_sel) begin + soc_litedramcore_inti_p0_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin end else begin - litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + soc_litedramcore_inti_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_master_p1_wrdata_mask = 4'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; + soc_litedramcore_master_p3_wrdata_mask = 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; + soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_inti_p3_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_rddata_en = 1'd0; - if (litedramcore_sel) begin - litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; + soc_litedramcore_master_p3_rddata_en = 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_rddata_en = soc_litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; + soc_litedramcore_master_p3_rddata_en = soc_litedramcore_inti_p3_rddata_en; end end always @(*) begin - litedramcore_master_p2_address = 14'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_address = litedramcore_slave_p2_address; + soc_litedramcore_master_p0_address = 14'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_address = soc_litedramcore_slave_p0_address; end else begin - litedramcore_master_p2_address = litedramcore_inti_p2_address; + soc_litedramcore_master_p0_address = soc_litedramcore_inti_p0_address; end end always @(*) begin - litedramcore_master_p2_bank = 3'd0; - if (litedramcore_sel) begin - litedramcore_master_p2_bank = litedramcore_slave_p2_bank; + soc_litedramcore_master_p0_bank = 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_bank = soc_litedramcore_slave_p0_bank; end else begin - litedramcore_master_p2_bank = litedramcore_inti_p2_bank; + soc_litedramcore_master_p0_bank = soc_litedramcore_inti_p0_bank; end end always @(*) begin - litedramcore_master_p2_cas_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; + soc_litedramcore_master_p0_cas_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cas_n = soc_litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; + soc_litedramcore_master_p0_cas_n = soc_litedramcore_inti_p0_cas_n; end end always @(*) begin - litedramcore_master_p2_cs_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; + soc_litedramcore_master_p0_cs_n = 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cs_n = soc_litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; + soc_litedramcore_master_p0_cs_n = soc_litedramcore_inti_p0_cs_n; end end always @(*) begin - litedramcore_master_p2_ras_n = 1'd1; - if (litedramcore_sel) begin - litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; + soc_litedramcore_slave_p0_rddata = 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata = soc_litedramcore_master_p0_rddata; end else begin - litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; end end -assign litedramcore_inti_p0_cke = litedramcore_cke; -assign litedramcore_inti_p1_cke = litedramcore_cke; -assign litedramcore_inti_p2_cke = litedramcore_cke; -assign litedramcore_inti_p3_cke = litedramcore_cke; -assign litedramcore_inti_p0_odt = litedramcore_odt; -assign litedramcore_inti_p1_odt = litedramcore_odt; -assign litedramcore_inti_p2_odt = litedramcore_odt; -assign litedramcore_inti_p3_odt = litedramcore_odt; -assign litedramcore_inti_p0_reset_n = litedramcore_reset_n; -assign litedramcore_inti_p1_reset_n = litedramcore_reset_n; -assign litedramcore_inti_p2_reset_n = litedramcore_reset_n; -assign litedramcore_inti_p3_reset_n = litedramcore_reset_n; +assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; always @(*) begin - litedramcore_inti_p0_we_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); + soc_litedramcore_inti_p0_we_n = 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_we_n = (~soc_litedramcore_phaseinjector0_command_storage[1]); end else begin - litedramcore_inti_p0_we_n = 1'd1; + soc_litedramcore_inti_p0_we_n = 1'd1; end end always @(*) begin - litedramcore_inti_p0_cas_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]); + soc_litedramcore_inti_p0_cas_n = 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cas_n = (~soc_litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_inti_p0_cas_n = 1'd1; + soc_litedramcore_inti_p0_cas_n = 1'd1; end end always @(*) begin - litedramcore_inti_p0_cs_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + soc_litedramcore_inti_p0_cs_n = 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cs_n = {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_inti_p0_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p0_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_inti_p0_ras_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]); + soc_litedramcore_inti_p0_ras_n = 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_ras_n = (~soc_litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_inti_p0_ras_n = 1'd1; + soc_litedramcore_inti_p0_ras_n = 1'd1; end end -assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); -assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); -assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_inti_p0_wrdata_mask = 1'd0; +assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; +assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; +assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); +assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); +assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; +assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_inti_p1_we_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); + soc_litedramcore_inti_p1_we_n = 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_we_n = (~soc_litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_inti_p1_we_n = 1'd1; + soc_litedramcore_inti_p1_we_n = 1'd1; end end always @(*) begin - litedramcore_inti_p1_cas_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]); + soc_litedramcore_inti_p1_cas_n = 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cas_n = (~soc_litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_inti_p1_cas_n = 1'd1; + soc_litedramcore_inti_p1_cas_n = 1'd1; end end always @(*) begin - litedramcore_inti_p1_cs_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + soc_litedramcore_inti_p1_cs_n = 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cs_n = {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p1_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p1_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_inti_p1_ras_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]); + soc_litedramcore_inti_p1_ras_n = 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_ras_n = (~soc_litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_inti_p1_ras_n = 1'd1; + soc_litedramcore_inti_p1_ras_n = 1'd1; end end -assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); -assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); -assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_inti_p1_wrdata_mask = 1'd0; +assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; +assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; +assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); +assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); +assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; +assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_inti_p2_we_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); + soc_litedramcore_inti_p2_we_n = 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_we_n = (~soc_litedramcore_phaseinjector2_command_storage[1]); end else begin - litedramcore_inti_p2_we_n = 1'd1; + soc_litedramcore_inti_p2_we_n = 1'd1; end end always @(*) begin - litedramcore_inti_p2_cas_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]); + soc_litedramcore_inti_p2_cas_n = 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cas_n = (~soc_litedramcore_phaseinjector2_command_storage[2]); end else begin - litedramcore_inti_p2_cas_n = 1'd1; + soc_litedramcore_inti_p2_cas_n = 1'd1; end end always @(*) begin - litedramcore_inti_p2_cs_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + soc_litedramcore_inti_p2_cs_n = 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cs_n = {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p2_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p2_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_inti_p2_ras_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]); + soc_litedramcore_inti_p2_ras_n = 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_ras_n = (~soc_litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_inti_p2_ras_n = 1'd1; + soc_litedramcore_inti_p2_ras_n = 1'd1; end end -assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); -assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); -assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_inti_p2_wrdata_mask = 1'd0; +assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; +assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; +assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); +assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); +assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; +assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_inti_p3_we_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]); + soc_litedramcore_inti_p3_we_n = 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_we_n = (~soc_litedramcore_phaseinjector3_command_storage[1]); end else begin - litedramcore_inti_p3_we_n = 1'd1; + soc_litedramcore_inti_p3_we_n = 1'd1; end end always @(*) begin - litedramcore_inti_p3_cas_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]); + soc_litedramcore_inti_p3_cas_n = 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cas_n = (~soc_litedramcore_phaseinjector3_command_storage[2]); end else begin - litedramcore_inti_p3_cas_n = 1'd1; + soc_litedramcore_inti_p3_cas_n = 1'd1; end end always @(*) begin - litedramcore_inti_p3_cs_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + soc_litedramcore_inti_p3_cs_n = 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cs_n = {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p3_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p3_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_inti_p3_ras_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_ras_n = (~litedramcore_phaseinjector3_command_storage[3]); + soc_litedramcore_inti_p3_ras_n = 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_ras_n = (~soc_litedramcore_phaseinjector3_command_storage[3]); end else begin - litedramcore_inti_p3_ras_n = 1'd1; + soc_litedramcore_inti_p3_ras_n = 1'd1; end end -assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); -assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]); -assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_inti_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; +assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; +assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; +assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); +assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); +assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; +assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; +assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; +assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; +assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; +assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; +assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; +assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; +assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; +assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; +assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; +assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; +assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; +assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; +assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; +assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; +assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; +assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; +assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; +assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; +assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; +assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; +assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; +assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; +assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; +assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; +assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; +assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; +assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; +assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; +assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; +assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; +assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; +assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; +assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; +assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; +assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; +assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; +assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; +assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; +assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; +assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; +assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; +assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; +assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; +assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; +assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; +assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; +assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; +assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; +assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; +assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; +assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; +assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; +assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; +assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; +assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; +assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); +assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; +assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; +assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; +assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); +assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); +assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; +assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; +assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); +assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); +assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); +assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; +assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; always @(*) begin refresher_next_state = 2'd0; refresher_next_state = refresher_state; case (refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin + if (soc_litedramcore_cmd_ready) begin refresher_next_state = 2'd2; end end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin refresher_next_state = 2'd3; end else begin refresher_next_state = 1'd0; @@ -4486,13 +4539,13 @@ always @(*) begin end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin + if (soc_litedramcore_zqcs_executer_done) begin refresher_next_state = 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin + if (soc_litedramcore_wants_refresh) begin refresher_next_state = 1'd1; end end @@ -4500,178 +4553,178 @@ always @(*) begin endcase end always @(*) begin - litedramcore_cmd_valid = 1'd0; + soc_litedramcore_sequencer_start0 = 1'd0; case (refresher_state) 1'd1: begin - litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 = 1'd1; + end end 2'd2: begin - litedramcore_cmd_valid = 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid = 1'd0; - end - end end 2'd3: begin - litedramcore_cmd_valid = 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid = 1'd0; - end end default: begin end endcase end always @(*) begin - litedramcore_zqcs_executer_start = 1'd0; + soc_litedramcore_cmd_valid = 1'd0; case (refresher_state) 1'd1: begin + soc_litedramcore_cmd_valid = 1'd1; end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start = 1'd1; + soc_litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin end else begin + soc_litedramcore_cmd_valid = 1'd0; end end end 2'd3: begin + soc_litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid = 1'd0; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_last = 1'd0; + soc_litedramcore_zqcs_executer_start = 1'd0; case (refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start = 1'd1; end else begin - litedramcore_cmd_last = 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last = 1'd1; - end end default: begin end endcase end always @(*) begin - litedramcore_sequencer_start0 = 1'd0; + soc_litedramcore_cmd_last = 1'd0; case (refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 = 1'd1; - end end 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_last = 1'd1; + end + end end 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_last = 1'd1; + end end default: begin end endcase end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; +assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); +assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a = litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine0_cmd_payload_a = soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine0_cmd_payload_a = ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine0_cmd_payload_a = ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); +assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); +assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge = 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine0_auto_precharge = (litedramcore_bankmachine0_row_close == 1'd0); + soc_litedramcore_bankmachine0_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine0_auto_precharge = (soc_litedramcore_bankmachine0_row_close == 1'd0); end end end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); always @(*) begin bankmachine0_next_state = 4'd0; bankmachine0_next_state = bankmachine0_state; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin bankmachine0_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin bankmachine0_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin bankmachine0_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin + if ((~soc_litedramcore_bankmachine0_refresh_req)) begin bankmachine0_next_state = 1'd0; end end @@ -4688,13 +4741,13 @@ always @(*) begin bankmachine0_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (soc_litedramcore_bankmachine0_refresh_req) begin bankmachine0_next_state = 3'd4; end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin bankmachine0_next_state = 2'd2; end end else begin @@ -4709,9 +4762,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; case (bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -4728,13 +4784,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (soc_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready; + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; end else begin end end else begin @@ -4747,13 +4803,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -4766,37 +4825,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; case (bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -4811,19 +4859,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_valid = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -4836,12 +4878,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (soc_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -4852,16 +4897,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_open = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open = 1'd1; - end end 3'd4: begin end @@ -4874,22 +4916,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_row_close = 1'd0; + soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine0_row_close = 1'd1; end 3'd5: begin end @@ -4900,20 +4954,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready = soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin end @@ -4926,11 +4992,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid = soc_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4939,6 +5020,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -4949,34 +5033,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine0_cmd_valid = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; end end 3'd4: begin @@ -4990,20 +5062,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine0_row_open = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd1; - end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_open = 1'd1; + end end 3'd4: begin end @@ -5016,41 +5100,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine0_row_close = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; - end + soc_litedramcore_bankmachine0_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine0_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine0_row_close = 1'd1; end 3'd5: begin end @@ -5065,7 +5130,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -5084,15 +5149,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (soc_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -5103,13 +5165,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; case (bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -5122,115 +5190,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; +assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); +assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a = litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine1_cmd_payload_a = soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine1_cmd_payload_a = ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine1_cmd_payload_a = ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); +assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); +assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge = 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine1_auto_precharge = (litedramcore_bankmachine1_row_close == 1'd0); + soc_litedramcore_bankmachine1_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine1_auto_precharge = (soc_litedramcore_bankmachine1_row_close == 1'd0); end end end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); always @(*) begin bankmachine1_next_state = 4'd0; bankmachine1_next_state = bankmachine1_state; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin bankmachine1_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin bankmachine1_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin bankmachine1_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin + if ((~soc_litedramcore_bankmachine1_refresh_req)) begin bankmachine1_next_state = 1'd0; end end @@ -5247,13 +5300,13 @@ always @(*) begin bankmachine1_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin bankmachine1_next_state = 3'd4; end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin bankmachine1_next_state = 2'd2; end end else begin @@ -5268,9 +5321,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -5287,13 +5343,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready; + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; end else begin end end else begin @@ -5306,13 +5362,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -5325,37 +5384,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5370,19 +5418,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -5395,12 +5437,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -5411,16 +5456,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_open = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open = 1'd1; - end end 3'd4: begin end @@ -5433,22 +5475,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_row_close = 1'd0; + soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; case (bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close = 1'd1; end 3'd5: begin end @@ -5459,11 +5513,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready = soc_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5482,12 +5551,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas = 1'd1; + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid = soc_litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -5498,21 +5570,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -5527,16 +5596,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine1_cmd_valid = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd1; + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -5549,15 +5621,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd1; - end else begin - end + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; end else begin end end else begin @@ -5568,22 +5637,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine1_row_open = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_open = 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5598,18 +5663,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine1_row_close = 1'd0; case (bankmachine1_state) 1'd1: begin + soc_litedramcore_bankmachine1_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine1_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine1_row_close = 1'd1; end 3'd5: begin end @@ -5624,7 +5689,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5643,15 +5708,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (soc_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -5662,13 +5724,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -5681,115 +5749,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a = litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a = soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine2_cmd_payload_a = ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine2_cmd_payload_a = ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); +assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge = 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine2_auto_precharge = (litedramcore_bankmachine2_row_close == 1'd0); + soc_litedramcore_bankmachine2_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine2_auto_precharge = (soc_litedramcore_bankmachine2_row_close == 1'd0); end end end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); always @(*) begin bankmachine2_next_state = 4'd0; bankmachine2_next_state = bankmachine2_state; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin bankmachine2_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin bankmachine2_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin bankmachine2_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin + if ((~soc_litedramcore_bankmachine2_refresh_req)) begin bankmachine2_next_state = 1'd0; end end @@ -5806,13 +5859,13 @@ always @(*) begin bankmachine2_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (soc_litedramcore_bankmachine2_refresh_req) begin bankmachine2_next_state = 3'd4; end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin bankmachine2_next_state = 2'd2; end end else begin @@ -5827,9 +5880,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -5846,13 +5902,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (soc_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready; + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; end else begin end end else begin @@ -5865,13 +5921,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -5884,37 +5943,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5929,7 +5977,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5938,9 +5986,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -5951,23 +5996,32 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid = 1'd0; - case (bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -5980,12 +6034,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (soc_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -5996,16 +6053,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_open = 1'd0; + soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open = 1'd1; - end end 3'd4: begin end @@ -6018,22 +6072,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready = soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_row_close = 1'd0; + soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close = 1'd1; end 3'd5: begin end @@ -6044,11 +6110,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid = soc_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6057,6 +6138,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -6067,34 +6151,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine2_cmd_valid = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; end end 3'd4: begin @@ -6108,20 +6180,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine2_row_open = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd1; - end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_open = 1'd1; + end end 3'd4: begin end @@ -6134,41 +6218,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine2_row_close = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; - end + soc_litedramcore_bankmachine2_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine2_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine2_row_close = 1'd1; end 3'd5: begin end @@ -6183,7 +6248,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6202,15 +6267,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (soc_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -6221,13 +6283,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -6240,115 +6308,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; +assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); +assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a = litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine3_cmd_payload_a = soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine3_cmd_payload_a = ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine3_cmd_payload_a = ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); +assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge = 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine3_auto_precharge = (litedramcore_bankmachine3_row_close == 1'd0); + soc_litedramcore_bankmachine3_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine3_auto_precharge = (soc_litedramcore_bankmachine3_row_close == 1'd0); end end end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); always @(*) begin bankmachine3_next_state = 4'd0; bankmachine3_next_state = bankmachine3_state; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin bankmachine3_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin bankmachine3_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin bankmachine3_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin + if ((~soc_litedramcore_bankmachine3_refresh_req)) begin bankmachine3_next_state = 1'd0; end end @@ -6365,13 +6418,13 @@ always @(*) begin bankmachine3_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (soc_litedramcore_bankmachine3_refresh_req) begin bankmachine3_next_state = 3'd4; end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin bankmachine3_next_state = 2'd2; end end else begin @@ -6386,9 +6439,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -6405,13 +6461,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (soc_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready; + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; end else begin end end else begin @@ -6424,13 +6480,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -6443,37 +6502,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -6488,19 +6536,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -6513,12 +6555,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (soc_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -6529,16 +6574,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin end @@ -6551,20 +6593,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_row_open = 1'd0; + soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open = 1'd1; - end end 3'd4: begin end @@ -6577,22 +6631,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready = soc_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_row_close = 1'd0; + soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close = 1'd1; end 3'd5: begin end @@ -6603,11 +6669,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid = soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6616,6 +6697,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -6626,34 +6710,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine3_cmd_valid = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; end end 3'd4: begin @@ -6667,20 +6739,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine3_row_open = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd1; - end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open = 1'd1; + end end 3'd4: begin end @@ -6693,41 +6777,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine3_row_close = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; - end + soc_litedramcore_bankmachine3_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine3_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine3_row_close = 1'd1; end 3'd5: begin end @@ -6742,7 +6807,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6761,15 +6826,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (soc_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -6780,13 +6842,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -6799,115 +6867,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a = litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine4_cmd_payload_a = soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine4_cmd_payload_a = ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine4_cmd_payload_a = ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); +assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge = 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine4_auto_precharge = (litedramcore_bankmachine4_row_close == 1'd0); + soc_litedramcore_bankmachine4_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine4_auto_precharge = (soc_litedramcore_bankmachine4_row_close == 1'd0); end end end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); always @(*) begin bankmachine4_next_state = 4'd0; bankmachine4_next_state = bankmachine4_state; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin bankmachine4_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin bankmachine4_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin bankmachine4_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin + if ((~soc_litedramcore_bankmachine4_refresh_req)) begin bankmachine4_next_state = 1'd0; end end @@ -6924,13 +6977,13 @@ always @(*) begin bankmachine4_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (soc_litedramcore_bankmachine4_refresh_req) begin bankmachine4_next_state = 3'd4; end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin bankmachine4_next_state = 2'd2; end end else begin @@ -6945,9 +6998,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -6964,13 +7020,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (soc_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready; + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; end else begin end end else begin @@ -6983,13 +7039,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -7002,37 +7061,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -7047,19 +7095,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -7072,12 +7114,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (soc_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -7088,16 +7133,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open = 1'd1; - end end 3'd4: begin end @@ -7110,22 +7152,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_row_close = 1'd0; + soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close = 1'd1; end 3'd5: begin end @@ -7136,11 +7190,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready = soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7159,12 +7228,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (soc_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid = soc_litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -7175,21 +7247,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -7204,16 +7273,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine4_cmd_valid = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd1; + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -7226,15 +7298,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (soc_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd1; - end else begin - end + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; end else begin end end else begin @@ -7245,22 +7314,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine4_row_open = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_open = 1'd1; end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -7275,15 +7340,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine4_row_close = 1'd0; case (bankmachine4_state) 1'd1: begin + soc_litedramcore_bankmachine4_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine4_row_close = 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine4_row_close = 1'd1; end 3'd5: begin end @@ -7294,35 +7362,17 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin end @@ -7335,17 +7385,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -7358,115 +7426,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; +assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); +assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a = litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine5_cmd_payload_a = soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine5_cmd_payload_a = ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine5_cmd_payload_a = ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); +assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge = 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine5_auto_precharge = (litedramcore_bankmachine5_row_close == 1'd0); + soc_litedramcore_bankmachine5_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine5_auto_precharge = (soc_litedramcore_bankmachine5_row_close == 1'd0); end end end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); always @(*) begin bankmachine5_next_state = 4'd0; bankmachine5_next_state = bankmachine5_state; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin bankmachine5_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin bankmachine5_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin bankmachine5_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin + if ((~soc_litedramcore_bankmachine5_refresh_req)) begin bankmachine5_next_state = 1'd0; end end @@ -7483,13 +7536,13 @@ always @(*) begin bankmachine5_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (soc_litedramcore_bankmachine5_refresh_req) begin bankmachine5_next_state = 3'd4; end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin bankmachine5_next_state = 2'd2; end end else begin @@ -7504,16 +7557,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin end @@ -7526,17 +7579,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -7549,34 +7620,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -7587,26 +7650,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7615,9 +7663,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -7628,23 +7673,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -7657,12 +7711,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (soc_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -7673,16 +7730,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_open = 1'd0; + soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open = 1'd1; - end end 3'd4: begin end @@ -7695,22 +7749,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready = soc_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_row_close = 1'd0; + soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; case (bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close = 1'd1; end 3'd5: begin end @@ -7721,11 +7787,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid = soc_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7734,6 +7815,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -7744,34 +7828,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine5_cmd_valid = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; end end 3'd4: begin @@ -7785,20 +7857,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine5_row_open = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd1; - end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_open = 1'd1; + end end 3'd4: begin end @@ -7811,41 +7895,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine5_row_close = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; - end + soc_litedramcore_bankmachine5_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine5_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine5_row_close = 1'd1; end 3'd5: begin end @@ -7860,7 +7925,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7879,15 +7944,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (soc_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -7898,13 +7960,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -7917,115 +7985,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a = litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine6_cmd_payload_a = soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine6_cmd_payload_a = ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine6_cmd_payload_a = ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); +assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge = 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine6_auto_precharge = (litedramcore_bankmachine6_row_close == 1'd0); + soc_litedramcore_bankmachine6_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine6_auto_precharge = (soc_litedramcore_bankmachine6_row_close == 1'd0); end end end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); always @(*) begin bankmachine6_next_state = 4'd0; bankmachine6_next_state = bankmachine6_state; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin bankmachine6_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin bankmachine6_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin bankmachine6_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin bankmachine6_next_state = 1'd0; end end @@ -8042,13 +8095,13 @@ always @(*) begin bankmachine6_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (soc_litedramcore_bankmachine6_refresh_req) begin bankmachine6_next_state = 3'd4; end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin bankmachine6_next_state = 2'd2; end end else begin @@ -8063,9 +8116,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -8082,13 +8138,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (soc_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; end else begin end end else begin @@ -8101,13 +8157,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -8120,37 +8179,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8165,19 +8213,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -8190,12 +8232,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (soc_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -8206,16 +8251,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin end @@ -8228,20 +8270,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_row_open = 1'd0; + soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open = 1'd1; - end end 3'd4: begin end @@ -8254,22 +8308,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready = soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_row_close = 1'd0; + soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine6_row_close = 1'd1; end 3'd5: begin end @@ -8280,11 +8346,26 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid = soc_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8293,6 +8374,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -8303,34 +8387,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine6_cmd_valid = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; end end 3'd4: begin @@ -8344,20 +8416,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine6_row_open = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd1; - end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_open = 1'd1; + end end 3'd4: begin end @@ -8370,41 +8454,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine6_row_close = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; - end + soc_litedramcore_bankmachine6_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine6_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine6_row_close = 1'd1; end 3'd5: begin end @@ -8419,7 +8484,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8438,15 +8503,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (soc_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; - end + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -8457,13 +8519,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -8476,115 +8544,100 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; +assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); +assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a = 14'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a = litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; + if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine7_cmd_payload_a = soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end else begin - litedramcore_bankmachine7_cmd_payload_a = ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine7_cmd_payload_a = ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); +assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge = 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine7_auto_precharge = (litedramcore_bankmachine7_row_close == 1'd0); + soc_litedramcore_bankmachine7_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine7_auto_precharge = (soc_litedramcore_bankmachine7_row_close == 1'd0); end end end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); always @(*) begin bankmachine7_next_state = 4'd0; bankmachine7_next_state = bankmachine7_state; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin bankmachine7_next_state = 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin bankmachine7_next_state = 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin bankmachine7_next_state = 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin + if ((~soc_litedramcore_bankmachine7_refresh_req)) begin bankmachine7_next_state = 1'd0; end end @@ -8601,13 +8654,13 @@ always @(*) begin bankmachine7_next_state = 1'd0; end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin bankmachine7_next_state = 3'd4; end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin bankmachine7_next_state = 2'd2; end end else begin @@ -8622,9 +8675,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -8641,13 +8697,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready; + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; end else begin end end else begin @@ -8660,13 +8716,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -8679,37 +8738,26 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt = 1'd1; - end + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8724,19 +8772,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -8749,12 +8791,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + end end else begin end end else begin @@ -8765,16 +8810,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open = 1'd1; - end end 3'd4: begin end @@ -8787,22 +8829,34 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_row_close = 1'd0; + soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close = 1'd1; end 3'd5: begin end @@ -8813,37 +8867,26 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready = soc_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8862,12 +8905,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas = 1'd1; + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid = soc_litedramcore_bankmachine7_cmd_ready; + end end else begin end end else begin @@ -8878,21 +8924,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -8907,16 +8950,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine7_cmd_valid = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd1; + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -8929,15 +8975,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd1; - end else begin - end + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; end else begin end end else begin @@ -8948,22 +8991,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine7_row_open = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open = 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8978,15 +9017,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine7_row_close = 1'd0; case (bankmachine7_state) 1'd1: begin + soc_litedramcore_bankmachine7_row_close = 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine7_row_close = 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine7_row_close = 1'd1; end 3'd5: begin end @@ -8997,26 +9039,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9035,15 +9062,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (soc_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; - end else begin - end + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -9053,214 +9077,243 @@ always @(*) begin end endcase end -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids = 8'd0; - litedramcore_choose_cmd_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); +assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); +assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; +assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); +assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); +assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); +assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); +assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); +assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); +assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +always @(*) begin + soc_litedramcore_choose_cmd_valids = 8'd0; + soc_litedramcore_choose_cmd_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; +assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas = 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0; + soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras = 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1; + soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we = 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2; + soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready = 1'd1; + soc_litedramcore_bankmachine0_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready = 1'd1; + soc_litedramcore_bankmachine1_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready = 1'd1; + soc_litedramcore_bankmachine2_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready = 1'd1; + soc_litedramcore_bankmachine3_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready = 1'd1; + soc_litedramcore_bankmachine4_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready = 1'd1; + soc_litedramcore_bankmachine5_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready = 1'd1; + soc_litedramcore_bankmachine6_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready = 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready = 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready = 1'd1; + soc_litedramcore_bankmachine7_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready = 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready = 1'd1; + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready = 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids = 8'd0; - litedramcore_choose_req_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids = 8'd0; + soc_litedramcore_choose_req_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; +assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign soc_litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas = 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas = t_array_muxed3; + soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_cas = t_array_muxed3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras = 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras = t_array_muxed4; + soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_ras = t_array_muxed4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we = 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we = t_array_muxed5; + soc_litedramcore_choose_req_cmd_payload_we = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_we = t_array_muxed5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); +assign soc_litedramcore_dfi_p0_reset_n = 1'd1; +assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; +assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; +assign soc_litedramcore_dfi_p1_reset_n = 1'd1; +assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; +assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; +assign soc_litedramcore_dfi_p2_reset_n = 1'd1; +assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; +assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; +assign soc_litedramcore_dfi_p3_reset_n = 1'd1; +assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; +assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; +assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); always @(*) begin multiplexer_next_state = 4'd0; multiplexer_next_state = multiplexer_state; case (multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + if (soc_litedramcore_read_available) begin + if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin multiplexer_next_state = 2'd3; end end - if (litedramcore_go_to_refresh) begin + if (soc_litedramcore_go_to_refresh) begin multiplexer_next_state = 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin + if (soc_litedramcore_cmd_last) begin multiplexer_next_state = 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin + if (soc_litedramcore_twtrcon_ready) begin multiplexer_next_state = 1'd0; end end @@ -9283,33 +9336,34 @@ always @(*) begin multiplexer_next_state = 4'd10; end 4'd10: begin - multiplexer_next_state = 4'd11; - end - 4'd11: begin multiplexer_next_state = 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + if (soc_litedramcore_write_available) begin + if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin multiplexer_next_state = 3'd4; end end - if (litedramcore_go_to_refresh) begin + if (soc_litedramcore_go_to_refresh) begin multiplexer_next_state = 2'd2; end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates = 1'd0; + soc_litedramcore_steerer_sel0 = 2'd0; case (multiplexer_state) 1'd1: begin + soc_litedramcore_steerer_sel0 = 1'd0; if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + soc_litedramcore_steerer_sel0 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 1'd1; end end 2'd2: begin + soc_litedramcore_steerer_sel0 = 2'd3; end 2'd3: begin end @@ -9327,21 +9381,28 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin - end default: begin + soc_litedramcore_steerer_sel0 = 1'd0; if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + soc_litedramcore_steerer_sel0 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel3 = 2'd0; + soc_litedramcore_steerer_sel1 = 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 = 2'd2; + soc_litedramcore_steerer_sel1 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 1'd1; + end end 2'd2: begin end @@ -9361,17 +9422,66 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin + default: begin + soc_litedramcore_steerer_sel1 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel1 = 1'd1; + end + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel2 = 2'd0; + case (multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel2 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel2 = 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel2 = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - litedramcore_steerer_sel3 = 1'd0; + soc_litedramcore_steerer_sel2 = 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel2 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel2 = 1'd1; + end end endcase end always @(*) begin - litedramcore_en0 = 1'd0; + soc_litedramcore_choose_cmd_want_activates = 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -9391,20 +9501,61 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel3 = 2'd0; + case (multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel3 = 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel3 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - litedramcore_en0 = 1'd1; + soc_litedramcore_steerer_sel3 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 1'd1; + end end endcase end always @(*) begin - litedramcore_cmd_ready = 1'd0; + soc_litedramcore_en0 = 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready = 1'd1; end 2'd3: begin end @@ -9422,19 +9573,46 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin + default: begin + soc_litedramcore_en0 = 1'd1; + end + endcase +end +always @(*) begin + soc_litedramcore_cmd_ready = 1'd0; + case (multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_litedramcore_cmd_ready = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready = 1'd0; + soc_litedramcore_choose_cmd_cmd_ready = 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); end end 2'd2: begin @@ -9455,18 +9633,16 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin - end default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_req_want_reads = 1'd0; + soc_litedramcore_choose_req_want_reads = 1'd0; case (multiplexer_state) 1'd1: begin end @@ -9488,18 +9664,16 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin - end default: begin - litedramcore_choose_req_want_reads = 1'd1; + soc_litedramcore_choose_req_want_reads = 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes = 1'd0; + soc_litedramcore_en1 = 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes = 1'd1; + soc_litedramcore_en1 = 1'd1; end 2'd2: begin end @@ -9519,20 +9693,46 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_choose_req_want_writes = 1'd0; + case (multiplexer_state) + 1'd1: begin + soc_litedramcore_choose_req_want_writes = 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready = 1'd0; + soc_litedramcore_choose_req_cmd_ready = 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; end end 2'd2: begin @@ -9553,886 +9753,1547 @@ always @(*) begin end 4'd10: begin end - 4'd11: begin - end default: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; + end + end + endcase +end +assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); +assign soc_litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign soc_litedramcore_interface_bank0_we = rhs_array_muxed13; +assign soc_litedramcore_interface_bank0_valid = rhs_array_muxed14; +assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); +assign soc_litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign soc_litedramcore_interface_bank1_we = rhs_array_muxed16; +assign soc_litedramcore_interface_bank1_valid = rhs_array_muxed17; +assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); +assign soc_litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign soc_litedramcore_interface_bank2_we = rhs_array_muxed19; +assign soc_litedramcore_interface_bank2_valid = rhs_array_muxed20; +assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); +assign soc_litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign soc_litedramcore_interface_bank3_we = rhs_array_muxed22; +assign soc_litedramcore_interface_bank3_valid = rhs_array_muxed23; +assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); +assign soc_litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign soc_litedramcore_interface_bank4_we = rhs_array_muxed25; +assign soc_litedramcore_interface_bank4_valid = rhs_array_muxed26; +assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); +assign soc_litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign soc_litedramcore_interface_bank5_we = rhs_array_muxed28; +assign soc_litedramcore_interface_bank5_valid = rhs_array_muxed29; +assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); +assign soc_litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign soc_litedramcore_interface_bank6_we = rhs_array_muxed31; +assign soc_litedramcore_interface_bank6_valid = rhs_array_muxed32; +assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); +assign soc_litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign soc_litedramcore_interface_bank7_we = rhs_array_muxed34; +assign soc_litedramcore_interface_bank7_valid = rhs_array_muxed35; +assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); +assign soc_user_port_wdata_ready = new_master_wdata_ready1; +assign soc_user_port_rdata_valid = new_master_rdata_valid8; +always @(*) begin + soc_litedramcore_interface_wdata_we = 16'd0; + case ({new_master_wdata_ready1}) + 1'd1: begin + soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we; + end + default: begin + soc_litedramcore_interface_wdata_we = 1'd0; + end + endcase +end +always @(*) begin + soc_litedramcore_interface_wdata = 128'd0; + case ({new_master_wdata_ready1}) + 1'd1: begin + soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data; + end + default: begin + soc_litedramcore_interface_wdata = 1'd0; + end + endcase +end +assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; +always @(*) begin + next_state = 2'd0; + next_state = state; + case (state) + 1'd1: begin + next_state = 2'd2; + end + 2'd2: begin + next_state = 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state = 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 = 1'd0; + case (state) + 1'd1: begin + litedramcore_adr_next_value_ce1 = 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 = 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 = 1'd0; + case (state) + 1'd1: begin + litedramcore_we_next_value2 = 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 = 1'd0; + case (state) + 1'd1: begin + litedramcore_we_next_value_ce2 = 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 = 1'd1; end end endcase end always @(*) begin - litedramcore_en1 = 1'd0; - case (multiplexer_state) - 1'd1: begin - litedramcore_en1 = 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - default: begin - end - endcase + litedramcore_wishbone_dat_r = 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r = litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 = 8'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 = litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 = 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 = 1'd1; + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack = 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack = 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 = 14'd0; + case (state) + 1'd1: begin + litedramcore_adr_next_value1 = 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 = litedramcore_wishbone_adr; + end + end + endcase +end +assign litedramcore_wishbone_adr = soc_wb_bus_adr; +assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; +assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = soc_wb_bus_sel; +assign litedramcore_wishbone_cyc = soc_wb_bus_cyc; +assign litedramcore_wishbone_stb = soc_wb_bus_stb; +assign soc_wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = soc_wb_bus_we; +assign litedramcore_wishbone_cti = soc_wb_bus_cti; +assign litedramcore_wishbone_bte = soc_wb_bus_bte; +assign soc_wb_bus_err = litedramcore_wishbone_err; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_done0_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we = (~interface0_bank_bus_we); + end +end +always @(*) begin + csrbank0_init_done0_re = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re = interface0_bank_bus_we; + end +end +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_error0_re = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re = interface0_bank_bus_we; + end +end +always @(*) begin + csrbank0_init_error0_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we = (~interface0_bank_bus_we); + end +end +assign csrbank0_init_done0_w = soc_init_done_storage; +assign csrbank0_init_error0_w = soc_init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank1_dfii_control0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_control0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi0_command0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_command0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we); + end +end +assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_re = interface1_bank_bus_we; + end +end +always @(*) begin + soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi0_address1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_address1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_address0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_address0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_address0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_address0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank1_dfii_pi0_baddress0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_baddress0_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_baddress0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_baddress0_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_wrdata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_wrdata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_wrdata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi0_wrdata2_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_wrdata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi0_wrdata2_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_wrdata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_dfii_pi0_wrdata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_wrdata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_dfii_pi0_wrdata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_wrdata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi0_wrdata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_wrdata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi0_wrdata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_rddata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_rddata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_rddata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi0_rddata2_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_rddata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi0_rddata2_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_rddata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi0_rddata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi0_rddata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi0_rddata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi0_rddata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi0_rddata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi1_command0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_command0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we); + end +end +assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + soc_litedramcore_phaseinjector1_command_issue_re = interface1_bank_bus_we; + end +end +always @(*) begin + soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + soc_litedramcore_phaseinjector1_command_issue_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi1_address1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi1_address1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_address1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi1_address1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_address0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi1_address0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_address0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi1_address0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank1_dfii_pi1_baddress0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi1_baddress0_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_baddress0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi1_baddress0_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_wrdata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_wrdata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_wrdata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + csrbank1_dfii_pi1_wrdata2_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_wrdata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + csrbank1_dfii_pi1_wrdata2_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_wrdata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi1_wrdata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_wrdata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi1_wrdata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_wrdata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi1_wrdata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_wrdata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi1_wrdata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_rddata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_rddata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_rddata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi1_rddata2_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_rddata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi1_rddata2_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_rddata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin + csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi1_rddata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin + csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi1_rddata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin + csrbank1_dfii_pi1_rddata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi1_rddata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin + csrbank1_dfii_pi1_rddata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi2_command0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin + csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_command0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin + csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we); + end +end +assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin + soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin + soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi2_address1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin + csrbank1_dfii_pi2_address1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_address1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin + csrbank1_dfii_pi2_address1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_address0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin + csrbank1_dfii_pi2_address0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_address0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin + csrbank1_dfii_pi2_address0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank1_dfii_pi2_baddress0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin + csrbank1_dfii_pi2_baddress0_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_baddress0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin + csrbank1_dfii_pi2_baddress0_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_wrdata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin + csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_wrdata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin + csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_wrdata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin + csrbank1_dfii_pi2_wrdata2_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_wrdata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin + csrbank1_dfii_pi2_wrdata2_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_wrdata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin + csrbank1_dfii_pi2_wrdata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_wrdata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin + csrbank1_dfii_pi2_wrdata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_wrdata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin + csrbank1_dfii_pi2_wrdata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_wrdata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin + csrbank1_dfii_pi2_wrdata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_rddata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin + csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_rddata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin + csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_rddata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin + csrbank1_dfii_pi2_rddata2_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_rddata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin + csrbank1_dfii_pi2_rddata2_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_rddata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin + csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi2_rddata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin + csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi2_rddata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin + csrbank1_dfii_pi2_rddata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi2_rddata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin + csrbank1_dfii_pi2_rddata0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi3_command0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin + csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi3_command0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin + csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we); + end +end +assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin + soc_litedramcore_phaseinjector3_command_issue_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin + soc_litedramcore_phaseinjector3_command_issue_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank1_dfii_pi3_address1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin + csrbank1_dfii_pi3_address1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi3_address1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin + csrbank1_dfii_pi3_address1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_address0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin + csrbank1_dfii_pi3_address0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi3_address0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin + csrbank1_dfii_pi3_address0_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank1_dfii_pi3_baddress0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin + csrbank1_dfii_pi3_baddress0_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi3_baddress0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin + csrbank1_dfii_pi3_baddress0_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_wrdata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin + csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi3_wrdata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin + csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_wrdata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin + csrbank1_dfii_pi3_wrdata2_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi3_wrdata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin + csrbank1_dfii_pi3_wrdata2_we = (~interface1_bank_bus_we); + end +end +assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_wrdata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin + csrbank1_dfii_pi3_wrdata1_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi3_wrdata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin + csrbank1_dfii_pi3_wrdata1_re = interface1_bank_bus_we; + end end +assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - litedramcore_steerer_sel0 = 2'd0; - case (multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 = 1'd0; - end - 2'd2: begin - litedramcore_steerer_sel0 = 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - default: begin - litedramcore_steerer_sel0 = 1'd0; - end - endcase + csrbank1_dfii_pi3_wrdata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin + csrbank1_dfii_pi3_wrdata0_re = interface1_bank_bus_we; + end end always @(*) begin - litedramcore_steerer_sel1 = 2'd0; - case (multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 = 1'd0; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - default: begin - litedramcore_steerer_sel1 = 1'd1; - end - endcase + csrbank1_dfii_pi3_wrdata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin + csrbank1_dfii_pi3_wrdata0_we = (~interface1_bank_bus_we); + end end +assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - litedramcore_steerer_sel2 = 2'd0; - case (multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 = 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - default: begin - litedramcore_steerer_sel2 = 2'd2; - end - endcase + csrbank1_dfii_pi3_rddata3_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin + csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we; + end end -assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = new_master_wdata_ready2; -assign user_port_rdata_valid = new_master_rdata_valid9; always @(*) begin - litedramcore_interface_wdata = 128'd0; - case ({new_master_wdata_ready2}) - 1'd1: begin - litedramcore_interface_wdata = user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata = 1'd0; - end - endcase + csrbank1_dfii_pi3_rddata3_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin + csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we); + end end +assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - litedramcore_interface_wdata_we = 16'd0; - case ({new_master_wdata_ready2}) - 1'd1: begin - litedramcore_interface_wdata_we = user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we = 1'd0; - end - endcase + csrbank1_dfii_pi3_rddata2_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin + csrbank1_dfii_pi3_rddata2_we = (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dfii_pi3_rddata2_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin + csrbank1_dfii_pi3_rddata2_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_rddata1_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin + csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we); + end end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign roundrobin0_grant = 1'd0; -assign roundrobin1_grant = 1'd0; -assign roundrobin2_grant = 1'd0; -assign roundrobin3_grant = 1'd0; -assign roundrobin4_grant = 1'd0; -assign roundrobin5_grant = 1'd0; -assign roundrobin6_grant = 1'd0; -assign roundrobin7_grant = 1'd0; -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; -assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0)); -assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0)); -assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1)); -assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1)); -assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2)); -assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3)); -assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3)); -assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4)); -assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4)); -assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5)); -assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5)); -assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6)); -assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6)); -assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7)); -assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7)); -assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8)); -assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9)); -assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9)); -assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10)); -assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10)); -assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11)); -assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11)); -assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12)); -assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12)); -assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13)); -assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13)); -assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14)); -assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15)); -assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15)); -assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16)); -assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16)); -assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17)); -assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17)); -assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18)); -assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18)); -assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19)); -assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19)); -assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20)); -assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21)); -assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21)); -assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22)); -assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22)); -assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23)); -assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23)); -assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24)); -assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24)); -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank1_dfii_control0_w = litedramcore_storage[3:0]; -assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; -assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; -assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we; -assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; -assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; -assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we; -assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; -assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; -assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we; -assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; -assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; -assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we; -assign adr = litedramcore_adr; -assign we = litedramcore_we; -assign dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = dat_r; -assign interface0_bank_bus_adr = adr; -assign interface1_bank_bus_adr = adr; -assign interface0_bank_bus_we = we; -assign interface1_bank_bus_we = we; -assign interface0_bank_bus_dat_w = dat_w; -assign interface1_bank_bus_dat_w = dat_w; -assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r); -assign slice_proxy0 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_write_col); -assign slice_proxy1 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_read_col); -assign slice_proxy2 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_write_col); -assign slice_proxy3 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_read_col); -assign slice_proxy4 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_write_col); -assign slice_proxy5 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_read_col); -assign slice_proxy6 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_write_col); -assign slice_proxy7 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_read_col); -assign slice_proxy8 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_write_col); -assign slice_proxy9 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_read_col); -assign slice_proxy10 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_write_col); -assign slice_proxy11 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_read_col); -assign slice_proxy12 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_write_col); -assign slice_proxy13 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_read_col); -assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col); -assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col); +always @(*) begin + csrbank1_dfii_pi3_rddata1_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin + csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we; + end +end +assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank1_dfii_pi3_rddata0_re = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin + csrbank1_dfii_pi3_rddata0_re = interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_dfii_pi3_rddata0_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin + csrbank1_dfii_pi3_rddata0_we = (~interface1_bank_bus_we); + end +end +assign soc_litedramcore_sel = soc_litedramcore_storage[0]; +assign soc_litedramcore_cke = soc_litedramcore_storage[1]; +assign soc_litedramcore_odt = soc_litedramcore_storage[2]; +assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; +assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0]; +assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; +assign csrbank1_dfii_pi0_address1_w = soc_litedramcore_phaseinjector0_address_storage[13:8]; +assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank1_dfii_pi0_wrdata3_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign csrbank1_dfii_pi0_wrdata2_w = soc_litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign csrbank1_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign csrbank1_dfii_pi0_rddata3_w = soc_litedramcore_phaseinjector0_rddata_status[31:24]; +assign csrbank1_dfii_pi0_rddata2_w = soc_litedramcore_phaseinjector0_rddata_status[23:16]; +assign csrbank1_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_rddata_status[15:8]; +assign csrbank1_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_rddata_status[7:0]; +assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata0_we; +assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; +assign csrbank1_dfii_pi1_address1_w = soc_litedramcore_phaseinjector1_address_storage[13:8]; +assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank1_dfii_pi1_wrdata3_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign csrbank1_dfii_pi1_wrdata2_w = soc_litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign csrbank1_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign csrbank1_dfii_pi1_rddata3_w = soc_litedramcore_phaseinjector1_rddata_status[31:24]; +assign csrbank1_dfii_pi1_rddata2_w = soc_litedramcore_phaseinjector1_rddata_status[23:16]; +assign csrbank1_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_rddata_status[15:8]; +assign csrbank1_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_rddata_status[7:0]; +assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata0_we; +assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; +assign csrbank1_dfii_pi2_address1_w = soc_litedramcore_phaseinjector2_address_storage[13:8]; +assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign csrbank1_dfii_pi2_wrdata3_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign csrbank1_dfii_pi2_wrdata2_w = soc_litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign csrbank1_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign csrbank1_dfii_pi2_rddata3_w = soc_litedramcore_phaseinjector2_rddata_status[31:24]; +assign csrbank1_dfii_pi2_rddata2_w = soc_litedramcore_phaseinjector2_rddata_status[23:16]; +assign csrbank1_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_rddata_status[15:8]; +assign csrbank1_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_rddata_status[7:0]; +assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata0_we; +assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; +assign csrbank1_dfii_pi3_address1_w = soc_litedramcore_phaseinjector3_address_storage[13:8]; +assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign csrbank1_dfii_pi3_wrdata3_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign csrbank1_dfii_pi3_wrdata2_w = soc_litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign csrbank1_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign csrbank1_dfii_pi3_rddata3_w = soc_litedramcore_phaseinjector3_rddata_status[31:24]; +assign csrbank1_dfii_pi3_rddata2_w = soc_litedramcore_phaseinjector3_rddata_status[23:16]; +assign csrbank1_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_rddata_status[15:8]; +assign csrbank1_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_rddata_status[7:0]; +assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata0_we; +assign csr_interconnect_adr = litedramcore_adr; +assign csr_interconnect_we = litedramcore_we; +assign csr_interconnect_dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = csr_interconnect_dat_r; +assign interface0_bank_bus_adr = csr_interconnect_adr; +assign interface1_bank_bus_adr = csr_interconnect_adr; +assign interface0_bank_bus_we = csr_interconnect_we; +assign interface1_bank_bus_we = csr_interconnect_we; +assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; +assign csr_interconnect_dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r); +assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_write_col); +assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_read_col); +assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_write_col); +assign slice_proxy3 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_read_col); +assign slice_proxy4 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_write_col); +assign slice_proxy5 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_read_col); +assign slice_proxy6 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_write_col); +assign slice_proxy7 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_read_col); +assign slice_proxy8 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_write_col); +assign slice_proxy9 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_read_col); +assign slice_proxy10 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_write_col); +assign slice_proxy11 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_read_col); +assign slice_proxy12 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_write_col); +assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_read_col); +assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col); +assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col); always @(*) begin rhs_array_muxed0 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[0]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[1]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[2]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[3]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[4]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[5]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[6]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 = litedramcore_choose_cmd_valids[7]; + rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin rhs_array_muxed1 = 14'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed2 = 3'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed3 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed4 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed5 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed0 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed0 = soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed1 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed2 = 1'd0; - case (litedramcore_choose_cmd_grant) + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed6 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[0]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[1]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[2]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[3]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[4]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[5]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[6]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 = litedramcore_choose_req_valids[7]; + rhs_array_muxed6 = soc_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin rhs_array_muxed7 = 14'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed7 = soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed8 = 3'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed8 = soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed9 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed9 = soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed10 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed10 = soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed11 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed11 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed3 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed4 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed5 = 1'd0; - case (litedramcore_choose_req_grant) + case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end @@ -10440,7 +11301,7 @@ always @(*) begin rhs_array_muxed12 = 21'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed12 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10448,7 +11309,7 @@ always @(*) begin rhs_array_muxed13 = 1'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed13 = user_port_cmd_payload_we; + rhs_array_muxed13 = soc_user_port_cmd_payload_we; end endcase end @@ -10456,7 +11317,7 @@ always @(*) begin rhs_array_muxed14 = 1'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed14 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10464,7 +11325,7 @@ always @(*) begin rhs_array_muxed15 = 21'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed15 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10472,7 +11333,7 @@ always @(*) begin rhs_array_muxed16 = 1'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed16 = user_port_cmd_payload_we; + rhs_array_muxed16 = soc_user_port_cmd_payload_we; end endcase end @@ -10480,7 +11341,7 @@ always @(*) begin rhs_array_muxed17 = 1'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed17 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10488,7 +11349,7 @@ always @(*) begin rhs_array_muxed18 = 21'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed18 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10496,7 +11357,7 @@ always @(*) begin rhs_array_muxed19 = 1'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed19 = user_port_cmd_payload_we; + rhs_array_muxed19 = soc_user_port_cmd_payload_we; end endcase end @@ -10504,7 +11365,7 @@ always @(*) begin rhs_array_muxed20 = 1'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed20 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10512,7 +11373,7 @@ always @(*) begin rhs_array_muxed21 = 21'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed21 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10520,7 +11381,7 @@ always @(*) begin rhs_array_muxed22 = 1'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed22 = user_port_cmd_payload_we; + rhs_array_muxed22 = soc_user_port_cmd_payload_we; end endcase end @@ -10528,7 +11389,7 @@ always @(*) begin rhs_array_muxed23 = 1'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed23 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10536,7 +11397,7 @@ always @(*) begin rhs_array_muxed24 = 21'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed24 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10544,7 +11405,7 @@ always @(*) begin rhs_array_muxed25 = 1'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed25 = user_port_cmd_payload_we; + rhs_array_muxed25 = soc_user_port_cmd_payload_we; end endcase end @@ -10552,7 +11413,7 @@ always @(*) begin rhs_array_muxed26 = 1'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed26 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10560,7 +11421,7 @@ always @(*) begin rhs_array_muxed27 = 21'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed27 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10568,7 +11429,7 @@ always @(*) begin rhs_array_muxed28 = 1'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed28 = user_port_cmd_payload_we; + rhs_array_muxed28 = soc_user_port_cmd_payload_we; end endcase end @@ -10576,7 +11437,7 @@ always @(*) begin rhs_array_muxed29 = 1'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed29 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10584,7 +11445,7 @@ always @(*) begin rhs_array_muxed30 = 21'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed30 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10592,7 +11453,7 @@ always @(*) begin rhs_array_muxed31 = 1'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed31 = user_port_cmd_payload_we; + rhs_array_muxed31 = soc_user_port_cmd_payload_we; end endcase end @@ -10600,7 +11461,7 @@ always @(*) begin rhs_array_muxed32 = 1'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed32 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end @@ -10608,7 +11469,7 @@ always @(*) begin rhs_array_muxed33 = 21'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed33 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end @@ -10616,7 +11477,7 @@ always @(*) begin rhs_array_muxed34 = 1'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed34 = user_port_cmd_payload_we; + rhs_array_muxed34 = soc_user_port_cmd_payload_we; end endcase end @@ -10624,1365 +11485,1346 @@ always @(*) begin rhs_array_muxed35 = 1'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed35 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin array_muxed0 = 3'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed0 = litedramcore_nop_ba[2:0]; + array_muxed0 = soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed0 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed0 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 = litedramcore_cmd_payload_ba[2:0]; + array_muxed0 = soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed1 = 14'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed1 = litedramcore_nop_a; + array_muxed1 = soc_litedramcore_nop_a; end 1'd1: begin - array_muxed1 = litedramcore_choose_cmd_cmd_payload_a; + array_muxed1 = soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 = litedramcore_choose_req_cmd_payload_a; + array_muxed1 = soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 = litedramcore_cmd_payload_a; + array_muxed1 = soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed2 = 1'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin array_muxed2 = 1'd0; end 1'd1: begin - array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + array_muxed2 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + array_muxed2 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + array_muxed2 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed3 = 1'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin array_muxed3 = 1'd0; end 1'd1: begin - array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + array_muxed3 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + array_muxed3 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + array_muxed3 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed4 = 1'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin array_muxed4 = 1'd0; end 1'd1: begin - array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + array_muxed4 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + array_muxed4 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + array_muxed4 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed5 = 1'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin array_muxed5 = 1'd0; end 1'd1: begin - array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed5 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + array_muxed5 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + array_muxed5 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed6 = 1'd0; - case (litedramcore_steerer_sel0) + case (soc_litedramcore_steerer_sel0) 1'd0: begin array_muxed6 = 1'd0; end 1'd1: begin - array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed6 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + array_muxed6 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + array_muxed6 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed7 = 3'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed7 = litedramcore_nop_ba[2:0]; + array_muxed7 = soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed7 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed7 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 = litedramcore_cmd_payload_ba[2:0]; + array_muxed7 = soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed8 = 14'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed8 = litedramcore_nop_a; + array_muxed8 = soc_litedramcore_nop_a; end 1'd1: begin - array_muxed8 = litedramcore_choose_cmd_cmd_payload_a; + array_muxed8 = soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 = litedramcore_choose_req_cmd_payload_a; + array_muxed8 = soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 = litedramcore_cmd_payload_a; + array_muxed8 = soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed9 = 1'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin array_muxed9 = 1'd0; end 1'd1: begin - array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + array_muxed9 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + array_muxed9 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + array_muxed9 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed10 = 1'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin array_muxed10 = 1'd0; end 1'd1: begin - array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + array_muxed10 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + array_muxed10 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + array_muxed10 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed11 = 1'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin array_muxed11 = 1'd0; end 1'd1: begin - array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + array_muxed11 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + array_muxed11 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + array_muxed11 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed12 = 1'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin array_muxed12 = 1'd0; end 1'd1: begin - array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed12 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + array_muxed12 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + array_muxed12 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed13 = 1'd0; - case (litedramcore_steerer_sel1) + case (soc_litedramcore_steerer_sel1) 1'd0: begin array_muxed13 = 1'd0; end 1'd1: begin - array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed13 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + array_muxed13 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + array_muxed13 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed14 = 3'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed14 = litedramcore_nop_ba[2:0]; + array_muxed14 = soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed14 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed14 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 = litedramcore_cmd_payload_ba[2:0]; + array_muxed14 = soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed15 = 14'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed15 = litedramcore_nop_a; + array_muxed15 = soc_litedramcore_nop_a; end 1'd1: begin - array_muxed15 = litedramcore_choose_cmd_cmd_payload_a; + array_muxed15 = soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 = litedramcore_choose_req_cmd_payload_a; + array_muxed15 = soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 = litedramcore_cmd_payload_a; + array_muxed15 = soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed16 = 1'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin array_muxed16 = 1'd0; end 1'd1: begin - array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + array_muxed16 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + array_muxed16 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + array_muxed16 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed17 = 1'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin array_muxed17 = 1'd0; end 1'd1: begin - array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + array_muxed17 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + array_muxed17 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + array_muxed17 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed18 = 1'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin array_muxed18 = 1'd0; end 1'd1: begin - array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + array_muxed18 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + array_muxed18 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + array_muxed18 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed19 = 1'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin array_muxed19 = 1'd0; end 1'd1: begin - array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed19 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + array_muxed19 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + array_muxed19 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed20 = 1'd0; - case (litedramcore_steerer_sel2) + case (soc_litedramcore_steerer_sel2) 1'd0: begin array_muxed20 = 1'd0; end 1'd1: begin - array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed20 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + array_muxed20 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + array_muxed20 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed21 = 3'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed21 = litedramcore_nop_ba[2:0]; + array_muxed21 = soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed21 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed21 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 = litedramcore_cmd_payload_ba[2:0]; + array_muxed21 = soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed22 = 14'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed22 = litedramcore_nop_a; + array_muxed22 = soc_litedramcore_nop_a; end 1'd1: begin - array_muxed22 = litedramcore_choose_cmd_cmd_payload_a; + array_muxed22 = soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 = litedramcore_choose_req_cmd_payload_a; + array_muxed22 = soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 = litedramcore_cmd_payload_a; + array_muxed22 = soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed23 = 1'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin array_muxed23 = 1'd0; end 1'd1: begin - array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + array_muxed23 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + array_muxed23 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + array_muxed23 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed24 = 1'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin array_muxed24 = 1'd0; end 1'd1: begin - array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + array_muxed24 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + array_muxed24 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + array_muxed24 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed25 = 1'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin array_muxed25 = 1'd0; end 1'd1: begin - array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + array_muxed25 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + array_muxed25 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + array_muxed25 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed26 = 1'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin array_muxed26 = 1'd0; end 1'd1: begin - array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed26 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + array_muxed26 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + array_muxed26 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed27 = 1'd0; - case (litedramcore_steerer_sel3) + case (soc_litedramcore_steerer_sel3) 1'd0: begin array_muxed27 = 1'd0; end 1'd1: begin - array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed27 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + array_muxed27 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + array_muxed27 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(posedge por_clk) begin - int_rst <= 1'd0; + soc_int_rst <= 1'd0; end always @(posedge sys_clk) begin - state <= next_state; - ddrphy_new_bank_write0 <= ddrphy_bank_write0; - ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0; - ddrphy_new_bank_write1 <= ddrphy_new_bank_write0; - ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0; - ddrphy_new_bank_write2 <= ddrphy_bank_write1; - ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1; - ddrphy_new_bank_write3 <= ddrphy_new_bank_write2; - ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2; - ddrphy_new_bank_write4 <= ddrphy_bank_write2; - ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2; - ddrphy_new_bank_write5 <= ddrphy_new_bank_write4; - ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4; - ddrphy_new_bank_write6 <= ddrphy_bank_write3; - ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3; - ddrphy_new_bank_write7 <= ddrphy_new_bank_write6; - ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6; - ddrphy_new_bank_write8 <= ddrphy_bank_write4; - ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4; - ddrphy_new_bank_write9 <= ddrphy_new_bank_write8; - ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8; - ddrphy_new_bank_write10 <= ddrphy_bank_write5; - ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5; - ddrphy_new_bank_write11 <= ddrphy_new_bank_write10; - ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10; - ddrphy_new_bank_write12 <= ddrphy_bank_write6; - ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6; - ddrphy_new_bank_write13 <= ddrphy_new_bank_write12; - ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12; - ddrphy_new_bank_write14 <= ddrphy_bank_write7; - ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7; - ddrphy_new_bank_write15 <= ddrphy_new_bank_write14; - ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14; - ddrphy_new_banks_read0 <= ddrphy_banks_read; - ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data; - ddrphy_new_banks_read1 <= ddrphy_new_banks_read0; - ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0; - ddrphy_new_banks_read2 <= ddrphy_new_banks_read1; - ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1; - ddrphy_new_banks_read3 <= ddrphy_new_banks_read2; - ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2; - ddrphy_new_banks_read4 <= ddrphy_new_banks_read3; - ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3; - ddrphy_new_banks_read5 <= ddrphy_new_banks_read4; - ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4; - ddrphy_new_banks_read6 <= ddrphy_new_banks_read5; - ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5; - ddrphy_new_banks_read7 <= ddrphy_new_banks_read6; - ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6; - ddrphy_new_banks_read8 <= ddrphy_new_banks_read7; - ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7; - if (ddrphy_bankmodel0_precharge) begin - ddrphy_bankmodel0_active <= 1'd0; - end else begin - if (ddrphy_bankmodel0_activate) begin - ddrphy_bankmodel0_active <= 1'd1; - ddrphy_bankmodel0_row <= ddrphy_bankmodel0_activate_row; - end - end - if (ddrphy_bankmodel1_precharge) begin - ddrphy_bankmodel1_active <= 1'd0; - end else begin - if (ddrphy_bankmodel1_activate) begin - ddrphy_bankmodel1_active <= 1'd1; - ddrphy_bankmodel1_row <= ddrphy_bankmodel1_activate_row; - end - end - if (ddrphy_bankmodel2_precharge) begin - ddrphy_bankmodel2_active <= 1'd0; - end else begin - if (ddrphy_bankmodel2_activate) begin - ddrphy_bankmodel2_active <= 1'd1; - ddrphy_bankmodel2_row <= ddrphy_bankmodel2_activate_row; - end - end - if (ddrphy_bankmodel3_precharge) begin - ddrphy_bankmodel3_active <= 1'd0; - end else begin - if (ddrphy_bankmodel3_activate) begin - ddrphy_bankmodel3_active <= 1'd1; - ddrphy_bankmodel3_row <= ddrphy_bankmodel3_activate_row; - end - end - if (ddrphy_bankmodel4_precharge) begin - ddrphy_bankmodel4_active <= 1'd0; - end else begin - if (ddrphy_bankmodel4_activate) begin - ddrphy_bankmodel4_active <= 1'd1; - ddrphy_bankmodel4_row <= ddrphy_bankmodel4_activate_row; - end - end - if (ddrphy_bankmodel5_precharge) begin - ddrphy_bankmodel5_active <= 1'd0; - end else begin - if (ddrphy_bankmodel5_activate) begin - ddrphy_bankmodel5_active <= 1'd1; - ddrphy_bankmodel5_row <= ddrphy_bankmodel5_activate_row; - end - end - if (ddrphy_bankmodel6_precharge) begin - ddrphy_bankmodel6_active <= 1'd0; - end else begin - if (ddrphy_bankmodel6_activate) begin - ddrphy_bankmodel6_active <= 1'd1; - ddrphy_bankmodel6_row <= ddrphy_bankmodel6_activate_row; - end - end - if (ddrphy_bankmodel7_precharge) begin - ddrphy_bankmodel7_active <= 1'd0; - end else begin - if (ddrphy_bankmodel7_activate) begin - ddrphy_bankmodel7_active <= 1'd1; - ddrphy_bankmodel7_row <= ddrphy_bankmodel7_activate_row; - end - end - if (litedramcore_inti_p0_rddata_valid) begin - litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; - end - if (litedramcore_inti_p1_rddata_valid) begin - litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata; + soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0; + soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0; + soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1; + soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1; + soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2; + soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2; + soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3; + soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3; + soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4; + soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4; + soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5; + soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5; + soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6; + soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6; + soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7; + soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7; + soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read; + soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data; + soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0; + soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0; + soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1; + soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1; + soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2; + soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2; + soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3; + soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3; + soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4; + soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4; + soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5; + soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5; + soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6; + soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6; + if (soc_ddrphy_bankmodel0_precharge) begin + soc_ddrphy_bankmodel0_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel0_activate) begin + soc_ddrphy_bankmodel0_active <= 1'd1; + soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row; + end + end + if (soc_ddrphy_bankmodel1_precharge) begin + soc_ddrphy_bankmodel1_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel1_activate) begin + soc_ddrphy_bankmodel1_active <= 1'd1; + soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row; + end + end + if (soc_ddrphy_bankmodel2_precharge) begin + soc_ddrphy_bankmodel2_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel2_activate) begin + soc_ddrphy_bankmodel2_active <= 1'd1; + soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row; + end + end + if (soc_ddrphy_bankmodel3_precharge) begin + soc_ddrphy_bankmodel3_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel3_activate) begin + soc_ddrphy_bankmodel3_active <= 1'd1; + soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row; + end + end + if (soc_ddrphy_bankmodel4_precharge) begin + soc_ddrphy_bankmodel4_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel4_activate) begin + soc_ddrphy_bankmodel4_active <= 1'd1; + soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row; + end + end + if (soc_ddrphy_bankmodel5_precharge) begin + soc_ddrphy_bankmodel5_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel5_activate) begin + soc_ddrphy_bankmodel5_active <= 1'd1; + soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row; + end + end + if (soc_ddrphy_bankmodel6_precharge) begin + soc_ddrphy_bankmodel6_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel6_activate) begin + soc_ddrphy_bankmodel6_active <= 1'd1; + soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row; + end + end + if (soc_ddrphy_bankmodel7_precharge) begin + soc_ddrphy_bankmodel7_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel7_activate) begin + soc_ddrphy_bankmodel7_active <= 1'd1; + soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row; + end end - if (litedramcore_inti_p2_rddata_valid) begin - litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata; + if (soc_litedramcore_inti_p0_rddata_valid) begin + soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_inti_p0_rddata; end - if (litedramcore_inti_p3_rddata_valid) begin - litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata; + if (soc_litedramcore_inti_p1_rddata_valid) begin + soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_inti_p1_rddata; end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if (soc_litedramcore_inti_p2_rddata_valid) begin + soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_inti_p2_rddata; + end + if (soc_litedramcore_inti_p3_rddata_valid) begin + soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_inti_p3_rddata; + end + if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin + soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + soc_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; + soc_litedramcore_postponer_req_o <= 1'd0; + if (soc_litedramcore_postponer_req_i) begin + soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); + if ((soc_litedramcore_postponer_count == 1'd0)) begin + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_postponer_req_o <= 1'd1; end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; + if (soc_litedramcore_sequencer_start0) begin + soc_litedramcore_sequencer_count <= 1'd0; end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + if (soc_litedramcore_sequencer_done1) begin + if ((soc_litedramcore_sequencer_count != 1'd0)) begin + soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); end end end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; + if ((soc_litedramcore_sequencer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd1; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd0; end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; + if ((soc_litedramcore_sequencer_counter == 6'd35)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd1; end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_sequencer_counter <= 1'd0; + if ((soc_litedramcore_sequencer_counter == 6'd35)) begin + soc_litedramcore_sequencer_counter <= 1'd0; end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if ((soc_litedramcore_sequencer_counter != 1'd0)) begin + soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (soc_litedramcore_sequencer_start1) begin + soc_litedramcore_sequencer_counter <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin + soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; + soc_litedramcore_zqcs_executer_done <= 1'd0; + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; + if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_zqcs_executer_done <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin + soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (soc_litedramcore_zqcs_executer_start) begin + soc_litedramcore_zqcs_executer_counter <= 1'd1; end end end refresher_state <= refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine0_row_close) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine0_row_open) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd1; + soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; + soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine0_twtpcon_valid) begin + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin + soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine0_trccon_valid) begin + soc_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin + soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine0_trascon_valid) begin + soc_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end bankmachine0_state <= bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine1_row_close) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine1_row_open) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd1; + soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; + soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine1_twtpcon_valid) begin + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin + soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine1_trccon_valid) begin + soc_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin + soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine1_trascon_valid) begin + soc_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end bankmachine1_state <= bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine2_row_close) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine2_row_open) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd1; + soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; + soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine2_twtpcon_valid) begin + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin + soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine2_trccon_valid) begin + soc_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin + soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine2_trascon_valid) begin + soc_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end bankmachine2_state <= bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine3_row_close) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine3_row_open) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd1; + soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; + soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine3_twtpcon_valid) begin + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin + soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine3_trccon_valid) begin + soc_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin + soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine3_trascon_valid) begin + soc_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end bankmachine3_state <= bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine4_row_close) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine4_row_open) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd1; + soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; + soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine4_twtpcon_valid) begin + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin + soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine4_trccon_valid) begin + soc_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin + soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine4_trascon_valid) begin + soc_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end bankmachine4_state <= bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine5_row_close) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine5_row_open) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd1; + soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; + soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine5_twtpcon_valid) begin + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin + soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine5_trccon_valid) begin + soc_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin + soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine5_trascon_valid) begin + soc_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end bankmachine5_state <= bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine6_row_close) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine6_row_open) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd1; + soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; + soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine6_twtpcon_valid) begin + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin + soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine6_trccon_valid) begin + soc_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin + soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine6_trascon_valid) begin + soc_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end bankmachine6_state <= bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + if (soc_litedramcore_bankmachine7_row_close) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + if (soc_litedramcore_bankmachine7_row_open) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd1; + soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; + soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (soc_litedramcore_bankmachine7_twtpcon_valid) begin + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin + soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; + if (soc_litedramcore_bankmachine7_trccon_valid) begin + soc_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin + soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (soc_litedramcore_bankmachine7_trascon_valid) begin + soc_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end bankmachine7_state <= bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + if ((~soc_litedramcore_en0)) begin + soc_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~soc_litedramcore_max_time0)) begin + soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~soc_litedramcore_en1)) begin + soc_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~soc_litedramcore_max_time1)) begin + soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (soc_litedramcore_choose_cmd_ce) begin + case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -11992,26 +12834,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -12021,26 +12863,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -12050,26 +12892,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -12079,26 +12921,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -12108,26 +12950,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -12137,26 +12979,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -12166,26 +13008,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -12196,29 +13038,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (soc_litedramcore_choose_req_ce) begin + case (soc_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end end end @@ -12228,26 +13070,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end end end @@ -12257,26 +13099,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end end end @@ -12286,26 +13128,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end end end @@ -12315,26 +13157,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end end end @@ -12344,26 +13186,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end end end @@ -12373,26 +13215,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end end end @@ -12402,26 +13244,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; end end end @@ -12432,96 +13274,95 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd0; + soc_litedramcore_dfi_p0_bank <= array_muxed0; + soc_litedramcore_dfi_p0_address <= array_muxed1; + soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2); + soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3); + soc_litedramcore_dfi_p0_we_n <= (~array_muxed4); + soc_litedramcore_dfi_p0_rddata_en <= array_muxed5; + soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6; + soc_litedramcore_dfi_p1_cs_n <= 1'd0; + soc_litedramcore_dfi_p1_bank <= array_muxed7; + soc_litedramcore_dfi_p1_address <= array_muxed8; + soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9); + soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10); + soc_litedramcore_dfi_p1_we_n <= (~array_muxed11); + soc_litedramcore_dfi_p1_rddata_en <= array_muxed12; + soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13; + soc_litedramcore_dfi_p2_cs_n <= 1'd0; + soc_litedramcore_dfi_p2_bank <= array_muxed14; + soc_litedramcore_dfi_p2_address <= array_muxed15; + soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16); + soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17); + soc_litedramcore_dfi_p2_we_n <= (~array_muxed18); + soc_litedramcore_dfi_p2_rddata_en <= array_muxed19; + soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20; + soc_litedramcore_dfi_p3_cs_n <= 1'd0; + soc_litedramcore_dfi_p3_bank <= array_muxed21; + soc_litedramcore_dfi_p3_address <= array_muxed22; + soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23); + soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24); + soc_litedramcore_dfi_p3_we_n <= (~array_muxed25); + soc_litedramcore_dfi_p3_rddata_en <= array_muxed26; + soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (soc_litedramcore_trrdcon_valid) begin + soc_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + soc_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~soc_litedramcore_trrdcon_ready)) begin + soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); + if ((soc_litedramcore_trrdcon_count == 1'd1)) begin + soc_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; + if ((soc_litedramcore_tfawcon_count < 3'd4)) begin + if ((soc_litedramcore_tfawcon_count == 2'd3)) begin + soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (soc_litedramcore_tccdcon_valid) begin + soc_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + soc_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~soc_litedramcore_tccdcon_ready)) begin + soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); + if ((soc_litedramcore_tccdcon_count == 1'd1)) begin + soc_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (soc_litedramcore_twtrcon_valid) begin + soc_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + soc_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; + if ((~soc_litedramcore_twtrcon_ready)) begin + soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); + if ((soc_litedramcore_twtrcon_count == 1'd1)) begin + soc_litedramcore_twtrcon_ready <= 1'd1; end end end multiplexer_state <= multiplexer_next_state; - new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); new_master_wdata_ready1 <= new_master_wdata_ready0; - new_master_wdata_ready2 <= new_master_wdata_ready1; - new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); new_master_rdata_valid1 <= new_master_rdata_valid0; new_master_rdata_valid2 <= new_master_rdata_valid1; new_master_rdata_valid3 <= new_master_rdata_valid2; @@ -12530,10 +13371,19 @@ always @(posedge sys_clk) begin new_master_rdata_valid6 <= new_master_rdata_valid5; new_master_rdata_valid7 <= new_master_rdata_valid6; new_master_rdata_valid8 <= new_master_rdata_valid7; - new_master_rdata_valid9 <= new_master_rdata_valid8; + state <= next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[0]) + case (interface0_bank_bus_adr[8:0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -12543,16 +13393,16 @@ always @(posedge sys_clk) begin endcase end if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + soc_init_done_storage <= csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; + soc_init_done_re <= csrbank0_init_done0_re; if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + soc_init_error_storage <= csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; + soc_init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[4:0]) + case (interface1_bank_bus_adr[8:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; end @@ -12560,391 +13410,533 @@ always @(posedge sys_clk) begin interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w; end 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; end 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; end 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w; end 3'd7: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w; end 4'd8: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w; end 4'd9: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; end 4'd10: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w; end 4'd13: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w; end 4'd14: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; end 4'd15: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w; end 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; end 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; end 5'd19: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w; end 5'd20: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w; end 5'd21: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w; end 5'd22: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; end 5'd23: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w; end 5'd24: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w; + end + 5'd25: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w; + end + 5'd26: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w; + end + 5'd27: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + end + 5'd28: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + end + 5'd29: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w; + end + 5'd30: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + end + 5'd31: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + end + 6'd32: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w; + end + 6'd33: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w; + end + 6'd34: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w; + end + 6'd35: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + end + 6'd36: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w; + end + 6'd37: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w; + end + 6'd38: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w; + end + 6'd39: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w; + end + 6'd40: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + end + 6'd41: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + end + 6'd42: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w; + end + 6'd43: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + end + 6'd44: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + end + 6'd45: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w; + end + 6'd46: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w; + end + 6'd47: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w; + end + 6'd48: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + end + 6'd49: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w; + end + 6'd50: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w; + end + 6'd51: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w; + end + 6'd52: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w; end endcase end if (csrbank1_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; + soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; end - litedramcore_re <= csrbank1_dfii_control0_re; + soc_litedramcore_re <= csrbank1_dfii_control0_re; if (csrbank1_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; + soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; + end + soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; + if (csrbank1_dfii_pi0_address1_re) begin + soc_litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r; end - litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; if (csrbank1_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; + soc_litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; + soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; if (csrbank1_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; + soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; + end + soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; + if (csrbank1_dfii_pi0_wrdata3_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r; + end + if (csrbank1_dfii_pi0_wrdata2_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r; + end + if (csrbank1_dfii_pi0_wrdata1_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; if (csrbank1_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; + soc_litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; + soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; + soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata0_re; if (csrbank1_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; + soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; + end + soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; + if (csrbank1_dfii_pi1_address1_re) begin + soc_litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r; end - litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; if (csrbank1_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; + soc_litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; + soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; if (csrbank1_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; + soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; + end + soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; + if (csrbank1_dfii_pi1_wrdata3_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r; + end + if (csrbank1_dfii_pi1_wrdata2_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r; + end + if (csrbank1_dfii_pi1_wrdata1_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; if (csrbank1_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; + soc_litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; + soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; + soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata0_re; if (csrbank1_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; + soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; + end + soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; + if (csrbank1_dfii_pi2_address1_re) begin + soc_litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r; end - litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; if (csrbank1_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; + soc_litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; + soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; if (csrbank1_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; + soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; + end + soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; + if (csrbank1_dfii_pi2_wrdata3_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r; + end + if (csrbank1_dfii_pi2_wrdata2_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r; + end + if (csrbank1_dfii_pi2_wrdata1_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; if (csrbank1_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; + soc_litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; + soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; + soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata0_re; if (csrbank1_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; + soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; + end + soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; + if (csrbank1_dfii_pi3_address1_re) begin + soc_litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r; end - litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; if (csrbank1_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; + soc_litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; + soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; if (csrbank1_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; + soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; + end + soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; + if (csrbank1_dfii_pi3_wrdata3_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r; + end + if (csrbank1_dfii_pi3_wrdata2_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r; + end + if (csrbank1_dfii_pi3_wrdata1_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; if (csrbank1_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; + soc_litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; + soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; + soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata0_re; if (sys_rst) begin - ddrphy_bankmodel0_active <= 1'd0; - ddrphy_bankmodel0_row <= 14'd0; - ddrphy_bankmodel1_active <= 1'd0; - ddrphy_bankmodel1_row <= 14'd0; - ddrphy_bankmodel2_active <= 1'd0; - ddrphy_bankmodel2_row <= 14'd0; - ddrphy_bankmodel3_active <= 1'd0; - ddrphy_bankmodel3_row <= 14'd0; - ddrphy_bankmodel4_active <= 1'd0; - ddrphy_bankmodel4_row <= 14'd0; - ddrphy_bankmodel5_active <= 1'd0; - ddrphy_bankmodel5_row <= 14'd0; - ddrphy_bankmodel6_active <= 1'd0; - ddrphy_bankmodel6_row <= 14'd0; - ddrphy_bankmodel7_active <= 1'd0; - ddrphy_bankmodel7_row <= 14'd0; - ddrphy_new_bank_write0 <= 1'd0; - ddrphy_new_bank_write_col0 <= 10'd0; - ddrphy_new_bank_write1 <= 1'd0; - ddrphy_new_bank_write_col1 <= 10'd0; - ddrphy_new_bank_write2 <= 1'd0; - ddrphy_new_bank_write_col2 <= 10'd0; - ddrphy_new_bank_write3 <= 1'd0; - ddrphy_new_bank_write_col3 <= 10'd0; - ddrphy_new_bank_write4 <= 1'd0; - ddrphy_new_bank_write_col4 <= 10'd0; - ddrphy_new_bank_write5 <= 1'd0; - ddrphy_new_bank_write_col5 <= 10'd0; - ddrphy_new_bank_write6 <= 1'd0; - ddrphy_new_bank_write_col6 <= 10'd0; - ddrphy_new_bank_write7 <= 1'd0; - ddrphy_new_bank_write_col7 <= 10'd0; - ddrphy_new_bank_write8 <= 1'd0; - ddrphy_new_bank_write_col8 <= 10'd0; - ddrphy_new_bank_write9 <= 1'd0; - ddrphy_new_bank_write_col9 <= 10'd0; - ddrphy_new_bank_write10 <= 1'd0; - ddrphy_new_bank_write_col10 <= 10'd0; - ddrphy_new_bank_write11 <= 1'd0; - ddrphy_new_bank_write_col11 <= 10'd0; - ddrphy_new_bank_write12 <= 1'd0; - ddrphy_new_bank_write_col12 <= 10'd0; - ddrphy_new_bank_write13 <= 1'd0; - ddrphy_new_bank_write_col13 <= 10'd0; - ddrphy_new_bank_write14 <= 1'd0; - ddrphy_new_bank_write_col14 <= 10'd0; - ddrphy_new_bank_write15 <= 1'd0; - ddrphy_new_bank_write_col15 <= 10'd0; - ddrphy_new_banks_read0 <= 1'd0; - ddrphy_new_banks_read_data0 <= 128'd0; - ddrphy_new_banks_read1 <= 1'd0; - ddrphy_new_banks_read_data1 <= 128'd0; - ddrphy_new_banks_read2 <= 1'd0; - ddrphy_new_banks_read_data2 <= 128'd0; - ddrphy_new_banks_read3 <= 1'd0; - ddrphy_new_banks_read_data3 <= 128'd0; - ddrphy_new_banks_read4 <= 1'd0; - ddrphy_new_banks_read_data4 <= 128'd0; - ddrphy_new_banks_read5 <= 1'd0; - ddrphy_new_banks_read_data5 <= 128'd0; - ddrphy_new_banks_read6 <= 1'd0; - ddrphy_new_banks_read_data6 <= 128'd0; - ddrphy_new_banks_read7 <= 1'd0; - ddrphy_new_banks_read_data7 <= 128'd0; - ddrphy_new_banks_read8 <= 1'd0; - ddrphy_new_banks_read_data8 <= 128'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_status <= 32'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_status <= 32'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_status <= 32'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_status <= 32'd0; - litedramcore_dfi_p0_address <= 14'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 14'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 14'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 14'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_row <= 14'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_row <= 14'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_row <= 14'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_row <= 14'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_row <= 14'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_row <= 14'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_row <= 14'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_row <= 14'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - state <= 1'd0; + soc_ddrphy_bankmodel0_active <= 1'd0; + soc_ddrphy_bankmodel0_row <= 14'd0; + soc_ddrphy_bankmodel1_active <= 1'd0; + soc_ddrphy_bankmodel1_row <= 14'd0; + soc_ddrphy_bankmodel2_active <= 1'd0; + soc_ddrphy_bankmodel2_row <= 14'd0; + soc_ddrphy_bankmodel3_active <= 1'd0; + soc_ddrphy_bankmodel3_row <= 14'd0; + soc_ddrphy_bankmodel4_active <= 1'd0; + soc_ddrphy_bankmodel4_row <= 14'd0; + soc_ddrphy_bankmodel5_active <= 1'd0; + soc_ddrphy_bankmodel5_row <= 14'd0; + soc_ddrphy_bankmodel6_active <= 1'd0; + soc_ddrphy_bankmodel6_row <= 14'd0; + soc_ddrphy_bankmodel7_active <= 1'd0; + soc_ddrphy_bankmodel7_row <= 14'd0; + soc_ddrphy_new_bank_write0 <= 1'd0; + soc_ddrphy_new_bank_write_col0 <= 10'd0; + soc_ddrphy_new_bank_write1 <= 1'd0; + soc_ddrphy_new_bank_write_col1 <= 10'd0; + soc_ddrphy_new_bank_write2 <= 1'd0; + soc_ddrphy_new_bank_write_col2 <= 10'd0; + soc_ddrphy_new_bank_write3 <= 1'd0; + soc_ddrphy_new_bank_write_col3 <= 10'd0; + soc_ddrphy_new_bank_write4 <= 1'd0; + soc_ddrphy_new_bank_write_col4 <= 10'd0; + soc_ddrphy_new_bank_write5 <= 1'd0; + soc_ddrphy_new_bank_write_col5 <= 10'd0; + soc_ddrphy_new_bank_write6 <= 1'd0; + soc_ddrphy_new_bank_write_col6 <= 10'd0; + soc_ddrphy_new_bank_write7 <= 1'd0; + soc_ddrphy_new_bank_write_col7 <= 10'd0; + soc_ddrphy_new_banks_read0 <= 1'd0; + soc_ddrphy_new_banks_read_data0 <= 128'd0; + soc_ddrphy_new_banks_read1 <= 1'd0; + soc_ddrphy_new_banks_read_data1 <= 128'd0; + soc_ddrphy_new_banks_read2 <= 1'd0; + soc_ddrphy_new_banks_read_data2 <= 128'd0; + soc_ddrphy_new_banks_read3 <= 1'd0; + soc_ddrphy_new_banks_read_data3 <= 128'd0; + soc_ddrphy_new_banks_read4 <= 1'd0; + soc_ddrphy_new_banks_read_data4 <= 128'd0; + soc_ddrphy_new_banks_read5 <= 1'd0; + soc_ddrphy_new_banks_read_data5 <= 128'd0; + soc_ddrphy_new_banks_read6 <= 1'd0; + soc_ddrphy_new_banks_read_data6 <= 128'd0; + soc_ddrphy_new_banks_read7 <= 1'd0; + soc_ddrphy_new_banks_read_data7 <= 128'd0; + soc_litedramcore_storage <= 4'd1; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_storage <= 6'd0; + soc_litedramcore_phaseinjector0_command_re <= 1'd0; + soc_litedramcore_phaseinjector0_address_re <= 1'd0; + soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector0_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector0_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector1_command_storage <= 6'd0; + soc_litedramcore_phaseinjector1_command_re <= 1'd0; + soc_litedramcore_phaseinjector1_address_re <= 1'd0; + soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector1_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector1_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector2_command_storage <= 6'd0; + soc_litedramcore_phaseinjector2_command_re <= 1'd0; + soc_litedramcore_phaseinjector2_address_re <= 1'd0; + soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector2_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector2_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector3_command_storage <= 6'd0; + soc_litedramcore_phaseinjector3_command_re <= 1'd0; + soc_litedramcore_phaseinjector3_address_re <= 1'd0; + soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector3_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector3_rddata_re <= 1'd0; + soc_litedramcore_dfi_p0_address <= 14'd0; + soc_litedramcore_dfi_p0_bank <= 3'd0; + soc_litedramcore_dfi_p0_cas_n <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd1; + soc_litedramcore_dfi_p0_ras_n <= 1'd1; + soc_litedramcore_dfi_p0_we_n <= 1'd1; + soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p0_rddata_en <= 1'd0; + soc_litedramcore_dfi_p1_address <= 14'd0; + soc_litedramcore_dfi_p1_bank <= 3'd0; + soc_litedramcore_dfi_p1_cas_n <= 1'd1; + soc_litedramcore_dfi_p1_cs_n <= 1'd1; + soc_litedramcore_dfi_p1_ras_n <= 1'd1; + soc_litedramcore_dfi_p1_we_n <= 1'd1; + soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p1_rddata_en <= 1'd0; + soc_litedramcore_dfi_p2_address <= 14'd0; + soc_litedramcore_dfi_p2_bank <= 3'd0; + soc_litedramcore_dfi_p2_cas_n <= 1'd1; + soc_litedramcore_dfi_p2_cs_n <= 1'd1; + soc_litedramcore_dfi_p2_ras_n <= 1'd1; + soc_litedramcore_dfi_p2_we_n <= 1'd1; + soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p2_rddata_en <= 1'd0; + soc_litedramcore_dfi_p3_address <= 14'd0; + soc_litedramcore_dfi_p3_bank <= 3'd0; + soc_litedramcore_dfi_p3_cas_n <= 1'd1; + soc_litedramcore_dfi_p3_cs_n <= 1'd1; + soc_litedramcore_dfi_p3_ras_n <= 1'd1; + soc_litedramcore_dfi_p3_we_n <= 1'd1; + soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p3_rddata_en <= 1'd0; + soc_litedramcore_cmd_payload_a <= 14'd0; + soc_litedramcore_cmd_payload_ba <= 3'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_timer_count1 <= 10'd781; + soc_litedramcore_postponer_req_o <= 1'd0; + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + soc_litedramcore_sequencer_counter <= 6'd0; + soc_litedramcore_sequencer_count <= 1'd0; + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + soc_litedramcore_zqcs_executer_done <= 1'd0; + soc_litedramcore_zqcs_executer_counter <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine0_row <= 14'd0; + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_count <= 3'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_count <= 3'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine1_row <= 14'd0; + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_count <= 3'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_count <= 3'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine2_row <= 14'd0; + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_count <= 3'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_count <= 3'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine3_row <= 14'd0; + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_count <= 3'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_count <= 3'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine4_row <= 14'd0; + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_count <= 3'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_count <= 3'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine5_row <= 14'd0; + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_count <= 3'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_count <= 3'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine6_row <= 14'd0; + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_count <= 3'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_count <= 3'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine7_row <= 14'd0; + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_count <= 3'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_count <= 3'd0; + soc_litedramcore_choose_cmd_grant <= 3'd0; + soc_litedramcore_choose_req_grant <= 3'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_count <= 1'd0; + soc_litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_window <= 5'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_count <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_count <= 3'd0; + soc_litedramcore_time0 <= 5'd0; + soc_litedramcore_time1 <= 4'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; bankmachine1_state <= 4'd0; @@ -12957,7 +13949,6 @@ always @(posedge sys_clk) begin multiplexer_state <= 4'd0; new_master_wdata_ready0 <= 1'd0; new_master_wdata_ready1 <= 1'd0; - new_master_wdata_ready2 <= 1'd0; new_master_rdata_valid0 <= 1'd0; new_master_rdata_valid1 <= 1'd0; new_master_rdata_valid2 <= 1'd0; @@ -12967,472 +13958,473 @@ always @(posedge sys_clk) begin new_master_rdata_valid6 <= 1'd0; new_master_rdata_valid7 <= 1'd0; new_master_rdata_valid8 <= 1'd0; - new_master_rdata_valid9 <= 1'd0; + litedramcore_we <= 1'd0; + state <= 2'd0; end end reg [127:0] mem[0:2097151]; reg [20:0] memadr; always @(posedge sys_clk) begin - if (ddrphy_bankmodel0_write_port_we[0]) - mem[ddrphy_bankmodel0_write_port_adr][7:0] <= ddrphy_bankmodel0_write_port_dat_w[7:0]; - if (ddrphy_bankmodel0_write_port_we[1]) - mem[ddrphy_bankmodel0_write_port_adr][15:8] <= ddrphy_bankmodel0_write_port_dat_w[15:8]; - if (ddrphy_bankmodel0_write_port_we[2]) - mem[ddrphy_bankmodel0_write_port_adr][23:16] <= ddrphy_bankmodel0_write_port_dat_w[23:16]; - if (ddrphy_bankmodel0_write_port_we[3]) - mem[ddrphy_bankmodel0_write_port_adr][31:24] <= ddrphy_bankmodel0_write_port_dat_w[31:24]; - if (ddrphy_bankmodel0_write_port_we[4]) - mem[ddrphy_bankmodel0_write_port_adr][39:32] <= ddrphy_bankmodel0_write_port_dat_w[39:32]; - if (ddrphy_bankmodel0_write_port_we[5]) - mem[ddrphy_bankmodel0_write_port_adr][47:40] <= ddrphy_bankmodel0_write_port_dat_w[47:40]; - if (ddrphy_bankmodel0_write_port_we[6]) - mem[ddrphy_bankmodel0_write_port_adr][55:48] <= ddrphy_bankmodel0_write_port_dat_w[55:48]; - if (ddrphy_bankmodel0_write_port_we[7]) - mem[ddrphy_bankmodel0_write_port_adr][63:56] <= ddrphy_bankmodel0_write_port_dat_w[63:56]; - if (ddrphy_bankmodel0_write_port_we[8]) - mem[ddrphy_bankmodel0_write_port_adr][71:64] <= ddrphy_bankmodel0_write_port_dat_w[71:64]; - if (ddrphy_bankmodel0_write_port_we[9]) - mem[ddrphy_bankmodel0_write_port_adr][79:72] <= ddrphy_bankmodel0_write_port_dat_w[79:72]; - if (ddrphy_bankmodel0_write_port_we[10]) - mem[ddrphy_bankmodel0_write_port_adr][87:80] <= ddrphy_bankmodel0_write_port_dat_w[87:80]; - if (ddrphy_bankmodel0_write_port_we[11]) - mem[ddrphy_bankmodel0_write_port_adr][95:88] <= ddrphy_bankmodel0_write_port_dat_w[95:88]; - if (ddrphy_bankmodel0_write_port_we[12]) - mem[ddrphy_bankmodel0_write_port_adr][103:96] <= ddrphy_bankmodel0_write_port_dat_w[103:96]; - if (ddrphy_bankmodel0_write_port_we[13]) - mem[ddrphy_bankmodel0_write_port_adr][111:104] <= ddrphy_bankmodel0_write_port_dat_w[111:104]; - if (ddrphy_bankmodel0_write_port_we[14]) - mem[ddrphy_bankmodel0_write_port_adr][119:112] <= ddrphy_bankmodel0_write_port_dat_w[119:112]; - if (ddrphy_bankmodel0_write_port_we[15]) - mem[ddrphy_bankmodel0_write_port_adr][127:120] <= ddrphy_bankmodel0_write_port_dat_w[127:120]; - memadr <= ddrphy_bankmodel0_write_port_adr; + if (soc_ddrphy_bankmodel0_write_port_we[0]) + mem[soc_ddrphy_bankmodel0_write_port_adr][7:0] <= soc_ddrphy_bankmodel0_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel0_write_port_we[1]) + mem[soc_ddrphy_bankmodel0_write_port_adr][15:8] <= soc_ddrphy_bankmodel0_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel0_write_port_we[2]) + mem[soc_ddrphy_bankmodel0_write_port_adr][23:16] <= soc_ddrphy_bankmodel0_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel0_write_port_we[3]) + mem[soc_ddrphy_bankmodel0_write_port_adr][31:24] <= soc_ddrphy_bankmodel0_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel0_write_port_we[4]) + mem[soc_ddrphy_bankmodel0_write_port_adr][39:32] <= soc_ddrphy_bankmodel0_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel0_write_port_we[5]) + mem[soc_ddrphy_bankmodel0_write_port_adr][47:40] <= soc_ddrphy_bankmodel0_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel0_write_port_we[6]) + mem[soc_ddrphy_bankmodel0_write_port_adr][55:48] <= soc_ddrphy_bankmodel0_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel0_write_port_we[7]) + mem[soc_ddrphy_bankmodel0_write_port_adr][63:56] <= soc_ddrphy_bankmodel0_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel0_write_port_we[8]) + mem[soc_ddrphy_bankmodel0_write_port_adr][71:64] <= soc_ddrphy_bankmodel0_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel0_write_port_we[9]) + mem[soc_ddrphy_bankmodel0_write_port_adr][79:72] <= soc_ddrphy_bankmodel0_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel0_write_port_we[10]) + mem[soc_ddrphy_bankmodel0_write_port_adr][87:80] <= soc_ddrphy_bankmodel0_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel0_write_port_we[11]) + mem[soc_ddrphy_bankmodel0_write_port_adr][95:88] <= soc_ddrphy_bankmodel0_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel0_write_port_we[12]) + mem[soc_ddrphy_bankmodel0_write_port_adr][103:96] <= soc_ddrphy_bankmodel0_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel0_write_port_we[13]) + mem[soc_ddrphy_bankmodel0_write_port_adr][111:104] <= soc_ddrphy_bankmodel0_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel0_write_port_we[14]) + mem[soc_ddrphy_bankmodel0_write_port_adr][119:112] <= soc_ddrphy_bankmodel0_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel0_write_port_we[15]) + mem[soc_ddrphy_bankmodel0_write_port_adr][127:120] <= soc_ddrphy_bankmodel0_write_port_dat_w[127:120]; + memadr <= soc_ddrphy_bankmodel0_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel0_write_port_dat_r = mem[memadr]; -assign ddrphy_bankmodel0_read_port_dat_r = mem[ddrphy_bankmodel0_read_port_adr]; +assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[memadr]; +assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr]; reg [127:0] mem_1[0:2097151]; reg [20:0] memadr_1; always @(posedge sys_clk) begin - if (ddrphy_bankmodel1_write_port_we[0]) - mem_1[ddrphy_bankmodel1_write_port_adr][7:0] <= ddrphy_bankmodel1_write_port_dat_w[7:0]; - if (ddrphy_bankmodel1_write_port_we[1]) - mem_1[ddrphy_bankmodel1_write_port_adr][15:8] <= ddrphy_bankmodel1_write_port_dat_w[15:8]; - if (ddrphy_bankmodel1_write_port_we[2]) - mem_1[ddrphy_bankmodel1_write_port_adr][23:16] <= ddrphy_bankmodel1_write_port_dat_w[23:16]; - if (ddrphy_bankmodel1_write_port_we[3]) - mem_1[ddrphy_bankmodel1_write_port_adr][31:24] <= ddrphy_bankmodel1_write_port_dat_w[31:24]; - if (ddrphy_bankmodel1_write_port_we[4]) - mem_1[ddrphy_bankmodel1_write_port_adr][39:32] <= ddrphy_bankmodel1_write_port_dat_w[39:32]; - if (ddrphy_bankmodel1_write_port_we[5]) - mem_1[ddrphy_bankmodel1_write_port_adr][47:40] <= ddrphy_bankmodel1_write_port_dat_w[47:40]; - if (ddrphy_bankmodel1_write_port_we[6]) - mem_1[ddrphy_bankmodel1_write_port_adr][55:48] <= ddrphy_bankmodel1_write_port_dat_w[55:48]; - if (ddrphy_bankmodel1_write_port_we[7]) - mem_1[ddrphy_bankmodel1_write_port_adr][63:56] <= ddrphy_bankmodel1_write_port_dat_w[63:56]; - if (ddrphy_bankmodel1_write_port_we[8]) - mem_1[ddrphy_bankmodel1_write_port_adr][71:64] <= ddrphy_bankmodel1_write_port_dat_w[71:64]; - if (ddrphy_bankmodel1_write_port_we[9]) - mem_1[ddrphy_bankmodel1_write_port_adr][79:72] <= ddrphy_bankmodel1_write_port_dat_w[79:72]; - if (ddrphy_bankmodel1_write_port_we[10]) - mem_1[ddrphy_bankmodel1_write_port_adr][87:80] <= ddrphy_bankmodel1_write_port_dat_w[87:80]; - if (ddrphy_bankmodel1_write_port_we[11]) - mem_1[ddrphy_bankmodel1_write_port_adr][95:88] <= ddrphy_bankmodel1_write_port_dat_w[95:88]; - if (ddrphy_bankmodel1_write_port_we[12]) - mem_1[ddrphy_bankmodel1_write_port_adr][103:96] <= ddrphy_bankmodel1_write_port_dat_w[103:96]; - if (ddrphy_bankmodel1_write_port_we[13]) - mem_1[ddrphy_bankmodel1_write_port_adr][111:104] <= ddrphy_bankmodel1_write_port_dat_w[111:104]; - if (ddrphy_bankmodel1_write_port_we[14]) - mem_1[ddrphy_bankmodel1_write_port_adr][119:112] <= ddrphy_bankmodel1_write_port_dat_w[119:112]; - if (ddrphy_bankmodel1_write_port_we[15]) - mem_1[ddrphy_bankmodel1_write_port_adr][127:120] <= ddrphy_bankmodel1_write_port_dat_w[127:120]; - memadr_1 <= ddrphy_bankmodel1_write_port_adr; + if (soc_ddrphy_bankmodel1_write_port_we[0]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][7:0] <= soc_ddrphy_bankmodel1_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel1_write_port_we[1]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][15:8] <= soc_ddrphy_bankmodel1_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel1_write_port_we[2]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][23:16] <= soc_ddrphy_bankmodel1_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel1_write_port_we[3]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][31:24] <= soc_ddrphy_bankmodel1_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel1_write_port_we[4]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][39:32] <= soc_ddrphy_bankmodel1_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel1_write_port_we[5]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][47:40] <= soc_ddrphy_bankmodel1_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel1_write_port_we[6]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][55:48] <= soc_ddrphy_bankmodel1_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel1_write_port_we[7]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][63:56] <= soc_ddrphy_bankmodel1_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel1_write_port_we[8]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][71:64] <= soc_ddrphy_bankmodel1_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel1_write_port_we[9]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][79:72] <= soc_ddrphy_bankmodel1_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel1_write_port_we[10]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][87:80] <= soc_ddrphy_bankmodel1_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel1_write_port_we[11]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][95:88] <= soc_ddrphy_bankmodel1_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel1_write_port_we[12]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][103:96] <= soc_ddrphy_bankmodel1_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel1_write_port_we[13]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][111:104] <= soc_ddrphy_bankmodel1_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel1_write_port_we[14]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][119:112] <= soc_ddrphy_bankmodel1_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel1_write_port_we[15]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][127:120] <= soc_ddrphy_bankmodel1_write_port_dat_w[127:120]; + memadr_1 <= soc_ddrphy_bankmodel1_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1]; -assign ddrphy_bankmodel1_read_port_dat_r = mem_1[ddrphy_bankmodel1_read_port_adr]; +assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1]; +assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr]; reg [127:0] mem_2[0:2097151]; reg [20:0] memadr_2; always @(posedge sys_clk) begin - if (ddrphy_bankmodel2_write_port_we[0]) - mem_2[ddrphy_bankmodel2_write_port_adr][7:0] <= ddrphy_bankmodel2_write_port_dat_w[7:0]; - if (ddrphy_bankmodel2_write_port_we[1]) - mem_2[ddrphy_bankmodel2_write_port_adr][15:8] <= ddrphy_bankmodel2_write_port_dat_w[15:8]; - if (ddrphy_bankmodel2_write_port_we[2]) - mem_2[ddrphy_bankmodel2_write_port_adr][23:16] <= ddrphy_bankmodel2_write_port_dat_w[23:16]; - if (ddrphy_bankmodel2_write_port_we[3]) - mem_2[ddrphy_bankmodel2_write_port_adr][31:24] <= ddrphy_bankmodel2_write_port_dat_w[31:24]; - if (ddrphy_bankmodel2_write_port_we[4]) - mem_2[ddrphy_bankmodel2_write_port_adr][39:32] <= ddrphy_bankmodel2_write_port_dat_w[39:32]; - if (ddrphy_bankmodel2_write_port_we[5]) - mem_2[ddrphy_bankmodel2_write_port_adr][47:40] <= ddrphy_bankmodel2_write_port_dat_w[47:40]; - if (ddrphy_bankmodel2_write_port_we[6]) - mem_2[ddrphy_bankmodel2_write_port_adr][55:48] <= ddrphy_bankmodel2_write_port_dat_w[55:48]; - if (ddrphy_bankmodel2_write_port_we[7]) - mem_2[ddrphy_bankmodel2_write_port_adr][63:56] <= ddrphy_bankmodel2_write_port_dat_w[63:56]; - if (ddrphy_bankmodel2_write_port_we[8]) - mem_2[ddrphy_bankmodel2_write_port_adr][71:64] <= ddrphy_bankmodel2_write_port_dat_w[71:64]; - if (ddrphy_bankmodel2_write_port_we[9]) - mem_2[ddrphy_bankmodel2_write_port_adr][79:72] <= ddrphy_bankmodel2_write_port_dat_w[79:72]; - if (ddrphy_bankmodel2_write_port_we[10]) - mem_2[ddrphy_bankmodel2_write_port_adr][87:80] <= ddrphy_bankmodel2_write_port_dat_w[87:80]; - if (ddrphy_bankmodel2_write_port_we[11]) - mem_2[ddrphy_bankmodel2_write_port_adr][95:88] <= ddrphy_bankmodel2_write_port_dat_w[95:88]; - if (ddrphy_bankmodel2_write_port_we[12]) - mem_2[ddrphy_bankmodel2_write_port_adr][103:96] <= ddrphy_bankmodel2_write_port_dat_w[103:96]; - if (ddrphy_bankmodel2_write_port_we[13]) - mem_2[ddrphy_bankmodel2_write_port_adr][111:104] <= ddrphy_bankmodel2_write_port_dat_w[111:104]; - if (ddrphy_bankmodel2_write_port_we[14]) - mem_2[ddrphy_bankmodel2_write_port_adr][119:112] <= ddrphy_bankmodel2_write_port_dat_w[119:112]; - if (ddrphy_bankmodel2_write_port_we[15]) - mem_2[ddrphy_bankmodel2_write_port_adr][127:120] <= ddrphy_bankmodel2_write_port_dat_w[127:120]; - memadr_2 <= ddrphy_bankmodel2_write_port_adr; + if (soc_ddrphy_bankmodel2_write_port_we[0]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][7:0] <= soc_ddrphy_bankmodel2_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel2_write_port_we[1]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][15:8] <= soc_ddrphy_bankmodel2_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel2_write_port_we[2]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][23:16] <= soc_ddrphy_bankmodel2_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel2_write_port_we[3]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][31:24] <= soc_ddrphy_bankmodel2_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel2_write_port_we[4]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][39:32] <= soc_ddrphy_bankmodel2_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel2_write_port_we[5]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][47:40] <= soc_ddrphy_bankmodel2_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel2_write_port_we[6]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][55:48] <= soc_ddrphy_bankmodel2_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel2_write_port_we[7]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][63:56] <= soc_ddrphy_bankmodel2_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel2_write_port_we[8]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][71:64] <= soc_ddrphy_bankmodel2_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel2_write_port_we[9]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][79:72] <= soc_ddrphy_bankmodel2_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel2_write_port_we[10]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][87:80] <= soc_ddrphy_bankmodel2_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel2_write_port_we[11]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][95:88] <= soc_ddrphy_bankmodel2_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel2_write_port_we[12]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][103:96] <= soc_ddrphy_bankmodel2_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel2_write_port_we[13]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][111:104] <= soc_ddrphy_bankmodel2_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel2_write_port_we[14]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][119:112] <= soc_ddrphy_bankmodel2_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel2_write_port_we[15]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][127:120] <= soc_ddrphy_bankmodel2_write_port_dat_w[127:120]; + memadr_2 <= soc_ddrphy_bankmodel2_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2]; -assign ddrphy_bankmodel2_read_port_dat_r = mem_2[ddrphy_bankmodel2_read_port_adr]; +assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2]; +assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr]; reg [127:0] mem_3[0:2097151]; reg [20:0] memadr_3; always @(posedge sys_clk) begin - if (ddrphy_bankmodel3_write_port_we[0]) - mem_3[ddrphy_bankmodel3_write_port_adr][7:0] <= ddrphy_bankmodel3_write_port_dat_w[7:0]; - if (ddrphy_bankmodel3_write_port_we[1]) - mem_3[ddrphy_bankmodel3_write_port_adr][15:8] <= ddrphy_bankmodel3_write_port_dat_w[15:8]; - if (ddrphy_bankmodel3_write_port_we[2]) - mem_3[ddrphy_bankmodel3_write_port_adr][23:16] <= ddrphy_bankmodel3_write_port_dat_w[23:16]; - if (ddrphy_bankmodel3_write_port_we[3]) - mem_3[ddrphy_bankmodel3_write_port_adr][31:24] <= ddrphy_bankmodel3_write_port_dat_w[31:24]; - if (ddrphy_bankmodel3_write_port_we[4]) - mem_3[ddrphy_bankmodel3_write_port_adr][39:32] <= ddrphy_bankmodel3_write_port_dat_w[39:32]; - if (ddrphy_bankmodel3_write_port_we[5]) - mem_3[ddrphy_bankmodel3_write_port_adr][47:40] <= ddrphy_bankmodel3_write_port_dat_w[47:40]; - if (ddrphy_bankmodel3_write_port_we[6]) - mem_3[ddrphy_bankmodel3_write_port_adr][55:48] <= ddrphy_bankmodel3_write_port_dat_w[55:48]; - if (ddrphy_bankmodel3_write_port_we[7]) - mem_3[ddrphy_bankmodel3_write_port_adr][63:56] <= ddrphy_bankmodel3_write_port_dat_w[63:56]; - if (ddrphy_bankmodel3_write_port_we[8]) - mem_3[ddrphy_bankmodel3_write_port_adr][71:64] <= ddrphy_bankmodel3_write_port_dat_w[71:64]; - if (ddrphy_bankmodel3_write_port_we[9]) - mem_3[ddrphy_bankmodel3_write_port_adr][79:72] <= ddrphy_bankmodel3_write_port_dat_w[79:72]; - if (ddrphy_bankmodel3_write_port_we[10]) - mem_3[ddrphy_bankmodel3_write_port_adr][87:80] <= ddrphy_bankmodel3_write_port_dat_w[87:80]; - if (ddrphy_bankmodel3_write_port_we[11]) - mem_3[ddrphy_bankmodel3_write_port_adr][95:88] <= ddrphy_bankmodel3_write_port_dat_w[95:88]; - if (ddrphy_bankmodel3_write_port_we[12]) - mem_3[ddrphy_bankmodel3_write_port_adr][103:96] <= ddrphy_bankmodel3_write_port_dat_w[103:96]; - if (ddrphy_bankmodel3_write_port_we[13]) - mem_3[ddrphy_bankmodel3_write_port_adr][111:104] <= ddrphy_bankmodel3_write_port_dat_w[111:104]; - if (ddrphy_bankmodel3_write_port_we[14]) - mem_3[ddrphy_bankmodel3_write_port_adr][119:112] <= ddrphy_bankmodel3_write_port_dat_w[119:112]; - if (ddrphy_bankmodel3_write_port_we[15]) - mem_3[ddrphy_bankmodel3_write_port_adr][127:120] <= ddrphy_bankmodel3_write_port_dat_w[127:120]; - memadr_3 <= ddrphy_bankmodel3_write_port_adr; + if (soc_ddrphy_bankmodel3_write_port_we[0]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][7:0] <= soc_ddrphy_bankmodel3_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel3_write_port_we[1]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][15:8] <= soc_ddrphy_bankmodel3_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel3_write_port_we[2]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][23:16] <= soc_ddrphy_bankmodel3_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel3_write_port_we[3]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][31:24] <= soc_ddrphy_bankmodel3_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel3_write_port_we[4]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][39:32] <= soc_ddrphy_bankmodel3_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel3_write_port_we[5]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][47:40] <= soc_ddrphy_bankmodel3_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel3_write_port_we[6]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][55:48] <= soc_ddrphy_bankmodel3_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel3_write_port_we[7]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][63:56] <= soc_ddrphy_bankmodel3_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel3_write_port_we[8]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][71:64] <= soc_ddrphy_bankmodel3_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel3_write_port_we[9]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][79:72] <= soc_ddrphy_bankmodel3_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel3_write_port_we[10]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][87:80] <= soc_ddrphy_bankmodel3_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel3_write_port_we[11]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][95:88] <= soc_ddrphy_bankmodel3_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel3_write_port_we[12]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][103:96] <= soc_ddrphy_bankmodel3_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel3_write_port_we[13]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][111:104] <= soc_ddrphy_bankmodel3_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel3_write_port_we[14]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][119:112] <= soc_ddrphy_bankmodel3_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel3_write_port_we[15]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][127:120] <= soc_ddrphy_bankmodel3_write_port_dat_w[127:120]; + memadr_3 <= soc_ddrphy_bankmodel3_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3]; -assign ddrphy_bankmodel3_read_port_dat_r = mem_3[ddrphy_bankmodel3_read_port_adr]; +assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3]; +assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr]; reg [127:0] mem_4[0:2097151]; reg [20:0] memadr_4; always @(posedge sys_clk) begin - if (ddrphy_bankmodel4_write_port_we[0]) - mem_4[ddrphy_bankmodel4_write_port_adr][7:0] <= ddrphy_bankmodel4_write_port_dat_w[7:0]; - if (ddrphy_bankmodel4_write_port_we[1]) - mem_4[ddrphy_bankmodel4_write_port_adr][15:8] <= ddrphy_bankmodel4_write_port_dat_w[15:8]; - if (ddrphy_bankmodel4_write_port_we[2]) - mem_4[ddrphy_bankmodel4_write_port_adr][23:16] <= ddrphy_bankmodel4_write_port_dat_w[23:16]; - if (ddrphy_bankmodel4_write_port_we[3]) - mem_4[ddrphy_bankmodel4_write_port_adr][31:24] <= ddrphy_bankmodel4_write_port_dat_w[31:24]; - if (ddrphy_bankmodel4_write_port_we[4]) - mem_4[ddrphy_bankmodel4_write_port_adr][39:32] <= ddrphy_bankmodel4_write_port_dat_w[39:32]; - if (ddrphy_bankmodel4_write_port_we[5]) - mem_4[ddrphy_bankmodel4_write_port_adr][47:40] <= ddrphy_bankmodel4_write_port_dat_w[47:40]; - if (ddrphy_bankmodel4_write_port_we[6]) - mem_4[ddrphy_bankmodel4_write_port_adr][55:48] <= ddrphy_bankmodel4_write_port_dat_w[55:48]; - if (ddrphy_bankmodel4_write_port_we[7]) - mem_4[ddrphy_bankmodel4_write_port_adr][63:56] <= ddrphy_bankmodel4_write_port_dat_w[63:56]; - if (ddrphy_bankmodel4_write_port_we[8]) - mem_4[ddrphy_bankmodel4_write_port_adr][71:64] <= ddrphy_bankmodel4_write_port_dat_w[71:64]; - if (ddrphy_bankmodel4_write_port_we[9]) - mem_4[ddrphy_bankmodel4_write_port_adr][79:72] <= ddrphy_bankmodel4_write_port_dat_w[79:72]; - if (ddrphy_bankmodel4_write_port_we[10]) - mem_4[ddrphy_bankmodel4_write_port_adr][87:80] <= ddrphy_bankmodel4_write_port_dat_w[87:80]; - if (ddrphy_bankmodel4_write_port_we[11]) - mem_4[ddrphy_bankmodel4_write_port_adr][95:88] <= ddrphy_bankmodel4_write_port_dat_w[95:88]; - if (ddrphy_bankmodel4_write_port_we[12]) - mem_4[ddrphy_bankmodel4_write_port_adr][103:96] <= ddrphy_bankmodel4_write_port_dat_w[103:96]; - if (ddrphy_bankmodel4_write_port_we[13]) - mem_4[ddrphy_bankmodel4_write_port_adr][111:104] <= ddrphy_bankmodel4_write_port_dat_w[111:104]; - if (ddrphy_bankmodel4_write_port_we[14]) - mem_4[ddrphy_bankmodel4_write_port_adr][119:112] <= ddrphy_bankmodel4_write_port_dat_w[119:112]; - if (ddrphy_bankmodel4_write_port_we[15]) - mem_4[ddrphy_bankmodel4_write_port_adr][127:120] <= ddrphy_bankmodel4_write_port_dat_w[127:120]; - memadr_4 <= ddrphy_bankmodel4_write_port_adr; + if (soc_ddrphy_bankmodel4_write_port_we[0]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][7:0] <= soc_ddrphy_bankmodel4_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel4_write_port_we[1]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][15:8] <= soc_ddrphy_bankmodel4_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel4_write_port_we[2]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][23:16] <= soc_ddrphy_bankmodel4_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel4_write_port_we[3]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][31:24] <= soc_ddrphy_bankmodel4_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel4_write_port_we[4]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][39:32] <= soc_ddrphy_bankmodel4_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel4_write_port_we[5]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][47:40] <= soc_ddrphy_bankmodel4_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel4_write_port_we[6]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][55:48] <= soc_ddrphy_bankmodel4_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel4_write_port_we[7]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][63:56] <= soc_ddrphy_bankmodel4_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel4_write_port_we[8]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][71:64] <= soc_ddrphy_bankmodel4_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel4_write_port_we[9]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][79:72] <= soc_ddrphy_bankmodel4_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel4_write_port_we[10]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][87:80] <= soc_ddrphy_bankmodel4_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel4_write_port_we[11]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][95:88] <= soc_ddrphy_bankmodel4_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel4_write_port_we[12]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][103:96] <= soc_ddrphy_bankmodel4_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel4_write_port_we[13]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][111:104] <= soc_ddrphy_bankmodel4_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel4_write_port_we[14]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][119:112] <= soc_ddrphy_bankmodel4_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel4_write_port_we[15]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][127:120] <= soc_ddrphy_bankmodel4_write_port_dat_w[127:120]; + memadr_4 <= soc_ddrphy_bankmodel4_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4]; -assign ddrphy_bankmodel4_read_port_dat_r = mem_4[ddrphy_bankmodel4_read_port_adr]; +assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4]; +assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr]; reg [127:0] mem_5[0:2097151]; reg [20:0] memadr_5; always @(posedge sys_clk) begin - if (ddrphy_bankmodel5_write_port_we[0]) - mem_5[ddrphy_bankmodel5_write_port_adr][7:0] <= ddrphy_bankmodel5_write_port_dat_w[7:0]; - if (ddrphy_bankmodel5_write_port_we[1]) - mem_5[ddrphy_bankmodel5_write_port_adr][15:8] <= ddrphy_bankmodel5_write_port_dat_w[15:8]; - if (ddrphy_bankmodel5_write_port_we[2]) - mem_5[ddrphy_bankmodel5_write_port_adr][23:16] <= ddrphy_bankmodel5_write_port_dat_w[23:16]; - if (ddrphy_bankmodel5_write_port_we[3]) - mem_5[ddrphy_bankmodel5_write_port_adr][31:24] <= ddrphy_bankmodel5_write_port_dat_w[31:24]; - if (ddrphy_bankmodel5_write_port_we[4]) - mem_5[ddrphy_bankmodel5_write_port_adr][39:32] <= ddrphy_bankmodel5_write_port_dat_w[39:32]; - if (ddrphy_bankmodel5_write_port_we[5]) - mem_5[ddrphy_bankmodel5_write_port_adr][47:40] <= ddrphy_bankmodel5_write_port_dat_w[47:40]; - if (ddrphy_bankmodel5_write_port_we[6]) - mem_5[ddrphy_bankmodel5_write_port_adr][55:48] <= ddrphy_bankmodel5_write_port_dat_w[55:48]; - if (ddrphy_bankmodel5_write_port_we[7]) - mem_5[ddrphy_bankmodel5_write_port_adr][63:56] <= ddrphy_bankmodel5_write_port_dat_w[63:56]; - if (ddrphy_bankmodel5_write_port_we[8]) - mem_5[ddrphy_bankmodel5_write_port_adr][71:64] <= ddrphy_bankmodel5_write_port_dat_w[71:64]; - if (ddrphy_bankmodel5_write_port_we[9]) - mem_5[ddrphy_bankmodel5_write_port_adr][79:72] <= ddrphy_bankmodel5_write_port_dat_w[79:72]; - if (ddrphy_bankmodel5_write_port_we[10]) - mem_5[ddrphy_bankmodel5_write_port_adr][87:80] <= ddrphy_bankmodel5_write_port_dat_w[87:80]; - if (ddrphy_bankmodel5_write_port_we[11]) - mem_5[ddrphy_bankmodel5_write_port_adr][95:88] <= ddrphy_bankmodel5_write_port_dat_w[95:88]; - if (ddrphy_bankmodel5_write_port_we[12]) - mem_5[ddrphy_bankmodel5_write_port_adr][103:96] <= ddrphy_bankmodel5_write_port_dat_w[103:96]; - if (ddrphy_bankmodel5_write_port_we[13]) - mem_5[ddrphy_bankmodel5_write_port_adr][111:104] <= ddrphy_bankmodel5_write_port_dat_w[111:104]; - if (ddrphy_bankmodel5_write_port_we[14]) - mem_5[ddrphy_bankmodel5_write_port_adr][119:112] <= ddrphy_bankmodel5_write_port_dat_w[119:112]; - if (ddrphy_bankmodel5_write_port_we[15]) - mem_5[ddrphy_bankmodel5_write_port_adr][127:120] <= ddrphy_bankmodel5_write_port_dat_w[127:120]; - memadr_5 <= ddrphy_bankmodel5_write_port_adr; + if (soc_ddrphy_bankmodel5_write_port_we[0]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][7:0] <= soc_ddrphy_bankmodel5_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel5_write_port_we[1]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][15:8] <= soc_ddrphy_bankmodel5_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel5_write_port_we[2]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][23:16] <= soc_ddrphy_bankmodel5_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel5_write_port_we[3]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][31:24] <= soc_ddrphy_bankmodel5_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel5_write_port_we[4]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][39:32] <= soc_ddrphy_bankmodel5_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel5_write_port_we[5]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][47:40] <= soc_ddrphy_bankmodel5_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel5_write_port_we[6]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][55:48] <= soc_ddrphy_bankmodel5_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel5_write_port_we[7]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][63:56] <= soc_ddrphy_bankmodel5_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel5_write_port_we[8]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][71:64] <= soc_ddrphy_bankmodel5_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel5_write_port_we[9]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][79:72] <= soc_ddrphy_bankmodel5_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel5_write_port_we[10]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][87:80] <= soc_ddrphy_bankmodel5_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel5_write_port_we[11]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][95:88] <= soc_ddrphy_bankmodel5_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel5_write_port_we[12]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][103:96] <= soc_ddrphy_bankmodel5_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel5_write_port_we[13]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][111:104] <= soc_ddrphy_bankmodel5_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel5_write_port_we[14]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][119:112] <= soc_ddrphy_bankmodel5_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel5_write_port_we[15]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][127:120] <= soc_ddrphy_bankmodel5_write_port_dat_w[127:120]; + memadr_5 <= soc_ddrphy_bankmodel5_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5]; -assign ddrphy_bankmodel5_read_port_dat_r = mem_5[ddrphy_bankmodel5_read_port_adr]; +assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5]; +assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr]; reg [127:0] mem_6[0:2097151]; reg [20:0] memadr_6; always @(posedge sys_clk) begin - if (ddrphy_bankmodel6_write_port_we[0]) - mem_6[ddrphy_bankmodel6_write_port_adr][7:0] <= ddrphy_bankmodel6_write_port_dat_w[7:0]; - if (ddrphy_bankmodel6_write_port_we[1]) - mem_6[ddrphy_bankmodel6_write_port_adr][15:8] <= ddrphy_bankmodel6_write_port_dat_w[15:8]; - if (ddrphy_bankmodel6_write_port_we[2]) - mem_6[ddrphy_bankmodel6_write_port_adr][23:16] <= ddrphy_bankmodel6_write_port_dat_w[23:16]; - if (ddrphy_bankmodel6_write_port_we[3]) - mem_6[ddrphy_bankmodel6_write_port_adr][31:24] <= ddrphy_bankmodel6_write_port_dat_w[31:24]; - if (ddrphy_bankmodel6_write_port_we[4]) - mem_6[ddrphy_bankmodel6_write_port_adr][39:32] <= ddrphy_bankmodel6_write_port_dat_w[39:32]; - if (ddrphy_bankmodel6_write_port_we[5]) - mem_6[ddrphy_bankmodel6_write_port_adr][47:40] <= ddrphy_bankmodel6_write_port_dat_w[47:40]; - if (ddrphy_bankmodel6_write_port_we[6]) - mem_6[ddrphy_bankmodel6_write_port_adr][55:48] <= ddrphy_bankmodel6_write_port_dat_w[55:48]; - if (ddrphy_bankmodel6_write_port_we[7]) - mem_6[ddrphy_bankmodel6_write_port_adr][63:56] <= ddrphy_bankmodel6_write_port_dat_w[63:56]; - if (ddrphy_bankmodel6_write_port_we[8]) - mem_6[ddrphy_bankmodel6_write_port_adr][71:64] <= ddrphy_bankmodel6_write_port_dat_w[71:64]; - if (ddrphy_bankmodel6_write_port_we[9]) - mem_6[ddrphy_bankmodel6_write_port_adr][79:72] <= ddrphy_bankmodel6_write_port_dat_w[79:72]; - if (ddrphy_bankmodel6_write_port_we[10]) - mem_6[ddrphy_bankmodel6_write_port_adr][87:80] <= ddrphy_bankmodel6_write_port_dat_w[87:80]; - if (ddrphy_bankmodel6_write_port_we[11]) - mem_6[ddrphy_bankmodel6_write_port_adr][95:88] <= ddrphy_bankmodel6_write_port_dat_w[95:88]; - if (ddrphy_bankmodel6_write_port_we[12]) - mem_6[ddrphy_bankmodel6_write_port_adr][103:96] <= ddrphy_bankmodel6_write_port_dat_w[103:96]; - if (ddrphy_bankmodel6_write_port_we[13]) - mem_6[ddrphy_bankmodel6_write_port_adr][111:104] <= ddrphy_bankmodel6_write_port_dat_w[111:104]; - if (ddrphy_bankmodel6_write_port_we[14]) - mem_6[ddrphy_bankmodel6_write_port_adr][119:112] <= ddrphy_bankmodel6_write_port_dat_w[119:112]; - if (ddrphy_bankmodel6_write_port_we[15]) - mem_6[ddrphy_bankmodel6_write_port_adr][127:120] <= ddrphy_bankmodel6_write_port_dat_w[127:120]; - memadr_6 <= ddrphy_bankmodel6_write_port_adr; + if (soc_ddrphy_bankmodel6_write_port_we[0]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][7:0] <= soc_ddrphy_bankmodel6_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel6_write_port_we[1]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][15:8] <= soc_ddrphy_bankmodel6_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel6_write_port_we[2]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][23:16] <= soc_ddrphy_bankmodel6_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel6_write_port_we[3]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][31:24] <= soc_ddrphy_bankmodel6_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel6_write_port_we[4]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][39:32] <= soc_ddrphy_bankmodel6_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel6_write_port_we[5]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][47:40] <= soc_ddrphy_bankmodel6_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel6_write_port_we[6]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][55:48] <= soc_ddrphy_bankmodel6_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel6_write_port_we[7]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][63:56] <= soc_ddrphy_bankmodel6_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel6_write_port_we[8]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][71:64] <= soc_ddrphy_bankmodel6_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel6_write_port_we[9]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][79:72] <= soc_ddrphy_bankmodel6_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel6_write_port_we[10]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][87:80] <= soc_ddrphy_bankmodel6_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel6_write_port_we[11]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][95:88] <= soc_ddrphy_bankmodel6_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel6_write_port_we[12]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][103:96] <= soc_ddrphy_bankmodel6_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel6_write_port_we[13]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][111:104] <= soc_ddrphy_bankmodel6_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel6_write_port_we[14]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][119:112] <= soc_ddrphy_bankmodel6_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel6_write_port_we[15]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][127:120] <= soc_ddrphy_bankmodel6_write_port_dat_w[127:120]; + memadr_6 <= soc_ddrphy_bankmodel6_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6]; -assign ddrphy_bankmodel6_read_port_dat_r = mem_6[ddrphy_bankmodel6_read_port_adr]; +assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6]; +assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr]; reg [127:0] mem_7[0:2097151]; reg [20:0] memadr_7; always @(posedge sys_clk) begin - if (ddrphy_bankmodel7_write_port_we[0]) - mem_7[ddrphy_bankmodel7_write_port_adr][7:0] <= ddrphy_bankmodel7_write_port_dat_w[7:0]; - if (ddrphy_bankmodel7_write_port_we[1]) - mem_7[ddrphy_bankmodel7_write_port_adr][15:8] <= ddrphy_bankmodel7_write_port_dat_w[15:8]; - if (ddrphy_bankmodel7_write_port_we[2]) - mem_7[ddrphy_bankmodel7_write_port_adr][23:16] <= ddrphy_bankmodel7_write_port_dat_w[23:16]; - if (ddrphy_bankmodel7_write_port_we[3]) - mem_7[ddrphy_bankmodel7_write_port_adr][31:24] <= ddrphy_bankmodel7_write_port_dat_w[31:24]; - if (ddrphy_bankmodel7_write_port_we[4]) - mem_7[ddrphy_bankmodel7_write_port_adr][39:32] <= ddrphy_bankmodel7_write_port_dat_w[39:32]; - if (ddrphy_bankmodel7_write_port_we[5]) - mem_7[ddrphy_bankmodel7_write_port_adr][47:40] <= ddrphy_bankmodel7_write_port_dat_w[47:40]; - if (ddrphy_bankmodel7_write_port_we[6]) - mem_7[ddrphy_bankmodel7_write_port_adr][55:48] <= ddrphy_bankmodel7_write_port_dat_w[55:48]; - if (ddrphy_bankmodel7_write_port_we[7]) - mem_7[ddrphy_bankmodel7_write_port_adr][63:56] <= ddrphy_bankmodel7_write_port_dat_w[63:56]; - if (ddrphy_bankmodel7_write_port_we[8]) - mem_7[ddrphy_bankmodel7_write_port_adr][71:64] <= ddrphy_bankmodel7_write_port_dat_w[71:64]; - if (ddrphy_bankmodel7_write_port_we[9]) - mem_7[ddrphy_bankmodel7_write_port_adr][79:72] <= ddrphy_bankmodel7_write_port_dat_w[79:72]; - if (ddrphy_bankmodel7_write_port_we[10]) - mem_7[ddrphy_bankmodel7_write_port_adr][87:80] <= ddrphy_bankmodel7_write_port_dat_w[87:80]; - if (ddrphy_bankmodel7_write_port_we[11]) - mem_7[ddrphy_bankmodel7_write_port_adr][95:88] <= ddrphy_bankmodel7_write_port_dat_w[95:88]; - if (ddrphy_bankmodel7_write_port_we[12]) - mem_7[ddrphy_bankmodel7_write_port_adr][103:96] <= ddrphy_bankmodel7_write_port_dat_w[103:96]; - if (ddrphy_bankmodel7_write_port_we[13]) - mem_7[ddrphy_bankmodel7_write_port_adr][111:104] <= ddrphy_bankmodel7_write_port_dat_w[111:104]; - if (ddrphy_bankmodel7_write_port_we[14]) - mem_7[ddrphy_bankmodel7_write_port_adr][119:112] <= ddrphy_bankmodel7_write_port_dat_w[119:112]; - if (ddrphy_bankmodel7_write_port_we[15]) - mem_7[ddrphy_bankmodel7_write_port_adr][127:120] <= ddrphy_bankmodel7_write_port_dat_w[127:120]; - memadr_7 <= ddrphy_bankmodel7_write_port_adr; + if (soc_ddrphy_bankmodel7_write_port_we[0]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][7:0] <= soc_ddrphy_bankmodel7_write_port_dat_w[7:0]; + if (soc_ddrphy_bankmodel7_write_port_we[1]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][15:8] <= soc_ddrphy_bankmodel7_write_port_dat_w[15:8]; + if (soc_ddrphy_bankmodel7_write_port_we[2]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][23:16] <= soc_ddrphy_bankmodel7_write_port_dat_w[23:16]; + if (soc_ddrphy_bankmodel7_write_port_we[3]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][31:24] <= soc_ddrphy_bankmodel7_write_port_dat_w[31:24]; + if (soc_ddrphy_bankmodel7_write_port_we[4]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][39:32] <= soc_ddrphy_bankmodel7_write_port_dat_w[39:32]; + if (soc_ddrphy_bankmodel7_write_port_we[5]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][47:40] <= soc_ddrphy_bankmodel7_write_port_dat_w[47:40]; + if (soc_ddrphy_bankmodel7_write_port_we[6]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][55:48] <= soc_ddrphy_bankmodel7_write_port_dat_w[55:48]; + if (soc_ddrphy_bankmodel7_write_port_we[7]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][63:56] <= soc_ddrphy_bankmodel7_write_port_dat_w[63:56]; + if (soc_ddrphy_bankmodel7_write_port_we[8]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][71:64] <= soc_ddrphy_bankmodel7_write_port_dat_w[71:64]; + if (soc_ddrphy_bankmodel7_write_port_we[9]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][79:72] <= soc_ddrphy_bankmodel7_write_port_dat_w[79:72]; + if (soc_ddrphy_bankmodel7_write_port_we[10]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][87:80] <= soc_ddrphy_bankmodel7_write_port_dat_w[87:80]; + if (soc_ddrphy_bankmodel7_write_port_we[11]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][95:88] <= soc_ddrphy_bankmodel7_write_port_dat_w[95:88]; + if (soc_ddrphy_bankmodel7_write_port_we[12]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][103:96] <= soc_ddrphy_bankmodel7_write_port_dat_w[103:96]; + if (soc_ddrphy_bankmodel7_write_port_we[13]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][111:104] <= soc_ddrphy_bankmodel7_write_port_dat_w[111:104]; + if (soc_ddrphy_bankmodel7_write_port_we[14]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][119:112] <= soc_ddrphy_bankmodel7_write_port_dat_w[119:112]; + if (soc_ddrphy_bankmodel7_write_port_we[15]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][127:120] <= soc_ddrphy_bankmodel7_write_port_dat_w[127:120]; + memadr_7 <= soc_ddrphy_bankmodel7_write_port_adr; end always @(posedge sys_clk) begin end -assign ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7]; -assign ddrphy_bankmodel7_read_port_dat_r = mem_7[ddrphy_bankmodel7_read_port_adr]; +assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7]; +assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr]; reg [23:0] storage[0:15]; reg [23:0] memdat; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_1[0:15]; reg [23:0] memdat_1; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_2[0:15]; reg [23:0] memdat_2; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_3[0:15]; reg [23:0] memdat_3; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_4[0:15]; reg [23:0] memdat_4; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_5[0:15]; reg [23:0] memdat_5; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_6[0:15]; reg [23:0] memdat_6; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_7[0:15]; reg [23:0] memdat_7; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; endmodule